IPS Alpha AX080A002A Specification

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Date

Sheet

No.

IPS4PS -AX080A002A-5Sep.01,2008IPS Alpha Technology,Ltd.

2601

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The upper section:Be䌦ore revision

Date

The lower section:After revision

Sheet No. Page

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RECORD OF REVISION

Summary

May.16,2007

Aug.20,2007

Sep.01,2008

IPS4PS 2611-AX080A002A-2

IPS4PS 2611-AX080A002A-3

IPS4PS 2611-AX080A002A-3

IPS4PS 2611-AX080A002A-4

IPS4PS 2611-AX080A002A-4

IPS4PS 2611-AX080A002A-5

IPS4PS 2614-AX080A002A-4

IPS4PS 2614-AX080A002A-5

IPS4PS 2614-AX080A002A-5

IPS4PS 2614-AX080A002A-4

IPS4PS 2614-AX080A002A-5

11-2/2

11-2/2

11-2/2

14-1/2

14-1/3

14-2/3

14-2/2

14-3/3

Added Rev.B

Prevention of 䌣reak noise

Added Rev.C

Changing Mold Frame

Diffusion Sheet:D124Z / RBEF Sheet / Diffusion Sheet:D121UY

㸢 Diffusion Sheet:D141Z / Diffusion Sheet:D141Z

Added Rev.G

Changing Mold Frame and lower side mold

A page number is changed by the addition of
new packing specifications.

A page number is changed by the addition of
new packing specifications.
(Details of new packing specifications)

A page number is changed by the addition of
new packing specifications.

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2602

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The following specifications are applied to the following TFT-LCD module.
Note : Inverter for back light unit is built in this module.

Product Name : AX080A002A

Place of production : Mobara
The factory of production : IPS-Alpha Technology
The country of origin : Japan

Effective Display Area : (H)697.6845×(V)392.256 (mm)

Number of Pixels : (H)1,366×(V)768 (pixels)

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DESCRIPTION

General Specifications

Pixel Pitch : (H)0.51075×(V)0.51075 (mm)

Color Pixel Arrangement : R+G+B Vertical Stripe

Display Mode : Transmissive Mode
Normally Black Mode

Top Polarizer Type : Anti-Glare

Number of Colors : 16,777,216 (colors)

Viewing Angle Range : Super Wide Version
(Horizontal & Vertical : 178°, CR㻢10)

Input Signal : 2-channel LVDS (LVDS:Low Voltage Differential Signaling)

Back Light : 18 pcs. of EEFL

External Dimensions : (H)760.0×(V)450.0×(t)77.0 (mm)

Weight : 7,200g typ.

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1. ABSOLUTE MAXIMUM RATINGS

1.1 Environmental Absolute Maximum Ratings

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ITEM

Temperature

Humidity

Vibration

Shock 29.4(3G)

Min. Max. Min. Max.

0-20

㪌㪇 60

2)

-

4.9(0.5G)

-

Corrosive Gas Not Acceptable

2)

-

-

14.7 (1.5G)

294 (30G)

Not Acceptable

Unit Note

㷄

䋦RH

m/s
m/s

2

2

1),5),6)

1)

3)

4)

-

Illumination at

LCD Surface

--

50,000 50,000 lx

Note 1) Temperature and Humidity should be applied to the LCD front surface of a Super-TFT module,
not to the system installed with a module.
The brightness of a EEFL tends to drop at low temperature. Besides, the life-time becomes shorter
at low temperature.

2) Ta㻡40 㷄㵹㵹㵹Relative humidity should be less than

85%RH max. Dew is prohibited.
Ta䋾40 㷄㵹㵹㵹Relative humidity should be lower than
the moisture of the 85%RH at 40㷄.

㪩㪼㫃㪸㫋㫀㫍㪼㩷㪟㫌㫄㫀㪻㫀㫋㫐㩷㩿㩼㪩㪟㪀

㪈㪇㪇

㪏㪌
㪏㪇

㪍㪇

㪦㫇㪼㫉㪸㫋㫀㫅㪾㩷㫉㪸㫅㪾㪼

㪋㪇

㪉㪇

㪪㫋㫆㫉㪸㪾㪼㩷㫉㪸㫅㪾㪼

㪌

㪄㪋㪇 㪄㪉㪇 㪇 㪉㪇 㪋㪇 㪍㪇 㪏㪇

㪫㪼㫄㫇㪼㫉㪸㫋㫌㫉㪼㩷㩿㷄㪀

3) Frequency of the vibration is between 15Hz and 100Hz. (Remove the resonance point)

4) Pulse width of the shock is 10 ms.

5) Long operation under low temperature may cause some portion of display area to be reddish for
several minutes after turning on the product.
However, it does not affect the characteristics and reliability of the product.

6) The temperature of LCD front surface would be 65㷄 in operation , it may affect the optical

charactoristics however it does not damage the function of the module.

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1.2 Electrical Absolute Maximum Ratings
(1)Super-TFT Module

ITEM SYMBOL Min. Max. Unit Note

Power Supply Voltage

Input Voltage for logic

Electrostatic Durability

Note 1)It is applied to pixel data signal and clock signal.

2)Discharge Coefficient䋺250pF-100, Environmental䋺25㷄-70䋦RH

3)It is applied to I/F connector pins.

4)It is applied to the surface of a metallic bezel and a LCD panel.

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DD 0

䌖

I -0.3

䌖

ESD0

䌖

ESD1

䌖

r100
r20

13.2

3.6

V
V
V

䌫 V

Vss = 0 V

1)

2),3)

2),4)

(2) Back-light

Input Current

Input Voltage

SYMBOLITEM

IL

VL

-

-

6.0

(3,000)

mArms

Vrms

GND = 0 V

NoteUnitMax.Min.

1)

2)

Note 1)The specification shall be applied to each EEFL. The specification is defined at ground line.

2)The specification shall be applied at connector pins for a EEFL at start-up.

(3) Back-light Inverter

ITEM

Input Voltage

ON/OFF Control Input Voltage

PWM signal Voltage

Analog Dimming Vadim V-

IC Power supply

SYMBOL

Vin

ON/OFF

Vpwm

VIC

Min. Max.

0

-

-

288

7.0

7.0

7.0

Vss = 0 V

Unit Note

V

V

V

V- 13.2

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2. INITIAL OPTICAL CHARACTERISTICS

The following optical characteristics are measured under stable conditions. It takes about 30 minutes
to reach stable conditions. The measuring point is the center of display area unless otherwise noted.
The optical characteristics should be measured in a dark room or equivalent state.

Measuring equipment䋺CS-1000A, or equivalent

Ambient Temperature =25㷄䇮VDD=12.0V䇮f V=120Hz䇮
ADIM=3.3V, On duty =100%

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ITEM

Contrast Ratio

Response

Time

Brightness of white
Brightness uniformity

Color

Chromaticity

䋨CIE䋩

Variation of

Color Position

(CIE)

Green

White

Green

White

Rise

Fall

Red

Blue

Red

Blue

SYMBOL CONDITION

CR

ton

toff

Bwh

Buni

㱣

䌹

㱣

䌹

㱣

䌹

㱣

䌹

㰱㱣

㰱䌹

㰱㱣

㰱䌹

㰱㱣

㰱䌹

㰱㱣

㰱䌹

㱔=+50

㱢=0

180

㱔䋽0

1)

㪃270

°

°

°

90

㪃

°

°

1)

Min.

750

-

-

420

-

0.62

0.30

0.26

0.58

0.12

0.035

0.243

0.245

-

-

°

-

-

-

-

-

-

Typ.

1000

8
6

5㪇0

-

0.65

0.33

0.29

0.61

0.15

0.065

0.273

0.275

-

-

-

-

-

-

-

-

Max. UNIT

--

16

12

-

30

0.68

0.36

0.32

0.64

0.18

0.095

0.303

0.305

0.04

0.04

0.04

0.04

0.04

0.04

0.04

0.04

ms
ms

cd/m

%

-

-

2

NOTE

2)

3)

3)

4)

[Gray scale
=255]

5)

[Gray scale
=255]

Contrast Ratio at 89

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Date

CR89°

--

Mosaic

Pattern

Sheet

No.

10

IPS4PS -AX080A002A-5Sep.01,2008IPS Alpha Technology,Ltd.

2605

--

invisible

Page

-

6)

5-1/3

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Note 1) Definition of Viewing Angle

䋨 12 o'clock䋩

㱢=180

X'

䍎

䋨 9 o'clock䋩

Super-TFT Module

㱢=90

Y

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㱔=0

䍎

䍎

Z

㱔

Z'

eye

㱢

Y'

㱢=270

䋨 6 o'clock䋩

㱢=0

䍎

X䋨 3 o'clock䋩

䍎

2) Definition of Contrast Ratio (CR)

䌃䌒=

(Luminance at displaying WHITE)

(Luminance at displaying BLACK)

3) Definition of Response Time

Displaying

Data Signal

Optical

BLACK WHITE BLACK

%

100

90

Response
( Luminance)

10

0

4䋩 Definition of Brightness Uniformity

10%

90%

(1) (2) (3)

(4) (5) (6)

(7)

10%

䋺 measuring points

(8) (9)

50%

50%

90%

ton toff

Display pattern is white (255 level) . The brightness
uniformity is defined as the following equation. Brightness at each
point is measured, and average, maximum and minimum
brightness is calculated.

Buni= ×100

| Bmax or Bmin – Bave |

Bave

where, Bmax = Maximum brightness

Bmin = Minimum brightness

9

㰿 (B(k))

Bave= Average brightness =

k=1

䋹

5䋩Variation of color position on CIE is defined as difference between colors at =0°and
at䋽50°& =0°,90°,180°,270°.

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6) Image sticking

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mosaic pattern

0 % 100 %

Condition : operating mosaic pattern for 2 hours and gray scale (22 %) for 1 hour.

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3. ELECTRICAL CHARACTERISTICS

3.1 TFT-LCD Module Ta=25㷄䋬Vss=0V

ITEM

Power Supply Voltage

Power Supply Current

Ripple Voltage of Power Supply

SYMBOL Min.

DD

䌖

䌖

DD

䌉

DDR

11.4 12.0 12.6

-

-

Typ. Max.

0.5

-

0.7

0.15

Unit

V

A1),2)

V

Note

Note 1) DC current at fv=120Hz, fCLK=135MHz, VDD=12.0V and Display pattern is Horizontal stripe.

Super-TFT Module

DC Ampere Meter

䌖DD

䌖

SS

2) Current fuse is built in a module. Current capacity of power supply for VDD
should be larger than 4A, so that the fuse can be opened at the trouble of power supply.

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3.2 Back Light

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VALUE

SymbolITEM

MaxTypMin

90 V139

100/110
120/127

NotesUnit

Specific assurance

Input Voltage
(full wave rectifier)

IC Power supply

ON/OFF Control

Input Voltage

Analog dimming

Input Voltage

PWM signal

ON

OFF

Min.Brightness

Max.Brightness

Low

High

Vin

ON/OFF

ADIM

Vpwm

198 V264220/240

85 V288-

47 Hz6350/60fin

10.8

㪄

㪄

--V0

-

(91)

(95) (99)

-2.3

0.5-0.3

mArmsILOutput Current

--3.0 V

360200

Specific assurance

Working assurance

V13.212.0VIC

V

V

V-3.3

ADIM=3.3V

PWM on duty =100%

V0.2--

Hz- -PWM Frequency

On-Duty Range for Burst-Dimming 15 - 100 %On-Duty

Status Output

EEFL Life Time

Normal

Failed stop

VLLamp Voltage

FAIL

-

(1740)

(1880) 2,080 (2,290)

59.5

60fOutput Frequency

Open Collector

60,00050,000

(2,120)1,930

60.5

-

Vrms

Vrms

kHz

V0.80-

V

keep Low while enable is on

and off as long as system is

Ta=25㷄

Ta=0㷄

normal.

1)Hours

1) Life time of a lamp is defined. The life is determined as the time at which brightness of the lamp
is 50% compared to that of initial value at ADIM=3.3V , PWM on duty=100%

on condition of continuous operating at 25 ± 2㷄(ambient temperature) .

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4. BLOCK DIAGRAM

(1) Super-TFT Module

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Drain Driver

LVDS
Display data.
Timing signal.

DC power supply

(2) Back light unit

power supply

CN1

CN3

LVDS

Receiver

Timing

Converter

DC/DC

Converter

& & &

)

)

Super TFT-LCD

)

Lamp 18

IC Power supply

ON/OFF Control

PWM Control

ADIM Control

Status Output

CN501

Lamp 17

Back light

Inverter

Lamp 2

Lamp 1

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5. INTERFACE PIN ASSIGNMENT

5. 1 TFT-LCD MODULE

CN3 : FI-R51S-HF

(Matching connector :FI-RE51HL)

㪧㫀㫅㩷㪥 㫆㪅 㪪㫐㫄㪹㫆㫃 㪛㪼 㫊㪺㫉㫀㫇㫋㫀㫆㫅 㪥㫆 㫋㪼

㪈㪭㪪㪪 㪞㪥㪛㩿㪇㪭㪀 㪉㪀
㪉㪫㪜㪪㪫 㪋㪀
㪊 㪠㪚 㪠㫅㫋㪼㫉㫅㪸㫃㫃㫐㩷㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㪃㩷㪢㪼㪼㫇㩷㫆㫇㪼㫅
㪋 㪠㪚 㪠㫅㫋㪼㫉㫅㪸㫃㫃㫐㩷㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㪃㩷㪢㪼㪼㫇㩷㫆㫇㪼㫅
㪌 㪠㪚 㪠㫅㫋㪼㫉㫅㪸㫃㫃㫐㩷㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㪃㩷㪢㪼㪼㫇㩷㫆㫇㪼㫅
㪍 㪠㪚 㪠㫅㫋㪼㫉㫅㪸㫃㫃㫐㩷㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㪃㩷㪢㪼㪼㫇㩷㫆㫇㪼㫅
㪎 㪣㪭㪛㪪㪪㪜㪣 㪪㪼㫃㪼㪺㫋㩷㪣㪭㪛㪪㩷㪝㫆㫉㫄㪸㫋 㪌㪀
㪏 㪠㪚 㪠㫅㫋㪼㫉㫅㪸㫃㫃㫐㩷㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㪃㩷㪢㪼㪼㫇㩷㫆㫇㪼㫅

㪐 㪠㪚 㪠㫅㫋㪼㫉㫅㪸㫃㫃㫐㩷㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㪃㩷㪢㪼㪼㫇㩷㫆㫇㪼㫅
㪈㪇 㪠㪚 㪠㫅㫋㪼㫉㫅㪸㫃㫃㫐㩷㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㪃㩷㪢㪼㪼㫇㩷㫆㫇㪼㫅
㪈㪈 㪭㪪㪪 㪞㪥㪛㩿㪇㪭㪀 㪉㪀
㪈㪉 㪩㫏㪘㪇㪄
㪈㪊 㪩㫏㪘㪇㪂
㪈㪋 㪩㫏㪘㪈㪄
㪈㪌 㪩㫏㪘㪈㪂
㪈㪍 㪩㫏㪘㪉㪄
㪈㪎 㪩㫏㪘㪉㪂
㪈㪏 㪭㪪㪪 㪞㪥㪛㩿㪇㪭㪀 㪉㪀
㪈㪐 㪚㪣㪢㪘㪄
㪉㪇 㪚㪣㪢㪘㪂
㪉㪈 㪭㪪㪪 㪞㪥㪛㩿㪇㪭㪀 㪉㪀
㪉㪉 㪩㫏㪘㪊㪄
㪉㪊 㪩㫏㪘㪊㪂
㪉㪋 㪠㪚 㪠㫅㫋㪼㫉㫅㪸㫃㫃㫐㩷㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㪃㩷㪢㪼㪼㫇㩷㫆㫇㪼㫅
㪉㪌 㪠㪚 㪠㫅㫋㪼㫉㫅㪸㫃㫃
㪉㪍 㪭㪪㪪 㪞㪥㪛㩿㪇㪭㪀 㪉㪀
㪉㪎 㪭㪪㪪 㪞㪥㪛㩿㪇㪭㪀 㪉㪀
㪉㪏 㪩㫏㪙㪇㪄
㪉㪐 㪩㫏㪙㪇㪂
㪊㪇 㪩㫏㪙㪈㪄
㪊㪈 㪩㫏㪙㪈㪂
㪊㪉 㪩㫏㪙㪉㪄
㪊㪊 㪩㫏㪙㪉㪂
㪊㪋 㪭㪪㪪 㪞㪥㪛㩿㪇㪭㪀 㪉㪀
㪊㪌 㪚㪣㪢㪙㪄
㪊㪍 㪚㪣㪢㪙㪂
㪊㪎 㪭㪪㪪 㪞㪥㪛㩿㪇㪭㪀 㪉㪀
㪊㪏 㪩㫏㪙㪊㪄
㪊㪐 㪩㫏㪙㪊㪂
㪋㪇 㪠㪚 㪠㫅㫋㪼㫉㫅㪸㫃㫃㫐㩷㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㪃㩷㪢㪼㪼㫇㩷㫆㫇㪼㫅
㪋㪈 㪠㪚 㪠㫅㫋㪼㫉㫅㪸㫃㫃㫐㩷㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㪃㩷㪢㪼㪼㫇㩷㫆㫇㪼㫅
㪋㪉 㪭㪪㪪
㪋㪊 㪭㪪㪪
㪋㪋 㪭㪪㪪
㪋㪌 㪭㪪㪪
㪋㪍 㪭㪪㪪
㪋㪎 㪠㪚 㪠㫅㫋㪼㫉㫅㪸㫃㫃㫐㩷㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㪃㩷㪢㪼㪼㫇㩷㫆㫇㪼㫅
㪋㪏 㪭㪛㪛
㪋㪐 㪭㪛㪛
㪌㪇 㪭㪛㪛
㪌㪈 㪭㪛㪛

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㪧㫀㫏㪼㫃㩷㪛㪸㫋㪸

㪧㫀㫏㪼㫃㩷㪛㪸㫋㪸

㪧㫀㫏㪼㫃㩷㪛㪸㫋㪸

㪧㫀㫏㪼㫃㩷㪛㪸㫋㪸

㪧㫀㫏㪼㫃㩷㪛㪸㫋㪸

㩷㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㪃㩷㪢㪼㪼㫇㩷㫆㫇㪼㫅

㪧㫀㫏㪼㫃㩷㪛㪸㫋㪸

㪧㫀㫏㪼㫃㩷㪛㪸㫋㪸

㪧㫀㫏㪼㫃㩷㪛㪸㫋㪸

㪧㫀㫏㪼㫃㩷㪛㪸㫋㪸

㪧㫀㫏㪼㫃㩷㪛㪸㫋㪸

㪞㪥㪛㩿㪇㪭㪀

㪧㫆㫎 㪼㫉㩷㫊㫌㫇㫇㫃㫐㩷㩿㫋㫐㫇㪅㪂㪈㪉㪭㪀

㪊㪀

㪊㪀

㪊㪀

㪊㪀

㪊㪀

㪊㪀

㪊㪀

㪊㪀

㪊㪀

㪊㪀

㪉㪀

㪈㪀

Notes 1) All VDD pins shall be connected to +12.0V(Typ.).

2) All VSS pins shall be grounded. Metal bezel is internally connected to VSS.

3) Rx n+ and Rx n- (n=0,1,2,3) should be wired by twist-pairs or side-by-side FPC patterns, respectively.

4) Open : Normal mode . GND : Test mode .

5) See page 8-4/7 and 8-5/7

Date

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

Sheet

No.

IPS4PS -AX080A002A-5Sep.01,2008IPS Alpha Technology,Ltd.

2608

Page

8-1/7

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5. 2 BACK-LIGHT UNIT

CN1 : JST B3P4-VH

(Matching connector : JST JST PHR-3)

1

2

V-

V-

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NoteDescriptionSYMBOLPin No.

- side of full wave rectification

- side of full wave rectification

3

4

IC

V+

Interally Connected , Keep Open

+ side of full wave rectification

CN501 : JST B14B-PH

(Matching connector : JST PHR-14)

1

2

3

4

5

6

7

8

VIC

ON/OFF

ADIM

FAIL

PWM

GND

GND

GND

Power supply of inverter IC (12V)

High : LAMP ON Low : LAMP OFF

Analog Dimming

FAIL signal

PWM signal

GND(0V)

GND(0V)

GND(0V)

NoteDescriptionSYMBOLPin No.

9

10

11

12

13

14

GND

GND

Vout

Vout

Vout

Vout

GND(0V)

GND(0V)

+24V

+24V

+24V

+24V

Date

Sheet

No.

IPS4PS -AX080A002A-5Sep.01,2008IPS Alpha Technology,Ltd.

2608

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BLOCK DIAGRAM OF INTERFACE

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CN3

TFT-LCD Module SideTV set Side

R0-R7

G0-G7

B0-B7

Hsync

Vsync

DTMG

Host

Graphics

Controller

R0-R7

G0-G7

B0-B7

Hsync

Vsync

DTMG

TxIN

TxIN

PLL

4Z#
4Z#
4Z#

4Z#
4Z#

4Z#
4Z#
4Z#

%.-#

%.-#

4Z$
4Z$

4Z$

4Z$
4Z$

4Z$
4Z$
4Z$

㱅

㱅

㱅

㱅

㱅

㱅

㱅

㱅

㱅

PLL

RxOUT

R0㵥 R7
G0 㵥 G7

B0㵥 B7

Hsync

Vsync

DTMG

DCLK

Timing

Converter

RxOUT

R0㵥 R7
G0 㵥 G7

B0㵥 B7

Hsync

Vsync

DTMG

Host

Graphics

Controller

PLL

%.-$

%.-$

R0䌾R7 䋺Pixel R Data
G0䌾G7 䋺Pixel G Data
B0䌾B7 䋺Pixel B Data
HSYNC 䋺Horizontal synchronization signal
VSYNC 䋺Vertical synchronization signal
DTMG 䋺Display timing signal

Notes 1) The system must have the transmitter to drive the module.

2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is used
differentially.

㱅

PLL

DCLK

Timing

Converter

Date

Sheet

No.

IPS4PS -AX080A002A-5Sep.01,2008IPS Alpha Technology,Ltd.

2608

Page

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LVDS INTERFACE

SIGNAL THC63LVDM83A THC63LVDM83A THC63LVDF84A THC63LVDF84A CONTROL

R2 51 Tx IN0 27 Rx OUT0 R2
R3 52 Tx IN1 29 Rx OUT1 R3
R4 54 Tx IN2 TA OUT0+ Rx 0+ 30 Rx OUT2 R4
R5 55 Tx IN3 32 Rx OUT3 R5
R6 56 Tx IN4 33 Rx OUT4 R6
R7 3 Tx IN6 TA OUT0- Rx 0- 35 Rx OUT6 R7
G2 4 Tx IN7 37 Rx OUT7 G2
G3 6 Tx IN8 38 Rx OUT8 G3
G4 7 Tx IN9 39 Rx OUT9 G4
G5 11 Tx IN12 TA OUT1+ Rx 1+ 43 Rx OUT12 G5
G6 12 Tx IN13 45 Rx OUT13 G6
G7 14 Tx IN14 46 Rx OUT14 G7
B2 15 Tx IN15 TA OUT1- Rx 1- 47 Rx OUT15 B2

24bit B3 19 Tx IN18 51 Rx OUT18 B3

B4 20 Tx IN19 53 Rx OUT19 B4
B5 22 Tx IN20 54 Rx OUT20 B5
B6 23 Tx IN21 TA OUT2+ Rx 2+ 55 Rx OUT21 B6

B7 24 Tx IN22 1 Rx OUT22 B7
HSYNC 27 Tx IN24 3 Rx OUT24 HSYNC
VSYNC 28 Tx IN25 TA OUT2- Rx 2- 5 Rx OUT25 VSYNC

DTMG 30 Tx IN26 6 Rx OUT26 DTMG

R0 50 Tx IN27 7 Rx OUT27 R0

R1 2 Tx IN5 34 Rx OUT5 R1

G0 8 Tx IN10 TA OUT3+ Rx 3+ 41 Rx OUT10 G0

G1 10 Tx IN11 42 Rx OUT11 G1

B0 16 Tx IN16 49 Rx OUT16 B0

B1 18 Tx IN17 TA OUT3- Rx 3- 50 Rx OUT17 B1
RSVD 1) 25 Tx IN23 2 Rx OUT23 not connect

DCLK 31 TxCLK IN TxCLK OUT+ RxCLK IN+ 26 RxCLK OUT DCLK

(Pin 7 (CN3) =High )

TRANSMITTER TRANSMITTER INTERFACE CONNECTOR INTERFACE CONNECTOR RECEIVER RECEIVER TFT

PIN INPUT PC TFT-LCD PIN OUTPUT INPUT

TxCLK OUT- RxCLK IN-

R0䌾R7 䋺Pixel R Data 䋨7䋻MSB䋬䇭0䋻LSB䋩
G0䌾G7 䋺Pixel G Data 䋨7䋻MSB䋬䇭0䋻LSB䋩
B0䌾B7 䋺Pixel B Data 䋨7䋻MSB䋬䇭0䋻LSB䋩
HSYNC 䋺Horizontal synchronization signal
VSYNC 䋺Vertical synchronization signal
DTMG 䋺Display timing signal

Notes 1) RSVD(reserved) pins on the transmitter shall be "H" or "L".

Date

Sheet

No.

IPS4PS -AX080A002A-5Sep.01,2008IPS Alpha Technology,Ltd.

2608

Page

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LVDS INTERFACE

TRANSMITTER TRANSMITTER INTERFACE CONNECTOR INTERFACE CONNECTOR RECEIVER RECEIVER TFT

SIGNAL THC63LVDM83A THC63LVDM83A THC63LVDF84A THC63LVDF84A CONTROL

R0 51 Tx IN0 27 Rx OUT0 R0
R1 52 Tx IN1 29 Rx OUT1 R1
R2 54 Tx IN2 TA OUT0+ Rx 0+ 30 Rx OUT2 R2
R3 55 Tx IN3 32 Rx OUT3 R3
R4 56 Tx IN4 33 Rx OUT4 R4
R5 3 Tx IN6 TA OUT0- Rx 0- 35 Rx OUT6 R5
G0 4 Tx IN7 37 Rx OUT7 G0
G1 6 Tx IN8 38 Rx OUT8 G1
G2 7 Tx IN9 39 Rx OUT9 G2
G3 11 Tx IN12 TA OUT1+ Rx 1+ 43 Rx OUT12 G3
G4 12 Tx IN13 45 Rx OUT13 G4
G5 14 Tx IN14 46 Rx OUT14 G5
B0 15 Tx IN15 TA OUT1- Rx 1- 47 Rx OUT15 B0

24bit B1 19 Tx IN18 51 Rx OUT18 B1

B2 20 Tx IN19 53 Rx OUT19 B2
B3 22 Tx IN20 54 Rx OUT20 B3
B4 23 Tx IN21 TA OUT2+ Rx 2+ 55 Rx OUT21 B4

B5 24 Tx IN22 1 Rx OUT22 B5
HSYNC 27 Tx IN24 3 Rx OUT24 HSYNC
VSYNC 28 Tx IN25 TA OUT2- Rx 2- 5 Rx OUT25 VSYNC

DTMG 30 Tx IN26 6 Rx OUT26 DTMG

R6 50 Tx IN27 7 Rx OUT27 R6

R7 2 Tx IN5 34 Rx OUT5 R7

G6 8 Tx IN10 TA OUT3+ Rx 3+ 41 Rx OUT10 G6

G7 10 Tx IN11 42 Rx OUT11 G7

B6 16 Tx IN16 49 Rx OUT16 B6

B7 18 Tx IN17 TA OUT3- Rx 3- 50 Rx OUT17 B7

RSVD 1) 25 Tx IN23 2 Rx OUT23 not connect

DCLK 31 TxCLK IN TxCLK OUT+ RxCLK IN+ 26 RxCLK OUT DCLK

(Pin 7 (CN3) =Low or open )

PIN INPUT PC TFT-LCD PIN OUTPUT INPUT

TxCLK OUT- RxCLK IN-

R0䌾R7 䋺Pixel R Data 䋨7䋻MSB䋬䇭0䋻LSB䋩
G0䌾G7 䋺Pixel G Data 䋨7䋻MSB䋬䇭0䋻LSB䋩
B0䌾B7 䋺Pixel B Data 䋨7䋻MSB䋬䇭0䋻LSB䋩
HSYNC 䋺Horizontal synchronization signal
VSYNC 䋺Vertical synchronization signal
DTMG 䋺Display timing signal

Notes 1) RSVD(reserved) pins on the transmitter shall be "H" or "L".

Date

Sheet

No.

IPS4PS -AX080A002A-5Sep.01,2008IPS Alpha Technology,Ltd.

2608

Page

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CORRESPONDENCE BETWEEN INPUT DATA AND DISPLAY IMAGE

Display data of adjacent one pixel is latched during one cycle of DCLK.

pixel 䋺 R0䌾R7 :R data

G0䌾G7 :G data
B0䌾B7 :B data

   

&%.-

   

   

  



4䌾4
)䌾)

+08#.+&      +08#.+&

$䌾$

&6/)

Date

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2608

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RELATIONSHIP BETWEEN DISPLAY COLORS AND INPUT SIGNALS

Red DataRed DataRed Data Green DataGreen DataGreen DataGreen Data Blue DataBlue DataBlue Data

Input R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

Color

Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Red (255) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Green(255) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

Basic Blue (255) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Color Cyan 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Magenta 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Yellow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Red (1) 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Red (2) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Red : : : : : : : : : : : : : : : : : : : : : : : : :

: : : : : : : : : : : : : : : : : : : : : : : : :

Red (254) 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Red (255) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Green(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

Green(2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

Green : : : : : : : : : : : : : : : : : : : : : : : : :

: : : : : : : : : : : : : : : : : : : : : : : : :

Green(254) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0

Green(255) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Blue(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Blue(2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

Blue : : : : : : : : : : : : : : : : : : : : : : : : :

: : : : : : : : : : : : : : : : : : : : : : : : :

Blue(254) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0

Blue(255) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 11

MSB LSB MS B LSB MSB LSB

Notes 1) Definition of gray scale:
Color(n)䊶䊶䊶䊶Number in parenthesis indicates gray scale level. Larger n corresponds to brighter level.

2) Data: 1:High, 0:Low

Date

Sheet

No.

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2608

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6. INTERFACE TIMING

6.1 TIMING CHART

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tRPA2

tRPA3

tRPA4

tRPA5

tRPA6

tRPA0

tRPA1

RxA0

RxA1

RxA2

RxA3

CLKA

CLKB

GA2/0

BA3/1

RA7/5 RA6/4 RA5/3 RA4/2 RA3/1 RA2/0

BA2/0 GA7/5

DE

VSYNCHSY

NC

X BA1/7 BA0/6 GA1/7 GA0/6 RA1/7 RA0/6

GA6/4 GA5/3 GA4/2

BA7/5 BA6/4 BA5/3 BA4/2

tSC

tRPB6

tRPB0

tRPB1

GA3/1

tRPB5

Vdiff=0V

Vdiff=0V

Vdiff=0V

Vdiff=0V

tCLKA

Vdiff=0V

tCLKB

Vdiff=0V

tRPB2

tRPB3

tRPB4

RxB0

RxB1

RxB2

RxB3

CLK

Rx*0

Rx*1

Rx*2

Rx*3

GB2/0 RB7/5 RB6/4 RB5/3 RB4/2 RB3/1 RB2/0

BB3/1 BB2/0 GB7/5 GB6/4 GB5/3 GB4/2 GB3/1

DE

VSYNCHSY

NC

X BB1/7 BB0/6 GB1/7 GB0/6 RB1/7 RB0/6

BB7/5 BB6/4 BB5/3 BB4/2

Item Symbol

Frequency DCLK

65 67.5 72.5 MHz

CLK Skew tSC -4.0 0 4.0 ns

0 data position

1st data position

2nd data position

3rd data position

4th data position

5th data position

6th data position

tRP0

tRP1

tRP2

tRP3

tRP4

tRP5

tRP6

1/7tCLK 㵨 0.4

-0.4

6/7tCLK -0.4

5/7tCLK -0.4

4/7tCLK - 0.4

3/7tCLK - 0.4

2/7tCLK - 0.4

Typ MaxMin

1/7tCLK

0

6/7tCLK

5/7tCLK

4/7tCLK

3/7tCLK

2/7tCLK

1/7tCLK +0.4

+0.4

6/7tCLK +0.4

5/7tCLK + 0.4

4/7tCLK +0.4

3/7tCLK + 0.4

2/7tCLK + 0.4

Unit

ns

Vdiff=0V

Vdiff=0V

Vdiff=0V

Vdiff=0V

Note

=1/tclk

Date

Sheet

No.

IPS4PS -AX080A002A-5Sep.01,2008IPS Alpha Technology,Ltd.

2609

Page

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6.2 TIMING CHART

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DCLK

DTMG

DTMG

TCIP

TCIL

0.8V

tHD

tH

tV

tVD

DCLK

DTMG䋬
R0䌾7䋬 G0䌾7䋬 B0䌾7

1.5V

1.5V

TSTC THTC

1.5V

Notes 1) Reference level for each timing signal is 1.5V unless it is stated on the chart , high level voltage(VIH) and

low level voltage(VIL) are defined as follows:

䌖IH㻢2.0䌖䇭䇭䇭䇭䌖IL㻡0.8䌖

The above definition conforms to the specifications of LVDS transmitter

(THC63LVDM83A / by THine Microsystems, Inc.).

2) The timing of DCLK to other signals conforms to the specifications of LVDS transmitter.

3) Please input DTMG and DCLK into both Ach and Bch.

Date

Sheet

No.

IPS4PS -AX080A002A-5Sep.01,2008IPS Alpha Technology,Ltd.

2609

Page

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6.3 INTERFACE TIMING SPECIFICATIONS

100Hz

Item Symbol Min. Typ. Max. Unit Note

Vertical Frequency fV 100 Hz

Vertical Period tV 961 tH

DTMG

Vertical Valid tVD 768 tH

Horizontal Frequency

Horizontal Period

Horizontal Valid tHD

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98 104

900 1500

fH

tH 700

䋭

96.05

702

683

䋭

1000

kHz

tCLK

tCLK

2pxl/CLK

2pxl/CLK

120Hz

DTMG

Item Symbol Min. Typ. Max. Unit Note

Vertical Frequency fV 120 Hz

Vertical Period tV 800 tH

Vertical Valid tVD 768 tH

Horizontal Frequency

Horizontal Period

Horizontal Valid tHD

fH

tH 700

115 125

773 900

䋭

96.05

702

683

䋭

1000

kHz

tCLK

tCLK

2pxl/CLK

2pxl/CLK

Date

Sheet

No.

IPS4PS -AX080A002A-5Sep.01,2008IPS Alpha Technology,Ltd.

2609

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6.4 TIMING BETWEEN INTERFACE SIGNALS AND POWER SUPPLY

T16

Power Supply

VDD

Interface

VI

Back light

power supply

VIN

Inverter IC

power supply

VIC

PWM

0V

0V

0V

12V

0V

0V

11.4V

1V

T1

Hi-Z or Lo

T3

T4

T2

T6

T5

12V

Active Signal

10.8V

6.2V

T15

T17

T14

Hi-Z or Lo

T13

T12

T11

ADIM

Back light

ON/OFF

0V

0V

0.5㻡T1㻡10

400㻡T2

10㻡T3

0䋼T4,T5,T6

0.1䋼T7

2000䋼T8

100䋼T9

T7

T8

0.1䋼T10

0䋼T11,T12,T13

0㻡T14

0㻡T15

10䋼T16

1000㻡T17

T10

T9

Unit : ms

Date

Sheet

No.

IPS4PS -AX080A002A-5Sep.01,2008IPS Alpha Technology,Ltd.

2609

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㪌

㪪㪼㫇㪅㪇㪈㪃㪉㪇㪇㪏

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㪌

㪪㪼㫇㪅㪇㪈㪃㪉㪇㪇㪏

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8. DESIGNATION OF LOT MARK

8.1 LOT MARK

Month 2)

Year 1)

Notes

1)

Year Mark

2006

2007
2008

06

07

08

2䋩

Month Mark

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Production management sign

Week 3)

Month Mark

101

2

3

02

03

Special mark 4)

7

8

9

07

08

09

䋨000001䌾999999䋩

3)
Week(Day) Mark

1䌾7

8䌾14

1

2

4

5

04

05

10

11

10

11

15䌾21

22䌾28

6

06

12

12

29䌾31

4) 㵰A㵱 : Liquid crystal A . 㵰B㵱 : Liquid crystal B

8.2 Revision (REV.) control
REV. is the column for manufacturing convenience. A-Z except I and O may be written

on this column.

8.3 Location of lot mark
Lot mark is printed on a label. The label is on the metallic bezel as shown in 7.

External Dimensional.
The style of character will be changed without notice.

Lot mark

3

4

5

REV.

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2611

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8.4 The Record of the revision descrrived on the label

Rev.

Item

initial

Changing Mold Frame ,
Optical sheet parte

Changing Mold Frame and

lower side mold

䂾䋺Application product

1) Kumimura improvement

2) Dust countermeasure

A Note

B

C

G

䂾

䂾Prevention of 䌣reak noise

䂾

䂾

䂾

䂾

䂾

1) 2)

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9. COSMETIC SPECIFICATIONS

9.1 Condition for cosmetic inspection
(1) Viewing zone
a) The figure shows the correspondence

Inspection view

between eyes (of inspector) and
TFT-LCD module.

㻡45䉙: when non-operating inspection

㻡5䉙: when operating inspection

b) Inspection should be executed only from
front side and only A-zone.
Cosmetic of B-zone and C-zone are ignore.
(refer to 9.2 Definition of zone)

TFT-LCD Module

(2) Environmental
a) Temperature : 25 degrees
b) Ambient light : about 700 lx and non-directive when operating inspection.

: about 1000 lx and non-directive when non-operating inspection.

c) Back-light : when non-operating inspection, back-light should be off .

Light

㱔 㱔about 500mm

9.2 Definition of zone

䍃A-zone : Display area (pixel area)
䍃B-zone : Area between A-zone and C-zone
䍃C-zone : Metallic bezel area

A-zone

B-zone

C-zone

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9.3 COSMETIC SPECIFICATIONS
When displaying conditions are not stable (ex. at turn on or off), the following specifications
are not applied.

Operating

inspection

No.

1

2
3

4

5

6

7

Dot defect

Line defect

Uneven brightness

Stain inclusion

Line shape

W : width(mm)

L : length(mm)

Stain inclusion

Dot shape

D : ave. dia.(mm)

Scratch on polarizer

Line shape

W : width(mm)

L : length(mm)

Scratch on polarizer

Dot shape

D : ave. dia.(mm)

ITEM

Sparkle

mode

Black

mode

W㻡0.02

W㻡0.04

W㻡0.08

W>0.08

W㻡0.02

W㻡0.08

W㻡0.08

Max. acceptable number

Bright
defect

1-dot

2-dots

3-dots 0

4-dots

Density

Total

1-dot

2-dots

3-dots

4-dots

Density

Total

Total

L : Ignore

L㻡4.0

L>4.0

L㻡2.0

L>2.0

D㻡0.22

D㻡0.5 8

D>0.5

L : Ignore Ignore

L㻡20

L>20

D㻡0.2

D㻡0.6

D>0.6

0

Serious one is
not allowed.

Ignore

(See dot shape)

Ignore

Ignore

Low
bright
defect

4

0

0

0

41),2)

7

0

0

0

3

㪎

91)

8

07)

8

0

0

10

0

0

10

0

Unit Note

pcs

Units

pcs/㱢20

pcs/㱢20

mm

pcs

pcs

Units

mm

pcs

pcs

pcs

pcs

pcs

pcs

1),2),4)

1),2),5)

1),2),6)

1),3),4)

1),3),5)

1),3),6)

1),3)

7)

8)

8)

Date

Sheet

No.

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2612

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Max. acceptable number

A-zone

Ignore

10

Serious one is
not allowed.

Unit

non-operating
inspection

No.

8

9

Bubbles, peeling
in polarizer

D : ave. dia.(mm)

Wrinkles on polarizer

ITEM

D㻡0.2

D㻡0.5

D> 0.5 0

Note 1) Dot defect : defect area > 1/2 dot

2) Sparkle mode
bright defect G >24.3%

R > 24.3%

B > 24.3%
Low bright defect 24.3% 㻢 G > 4.1%

24.3% 㻢 R > 7.8%

24.3% 㻢 B > 18.0%

3) Black mode : brightness of dot is less than 70% at white. (visible to eye)

4) 1 dot : defect dot is isolated, not attached to other defect dot.

5) N dots: N defect dots are consecutive. (N means the number of defects dots)

6) Density : number of defect dots inside 20mm .

7) Those stains which can be wiped out easily are acceptable.

8) Polarizer area inside of B-zone is not applied.

9) No major (serious) defects when viewed in gray scale mode.

Note

pcs

--

8)

Date

Sheet

No.

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2612

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10. PRECAUTION

Please pay attention to the followings when a Super-TFT module with a back-light unit is used,
handled and mounted.

10.1 Precaution to handling and mounting

(1) Applying strong force to a part of the module may cause partial deformation of frame or mold,
and cause damage to the display.
(2) The module should gently and firmly be held by both hands. Never hold by just one hand in order
to avoid any internal damage. Never drop or hit the module.
(3) The module should be installed with mounting holes of a module.
(4) Uneven force such as twisted stress should not be applied to a module when a module is mounted
on the cover case. The cover case must have sufficient strength so that external force can not be
transmitted directly to a module.
(5) It is recommended to leave a space between a module and a holding board of a module so that
partial force is not applied to a module.

B-zone

Cover case

Effective display area

Edge of
cover case

Super-TFT module

Polarizer

above precaution(5)

Fig.1 Cross sectional view of a monitor set

(6) The edge of a cover case should be located inside more than 1mm from the edge of a module front
frame.
(7) A transparent protective plate should be added on the display area of a module in order to protect
a polarizer and Super-TFT cell. The transparent protective plate should have sufficient strength
so that the plate can not touch a module by external force.
(8) Materials included acetic acid and choline should not be used for a cover case as well as other parts
and boards near a module. Acetic acid attacks a polarizer. Choline attacks electric circuits due to
electro-chemical reaction.
(9) The polarizer on a TFT cell should carefully be handled due to its softness, and should not be touched,
pushed or rubbed with glass, tweezers or anything harder than HB pencil lead. The surface of
a polarizer should not be touched and rubbed with bare hand, greasy clothes or dusty clothes.
(10) The surface of a polarizer should be gently wiped with absorbent cotton, chamois or other soft
materials slightly contained petroleum benzene when the surface becomes dirty. Normal-hexane
as cleaning chemicals is recommended in order to clean adhesives which fix front/rear polarizers
on a Super-TFT cell. Other cleaning chemicals such as acetone, toluen and alcohol should not be
used to clean adhesives because they cause chemical damage to a polarizer.
(11) Saliva or water drops should be immediately wiped off. Otherwise, the portion of a polarizer may
be deformed and its color may be faded.
(12) The module should not be opened or modified. It may cause not to operate properly.
(13) Metallic bezel of a module should not be handled with bare hand or dirty gloves. Otherwise,
color of a metallic frame may become dirty during its storage. It is recommended to use clean
soft gloves and clean finger stalls when a module is handled at incoming inspection process and
production (assembly) process.
(14) Lamp(EEFL) cables should not be pulled and held.

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10.2 Precaution to operation

(1) The ambient temperature near the operated module should be satisfied with the absolute maximum
ratings. Unless it meets the specifications, sufficient cooling system should be adopted to system.
(2) The spike noise causes the mis-operation of a module. The level of spike noise should be as follows:

-200mV<=over- and under- shoot of VDD<= +200mV
VDD including over- and under- shoot should be satisfied with the absolute maximum ratings.
(3) Optical response time, luminance and chromaticity depend on the temperature of a Super-TFT
module. Response time and saturation time of EEFL luminance become longer at lower temperature
operation.
(4) Sudden temperature change may cause dew on and/or in the a module. Dew males damage to a
polarizer and/or electrical contacting portion. Dew causes fading of displayed quality.
(5) Fixed patterns displayed on a module for a long time may cause after-image. It will be recovered
soon.
(6) A module has high frequency circuits. Sufficient suppression to electromagnetic interference should
be done by system manufacturers. Grounding and shielding methods may be effective to minimize
the interference.
(7) Noise may be heard when a back-light is operated. If necessary, sufficient suppression should be
done by system manufacturers.
(8) The module should not be connected or removed while a main system works.
(9) Inserting or pulling I/F connectors causes any trouble when power supply and signal dates are
on-state.I/F connectors should be inserted and pulled after power supply and signal dates are
turned off.

10.3 Electrostatic discharge control

(1) Since a module consists of a Super-TFT cell and electronic circuits with CMOS-ICs, which are
very weak to electrostatic discharge, persons who are handling a module should be grounded
through adequate methods such as a list band. I/F connector pins should not be touched directly
with bare hands.
(2) Protection film for a polarizer on a module should be slowly peeled off so that the electrostatic
charge can be minimized.

10.4 Precaution to strong light exposure

(1) A module should not be exposed under strong light. Otherwise, characteristics of a polarizer and
color filter in a module may be degraded.

10.5 Precaution to storage

When modules for replacement are stored for a long time, following precautions should be taken care of:
(1) Modules should be stored in a dark place. It is prohibited to apply sunlight or fluorescent light

during storage. Modules should be stored at 0 to 35䍎C at normal humidity (60%RH or less).
(2) The surface of polarizers should not come in contact with any other object. It is recommended that
modules should be stored in the IPS Alpha Technology㵭s shipping box.

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10.6 Precaution to handling protection film

(1) The protection film for polarizers should be pealed off slowly and carefully by persons who are
electrically grounded with adequate methods such as a list band. Besides, ionized air should be blown
over during peeling action. Dusts on a polarizer should be blown off by an ionized nitrogen gun and
so on.
(2) The protection film should be peeling off without rubbing it to the polarizer. Because, if the film is
rubbed together with the polarizer, since the film is attached to the polarizer with a small amount
of adhesive, the adhesive may remain on a polarizer.
(3) The module with protection film should be stored on the conditions explained in 10.5 (1). However,
in case that the storage time is too long, adhesive may remain on a polarizer even after a protection
film is peeled off. Besides, in case that a module is stored at higher temperature and/or higher
humidity, adhesive may remain on a polarizer. The remained adhesive may cause non-uniformity
of display image.
(4) The adhesive can be removed easily with Normal-Hexane. The remained adhesive or its vestige on
the polarizer should be wiped off with absorbent cotton or other soft materials such as chamois
slightly contained Normal-Hexane.

10.7 Safety

(1) Since a Super-TFT cell and lamps are made of glass, handling to the broken module should be taken
care sufficiently in order not to be injured. Hands touched liquid crystal from a broken cell should be
washed sufficiently.
(2) The module should not be taken apart during operation so that back-light drives by high voltage.

10.8 Environmental protection

(1) The Super-TFT module contains external electrode fluorescent lamps.Please follow local

ordinance or regulations for its disposal.
(2) Flexible printed circuits and printed circuits board used in a module contain small amount of lead.
Please follow local ordinance or regulations for its disposal.

10.9 Use restrictions and limitations

(1) This product is not authorized for use in life support devices or systems, military applications or
other applications which pose a significant risk of personal injury.
(2) In no event shall IPS Alpha Technology, Ltd., be liable for any incidental, indirect or consequential

damages in connection with the installation or use of this product, even if informed of the possibility

there of in advance. These limitations apply to all causes of action in the aggregate, including
without limitation breach of contact, breach of warranty, negligence, strict liability,
misrepresentation and other torts.

10.10 Others

(1) Electrical components which may not affect electrical performance are subjective to change without
notice because of their availability.

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11.Packing

www.panelook.com

㪣㫀㪻㩿㪺㫆㫉㫉㫌㪾㪸㫋㪼㪻㩷㫇㪸㫇㪼㫉㪀

㪺㫆㫉㫉㫌㪾㪸㫋㪼㪻㩷㫇㪸㫇㪼㫉

㪹㫌㪽㪽㪼㫉㩷㫄㪸㫋㪼㫉㫀㪸㫃

㫇㫉㫆㪻㫌㪺㫋
㩿㫊㪺㫉㪼㪼㫅㩷㫊㫀㪻㪼㪀

㫇㫉㫆㪻㫌㪺㫋
㩿㪹㪸㪺㫂㩷㫊㫀㪻㪼㪀

㪹㫌㪽㪽㪼㫉
㩷㩷㩷㩷㫄㪸㫋㪼㫉㫀㪸㫃

㪧㪜㩷㪹㪸㪾

㫇㫉㫆㪻㫌㪺㫋

㪧㪜ⴼ

㪪㫋㪸㫋㪼㩷㫆㪽㩷㫇㫉㫆㪻㫌㪺㫋

㪫㫌㫉㫅㫊㩷㫆㫅㩷㪹㪸㪺㫂
㫆㪽㩷㫋㪿㪼㩷㫇㫉㫆㪻㫌㪺㫋

㪚㫆㫉㫉㫌㪾㪸㫋㪼㪻㩷㫇㪸㫇㪼㫉

㫇㫉㫆㪻㫌㪺㫋

㪙㪸㫅㪻

㪣

㩿㪈㪋㫇㫉㫆㪻㫌㪺㫋㫊㪆㫇㪸㫃㪼㫋㫋㪼㪀

㪝㫉㪸㫄㩿㪺㫆㫉㫉㫌㪾㪸㫋㪼㪻㩷㫇㪸㫇㪼㫉㪀

㪬㫅㪻㪼㫉㩷㪣㫀㪻㩷㩿㪺㫆㫉㫉㫌㪾㪸㫋㪼㪻㩷㫇㪸㫇㪼㫉㪀

㪧㫃㪸㫊 㫋㫀㪺㩷㫇㪸㫃㪼㫋㫋㪼

㪟

㪮

Sizeޓޓ㧦1210(L)×1000(W)×675(H) mm
Weight 㧦127kg

Date

Sheet

No.

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11

10.Packing

2TQFWEV

UETGGPUKFG

&GUKRCEMJQNFGT

www.panelook.com

NKFEQTTWICVGFRCRGT

2TQFWEV

DCEMUKFG

EQTTWICVGFRCRGT

2TQFWEV

DCI

EQTTWICVGFRCRGT

Turns on the back

of the product.

㪙㪸㫅㪻

DWHHGT

OCVGTKCN

2'DCI

5KFGDQCTFEQTTWICVGFRCRGT

7PFGT.KFEQTTWICVGFRCRGT

2NCUVKERCNGVVG

2TQFWEV

(TCOGEQTTWICVGFRCRGT

㪟

㪮

㪣

㩿㪈㪏㩷㫇㫉㫆㪻㫌㪺㫋㫊㪆㫇㪸㫃㪼㫋㫋㪼㪀

Date

Sheet

No.

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(4

#:##

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Production

ship

address

Product Name



Revision

#

REU

quantity

L5EDD8Q00030

Label Size(102×70)

Production ship(ex.)

Label Size(100×100mm)

Address label

Date

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12.RELIABILITY TEST

www.panelook.com

No.

1

2

3

4

5

6

7

8

ITEM condition Quantity

Low Temperature
/ operating
High Temperature
/ operating

High Temperature
High Humidity
/ operating

Low Temperature
/ storage
High Temperature
/ storage

High Temperature
High Humidity
/ storage

Heat shock

Heat shock test
for solder

Ta = 0㷄

Ta = 45㷄

45㷄95%RH

Ta = -30㷄

Ta = 70㷄

45㷄95%RH

-25 / 70㷄
30min / 30min

-35 / 85㷄
30min / 30min

Period

determination end

3

3

500h 1000h

500h 1000h

3 500h 1000h

3

3

3

3

3

500h

500h

500h

100cy

200cy

1000h

1000h

1000h

200cy

500cy

Result Evaluation

Display function should be kept.

13.Condition of Withstand Voltage and Insulation Resistance Test

䊶AC3000V (+100V,-0V),60Hz 1s(+1s,-0s) Maximum Detection Current 3mA Between CN1 and FG.
䊶150M㱅 min , at DC500V Between CN1 and FG.

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