IP Mobilenet IPMNIP4 User Manual
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Owner’s Manual
Date Prepared:
August 7, 2002
Document Control #: DC-67
Version: C-1 (Special Release)
Copyright 2002 IPMobileNet, Inc.
11909 East Telegraph Road Santa Fe Springs, CA 90670-3785
Voice: (562) 946-9493 Fax: (562) 949-0223
TABLE OF CONTENTS
SECTION 1: THEORY OF OPERATION ................................................................................. 3
General Block Diagram................................................................................................ 3
General Block Diagram Definitions
IP4HPV Mobile Radio Section Descriptions ..............................................................5
Microcontroller
.................................................................................................... 5
Support Circuitry ................................................................................... 5
Inputs/Outputs
Modem
.............................................................................................................. 6
VLogic and Digital Ground
Receiver 1 Front-End
Receiver 1 IF
Transmit Modulation
Injection Synthesizer
Transmitter/TR Switch
Power and Analog Ground
.................................................................................................... 5
................................................................................. 6
......................................................................................... 7
...................................................................................................... 7
........................................................................................... 7
.......................................................................................... 8
........................................................................................ 8
................................................................................. 8
SECTION 2: FACTORY TEST PROCEDURE .......................................................................10
Equipment List ........................................................................................................... 10
Programming and Configuring Mobile Radio.......................................................... 11
Adjustment / Alignment Procedures ........................................................................ 12
Receiver Injection
Receiver 1
Receiver 2
........................................................................................................ 12
........................................................................................................ 13
Transmit Data
Transmit Power Control
Receive Data
Final Test
.......................................................................................................... 15
............................................................................................. 12
................................................................................................... 14
.................................................................................... 14
.................................................................................................... 15
Uplink Hardware Timing Verification
Downlink Hardware Timing Verification
SECTION 3: FCC LABEL ...................................................................................................... 21
IP4 HPV Mobile Radio FCC Label Placement ..........................................................21
IP4 HPV Mobile Radio FCC Label .............................................................................21
APPENDIX A: IP4 HPV CIRCUIT BOARD DIAGRAM .......................................................... 44
APPENDIX B: IP4 HPV TEST DATA SHEET ........................................................................ 45
..................................................................... 3
................................................................ 17
............................................................ 19
IP4HPVGPS-MRFCCRpt.doc Page 2
SECTION 1: THEORY OF OEPRATION
General Block Diagram
General Block Diagram Definitions
For increased data security, the modem supports the Federal Government developed Digital
Encryption Standard (DES) data encryption and decryption protocols. This capability requires
installation of third party, Internet Protocol (IP) compliant DES encryption and decryption
software on the system.
The IP4HPV mobile radio is comprised of two (2) circuit boards, the digital board and the RF board. The
digital circuit board contains the following sections:
Input/Output Circuitry associated with the radio’s DB9 data connector providing all the
Microcontroller Manages the operation of the radio, the modem, and determines which
Modem Converts serial data into an analog audio waveform for transmission and
Power Supply The power supply creates the various voltages required by the digital
RS232 data and handshake functions, including the necessary level
changes.
receiver provides a better signal from a given transmission. Also provides
transmit time-out protection in the event a fault causes the radio to halt in
the transmit mode.
analog audio from the receiver to serial data. Within a single chip it
provides forward error detection and correction, bit interleaving for more
robust data communications, and third generation collision detection and
correction capabilities.
portion of the mobile radio.
IP4HPVGPS-MRFCCRpt.doc Page 3
SECTION 1: THEORY OF OPERATION
The RF circuit board contains the following sections:
Transmit Processing Circuitry that amplifies the analog audio signal from the modem and uses it
to modulate the voltage controlled oscillator (VCO) and 10 MHz reference
oscillator in the injection synthesizer section. Modulating the VCO and
reference oscillator simultaneously results in a higher quality FM signal.
Injection Synthesizer Provides programmable, ultra stable signals for the radio. Synthesizer
incorporates phase lock loop technology used for both receiving and
transmitting.
Injection In the receive mode, the synthesizer provides a local oscillator signal of 45
MHz above or below the selected receive channel frequency.
Transmitter Consists of an exciter and power amplifier module. The transmitter covers
the various frequency bands in segments. A different power amplifier
module is required for each segment. The transmitter circuitry includes a
T/R switch switching the antenna between transmitter and receiver 1
(TX/RX1).
Receiver 1/Receiver 2 Required to support the mobile DRS; two (2) discrete receivers are tuned
to the same channel and use two (2) antennas.
The receivers are double-conversion superheterodyne with a first
Intermediate Frequency (IF) of 45 MHz and a second IF frequency of 455
KHz. Each receiver consists of bandpass filters, an RF amplifier, a MMIC
mixer, crystal filters, and a one-chip IF system. The injection synthesizer
provides the first local oscillator signal. Outputs from each receiver include
RSSI and analog audio for the baseband routing circuitry and modem.
Power Supply Consists of circuitry that derives the various operating voltages for the RF
portion of the mobile radio.
IP4HPVGPS-MRFCCRpt.doc Page 4
SECTION 1: THEORY OF OPERATION
IP4HPV Mobile Radio Section Descriptions
The IP4HPV Mobile Radio works within a frequency range of 506 to 512 MHz and requires a 1/4-
This section provides detailed descriptions of each of the sections within the IP4HPV Mobile Radio.
Refer to Appendix A to view the IP4HPV Mobile Radio Circuit Board Diagram.
Microcontroller
The microcontroller (U30) is a major component of the radio as it manages the operation of the radio. It
also controls the operation of the modem, and determines which receiver provides a better signal from a
given transmission. It provides transmit time-out protection in the event a fault causes the radio to halt in
the transmit mode. It utilizes a reduced instruction set computer (RISC) architecture which provides low
power operation and a powerful instruction set. Other features include a watchdog timer, serial universal
asynchronous receiver/transmitter (UART), two 8-bit timers, and 2 KB of electrically erasable
programmable read only memory (EEPROM) storage.
NOTE
Support circuitry
The support circuitry consists of the following:
A Supervisor Control Chip (U25) provides power-on reset.
The clock controls microcontroller operation and is generated by crystal Y3 and a Pierce oscillator
The latch (U28) decodes low order address bits (A0-A7) from the address/data bits (AD0-AD7). It is
A 512Kx8 Static RAM Chip (U31) provides temporary storage of the radio’s configuration data
Control logic is also an important part in the microcontroller section. The RAM chip select (RAMCS*)
Input/Output
Input/output components convert serial and handshake data from the modem section to RS232 levels,
and vice-versa. Chip U22 is an RS232 transmitter and receiver. It converts data in 5-volt logic form to
data in +/-12-volt form, as required by the RS232 standard. A charge pump power supply on the chip
converts the +5-volt DC logic power on pin 26 to the +12-volt and –12-volt levels required. Capacitors
C106-C109 generate these voltages by a charge pump. These values determine the operating voltages.
wavelength antenna.
: The EEPROM Random Access Memory (RAM) stores the setup data entered by the
technician even if there is a loss of power.
circuit (inside the U30-microcontroller).
controlled by Address Latch Enable (ALE) output of U30 and the bits are used by the modem.
facilitating the technician with access to make changes.
and modem chip select (MODEMCS*) command lines are created by U26A, U27BCD, and U44ABC.
These gates decode four (4) high order address bits (A11-A15). The RAM is addressed by five (5)
memory addresses (MA14-MA18) bits decoded by U26D, U27A, and U24. This logic decodes port
address bits (PA14-PA18) to produce memory address bits (MA14-MA18) for the RAM chip.
IP4HPVGPS-MRFCCRpt.doc Page 5
SECTION 1: THEORY OF OPERATION
Modem
The single-chip modem circuit converts parallel data to an analog audio waveform for transmission and
analog audio from a receiver to parallel data. In addition to the modem functions, the chip provides
forward error detection and correction (FEC), bit interleaving and Viterbi Soft Decision Algorithms for
more robust data communications.
The microcontroller section controls the modem operation. Address bus, address/data bus, and control
lines operate the modem chip. The modem circuitry is also run by a crystal-controlled clock, which
consists of crystal Y1 and an internal Pierce oscillator.
The received audio signal is demodulated into digital data appearing on the AD0-AD07 lines when the
MODEMCS* and RD* lines are low. The data goes to the microcontroller section for futher processing,
and then to the input/output section for conversion to RS232 or Ethernet signal levels.
During a transmission, outgoing data appearing on the AD0-AD07 lines is converted into a 4-level FSK
analog signal by the modem chip. This operation takes place when the MODEMCS* and WR* lines are
low. Data from the user’s MDC or VIU passes through the input/output section and microcontroller
section to the AD0-AD07 bus. After processing, data passes through a root raised cosine filter and is
output to TXMOD.
This modem supports 115.2 KBPS (serial port) and 19.2 KBPS (over-the-air) data transmission rates.
VLogic and Digital Ground
The VLogic and Digital Ground section consists of a pulse-width modulation (PWM) step-down DC-DC
converter (U20) that provides an adjustable output. It also reduces noise in sensitive communications
applications and minimizes drop out voltage.
An external Schottky diode (D2) is required as an output rectifier to pass inductor current during the
second half of each cycle to prevent the slow internal diode of the N-channel MOSFET from turning on.
This diode operates in pulse-frequency modulation (PFM) mode and during transition periods while the
synchronous rectifier is off.
IP4HPVGPS-MRFCCRpt.doc Page 6
SECTION 1: THEORY OF OPERATION
Receiver 1 Front-End
This section contains components that include several RF Bandpass filters, a low-noise amplifier, and a
MMIC mixer.
Incoming signals pass through one (1) pre-selector filter (FLT7) that selectively provides a high degree of
out-of-band signal rejection. A low-noise amplifier (U3) amplifies the selected signals and is followed by
an image and noise reject filter (FLT8). The output from FLT8 passes through a mixer (U4). U4 is a
MMIC mixer which mixes the receive injection (RXINJ1) signal from the synthesizer and the RF signal
from the antenna to produce a 45 MHz IF signal. This 45 MHz signal passes through crystal filters (FLT3
and FLT4) to the Receiver 1 IF section to provide the bulk of the Receiver’s selectivity.
Receiver 2 Front-End operates identical to Receiver 1 Front-End.
Receiver 1 IF
The major contributor of the IF subsystem (U33) a complete 45 MHz superheterodyne receiver chip
incorporating a mixer/oscillator, two limiting intermediate frequency amplifiers, quadrature detector,
logarithmic received signal strength indicator (RSSI), voltage regulator and audio and RSSI op amps.
Incoming 45 MHz signals appearing at RX1_45MHz pass through the low-voltage high performance
monolithic FM IF system. Within U33, the signals pass through a simple LC filter and are boosted by the
RF amplifier. The output of the RF amplifier drives a mixer. A crystal oscillator is controlled by crystal Y4
and provides the injection frequency for the mixer. The mixer output passes through a 455 KHz ceramic
filter (FL6). It is then amplified and passed through another ceramic filter (FL5) to a second gain stage.
The IF output drives a quadrature detector. The phase shift elements for the detector are C123 and
FLT5. The RSSI detector converts the AGC voltage generated inside the chip into a DC level
corresponding logarithmically to the signal strength. The Diversity Reception Controller uses BRSSI1 to
select the receiver with the best quality signal.
The audio is amplified by an op amp (U19C) and delivered to the power and analog ground circuitry via
the RXMOD1 output. High frequency de-emphasis is provided by a filter consisting of a resistor and a
capacitor. In order to match the audio signal levels with the other circuitry, a gain control is included. A
pot (R81) is necessary to adjust gain.
Receiver 2 IF operates identical to Receiver 1 IF.
Transmit Modulation
The analog circuitry in this section modulates the Transmitter. The data-bearing audio signal from the
modem appears at TXMOD. The audio is amplified by op amp (U70D). The output of U70D drives two
(2) amplifiers (U70B and U70C).
The transmitter uses dual-point modulation meaning the modulation is applied both to the VCO as well as
the reference oscillator (VCTCXO).
The upper amplifier (U70B) has adjustable gain. The output drives op amp (U70A), which inverts the
phase of the signal. Upon the start of a transmission, the modulating signal passes through to the
VCTCXO reference oscillator in the synthesizer. Some makes of VCTCXO oscillators do not require the
modulation signal to be inverted and a jumper block (JMP4) is provided to accommodate the oscillators.
IP4HPVGPS-MRFCCRpt.doc Page 7
SECTION 1: THEORY OF OPERATION
The lower op amp (U70C) amplifies the signal from the low pass filter and applies it to the VCO via the
VCOMOD output. Pot RV1 and RV2 are used to adjust maximum deviation.
Injection Synthesizer
The dual synthesizer chip (U38) is the major contributor of the injection synthesizer. This device contains
the key components of a phase locked loop (PLL), including a prescaler, programmable divider, and
phase detector. The selected frequencies are loaded into U38 as a clocked serial bit stream via the PLL
DATA, PLL CLOCK and PLL ENABLE signals.
Frequency stability is determined by a temperature-compensated crystal oscillator module (VCTCXO)
(Y5) at a frequency stability of 1 PPM from –30C to +60C. This device has an input (REFMOD) that
accepts transmit modulation and voltage from a RX FREQ ADJUST pot. The pot allows the receiver to
be fine-tuned to the exact operating frequency.
Two (2) voltage control oscillators (VCO) are formed by integrated low-noise oscillators with buffered
outputs (U39 and U40) and associated circuitry. The VCO’s generate receiver and transmit injection
signals. The receiver control voltage is generated by the phase detector output (PDOUT) of U38 driving a
loop filter consisting of R111, R112, C185, C186, C42, R133, and C213. It integrates the pulses that
normally appear on PDOUT into a smooth DC control signal for U40. The output of U40 is split by U63
leading to outputs RXINJ1 and RXINJ2. A second output of U40 is returned to the synthesizer FIN input
via RXFB. This completes the loop signal path.
The transmitter control voltage is generated by the phase detector output (PDOUT-L) of U38 driving a
loop filter consisting of transmitter R135, R118, C195, C196, and C214. It integrates the pulses that
normally appear on PDOUT-L into a smooth DC control signal for U39. Upon transmit, the analog signal
from the modem and transmit processing circuitry is applied to the U39 tuning circuit at CR6. The output
of U39 is the TXINJ signal. A second output of U39 returns to the synthesizer F-IN input via TXFB.
Transmitter/TR Switch
The transmitter section consists of a driver amplifier (U36) and a final power amplifier (U35). To transmit,
5-volt power is applied to the KEYPWR line. PA12V line is also powered up. This causes power
amplifier (U35) to boost the RF power to the desired level. Up to 40 watts are available from the
transmitter. Harmonic suppression is provided by C233, L43, and L44.
Power and Analog Ground
These sections consist of the power supplies and transmit control circuitry. Power from the vehicle’s
battery appears at VBATT. Diode D1 protects the voltage regulators by clamping any transient spikes on
the supply line. Such spikes typically occur while the engine is started. The supply line powers a series
of voltage regulators and the transmitter control circuitry, as follows:
Voltage regulator U46 provides 8-volt power for most other sections in the radio.
Voltage regulator U21 powers the transmit driver and T/R switch diodes as controlled by the
microcontroller.
Voltage regulator VR2 provides a low noise 3.3-volt source for the radio electronics.
In the transmit control circuitry, to transmit, the microcontroller makes TXKEYOUT* high. Forcing the Pchannel device to conduct, applying 12-volts via PA12V to the transmitter power amplifier bias pins.
IP4HPVGPS-MRFCCRpt.doc Page 8
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