IP Mobilenet IPB800 Owners Manual

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Version Date: September 29, 2003

Document #: 516.80510.POM

Copyright 2003 IPMobileNet, Inc.

16842 Von Karman Avenue, Suite 200  Irvine, CA 92606

Voice: [phone]  Fax: [phone]

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Version: A

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The term “IC”: before the radio certification number only signifies that Industry of Canada
technical specifications were met.

Operation is subject to the following two (2) conditions: (1) this devise may not cause
interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of this device.

The following U.S. Patents apply to this product:

U.S. Patent numbers 5,640,695,6,018,647,6,243,393

Information contained in this document is subject to change without notice.

All rights reserved. Reproductions, adaptations, or translation without prior written permission is
prohibited, except as allowed under copyright laws.

369548.DOC Page ii

TABLE OF CONTENTS

SECTION 1: THEORY OF OPERATION .................................................................................................... 3

General Block Diagram.................................................................................................................. 3

General Block Diagram Definitions

Input/Output ........................................................................................................... 3

System Controller................................................................................................... 3

Modems
Diversity Reception

RX Injection............................................................................................................ 4

Transmitter ............................................................................................................. 4

Receiver 1/ 2/ 3...................................................................................................... 4

Power Supply......................................................................................................... 4

IP8B Base Station Section Descriptions ..................................................................................... 5

System Controller
Input/Output
Modem Switching
Modem
Receive Signal Strength Indication Comparator

Baseband ............................................................................................................................ 7

Receiver Board ................................................................................................................... 7

IF Amplifier

Receiver Injection................................................................................................................ 8

Exciter Board....................................................................................................................... 8

Analog Modulation

Phase Locked Loop ............................................................................................................ 9

Power Amplifier................................................................................................................. 10

SECTION 2: FACTORY TEST PROCEDURE .......................................................................................... 11

Equipment List ............................................................................................................................. 11

Programming and Configuring the Base Station ..................................................................... 12

Adjustment / Alignment Procedure............................................................................................ 13

Receiver Injection

Receiver............................................................................................................................ 13

Diversity Reception
Receive Data

Exciter ............................................................................................................................. 16

Power Amplifier

SECTION 3: FCC LABEL.......................................................................................................................... 17

IP8B Base Station FCC Label Placement .................................................................................. 17

IP8B Base Station FCC Label ..................................................................................................... 17

APPENDIX A: IP8B CIRCUIT BOARD DIAGRAM.................................................................................... 18

APPENDIX B: IP8B TEST DATA SHEET.................................................................................................. 22

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369548.DOC Page 2

SECTION 1: THEORY OF OPERATION

GENERAL BLOCK DIAGRAM

General Block Diagram Definitions

For increased data security, the modem supports the U.S. Government developed Digital Encryption

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Standard (DES) data encryption and decryption protocols. This capability requires installation of third­party IP compliant DES encryption and decryption software.

The standard IPSeries base station circuit board contains five (5) main sections defined below:

Input/Output Circuitry associated with one of the following base station’s data

connectors:

 RS232 Serial Port DB9 Data Connector

 RJ45 Ethernet 10 Base T Interface Connection

System Controller Houses the modem, diversity, and Ethernet circuitry. Manages the

operation of the base station’s modem providing transmit timeout
protection in the event a fault causes the base station to become
halted in the transmit mode. The system controller also handles the
loading of selected transmit and receive frequencies into the injection
synthesizer. Includes memory for storage through Electrically
Erasable Programmable Read Only Memory (EEPROM) of the base
station’s operating parameters, which are retained after the base
stations power is cycled off.

369548.DOC Page 3

SECTION 1: THEORY OF OPERATION

Modems Convert data into an analog audio waveform for transmission and

analog audio from the receiver to serial data interface. There is one
(1) modem that is dedicated to the transmit operation and two (2)
modems dedicated to the receive operation. The modem dedicated
to the transmit supports a 115.2 KBPS data transmission rate on the
serial port, SLIP protocol, and 19.2 KBPS and 32 KPBS over-the-air
data transmission rate. Provides Forward Error Correction (FEC)
and Error Detection (CRC), bit interleaving for more robust data
communications, and third generation collision detection and
correction capabilities.

Diversity Reception

RX Injection The Injection Synthesizer board provides a highly stable local

Transmitter Consists of an exciter and a power amplifier module covering various

Receiver 1/Receiver 2/ Uses three (3) discrete receivers tuned to the same frequency.
Receiver 3 The three (3) receivers are required to support IPMobileNet’s base

NOTE

The receivers are double-conversion superhetrodynes with an

Power Supply Power supply circuitry derives the various operating voltages

Circuitry selects one of three (3) diversity receiver audio outputs for

processing by the modem by comparing the Received Signal
Strength Indication (RSSI) output from each receiver. Audio from the
receiver with the highest RSSI value is passed to the modems.

oscillator signal for the three (3) receivers. This displays a serial
data input/output interface, synthesizer, and VCO.

frequency bands in segments. A different power amplifier module is
required for each segment. The transmitter power control is included
with the power supply circuitry on the same board.

station Diversity Reception System (DRS).

: Some installations use only two (2) receivers.

Intermediate Frequency (IF) of 45 MHz. Each receiver consist of
bandpass filters, RF amplifiers, a mixer, 45 MHz crystal filter, and a
one-chip IF system. The injection synthesizer provides the first local
oscillator signal and outputs from each receiver including RSSI and
analog audio for Diversity Reception.

required by the base station. Fixed voltage regulators are employed
through the base station for this purpose.

369548.DOC Page 4

SECTION 1: THEORY OF OPERATION

IP8B Base Station Section Descriptions

System Controller

This section displays the Central Processing Unit (CPU)(U1), clock, and power-on reset circuitry. It
provides more processing power than required for future capabilities to be incorporated without changing
processors. Such capabilities include data encryption/decryption (DES) and remote fault monitoring. U1
features a 16-bit address bus and 128K of internal flash random access memory (RAM).

NOTE

: To enter the programming mode it is necessary to reset the switch (S1) and power up again.

CPU operations are controlled by Y3 an 18.432 MHz clock module. Capacitor (C1) and an internal
Schmidt trigger circuit inside of U1 generates the power on reset signal. The RESET* output from U1
drives a latch and decoder found elsewhere on the board.

This section displays the RAM, decoder, EEPROM, and programming power supply circuitry. U2 is a
512K x 8 bit static RAM chip, which provides temporary storage of base station configuration data while
the power is on. This is necessary in order to program the base station. U2 is controlled directly by the
address, data, and control busses from the CPU.

Chip U5 decodes the A11-A14 address bus to provide chip selects for the modem and EEPROM
memory. Chip U6 is an 8-bit latch. It latches inputs from the D0-D7 bus and lights the front panel status
indicators (

Chip U3 is a serial EEPROM, which provides 2K bits of pre-programmed data storage for the CPU. Data
is clocked out of U3 by EECLK, and back into the CPU via EEDATA.

A programming power supply is required for the flash RAM inside of the CPU, and this function is
performed by U4. This chip is a low dropout voltage regulator with a shutdown control. Resistors R22
and R21 set the output voltage. When the base station configuration data is to be stored in flash RAM,
the CPU makes VPP_ENABLE high. This turns on the regulator, producing a 12-volt output via VPP for
the flash RAM.

This section displays a dedicated processor and voltage regulator. Chip U7 is a processor, which permits
manual keyboard operation of the base station. Regulator VR2 provides 5 volts DC power for all logic
circuitry on the System Controller Board.

Input/Output

This section displays the CPU input/output circuitry. Chip U8 is an RS232 transceiver, which interfaces
the CPU to the modem via J1. From there, the RS232 data goes directly to a rear panel DB9 connector.
U8 converts 5-volt logic-level data to +/-12 volt data in RS232C form, and vice-versa. A charge pump
power supply on the chip converts the +5 volt DC power to the +/-12 volt levels required. The charge
pump uses capacitors (C28 to C31) to generate voltages.

NOTE

Modem Switching

This section displays the connector wiring and modem switching circuitry. Connector J7 is routed to the
front-panel TX, CD, and RX1-RX3 LED indicators. The base station will also accept modulation from an
external source (modem or amplified microphone audio). Transmission gate U10A switches this signal
source.

TX, CD, RX1, RX2, and RX3).

: The RS232 serial port data transmission rate of the base station is 115.2 KBPS.

(refer to schematic on page 26)

(refer to schematic on page 30)

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SECTION 1: THEORY OF OPERATION

Modem (refer to schematic on page 29)

This base station uses separate modems for receive and transmit functions so that full-duplex operation
may be obtained. The A0-A1 address bus in addition to the individual read (RD*), write (WR*), and chip
select (MODEMTXCS*) lines control all three (3) modems. Modem operations are timed by Y2, a 4.9152
MHz clock module.

Modem chip U14 is dedicated to the transmit operation. Data from the D0-D7 bus is read by the chip,
and then converted to a 4-level FSK analog signal, which appears on the TXOUT pin. Op amp U21B
buffers the signal, which becomes the MODEM_TXMOD output. From this point, the signal is routed to
the modulation circuitry on the Exciter Board.

Chip U14 has the ability to demodulate receiver audio, although this capability is not used in most
systems. Incoming data-bearing audio from the Diversity Reception circuitry (and selected receiver)
appears at DISC_AUDIO. The signal passes through resistor R54 and into the modem chip. Resistor
R52 and capacitor C41 serve as feedback elements, limiting both the gain and bandwidth of an amplifier
within U14. The modem chip demodulates the audio into 8-bits of data, which exit U14 on the D0-D7 bus.

Chip U14 also provides a bias voltage for the analog circuitry on the Exciter Board. This voltage is about

2.5 volts DC, and it appears on the VBIAS line. The purpose of VBIAS is to bias the Exciter Board analog
circuitry for proper operation. Please note that if this voltage is low or missing, the Exciter Board circuitry
may not work.

Modem chip U15 is dedicated to the receive operation. Incoming data-bearing audio from the Diversity
Reception circuitry (and selected receiver) appears at DISC_ AUDIO. The signal passes through resistor
R56 and into the modem chip. Resistor R55 and capacitor C46 serve as feedback elements, limiting both
the gain and bandwidth of an amplifier within U15. The modem chip breaks down the audio into 8 bits of
data, which exit U15 on the D0-D7 bus.

Modem chip U16 is also dedicated to the receive operation, although it may not be used in this
application. The operation of U16 is exactly the same as U15.

Receive Signal Strength Indication Comparator

This section displays the RSSI comparator circuitry. A series of comparators (U20BCD) simultaneous
compare RSSI1 to RSSI2, RSSI2 to RSSI3, and RSSI1 to RSSI3. Within this process eight (8) possible
results are then forwarded by the comparators to a series of NAND gates (U18ABC), which reduce the
number of results to three (3) and translates the results for an analog multiplexer (U19A). To determine
which of the three (3) results is the strongest, the following needs to occur:

 For Receiver 1 to be selected as the strongest signal, both input pins on the NAND gate (U18D) must

go high (driving pin 7 of U19A). If Receiver 1 has the strongest signal, a light emitting diode
(LED)(D1) lights indicating Receiver 1 was selected.

 For Receiver 2 to be selected as the strongest signal, the inverter (U17B) must go high (driving pin 6

of U19A). If Receiver 2 has the strongest signal, D2 lights indicating Receiver 2 was selected.

 For Receiver 3 to be selected the strongest signal, the inverter (U17C) must go high (driving pin 5 of

U19A). If Receiver 3 has the strongest signal, D3 lights indicating Receiver 3 was selected.

SEL_RSSI is the output selected with the strongest signal. When RSSI voltage exceeds a threshold,
another LED (D4) lights. As the other three (3) LEDs, this circuit is intended as a diagnostic tool. It
provides a go/no go indication that an RF signal has been received. A pot (R74) sets the turn-on voltage.

(refer to schematic on pages 32 & 33)

369548.DOC Page 6

SECTION 1: THEORY OF OPERATION

Baseband (refer to schematic on page 34)

This circuitry amplifies the audio from each receiver, routes it through a RF multiplexer, and selects the
audio from the receiver with the highest RSSI value. The comparator circuit on the previous sheet
controls it.

There are three (3) channels of audio, with separate gain and DC offset adjustments to compensate for
performance differences in the receivers. For example, incoming audio from receiver 1 appears at
AUDIO 1. An op amp (U12D) is then amplifies the audio. A pot (R72) adjusts the gain, while another pot
(R57) adjusts the DC offset on the output. The amplifier output passes through a RF multiplexer (U19B),
then drives a low pass filter (U9) through another op amp (U12A) and through the AUDIO_OUT line,
which goes to a switch (S3) and to pin 4 of a connector (J3).

The remaining audio circuits work in the same manner.

The output from U19B also appears on DISC_AUDIO, which goes to the CPU (U1) and from there the
audio is demodulated by the modems.

Receiver Board

Please be aware that the base station uses three (3) identical receiver boards. As a result, the circuitry

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Front end. Incoming signals pass through a bandpass filter (FLT1). The desired signals are amplified by

U4 and additional selectivity is provided by a SAW filter (FLT2). The signal passes through an IC mixer
(U5) and the output passes through two (2) crystal filters (FLT3 and FLT4).

IF Amplifier

The incoming 45 MHz signal passes through C15, C17, and R12 which provides impedance matching to
the IF amplifier input. U2 is a super heterodyne IF subsystem. Inside the chip, the signal is applied to a
mixer. The mixer also accepts a 44.545 MHz local oscillator input. The local oscillator consists of an
internal amplifier, plus crystal (Y1) and associated components. The mixer output passes through Y4, a
455 KHz ceramic IF filter. It is amplified, passed through another 455 KHz ceramic filter (Y3), and on to a
second IF stage. The IF output drives a quadrature detector. The phase shift elements for the detector
are C8 and Y5. The recovered audio appears at pin 9, while RSSI appears at pin 7.

Within the RSSI circuitry, chip U2 uses a detector, which converts the AGC voltage generated inside the
chip into a DC level corresponding logarithmically to signal strength. RSSI is used by Diversity Reception
on the System Controller to select the receiver with the highest quality signal.

A filter consisting of a resistor (R8) and a capacitor (C18) provides high frequency de-emphasis for the
audio. The audio is buffered by op amp U1A. From there the AUDIO output line goes to a connector, for
hookup to Diversity Reception on the System Controller Board.

Resistor (R9) and capacitor (C10) provides RF filtering for the DC RSSI voltage. The RSSI is buffered by
op amp U1B. From there the RSSI output line goes to a connector, for hookup to Diversity Reception on
the System Controller Board.

Several sets of 455 KHz IF filters (Y4 and Y3) are available to suit receiver selectivity requirements.

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(refer to schematic on page 44)

will be described only once.

(refer to schematic on page 45)

Should replacement of these filters be required, exact replacement parts must be used.

369548.DOC Page 7