IP Mobilenet ECSDR4BSTX User Manual
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Owner’s Manual
Date Prepared:
March 1, 2000
16842 Von Karman Avenue, Suite 200 Irvine, CA 92606
Voice: (949) 417-4590 Fax: (949) 417-4591
Document Control #: DC-95
Version: C-1 (Special Release)
Copyright 2000-2002 IP MobileNet, Inc.
TABLE OF CONTENTS
SECTION 1: THEORY OF OPERATION .................................................................................. 3
General Block Diagram ........................................................................................................... 3
General Block Diagram Definitions
DR4B Base Station Data Radio Circuitry
System Controller ................................................................................................ 5
Input/Output ......................................................................................................... 5
Modem Switching................................................................................................. 6
Modem .................................................................................................................6
Diversity Reception Controller .............................................................................6
Receive Signal Strength Indication Comparator .................................................. 7
Baseband............................................................................................................. 8
Receiver Board .................................................................................................... 8
IF Amplifier........................................................................................................... 9
Receiver Injection ................................................................................................ 9
Exciter ................................................................................................................10
Analog Modulation ............................................................................................. 10
Phase Locked Loop ........................................................................................... 11
Power Amplifier.................................................................................................. 11
SECTION 2: FACTORY TEST PROCEDURE ........................................................................12
Equipment List ........................................................................................................... 12
Programming and Configuring the Base Station Data Radio ................................ 13
Adjustment / Alignment Procedure .......................................................................... 14
Receiver Injection
Receiver 1
........................................................................................................ 14
............................................................................................. 14
Diversity Reception Controller
Receive Data
Exciter
............................................................................................................ 16
Power Amplifier
.................................................................................................... 15
................................................................................................ 16
SECTION 3: FCC LABEL ....................................................................................................... 17
DR4B Base Station Data Radio FCC Label Placement ........................................... 17
DR4B Base Station Data Radio FCC Label .............................................................. 17
APPENDIX A: DR4B BASE STATION DATA RADIO CIRCUIT BOARD DIAGRAM ............ 18
................................................................................ 3
....................................................................... 5
.......................................................................... 14
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SECTION 1: THEORY OF OPERATION
General Block Diagram
General Block Diagram Definitions
For increased data security, the modem supports the U.S. Government developed Digital Encryption
Standard (DES) data encryption and decryption protocols.
The standard Base Station Data Radio circuit board contains eight (8) sections defined below:
Input/Output Circuitry associated with the base station’s DB25 data connector
System Controller Manages the operation of the base station loading selected transmit/
Includes memory for storage of base station operating parameters.
Transmit Processing Circuitry, which amplifies the analog audio signal from the modem
providing all of the RS232 data and handshake functions, including
the necessary RS232 to logic level changes.
receive frequencies into the injection synthesizer, controls the
operation of the modem and provides transmit timeout protection in
the event a fault causes the radio to become stuck in the transmit
mode.
Electrically erasable programmable read only memory (EEPROM) is
used to store parameters entered by the technician such as channel
numbers and RX/TX frequencies. This information is retained after
power is removed from the base station.
and uses it to modulate a voltage-controlled oscillator (VCO) and
reference oscillator in the transmitter synthesizer section.
Modulating the VCO and reference oscillator simultaneously results
in a higher quality FM signal.
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SECTION 1: THEORY OF OPERATION
Modem Converts parallel data into an analog audio waveform for
transmission and analog audio from the receiver to serial data.
Serial data appears on the base station’s DB25 serial port.
The radio supports a 115.2 KBPS data transmission rate on the
serial port, SLIP protocol, and a 19.2 KBPS OR 9.6 KBPS over-theair data transmission rate.
Within a single chip the modem provides forward error correction and
detection, bit interleaving for more robust data communications, and
third generation collision detection and correction capabilities.
Synthesizers Provides ultra stable signals for the three (3) receivers and the
transmitter. Two (2) independent synthesizers are used in the base
station to obtain full duplex (simultaneous receive and transmit)
operations. Both synthesizers incorporate phase lock loop (PLL)
technology and use separate reference oscillators.
RX Synthesizer The receive synthesizer provides a local oscillator signal 45 MHz
above or below the desired receive channel frequency. This is called
high side injection or low side injection.
TX Synthesizer The transmit synthesizer produces the desired frequency by
controlling a VCO. The VCO and the reference oscillator are both
frequency modulated by the modem output.
Diversity Reception Controller Circuitry selects one of three diversity receiver audio outputs for
processing by the modem by comparing the Received Signal
Strength Indication (RSSI) output from each receiver. Essentially,
audio from the receiver with the highest RSSI value is passed on to
the modem.
Transmitter Consists of an exciter and a power amplifier module covering various
frequency bands in segments. A different power amplifier module is
required for each segment. The transmitter power control is included
with the power supply circuitry on the same board.
Receiver 1/Receiver 2/ Uses three (3) discrete receivers tuned to the same frequency.
Receiver 3 The three (3) receivers are required to support IPMN’s base station
DRS.
NOTE
The receivers are double-conversion superhetrodynes with an
Power Supply Power supply circuitry derives the various operating voltages
: Some installations use only two (2) receivers.
Intermediate Frequency (IF) of 45 MHz. Each receiver consist of
bandpass filters, RF amplifiers, a mixer, 45 MHz crystal filter, and a
one-chip IF system. The injection synthesizer provides the first local
oscillator signal and outputs from each receiver including RSSI and
analog audio for the diversity reception controller.
required by the base station. Fixed voltage regulators are employed
through the radio for this purpose.
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SECTION 1: THEORY OF OPERATION
DR4B Base Station Data Radio Circuitry
The DR4B Base Station Data Radio works within the frequency range of 400-512 MHz.
The following section provides detail views, descriptions, and key areas on the DR4B Base Station Data
Radio circuit board especially useful during troubleshooting.
System Controller
This section displays the Central Processing Unit (CPU)(U1), clock, and power-on reset circuitry. It
provides more processing power than required for future capabilities to be incorporated into the radio
without changing processors. Such capabilities include data encryption/decryption (DES), remote fault
monitoring, etc. U1 features a 16-bit address bus and 128K of internal flash random access memory
(RAM). To enter the programming mode it is necessary to reset the switch (S1) and power up again.
CPU operations are controlled by Y2 an 4.9152 MHz clock module. Capacitor (C1) and an internal
Schmidt trigger circuit inside of U1 generates the power on reset signal. The RESET* output from U1
drives a latch and decoder found elsewhere on the board.
This section displays the RAM, decoder, EEPROM, and programming power supply circuitry. U2 is a
512K x 8 bit static RAM chip, which provides temporary storage of radio configuration data while the
power is on. This is necessary in order to program the radio configuration. U2 is controlled directly by the
address, data, and control busses from the CPU.
Chip U5 decodes the A11-A14 address bus to provide chip selects for the modem and EEPROM
memory. Chip U6 is an 8-bit latch. It latches inputs from the D0-D7 bus and lights the front panel status
indicators (
Chip U3 is a serial EEPROM, which provides 2K bits of pre-programmed data storage for the CPU. Data
is clocked out of U3 by EECLK, and back into the CPU via EEDATA.
A programming power supply is required for the flash RAM inside of the CPU, and this function is
performed by U4. This chip is an adjustable voltage regulator with a shutdown control. Resistors R8 and
R9 set the output voltage. When the radio configuration data is to be stored in flash RAM, the CPU
makes VPP_ENABLE high. This turns on the regulator, producing a 12-volt output via VPP for the flash
RAM.
This section displays a dedicated processor and voltage regulator. Chip U7 is an optional processor,
which permits manual keyboard operation of the radio. It is not used, and may not be installed on the
board. Regulator U10 provides 5 volts DC power for all logic circuitry on the System Controller Board.
Input/Output
This section displays the CPU input/output circuitry. Chip U11 is an RS232 transmitter/receiver, which
interfaces the CPU to the Diversity Reception Board via J6. From there, the RS232 data goes directly to
a rear panel DB25 connector. U11 converts 5-volt logic-level data to +/-12 volt data in RS232C form, and
vice-versa. A charge pump power supply on the chip converts the +5 volt DC power to the +/-12 volt
levels required. The charge pump uses capacitors (C28 to C31) to generate voltages.
The RS232 serial port data transmission rate of the base station is 115.2 KBPS.
TX, CD, RX1, RX2, and RX3).
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SECTION 1: THEORY OF OPERATION
Modem Switching
This section displays the connector wiring and modem switching circuitry. Connector J2 is routed to the
front-panel TX, CD, and RX1-RX3 LED indicators. The radio will also accept modulation from an external
source (modem or amplified microphone audio).
Modem
This base station uses separate modems for receive and transmit functions so that full-duplex operation
may be obtained. The A0-A1 address bus in addition to the individual read (RD*), write (WR*), and chip
select (MODEMTXCS*) lines control all three (3) modems. Modem operations are timed by Y2, a 4.9152
MHZ clock module.
Modem chip U14 is dedicated to the transmit operation. Data from the D0-D7 bus is read by the chip,
and then converted to a 4-level FSK analog signal, which appears on the TXOUT pin. Op amp U21B
buffers the signal, which becomes the MODEM_TXMOD output. From this point, the signal is routed to
the modulation circuitry on the Exciter Board.
Chip U14 has the ability to demodulate receiver audio, although this capability is not used in most
systems. Incoming data-bearing audio from the Diversity Reception Controller Board (and selected
receiver) appears at DISC_AUDIO. The signal passes through resistor R54 and into the modem chip.
Resistor R52 and capacitor C41 serve as feedback elements, limiting both the gain and bandwidth of an
amplifier within U14. The modem chip demodulates the audio into 8 bits of data, which exit U14 on the
D0-D7 bus.
Chip U14 also provides a bias voltage for the analog circuitry on the Exciter Board. This voltage is about
2.5 volts DC, and it appears on the VBIAS line. The purpose of VBIAS is to bias the Exciter Board analog
circuitry for proper operation. Please note that if this voltage is low or missing, the Exciter Board circuitry
may not work.
Modem chip U15 is dedicated to the receive operation. Incoming data-bearing audio from the Diversity
Reception Controller Board (and selected receiver) appears at DISC_ AUDIO. The signal passes through
resistor R56 and into the modem chip. Resistor R55 and capacitor C46 serve as feedback elements,
limiting both the gain and bandwidth of an amplifier within U15. The modem chip breaks down the audio
into 8 bits of data, which exit U15 on the D0-D7 bus.
Modem chip U16 is also dedicated to the receive operation, although it may not be used in this
application. The operation of U16 is exactly the same as U15.
Diversity Reception Controller Board
This section displays the power supply circuitry and input/output connector wiring. The power supply
consists of a diode (CR1), metal oxide varistor (MOV) (CR2), a fuse (F1), and voltage regulators (VR2
and VR3). 13.8 volts DC from the radio’s power connector appears on the anode of CR1. CR1 provides
reverse polarity protection, while CR2 absorbs any damaging transient spikes, which appear on the
unregulated supply line. F1 provides over-current protection. The SWB+ output powers the remaining
boards in the radio, with the exception of the power amplifier module. VR2 provides a 5-volt DC source
for all of the circuitry on the Diversity Reception Controller Board. VR3 provides 5 volts DC for the three
receiver boards via a connector (TB1).
Two (2) 16-pin DIP headers connect this board to the System Controller Board. One header (J2)
provides power and control signals for the System Controller Board. The ALARMA and ALARMC lines
are of particular interest because the base station has optional external fault monitoring capabilities. For
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