IOR IRS2453DS-PbF User Manual
Data Sheet No. PD60259
IRS2453D(S)PbF
SELF-OSCILLATING FULL-BRIDGE DRIVER IC
Features
CT, RT programmable oscillator
Logic level latched shutdown pin
Non-latched shutdown on CT pin (1/6th V
Description
The IRS2453D is based on the popular IR2153 self-oscillating
half-bridge gate driver IC, and incorporates a high voltage fullbridge gate driver with a front end oscillator similar to the
industry standard CMOS 555 timer. HVIC and latch immune
CMOS technologies enable ruggedized monolithic construction.
The output driver features a high pulse current buffer stage
designed for minimum driver cross-conduction. Noise immunity
is achieved with low di/dt peak of the gate drivers, and with a
undervoltage lockout hysteresis greater than 1.5 V. The
IRS2453D also includes latched and non-latched shutdown pins.
Typical Connection Diagram
Integrated 600 V full-bridge gate driver
15.6V Zener clamp on
Micropower startup
+ AC rectified line
V
CC
)
CC
Internal bootstrap FETs
Excellent latch immunity on all inputs & outputs
ESD protection on all pins
14-lead SOIC or PDIP package
1.0 µs (typ.) internal deadtime
Packages
14 Lead PDIP 14 Lead SOIC (Narrow Body)
IRS2453DPbF IRS2453DSPbF
15 V
VCC
1
COM
2
VB1
HO1
14
13
D
CT
3
RT
4
SD
5
LO1
6
LO2
7
- AC rectified line
3
5
4
2
S
R
I
VS1
NC
VB2
HO2
VS2
12
11
10
9
8
LOAD
1
IRS2453DPbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power
dissipation ratings are measured under board mounted and still air conditions.
Parameter
Symbol Definition Min. Max. Units
V
V
V
V
dVS/dt
B1, VB2
S1, VS2
, V
HO1
, V
LO1
High side floating supply voltage -0.3 625
High side floating supply offset voltage
High side floating output voltage
HO2
Low side output voltage -0.3
LO2
VRT RT pin voltage
VCT CT pin voltage
VSD
SD pin voltage -0.3
IRT RT pin current
ICC
Supply current (Note 1) --- 25
Allowable offset voltage slew rate -50 50 V/ns
PD
PD
R
R
TS
θJA
θJA
TJ
TL
Maximum power dissipation @ T
Maximum power dissipation @ T
Thermal resistance, junction to ambient, 8-Pin DIP --- 125
Thermal resistance, junction to ambient, 8-Pin SOIC --- 200
≤ +25 ºC, 8-Pin DIP
A
≤ +25 ºC, 8-Pin SOIC
A
Junction temperature -55 150
Storage temperature -55 150
Lead temperature (soldering, 10 seconds) --- 300
VB - 25 VB + 0.3
V
- 0.3 VB + 0.3
S
V
+ 0.3
CC
-0.3
-0.3
VCC + 0.3
VCC + 0.3
VCC + 0.3
-5 5
--- 1.0
--- 0.625
V
mA
W
ºC/W
ºC
Note 1:
This IC contains a zener clamp structure between the chip V
and COM which has a nominal
CC
breakdown voltage of 15.6 V. Please note that this supply pin should not be driven by a DC, low
impedance power source greater than the V
specified in the Electrical Characteristics section.
CLAMP
2
IRS2453DPbF
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Parameter
Symbol Definition Min. Max. Units
V
BS1, VBS2
VS1, VS2
VCC
Note 2:
Note 3:
Recommended Component Values
Symbol Component Min. Max. Units
RT
CT CT pin capacitor value
High side floating supply voltage
Steady state high side floating supply offset voltage -3.0 (Note 2) 600
Supply voltage V
ICC
TJ
Supply current (Note 3) 5 mA
Junction temperature -25 125 ºC
Care should be taken to avoid output switching conditions where the V
ground by more than 5 V.
Enough current should be supplied to the
pin of the IC to keep the internal 15.6 V zener diode
V
CC
clamping the voltage at this pin.
Parameter
Timing resistor value 1
VBIAS (V
CC, VBS) = 14 V, VS=0 V and TA = 25 °C, CLO1=CLO2 = CHO1=CHO2 = 1 nF.
V
- 0.7 V
CC
CCUV+
node flies inductively below
S
V
---
CLAMP
CLAMP
kΩ
330 --- pF
V
1000000
100000
10000
Frequency (Hz)
IRS2453 D Fre quenc y vs. RT
1000
100
10
1000 10000 100000 1000000
RT (O h m)
CT Values
330pf
470pF
1nF
2.2nF
4.7nF
10nF
3
IRS2453DPbF
Electrical Characteristics
V
(VCC, VBS) = 14 V, CT = 1 nF and TA = 25 °C unless otherwise specified. The VO and IO parameters are referenced to COM and are
BIAS
applicable to the respective output leads: HO or LO. CLO1=CLO2=CHO1=CHO2=1 nF.
Symbol Definition Min Typ Max Units
Low Voltage Supply Characteristics
V
Rising VCC undervoltage lockout threshold 10.0 11.0 12.0
+
CCUV
V
Falling VCC undervoltage lockout threshold 8.0 9.0 10.0
-
CCUV
V
CCUVHYS
I
QCCUV
VCC undervoltage lockout hysteresis 1.5 2.0 2.4
Micropower startup V
supply current --- 140 200 µA
CC
IQCC Quiescent VCC supply current --- 1.3 2.0
I
VCC supply current at f
CC_20K
I
VCC supply current when SD > VSD --- 360 500 µA
CCFLT
V
VCC Zener clamp voltage 14.6 15.6 16.6 V ICC = 5 mA
CLAMP
(RT = 36.5 kΩ) --- 3.0 3.5
osc
Floating Supply Characteristics
I
QBS1UV,
I
QBS2UV
I
QBS1,
I
QBS2
V
BS1UV+,
V
BS2UV+
V
BS1UV-,
V
BS2UV-,
I
LK1, ILK2
Micropower startup V
supply current
BS
--- 3 10
Quiescent V
supply current
BS
--- 30 100
supply undervoltage positive going
V
BS
threshold
supply undervoltage negative going
V
BS
threshold
Offset supply leakage current --- --- 50
8.0 9.0 10.0
7.0 8.0 9.0
V
mA
µA
V
µA
Test Conditions
V
≤ V
CC
V
≤ V
CC
V
CC
VB = VS = 600 V
CCUV-
CCUV-
= VBS
,
Oscillator I/O Characteristics
f
OSC
Oscillator frequency
19.6
88
20.2 20.8
94 100
d RT pin duty cycle 48 50 52 %
ICT CT pin current --- 0.05 1.0
I
UV-mode CT pin pulldown current 1 5 --- mA
CTUV
V
Upper CT ramp voltage threshold --- 9.3 ---
CT+
V
Lower CT ramp voltage threshold --- 4.7 ---
CT-
V
High level RT output voltage, VCC - VRT
RT+
V
Low level RT output voltage
RT-
V
UV-mode RT output voltage
RTUV
--- 10 50 I
--- 100 300 I
--- 10 50 I
--- 100 300 I
--- 0 100
kHz
µA
V
mV
R
= 36.5 kΩ
T
R
= 7.15 kΩ
T
fo < 100 kHz
VCC = 7 V
RT = 100 µA
RT = 1 mA
RT = 100 µA
RT = 1 mA
V
≤ V
CC
CCUV-
4
IRS2453DPbF
Electrical Characteristics
V
(VCC, VBS) = 14 V, CT = 1 nF and TA = 25 °C unless otherwise specified. The VO and IO parameters are referenced to COM and are
BIAS
applicable to the respective output leads: HO or LO. CLO1=CLO2=CHO1=CHO2=1 nF.
Symbol Definition Min Typ Max Units
Gate Driver Output Characteristics
VOH High level output voltage, V
VOL Low level output voltage, VO
V
UV-mode output voltage, VO
OL_UV
tr
tf
tsd
td
Output rise time --- 120 200
Output fall time --- 50 100
Shutdown propagation delay --- 250 ---
Output deadtime (HO or LO) 0.8 1.0 1.40
BIAS
- VO
--- V
---
CC
--- COM ---
--- COM ---
V
ns
µs
Test Conditions
≤ V
,
CCUV-
I
V
CC
I
O = 0 A
O = 0 A
IO+ Output source current --- 180 ---
IO- Output sink current --- 260 ---
Shutdown
VSD
V
CTSD
Shutdown threshold at SD pin (latched)
CT voltage shutdown threshold (non latched)
1.8 2.0 2.3
2.2 2.3 2.5
--- 10 50
V
SD mode RT output voltage, VCC - VRT
RTSD
--- 100 300
Bootstrap FET Characteristics
V
B1_ON
V
B2_ON
I
B1_CAP
I
B2_CAP
I
B1_10 V
I
B2_10 V
VB when the bootstrap FET is on 13.7 14.0 --- V
VB source current when FET is on 40 55 --- C
VB source current when FET is on 10 12 ---
mA
V
mV
mA
I
RT = 100 µA,
VCT = 0 V
I
RT = 1 mA,
VCT = 0 V
=0.1 µF
BS
VB=10 V
5
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