IOR IRS2166DS-PbF User Manual

Data Sheet No. PD60292

IRS2166D(S)PbF

PFC + BALLAST CONTROL IC

Features

 PFC, ballast control and 600 V half-bridge driver in one IC

Critical-conduction mode boost-type PFC

  Programmable half-bridge over-current protection  Programmable preheat frequency  Programmable deadtime

 Programmable preheat time  Programmable run frequency  RoHS compliant

Description

The IRS2166D is a fully integrated, fully protected 600 V ballast control IC designed to drive all types of fluorescent lamps. The IRS2166D is based on the popular IR2166 control IC with additional improvements to increase ballast performance. PFC circuitry operates in critical conduction mode and provides high PF, low THD, and DC bus regulation. The IRS2166D features include programmable preheat and run frequencies, programmable preheat time, and programmable end-of-life protection. Comprehensive

 End-of-life window comparator pin  Internal up/down current-sense fault counter  DC bus undervoltage reset  Lamp removal/auto-restart shutdown pin  Internal bootstrap MOSFET  Internal 15.6 V zener clamp diode on V  Micropower startup (250 µA)  Latch immunity and ESD protection

System Features

 Improved V  Increased SD pin shutdown voltage threshold hysteresis  Changed EOL pin internal 2.0 V bias to a +/-10 µA OTA  Internal bootstrap MOSFET

regulation voltage tolerance

BUS

Packages

protection features such as protection from failure of a lamp to strike, filament failures, end-of-life protection, DC bus undervoltage reset as well as an automatic restart function, have been included in the design.

16-Lead PDIP 16-Lead SOIC IRS2166DPbF IRS2166DSPbF

Application Diagram (Typical Only)

CC

LPFC

L

N

GND

F1

RV1

L1

C1

BR1

CY

C2

Note: Thick traces represent high-frequency, high-current paths. Lead lengths should be minimized and power and IC grounds should be separated to avoid high-frequency noise problems.

MPFC

RPFC

DPFC

CBUS

RBUS

RVDC

CVDC

VBUS

1

CPH

2

RT

DCOMP

RPH

CCOMP

RZX

RPH

COMP

PFC

3

4

CT

5

6

ZX

7

8

RT

CT

HO

16

IRS2166D

VS

15

VB

14

VCC

13

CVCC1

COM

12

LO

11

CS

10

SD/EOL

9

IC BALLAST

CCS

CBOOT

DSD

CSD1

CVCC2

CSD2

RH O

RL O

RLIM

RSUPPLY

MHS

CSNUB

DCP2

ML S

RPU

RSD

RCS

DCP1

LRES

CEOL

CDC

RDC

REOL1

REOL2

REOL3

REOL4

CRES

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IRS2166D(S)PbF

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.

Symbol Definition Min. Max. Units

VB High-side floating supply voltage -0.3 625 VS High-side floating supply offset voltage VB – 25 VB + 0.3

mA

ºC/W

CLAMP

V

W

ºC

V

VHO High-side floating output voltage VS - 0.3 VB + 0.3

VLO Low-side output voltage -0.3 VCC + 0.3

V

PFC gate driver output voltage -0.3 VCC + 0.3

PFC

I

O,MAX

V

Maximum allowable output current (HO, LO, PFC) due to external power transistor miller effect

VBUS pin voltage -0.3 VCC + 0.3

BUS

CPH pin voltage -0.3 VCC + 0.3

CPH

-500 500 mA

VRT RT pin voltage -0.3 VCC + 0.3

V

RPH pin voltage -0.3 VCC + 0.3

RPH

IRT RT pin current -5 5

I

RPH pin current -5 5

RPH

VCT CT pin voltage -0.3 VCC + 0.3 V

I

COM pin current -5 5

COMP

IZX ZX pin current -5 5

ICC VCC pin current (see Note 1) -25 25

V

SD/EOL pin voltage -0.3 VCC + 0.3 V

SD/EOL

I

SD/EOL pin current -5 5 mA

SD/EOL

VCS CS pin voltage -0.3 VCC + 0.3 V

ICS CS pin current -5 5 mA

dV/dt Allowable VS offset voltage slew rate -50 50 V/ns

PD

R

Package power dissipation @ T

)/R

PD = (T

JMAX-TA

Thermal resistance, junction to ambient

ΘJA

θJA

≤ +25 ºC

A

(16-Pin DIP) --- 1.8

(16-Pin SOIC) --- 1.4

(16-Pin DIP) --- 70

(16-Pin SOIC) --- 82

TJ Junction temperature -55 150

TS Storage temperature -55 150

TL Lead temperature (soldering, 10 seconds) --- 300

Note 1: This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6 V. This supply pin should not be driven by a DC, low impedance power source greater than the V specified in the electrical characteristics section.

Recommended Operating Conditions

For proper operation the device should be used within the recommended conditions.

Symbol Definition Min. Max. Units

VB-VS High side floating supply voltage V

VS Steady state high-side floating supply offset voltage -1 600

VCC Supply voltage V

ICC V

supply current (see Note 2) Note 2 20 mA

CC

CT CT pin capacitance 220 --- pF

I

SD/EOL pin current

SD/EOL

ICS CS pin current

IZX ZX pin current

TJ Junction temperature -25 125 ºC

Note 2: Enough current should be supplied into the VCC pin to keep the internal 15.6 V zener clamp diode on this pin regulating its voltage, V

CLAMP

.

V

BSUV+

V

CCUV+

CLAMP

-1 1 mA

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IRS2166D(S)PbF

Electrical Characteristics

VCC = VBS = V 1000 pF, C

Symbol Definition Min Typ Max Units Test Conditions

Supply Characteristics

V

CCUV+

V

CCUV-

V

UVHYS

I

UVLO mode VCC quiescent current --- 250 500 µA VCC = 8 V, CT = COM

QCCUV

I

Quiescent VCC supply current --- 4.3 5.1 mA CT = COM

QCC

I

QCCFLT

I

VCC current at RUN frequency --- 5.0 --- mA

CC,RUN

V

CLAMP

Floating Supply Characteristics

I

Quiescent VBS supply current --- 30 70 VHO = VS

QBS0

I

Quiescent VBS supply current --- 50 90

QBS1

V

BSUV+

V

BSUV-

I

VS offset supply leakage current --- --- 50 µA VB = VS = HO = 600 V

LKVS

PFC Error Amplifier Characteristics

I

COMP,SOURCE

I

COMP,SINK

V

COMPOH

V

COMPOL

PFC Control Characteristics

V

VBUSREG

V

VBUSOV+

V

VBUSOV-

VZX

=14 V +/- 0.25 V, V

BIAS

= 470 pF, TA =25 °C unless otherwise specified. See state diagram for MODE.

T

supply undervoltage positive going

V

CC

threshold

supply undervoltage negative going

V

CC

threshold

CPH=VSD/EOL=VCOMP=VCS=VBUS=VZX

11.5 12.5 13.5

9.5 10.5 11.5

VCC supply undervoltage lockout hysteresis 1.5 2.0 3.0

=0.0 V, RT = RPH = 39.2 kΩ, CLO = CHO = C

rising from 0 V,

V

CC

CT = COM

V

falling from 14 V,

V

CC

CT = COM

Fault quiescent VCC supply current --- 600 900 µA MODE = FAULT

MODE=RUN

COMP=2 V,

t

=2 µs

off,PFC

VCC zener clamp voltage 14.6 15.6 16.6 V ICC = 10 mA

supply undervoltage positive going

V

BS

threshold

supply undervoltage negative going

V

BS

threshold

8.0 9.0 10.0 V

7.0 8.0 9.0

OTA error amplifier output current sourcing 20 30 40

OTA error amplifier output current sinking -45 -35 -25

OTA error amplifier output voltage swing (high state)

OTA error amplifier output voltage swing (low state)

internal reference voltage

V

BUS

(guaranteed by design)

over-voltage comparator positive going

V

BUS

threshold

over-voltage comparator negative going

V

BUS

hysteresis

ZX pin positve edge triggered threshold voltage

12.0 12.5 13.0 V

200 300 400 mV

3.9 4.0 4.1

4.1 4.3 4.5

4.0 4.15 4.3

1.5 2.0 2.5

µA

V

µA

V

VHO = VB

rising from 0 V

BS

falling from 14 V

V

BS

MODE = RUN

= 3.5 V

V

VBUS

MODE = RUN

V

= 4.5 V

VBUS

=4.0 V

V

COMP

CT=COM

PFC

=

V

ZX pin comparator hysterisis 100 300 500 mV

ZXHYS

V

ZX pin clamp voltage (high state) 5.7 6.7 7.7 V IZX = 5 mA, CT=COM

ZXclamp

tWD PFC watch-dog pulse interval 150 400 500 µs

V

ZX

= 0 V, V

CT=COM

COMP

= 2.0 V

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IRS2166D(S)PbF

Electrical Characteristics (cont’d)

VCC = VBS = V 1000 pF, C

Symbol Definition Min Typ Max Units Test Conditions

PFC Protection Circuitry Characteristics

V

VBUSUV-

Gate Driver Output Characteristics (HO, LO and PFC pins)

VOL Low-level output voltage, LO, HO, PFC --- COM ---

VOH High-level output voltage, LO, HO, PFC --- VCC ---

tr Turn-on rise time --- 120 220

tf Turn-off fall time --- 50 100

I0+ Source current --- 180 ---

I0- Sink current --- 260 ---

Bootstrap FET Characteristics

V

B,ON

I

B,CAP

I

B,10V

Ballast Control Oscillator Characteristics

fPH Preheat half-bridge oscillator frequency 73 76 81 kHz MODE=PREHEAT

f

RUN

D Oscillator duty cycle --- 50 --- %

t

d,LO

t

d,HO

V

CT+

V

CT-

Ballast Control Preheat Characteristics

V

CPHEOP

V

CPHRUN

I

RPHLK

I

CPH

V

CPHFLT

Ballast Control Protection Circuitry Characteristics

V

CSTH+

n

EVENTS

V

SDTH+

V

SDTH-

V

SD,delay

V

EOLBIAS

I

EOL,SRC

I

EOL,SNK

V

EOLTH+

V

EOLTH-

V

EOL,delay

V

CTFLT

V

CPHFLT

=14 V +/- 0.25 V, V

BIAS

= 470 pF, TA=25 °C unless otherwise specified. See state diagram for MODE.

T

V

pin undervoltage reset threshold 2.7 3.0 3.3 V CT=COM

BUS

CPH=VSD/EOL

= V

COMP

= VCS= V

= VZX =0.0 V, RT = RPH = 39.2 kΩ, CLO = CHO = C

BUS

V

ns

mA

VB when the bootstrap FET is on 13.2 13.7 --- V

VB source current when FET is on 40 55 --- CBS=0.1 µF

VB source current when FET is on 9 12 ---

Run half-bridge oscillator frequency 40 43 46

LO output deadtime 0.7 1.0 1.5

HO output deadtime 0.7 1.0 1.5

CT pin rising threshold voltage 7.8 8.4 9.0

CT pin falling threshold voltage 4.1 4.6 5.1

CPH pin end of preheat threshold voltage --- 10.8 --- CT=COM, I

CPH pin run mode threshold voltage --- 12.0 ---

RPH pin leakage current --- 0.1 --- MODE=RUN

CPH pin charging current 2.6 3.6 4.6

mA

µs

V

µA

VB=10 V

MODE=RUN,

CPH=13 V

BUS=VCC

V

SDEOL

, CT=COM,

=3.5 V,

V

CPH=5 V

RPH

CPH pin voltage in fault mode --- 0 --- V MODE = FAULT

CS pin over-current sense threshold 1.075 1.20 1.325 V

CS pin fault counter number of events 70 100 140

SD pin rising non-latched shutdown threshold

4.5 5.0 5.5

SD pin falling reset threshold voltage 2.7 3.0 3.3

Delay from V

until LO goes low --- 450 --- ns

SDTH+

MODE=PREHEAT,

V

=0 V

V

BUS

CT=COM

EOL pin bias voltage 1.8 2.0 2.2 V

EOL pin internal OTA source current --- 10 ---

EOL pin internal OTA sink current --- 10 ---

EOL pin rising latched shutdown threshold (active during RUN MODE)

EOL pin falling latched shutdown threshold (active during RUN MODE)

Delay from V

until LO goes low --- 1 --- µs

EOLTH+

2.7 3.0 3.3

0.9 1.0 1.1

CT pin fault mode voltage --- 0 ---

CPH pin fault mode voltage --- 0 ---

µA SD = V

MODE=RUN, CT=COM

V

=4.0 V, CPH=13 V

V

BUS

MODE=RUN,

CT=COM, CPH=13 V

V MODE=FAULT

EOLBIAS

+ 0.5 V

PFC

<2 µA

=

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Schematic Block Diagram

S1

3

RT

S2

40 K

5

CT

RDT

3.0K

S3

S4

4

RP

2

CP

V

3 uA

VC

13

R

TH

R

VCC

S6

IRS2166D(S)PbF

CO

15.6 V

S5

RUN

12

Fault

Counter

Soft

Start

Fault

Logic

R1

R2 Q

QS

Driver Logic

R Q

VCC

14

16

15

11

10

V

HO

V

LO

CS

Bootstrap

Control

High-

Side

3.0 V

Driver

LowSide

Driver

1.25 V

2 V

QT

Ballast PFC

VBU

COM

Z

3.0 V

3.5 V

1

6

7

6.7 V

Q S

R1

R2Q

R Q

R1

R2 Q

RS3

QS

RS4

4.0 V

1.0 V

4.0 V

R Q

RS1

Q S

R Q

Gain

QS

VCC

RS2

R1 R2 Q

UVLO

OVP

4.3 V

Q S

Please Note: All values shown in block diagram are typical values only

1.0 V

5 V

3 V

VCC

400 us

Watch Dog

Timer

9

SD/EO

8

PF

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IRS2166D(S)PbF

State Diagram

Power Turned On

VCC < 10.5 V (VCCUV-)

(Power Turned Off)

(Lamp Removal)

SD/EOL > 5.0 V (VSDTH+)

(Lamp Removal)

or

VCC < 10.5 V (VCCUV-)

(Power Turned Off)

UVLO Mode

1

/2-Bridge Off

≅ 250µA

I

QCCUV

CPH = 0V

CT = 0V PFC Off

VCC > 12.5 V (VCCUV+)

and

SD/EOL < 3.0 V (VSDTH-)

SD/EOL > 5.0V (VSDTH+)

FAULT Mode

Fault Latch Set

1

/2-Bridge Off

≅ 600µA

I

QCCFLT

CPH = 0 V CT = 0 V PFC Off

CS > 1.2 V (VCSTH+) for 100

CS > 1.2 V (VCSTH+) (single event)

or

SD/EOL < 1.0 V (VEOLTH-)

or

SD/EOL > 3.0 V (VEOLTH+)

CS > 1.2 V (VCSTH+) for 100 events (nEVENTS)

events (nEVENTS)

PREHEAT Mode

1

/2-Bridge oscillating @ f

RPH // RT

CPH Charging

PFC Enabled (High Gain)

CS Enabled

Fault Counter Enabled

PH

CPH > 10.8 V (VCPHEOP)

IGNITION Mode

RPH>Open

f

ramps to f

PH

CPH charging

PFC = High Gain Mode

CS Enabled

Fault Counter Enabled

RUN

CPH > 12.0 V (VCPHRUN)

RUN Mode

RPH = Open

1/2-Bridge Oscillating @f

PFC = Low Gain Mode

VBUS UV Threshold Enabled

CS Enabled

Fault Counter Disabled

RUN

VBUS < 3.0 V

(VBUSUV)

Discharge

VCC to

UVLO

All values are typical. Applies to application diagram on page 1.

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