IOR IRS2104S-PbF User Manual

Data Sheet No.PD60267

IRS2104(S)PbF

HALF-BRIDGE DRIVER

Features

• Floating channel designed for bootstrap operation

• Fully operational to +600 V

• Tolerant to negative transient voltage, dV/dt

immune

• Gate drive supply range from 10 V to 20 V

• Undervoltage lockout

• 3.3 V, 5 V, and 15 V input logic compatible

• Cross-conduction prevention logic

• Internally set deadtime

• High-side output in phase with input

• Shutdown input turns off both channels

• Matched propagation delay for both channels

•

RoHS compliant

Description

The IRS2104 is a high voltage, high speed power MOS

FET and IGBT drive side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver crossconduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates from 10 V to 600 V.

r with dependent high- and low-

Product Summary

V

OFFSET

IO+/ - 130 mA/270 mA

V

OUT

t

(typ.) 680 ns/150 ns

on/off

Deadtime (typ.) 520 ns

600 V max.

10 V - 20 V

Packages

8 Lead SOIC

IRS2104S

8 Lead PDIP

IRS2104

Typical Connection

up to 600 V

V

CC

V

CC

IN

SD

(Refer to Lead Assignment for correct pin configuration). This diagram shows electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.

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IN SD

V

HO

V

LOCOM

B

TO

S

LOAD

IRS2104(S) PbF

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

IN

dVs/dt Allowable offset supply voltage transient — 50 V/ns

P

D

Rth

JA

T

J

T

S

T

L

High-side floating absolute voltage -0.3 625 High-side floating supply offset voltage VB - 25 VB + 0.3 High-side floating output voltage VS - 0.3 VB + 0.3 Low-side and logic fixed supply voltage -0.3 25 Low-side output voltage -0.3 VCC + 0.3 Logic input voltage (IN & SD) -0.3 V

Package power dissipation @ TA ≤ +25 °C

Thermal resistance, junction to ambient

Junction temperature — 150 Storage temperature - 55 150 Lead temperature (soldering, 10 seconds) — 30 0

(8 lead PDIP) — 1.0

(8 lead SOIC) — 0.625 (8 lead PDIP) — 125 (8 lead SOIC) — 200

CC

+ 0.3

V

W

°C/W

°C

Recommended Operating Conditions

The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at a 15 V differential.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

IN

T

A

Note 1: Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip DT97-3 for more details).

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High-side floating supply absolute voltage VS + 10 VS + 20 High-side floating supply offset voltage Note 1 600 High-side floating output voltage V Low-side and logic fixed supply voltage 10 20 Low-side output voltage 0 V Logic input voltage (IN & SD)0V Ambient temperature -40 125

S VB

CC

V

CC

°C

IRS2104(S) PbF

Dynamic Electrical Characteristics

V

(VCC, VBS) = 15 V, CL = 1000 pF and TA = 25 °C unless otherwise specified.

BIAS

Symbol Definition Min. Typ. Max. Units Test Conditions

t

on

t

off

t

sd t

r

t

f

DT

MT Delay matching, HS & LS turn-on/off — — 6 0

Static Electrical Characteristics

V

(VCC, VBS) = 15 V and TA = 25 °C unless otherwise specified. The VIN, V

BIAS

COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.

Symbol Definition Min. Typ. Max. Units Test Conditions

V

IH

V

IL

V

SD,TH+

V

SD,TH-

V

OH

V

OL

I

LK

I

QBS

I

QCC

I

IN+

I

IN-

V

CCUV+

V

CCUV-

I

O+

I

O-

Turn-on propagation delay — 680 820 VS = 0 V Turn-off propagation delay — 150 220 VS = 600 V Shutdown propagation delay — 160 220 Turn-on rise time — 70 170 Turn-off fall time — 35 90 Deadtime, LS turn-off to HS turn-on &

HS turn-on to LS turn-off

Logic “1” (HO) & Logic “0” (LO) input voltage 2.5 — — Logic “0” (HO) & Logic “1” (LO) input voltage — — 0.8 SD input positive going threshold 2.5 — — SD input negative going threshold — — 0.8 High level output voltage, V Low level output voltage, V Offset supply leakage current — — 5 0 VB = VS = 600 V Quiescent VBS supply current — 30 55 Quiescent VCC supply current — 150 270 Logic “1” input bias current — 3 10 VIN = 5 V Logic “0” input bias current — — 5 VIN = 0 V VCC supply undervoltage positive going

threshold VCC supply undervoltage negative going threshold

Output high short circuit pulsed current 130 290 —

Output low short circuit pulsed current 270 600 —

BIAS

O

- V

O

400 520 650

and IIN parameters are referenced to

TH,

— 0.05 0.2 — 0.02 0.1

8 8.9 9.8

7.4 8.2 9

ns

VCC = 10 V to 20 V

V

µA

mA

V

IO = 2 mA

= 0 V or 5 V

IN

VO = 0 V

PW ≤ 10 µs

VO = 15 V

PW ≤ 10 µs

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Functional Block Diagram

IN

DEAD TIME &

SHOOT-THROUGH

PREVENTION

DETECT

IRS2104(S) PbF

VB

HV LEVEL SHIFT

PULSE FILTER

PULSE

GEN

UV

Q

R S

HO

VS

VCC

SD

LO

COM

Lead Definitions

Symbol Description

IN Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO

SD

V

B

HO High-side gate drive output V

S

V

CC

LO Low-side gate drive output COM Low-side return

Logic input for shutdown High-side floating supply

High-side floating supply return Low-side and logic fixed supply

Lead Assignments

1

V

CC

2

IN

3

SD

4

COM

V

HO

V LO

8

B

7 6

S

5

1

V

CC

2

IN

3

SD

4

COM

HO

V

V LO

8

B

7 6

S

5

8 Lead PDIP 8 Lead SOIC

IRS2104PbF IRS2104SPbF

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IRS2104(S) PbF

IN

SD

HO

LO

Figure 1. Input/Output Timing Diagram

SD

50%

t

sd

HO

90%

LO

Figure 3. Shutdown Waveform Definitions

IN(LO)

50%

t

off

90% 90%

t

f

IN

(HO)

t

on

50%

t

r

LO HO

Figure 2. Switching Time Waveform Definitions

IN

HO

LO

10% 10%

50% 50%

10%

DT

90%

DT

10%

Figure 4. Deadtime Waveform Definitions

IN

(LO)

LO

50%

HO

10%

MT

90%

HOLO

50%

IN

(HO)

MT

Figure 5. Delay Matching Waveform Definitions

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