IOR IR2136, IR21362, IR21363, IR21365, IR21366 User Manual
...
Data Sheet No. PD60166 revS
IR2136/IR21362/IR21363/IR21365/
IR21366/IR21367/IR21368 (J&S) & (PbF)
Features
Floating channel designed for bootstrap operation
•
Fully operational to +600V
3-PHASE BRIDGE DRIVER
Packages
Tolerant to negative transient voltage - dV/dt immune
Gate drive supply range from 10 to 20V (IR2136/IR21368),
•
11.5 to 20V (IR21362) or 12 to 20V (IR21363/IR21365/
IR21366/IR21367)
Undervoltage lockout for all channels
•
Over-current shutdown turns off all six drivers
•
Independent 3 half-bridge drivers
•
Matched propagation delay for all channels
•
Cross-conduction prevention logic
•
Lowside outputs out of phase with inputs. High side
•
outputs out of phase (IR2136/IR21363/IR21365/
IR21366/IR21367/IR21368) or in phase
(IR21362) with inputs.
3.3V logic compatible
•
Lower di/dt gate driver for
•
better noise immunity
Externally programmable
•
delay for automatic fault
clear
Also available LEAD-FREE
•
Description
Part
Input Logic
Ton (typ.)
Toff (typ.)
VIH (typ.)
VIL (typ.)
Vitrip+
UV CC/BS+
UV CC/BS-
IR2136
HIN, LIN
400ns
380ns
2.7V
1.7V
0.46V
8.9V
8.2V
Feature Comparison: IR2136/IR21362/IR21363/
IR21362
HIN/LIN
400ns
380ns
2.7V
1.7V
0.46V
10.4V
9.4V
28-Lead SOIC
28-Lead PDIP
44-Lead PLCC w/o 12 leads
IR21365/IR21366/IR21367/IR21368
IR21363
HIN, LIN
400ns
380ns
2.7V
1.7V
0.46V
11.2V
11.0V
IR21365
HIN, LIN
400ns
380ns
2.7V
1.7V
4.3V
11.2V
11.0V
IR21366
HIN, LIN
250ns
180ns
2.0V
1.3V
0.46V
11.2V
11.0V
IR21367
HIN, LIN
250ns
180ns
2.0V
1.3V
4.3V
11.2V
11.0V
IR21368
HIN,LIN
400ns
380ns
2.0V
1.3V
4.3V
8.9V
8.2V
The IR2136/IR21362/IR21363/IR21365/IR21366/IR21367/IR21368(J&S) are high votage, high speed power MOSFET
and IGBT drivers with three independent high and low side referenced output channels for 3-phase applications.
Proprietary HVIC technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS
or LSTTL outputs, down to 3.3V logic. A current trip function which terminates all six outputs can be derived from
an external current sense resistor. An enable function is available to terminate all six outputs simultaneously. An
open-drain FAULT signal is provided to indicate that an overcurrent or undervoltage shutdown has occurred.
Overcurrent fault conditions are cleared automatically after a delay programmed externally via an RC network
connected to the RCIN input. The output drivers feature a high pulse current buffer stage designed for minimum
driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The
floating channel can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration which
operates up to 600 volts.
Typical Connection
HIN1,2,3 / HIN1,2,3
(Refer to Lead Assignments for correct pin configuration). This/These
diagram(s) show electrical connections only.
Please refer to our Application Notes and
DesignTips for proper circuit board layout.
VCC
LIN1,2,3
FAULT
GND
VCC
HIN1,2,3 / HIN1,2,3
LIN1,2,3
EN
FAULT
EN
RCIN
ITRIP
VSS COM
VB1,2,3
HO1,2,3
VS1,2,3
LO1,2,3
IR2136(2)(3)(5)(6)(7)(8)
up to 600V
TO
LOAD
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IR2136(2)(3)(5)(6)(7)(8)
(
J& S) & (PbF
)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board
mounted and still air conditions.
Symbol Definition Min. Max. Units
V
S
V
BS
V
HO
V
CC
V
SS
V
LO1,2,3
V
IN
V
FLT
dV/dt Allowable offset voltage slew rate — 50 V/ns
P
D
Rth
JA
T
J
T
S
T
L
High side offset voltage V
B1,2,3
- 25 V
B1,2,3
+ 0.3
High side floating supply voltage -0.3 625
High side floating output voltage V
S1,2,3
- 0.3 V
B1,2,3
+ 0.3
Low side and logic fixed supply voltage -0.3 25
Logic ground V
- 25 V
CC
CC
+ 0.3
Low side output voltage -0.3 VCC + 0.3
Input voltage LIN,HIN,ITRIP, EN, RCIN VSS - 0.3 lower of
(V
+ 15) or
SS
V
+ 0.3)
CC
FAULT output voltage VSS - 0.3 V
Package power dissipation @ T
≤ +25°C (28 lead PDIP) — 1.5
A
CC
+ 0.3
(28 lead SOIC) — 1.6
(44leadPLCC) — 2.0
Thermal resistance, junction to ambient (28 lead PDIP) — 83
(28 lead SOIC) — 78
(44 lead PLCC) — 63
Junction temperature — 150
Storage temperature -55 150
Lead temperature (soldering, 10 seconds) — 300
V
W
°C/W
°C
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute referenced to COM. The VS offset rating is tested with all supplies
biased at 15V differential.
Symbol Definition Min. Max. Units
V
B1,2,3
V
S1,2,3
V
HO1,2,3
V
LO1,2,3
V
CC
V
SS
V
FLT
V
RCIN
Note 1: Logic operational for VS of COM -5V to COM +600V. Logic state held for VS of COM -5V to COM -VBS.
(Please refer to the Design Tip DT97-3 for more details).
Note 2: All input pins and the ITRIP pin are internally clamped with a 5.2V zener diode.
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High side floating supply voltage IR2136(8) V
IR21362 V
IR2136(3)(5)(6)(7) V
S1,2,3
S1,2,3
S1,2,3
10 V
+
11.5 V
+
12 V
+
S1,2,3
S1,2,3
S1,2,3
High side floating supply offset voltage Note 1 600
High side output voltage V
S1,2,3
Low side output voltage 0 V
V
B1,2,3
CC
Low side and logic fixed supply voltage IR2136(8) 10 20
IR21362 11.5 20
IR2136(3)(5)(6)(7) 12 20
Logic ground -5 5
FAULT output voltage V
RCIN input voltage V
SS
SS
V
CC
V
CC
20
+
20
+
20
+
V
IR2136(2)(3)(5)(6)(7)(8)
(
J&S) & (PbF
Recommended Operating Conditions cont.
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute referenced to COM. The VS offset rating is tested with all supplies
biased at 15V differential.
Symbol Definition Min. Max. Units
V
ITRIP
V
IN
T
A
Note 2: All input pins and the ITRIP pin are internally clamped with a 5.2V zener diode.
ITRIP input voltage V
Logic input voltage , HIN (IR2136,IR21363(5)(6)(7)(8)),
HIN(IR21362), EN V
Ambient temperature -40 125
SS
SS
V
SS
V
SS
+5
+5
V
o
C
Static Electrical Characteristics
V
BIAS (VCC
are applicable to all six channels (HS1,2,3 and LS1,2,3). The VO and IO parameters are referenced to COM and VS1,2,3
and are applicable to the respective output leads: H
Symbol Definition Min. Typ. Max. Units Test Conditions
V
V
V
V
V
RCIN,TH+
V
RCIN,HYS
V
V
, VBS1,2,3) = 15V unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and
V
IH
V
EN,TH+
EN,TH-
IT,TH+
IT,HYS
V
OH
V
OL
CCUV+VCC
BSUV+
Logic “0” input voltage LIN1,2,3, HIN1,2,3
Logic “1” input voltage HIN1,2,3 IR21362
Logic “0” input voltage LIN1,2,3, HIN1,2,3
IR21366(7)(8) 2.5 — —
Logic “1” input voltage LIN1,2,3, HIN1,2,3
IL
Logic “0” input voltage HIN1,2,3 IR21362
Logic “0” input voltage LIN1,2,3, HIN1,2,3
IR21366(7)(8) — — 0.8
EN positive going threshold — — 3
EN negative going threshold 0.8 — —
ITRIP positive going threshold
ITRIP input hysteresis
RCIN positive going threshold — 8 —
RCIN input hysteresis — 3 —
High level output voltage, V
Low level output voltage, V
positive going threshold IR21362 9.6 10.4 11.2
and L
O1,2,3
IR2136(3)(5) 3.0 — —
IR2136(3)(5) — — 0.8
IR2136(2)(3)(6) 0.37 0.46 0.55
IR21365(7)(8) 3.85 4.30 4.75
IR2136(2)(3)(6) — 0.07 —
IR21365(7)(8) — .15 —
- V
BIAS
O
O
and VBS supply undervoltage IR2136(8) 8.0 8.9 9.8
IR21363(5)(6)(7) 10.6 11.1 11.6
O1,2,3.
— 0.9 1.4 IO = 20 mA
— 0.4 0.6 IO = 20 mA
V
)
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IR2136(2)(3)(5)(6)(7)(8)
(
J& S) & (PbF
)
Static Electrical Characteristics cont.
V
BIAS (VCC
are applicable to all six channels (HS1,2,3 and LS1,2,3). The VO and IO parameters are referenced to COM and VS1,2,3
and are applicable to the respective output leads: H
Symbol Definition Min. Typ. Max. Units Test Conditions
V
V
V
V
V
IN, CLAMP Input clamp voltage (HIN, LIN, ITRIP and EN)
I
I
R
ON,RCIN
R
, VBS1,2,3) = 15V unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and
and L
CCUV-
BSUV-
CCUVH
BSUVH
I
LK
I
QBS
I
QCC
I
LIN+
I
LIN-
I
HIN+
I
HIN-
ITRIP+
ITRIP-
I
EN+
I
EN-
I
RCIN
I
O+
I
O-
ON,FLT
O1,2,3
V
and V
CC
negative going threshold IR21362 8.6 9.4 10.2
V
and VBS supply undervoltage IR2136 0.3 0.7 —
CC
lockout hysteresis IR21362 0.5 1.0 —
Offset supply leakage current — — 50 V
Quiescent VBS supply current — 70 120
Quiescent VCC supply current — 1.6 2.3 mA
Input bias current (LOUT = HI) IR2136(2)(3)(5) — 200 300 V
Input bias current (LOUT = LO) IR2136(2)(3)(5) — 100 220 V
Input bias current (HOUT = HI) IR2136(3)(5) — 200 300 V
Input bias current (HOUT = LO) IR2136(3)(5) — 100 220 V
“high” ITRIP input bias current — 30 100 V
“low” ITRIP input bias current — 0 1 V
“high” ENABLE input bias current — 30 100 V
“low” ENABLE input bias current — 0 1 V
RCIN input bias current — 0 1 V
Output high short circuit pulsed current 120 200 — V
Output low short circuit pulsed current 250 350 — V
RCIN low on resistance — 50 100
FAULT low on resistance — 50 100
supply undervoltage IR2136(8) 7.4 8.2 9.0
BS
IR21363(5)(6)(7) 10.4 10.9 11.4
IR21363(5) — 0.2 —
IR21366(7)(8)
IR21366(7)(8)
IR21366(7)(8)
IR21362(6)(7)(8)
O1,2,3.
IR21362
V
µA
4.9 5.2 5.5 V I
—01
—01
— 30 100
—01
—01
µA
mA
Ω
B1,2,3=VS1,2,3=600V
V
= 0V or 5V
IN
IN =100µA
LIN = 5V
LIN = 0V
HIN = 5V
HIN = 0V
= 5V
ITRIP
= 0V
ITRIP
= 5V
ENABLE
= 0V
ENABLE
= 0V or 15V
RCIN
=0V, PW ≤ 10 µs
O
=15V, PW ≤10 µs
O
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IR2136(2)(3)(5)(6)(7)(8)
(
J&S) & (PbF
Dynamic Electrical Characteristics
VCC = VBS = V
Symbol Definition Min. Typ. Max. Units Test Conditions
t
on
t
off
t
r
t
f
t
EN
t
ITRIP
t
bl
t
FLT
t
FILIN
t
FLTCLR
DT Deadtime 220 290 360 VIN = 0 & 5V
MT Matching delay ON and OFF — 40 75
MDT Matching delay, max (ton,t
PM Output pulse width matching, PWin -PWout (fig.2) — 40 75
NOTE: For high side PWM, HIN pulse width must be ≥ 1µsec
= 15V, V
BIAS
Turn-on propagation delay IR2136(2)(3)(5)(8) 300 425 550
Turn-off propagation delay IR2136(2)(3)(5)(8) 250 400 550
Turn-on rise time — 125 190
Turn-off fall time — 50 75
ENABLE low to output IR2136(2)(3)(5)(8) 300 450 600 V
shutdown propagation delay IR21366(7) 100 250 400
ITRIP to output shutdown propagation delay 500 750 1000 V
ITRIP blanking time 100 150 — VIN = 0V or 5V
ITRIP to FAULT propagation delay 400 600 800 V
Input filter time (HIN, LIN, EN) 100 200 — VIN = 0 & 5V
(IR2136(2)(3)(5)(8) only)
FAULT clear time RCIN: R=2meg, C=1nF 1.3 1.65 2 mS V
(ton,toff are applicable to all 3 channels)
= VSS = COM, TA = 25oC and CL = 1000 pF unless otherwise specified.
S1,2,3
IR21366(7) — 250 —
IR21366(7) — 180 —
) - min (ton,t
off
), — 25 70
off
nS
nS
VIN = 0 & 5V
= 0V or 5V
IN, VEN
= 5V
ITRIP
V
= 5V
ITRIP
= 0V or 5V
IN
V
= 5V
ITRIP
= 0V or 5V
IN
V
= 0V
ITRIP
External dead
time
>400nsec
)
VCC VBS ITRIP ENABLE FAULT LO1,2,3 HO1,2,3
<UVCC X X X 0 (note 1) 0 0
15V <UVBS 0V 5V high imp LIN1,2,3 0
15V 15V 0V 5V high imp LIN1,2,3 HIN1,2,3
15V 15V >V
ITRIP
5V 0 (note 2) 0 0
15V 15V 0V 0V high imp 0 0
Note: A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously.
Note 1: UVCC is not latched, when VCC>UVCC, FAULT returns to high impedance.
Note 2: When ITRIP <V
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, FAULT returns to high-impedance after RCIN pin becomes greater than 8V (@ VCC = 15V)
ITRIP
IR2136(2)(3)(5)(6)(7)(8)
Functional Block Diagram
(
J& S) & (PbF
)
HIN1
LIN1
HIN2
LIN2
HIN3
LIN3
VSS
ITRIP
RCIN
FAULT
EN
+
-
0.5V
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
DEADTIME &
SHOOT-THROUGH
PREVENTION
DEADTIME &
SHOOT-THROUGH
PREVENTION
DEADTIME &
SHOOT-THROUGH
PREVENTION
UV
DETECT
S
SET
DOMINANT
R
LATCH
IR2136/21363/21365
VSS/COM
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFTER
Q
VSS/COM
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFTER
HV
LEVEL
SHIFTER
HV
LEVEL
SHIFTER
HV
LEVEL
SHIFTER
SET
RESET
SET
RESET
SET
RESET
DELAY
DELAY
DELAY
LATCH
UV
DETECT
LATCH
UV
DETECT
LATCH
UV
DETECT
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
VB1
HO1
VS1
VB2
HO2
VS2
VB3
HO3
VS3
VCC
LO1
LO2
LO3
COM
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Functional Block Diagram
IR2136(2)(3)(5)(6)(7)(8)
(
J&S) & (PbF
)
HIN1
LIN1
HIN2
LIN2
HIN3
LIN3
VSS
ITRIP
RCIN
FAULT
EN
+
-
0.5V
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
DEADTIME &
SHOOT-THROUGH
PREVENTION
DEADTIME &
SHOOT-THROUGH
PREVENTION
DEADTIME &
SHOOT-THROUGH
PREVENTION
DETECT
S
SET
DOMINANT
R
LATCH
UV
Q
IR21362
VSS/COM
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFTER
HV
LEVEL
SHIFTER
HV
LEVEL
SHIFTER
HV
LEVEL
SHIFTER
RESET
RESET
RESET
DELAY
DELAY
DELAY
SET
LATCH
UV
DETECT
DRIVER
HO1
VS1
VB2
VB1
SET
LATCH
UV
DETECT
DRIVER
HO2
VS2
VB3
SET
LATCH
UV
DETECT
DRIVER
HO3
VS3
VCC
DRIVER
DRIVER
DRIVER
LO1
LO2
LO3
COM
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IR2136(2)(3)(5)(6)(7)(8)
Functional Black Diagram
(
J& S) & (PbF
)
HIN1
LIN1
HIN2
LIN2
HIN3
LIN3
VSS
EN
ITRIP
RCIN
FAULT
IR21366/IR21367/IR21368
DEADTIME &
SHOOT-THROUGH
PREVENTION
VSS/COM
LEVEL
SHIFTER
HV
LEVEL
SHIFTER
SET
RESET
LATCH
UV
DETECT
DRIVER
VB1
HO1
VS1
VB2
SET
DEADTIME &
SHOOT-THROUGH
PREVENTION
VSS/COM
LEVEL
SHIFTER
HV
LEVEL
SHIFTER
RESET
LATCH
UV
DETECT
DRIVER
HO2
VS2
VB3
SET
DEADTIME &
SHOOT-THROUGH
PREVENTION
VSS/COM
LEVEL
SHIFTER
HV
LEVEL
SHIFTER
RESET
LATCH
UV
DETECT
DRIVER
HO3
VS3
VCC
S
DOMINANT
R
DETECT
SET
LATCH
UV
Q
INPUT
NOISE
FILTER
+
-
INPUT
NOISE
FILTER
VSS/COM
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFTER
DELAY
DELAY
DELAY
DRIVER
DRIVER
DRIVER
LO1
LO2
LO3
COM
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IR2136(2)(3)(5)(6)(7)(8)
(
J&S) & (PbF
Lead Definitions
Symbol Description
V
CC
VSS Logic Ground
HIN1,2,3 Logic inputs for high side gate driver outputs (HO1,2,3), out of phase (IR2136/IR21363(5)(6)(7)(8)
HIN1,2,3 Logic inputs for high side gate driver outputs (HO1,2,3), in phase (IR21362)
LIN1,2,3 Logic inputs for low side gate driver outputs (LO1,2,3), out of phase
FAULT Indicates over-current (ITRIP) or low-side undervoltage lockout has occured. Negative logic,
EN Logic input to enable I/O functionality. Positive logic, i.e. I/O logic functions when ENABLE is
ITRIP Analog input for overcurrent shutdown. When active, ITRIP shuts down outputs and activates
RCIN External RC network input used to define FAULT CLEAR delay, T
COM Low side gate driver return
VB1,2,3 High side floating supply
HO1,2,3 High side gate driver outputs
V
S1,2,3
LO1,2,3 Low side gate driver output
Low side and logic fixed supply
open-drain output
high. No effect on FAULT and not latched
FAULT and RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally
set time T
to R*C. When RCIN>8V, the FAULT pin goes back into open-drain high-impedance
High voltage floating supply returns
, then automatically becomes inactive (open-drain high impedance).
FLTCLR
FLTCLR
, approximately equal
)
Note: All input pins and the ITRIP pin are internally clamped with a 5.2V zener diode.
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IR2136(2)(3)(5)(6)(7)(8)
Lead Assignments
(
J& S) & (PbF
)
1
VCC
2
HIN1
3
HIN2
4
HIN3
5
LIN1
6
LIN2
7
LIN3
FAULT
ITRIP
EN
RCIN
VSS
COM
LO3
IR2136
8
9
10
11
12
13
14
VB1
HO1
VS1
VB2
HO2
VS2
VB3
HO3
VS3
LO1
LO2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LIN1
LIN2
LIN3
FAULT
ITRIP
RCIN
7
8
9
10
11
12
13
14
15
16
EN
17
18
VCC
HIN1
HIN2
HIN3
44 LEAD PLCC w/o 12 LEADS
IR2136
19 20 21 22 23 24 25
COM
LO3
VSS
VS1
HO1
VB1
41
42433456
37
VB2
36
HO2
35
VS2
31
VB3
30
HO3
29
VS3
LO2
LO1
1
VCC
2
HIN1
3
HIN2
4
HIN3
5
LIN1
6
LIN2
7
LIN3
FAULT
ITRIP
EN
RCIN
VSS
COM
LO3
IR2136
8
9
10
11
12
13
14
VB1
HO1
VS1
VB2
HO2
VS2
VB3
HO3
VS3
LO1
LO2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28 Lead PDIP 44 Lead PLCC w/o 12 leads 28 lead SOIC (wide body)
IR2136/IR21363(5)(6)(7)(8) IR2136/IR21363(5)(6)(7)(8) (J) IR2136/IR21363(5)(6)(7)(8) (S)
VS1
HO1
LO3
LO2
VB1
LO1
1
42433456
37
VB2
36
HO2
35
VS2
31
VB3
30
HO3
29
VS3
2
HIN1
3
HIN2
4
HIN3
5
LIN1
6
LIN2
7
LIN3
8
FAULT
9
ITRIP
10
EN
11
RCIN
12
VSS
13
COM
14
LO3
41
VCC
VB1
HO1
VS1
VB2
HO2
VS2
VB3
HO3
VS3
LO1
LO2
VCC
HIN1
HIN2
LIN1
LIN2
LIN3
HIN3
7
8
9
10
11
12
13
14
15
16
EN
17
18
19 20 21 22 23 24 25
VSS
COM
1
VCC
2
HIN1
3
HIN2
4
HIN3
5
LIN1
6
LIN2
7
LIN3
8
FAULT
9
ITRIP
10
EN
11
RCIN
12
VSS
13
COM
14
LO3
VB1
HO1
VS1
VB2
HO2
VS2
VB3
HO3
VS3
LO1
LO2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FAULT
ITRIP
RCIN
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28 Lead PDIP 44 Lead PLCC w/o 12 leads 28 lead SOIC (wide body)
IR21362 IR21362J IR21362S
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HIN1,2,3
HIN1,2,3
LIN1,2,3
FAULT
ITRIP
RCIN
EN
HO1,2,3
LO1,2,3
IR2136(2)(3)(5)(6)(7)(8)
Figure 1. Input/Output Timing Diagram
(
J&S) & (PbF
)
LIN1,2,3
HIN1,2,3
LIN1,2,3
HIN1,2,3
HO1,2,3
LO1,2,3
Figure 2. Switching Time Waveforms
50% 50%
PW
IN
50% 50%
ton tr tftoff
PW
OUT
90%
50%
EN
ten
HO1,2,3
90%
LO1,2,3
90%
10%10%
Figure 3. Output Enable Timing Waveform
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