IOR IR2117 S, IR2118 S User Manual

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Data Sheet No. PD60146 Rev N

IR2117(S)/IR2118(S) & ( PbF)

SINGLE CHANNEL DRIVER

Features

Floating channel designed for bootstrap operation

•

Fully operational to +600V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 10 to 20V

•

Undervoltage lockout

•

CMOS Schmitt-triggered inputs with pull-down

•

• Output in phase with input (IR2117) or out of

phase with input (IR2118) Also available LEAD-FREE

•

Description

The IR2117/IR2118(S) is a high voltage, high speed power MOSFET and IGBT driver. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS outputs. The output driver features a high pulse current buffer stage designed for minimum cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high or low side configuration which operates up to 600 volts.

Typical Connection

Product Summary

V

OFFSET

+/- 200 mA / 420 mA

I

O

V

OUT

t

(typ.) 125 & 105 ns

on/off

Packages

8-Lead PDIP

IR2117/IR2118

up to 600V

600V max.

10 - 20V

8-Lead SOIC

IR2117S/IR2118S

V

CC

IN

V

CC

COM

V

B

HOIN

V

S

TO

LOAD

IR2117

up to 600V

(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.

V

CC

IN

V

CC

COM

V

B

HOIN

V

S

IR2118

TO

LOAD

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IR2117(S)/IR2118(S) & ( PbF)

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 5 through 8.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

IN

dVs/dt Allowable offset supply voltage transient (figure 2) — 50 V/ns

P

D

Rth

JA

T

J

T

S

T

L

High side floating supply voltage -0.3 625 High side floating supply offset voltage VB - 25 VB + 0.3

CC

B

+ 0.3

High side floating output voltage VS - 0.3 V Logic supply voltage -0.3 25 Logic input voltage -0.3 V

Package power dissipation @ TA ≤ +25°C (8 lead PDIP) — 1.0

(8 lead SOIC) — 0.625

Thermal resistance, junction to ambient (8 lead PDIP) — 125

(8 lead SOIC) — 200 Junction temperature — 150 Storage temperature -55 150 Lead temperature (soldering, 10 seconds) — 300

W

°C/W

°C

V

Recommended Operating Conditions

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

IN

T

A

Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip DT97-3 for more details).

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High side floating supply absolute voltage VS + 10 VS + 20 High side floating supply offset voltage Note 1 600 High side floating output voltage V Logic supply voltage 10 20 Logic input voltage 0 V Ambient temperature -40 125 °C

S

V

B

CC

V

IR2117(S)/IR2118(S) & ( PbF)

Dynamic Electrical Characteristics

V

(VCC, VBS) = 15V, CL = 1000 pF and TA = 25°C unless otherwise specified. The dynamic electrical characteristics

BIAS

are measured using the test circuit shown in Figure 3.

Symbol Definition Min. Typ. Max. Units Test Conditions

t

on

t

off

t t

Static Electrical Characteristics

V

(VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to

BIAS

COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.

Symbol Definition Min. Typ. Max. Units Test Conditions

V

IH

V

OH

V

OL

I

LK

I

QBS

I

QCC

I

IN+

I

IN-

V

BSUV+

V

BSUV-

V

CCUV+VCC

V

CCUV-

I

O+

I

O-

Turn-on propagation delay — 125 200 VS = 0V Turn-off propagation delay — 105 180 VS = 600V Turn-on rise time — 80 130

r

Turn-off fall time — 40 65

f

input voltage - logic “1” (IR2117) logic “0” (IR2118) 9.5 — — Input voltage - logic “0” (IR2117) logic “1” (IR2118) — — 6.0

IL

High level output voltage, V Low level output voltage, V

BIAS

O

- V

O

— — 100 IO = 0A — — 100 IO = 0A

ns

V

mV

Offset supply leakage current — — 50 VB = VS = 600V Quiescent VBS supply current — 50 240 V Quiescent VCC Supply Current — 70 340 VIN = 0V or V Logic “1” input bias current (IR2117) VIN = V

(IR2118) VIN = 0V

Logic “0” input bias current (IR2117) VIN = 0V

(IR2118) VIN = V

— 20 40

— — 1.0

µA

VBS supply undervoltage positive going threshold 7.6 8.6 9.6 VBS supply undervoltage negative going threshold 7.2 8.2 9.2

V

supply undervoltage positive going threshold 7.6 8.6 9.6

V

supply undervoltage negative going threshold 7.2 8.2 9.2

CC

Output high short circuit pulsed current 200 250 — VO = 0V

Output low short circuit pulsed current 420 500 — VO = 15V

mA

= 0V or V

IN

V

= Logic “1”

IN

PW ≤ 10 µs

V

= Logic “0”

IN

PW ≤ 10 µs

CC CC

CC

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IR2117(S)/IR2118(S) & ( PbF)

Functional Block Diagram (IR2117)

V

CC

COM

IN

UV

DETECT

PULSE

GEN

Functional Block Diagram (IR2118)

V

CC

IN

PULSE

GEN

LEVEL

HV LEVEL SHIFT

HV

SHIFT

UV

DETECT

PULSE FILTER

UV

DETECT

PULSE FILTER

V

B

R

Q R S

R

Q

R S

V

HO

V

HO

V

S

B

S

UV

DETECT

COM

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IR2117(S)/IR2118(S) & ( PbF)

Lead Definitions

Symbol Description

V

CC

IN Logic input for gate driver output (HO), in phase with HO (IR2117) IN Logic input for gate driver output (HO), out of phase with HO (IR2118) COM Logic ground V

B

HO High side gate drive output V

S

Lead Assignments

Logic and gate drive supply

High side floating supply

High side floating supply return

1

V

CC

2

IN

3

COM

4

V

HO

V

8

B

7 6

S

5

1 2

IN

3

COM

4

8 Lead PDIP 8 Lead SOIC

IR2117 IR2117S

1

V

CC

2

IN

3

COM

4

8 Lead PDIP 8 Lead SOIC

V

HO

V

8

B

7 6

S

5

1

V

2

IN

3

COM

4

IR2118 IR2118S

V

CC

V

HO

V

HO

V

8

B

7 6

S

5

8

B

7 6

S

5

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IR2117(S)/IR2118(S) & ( PbF)

IN

(IR2118)

IN

(IR2117)

HO

Figure 1. Input/Output Timing Diagram

IR2117/IR2118

<50 V/ns

Figure 2. Floating Supply Voltage Transient Test Circuit

IN

(IR2118)

50%

50%50%

IN

(IR2117)

t

r

on

90% 90%

t

f

off

HO

10% 10%

Figure 3. Switching Time Test Circuit Figure 4. Switching Time Waveform Definition

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