IOR IR2110, IR2113S User Manual

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Data Sheet No. PD60147-

IR2110/IR2113 (S)

HIGH AND LOW SIDE DRIVER

Features

• Floating channel designed for bootstrap operation

Fully operational to +500V or +600V Tolerant to negative transient voltage dV/dt immune

• Gate drive supply range from 10 to 20V

• Undervoltage lockout for both channels

• 3.3V logic compatible

Separate logic supply range from 3.3V to 20V Logic and power ground ±5V offset

• CMOS Schmitt-triggered inputs with pull-down

• Cycle by cycle edge-triggered shutdown logic

• Matched propagation delay for both channels

• Outputs in phase with inputs

Description

The IR2110/IR2113 are high voltage, high speed power MOSFET and IGBT drivers with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL output, down to

3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 500 or 600 volts.

Product Summary

V

OFFSET

(IR2113) 600V max.

Delay Matching 10 ns

(IR2110) 500V max.

I

+/- 2A / 2A

O

V

OUT

t

(typ.) 120 & 94 ns

on/off

10 - 20V

Packages

14-Lead PDIP

IR2110/IR2113

16-Lead SOIC

IR2110S/IR2113S

Q

Typical Connection

HO

V

DD

HIN

SD LIN

V

SS

V

CC

(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.

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V

DD

HIN SD LIN V

SS

V V

V

COM

LO

B

S

CC

up to 500V or 600V

TO

LOAD

IR2110/IR2113 (S)

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

DD

V

SS

V

IN

dVs/dt Allowable offset supply voltage transient (figure 2) — 50 V/ns

P

D

R

THJA

T

J

T

S

T

L

High side floating supply voltage (IR2110) -0.3 525

(IR2113) -0.3 625 High side floating supply offset voltage VB - 25 VB + 0.3 High side floating output voltage VS - 0.3 V Low side fixed supply voltage -0.3 25 Low side output voltage -0.3 VCC + 0.3 Logic supply voltage -0.3 VSS + 25 Logic supply offset voltage VCC - 25 V Logic input voltage (HIN, LIN & SD) VSS - 0.3 V

Package power dissipation @ TA ≤ +25°C (14 lead DIP) — 1.6

(16 lead SOIC) — 1.25

Thermal resistance, junction to ambient (14 lead DIP) — 75

(16 lead SOIC) — 100 Junction temperature — 150 Storage temperature -55 150 Lead temperature (soldering, 10 seconds) — 300

CC DD

B

+ 0.3

+ 0.3 + 0.3

V

W

°C/W

°C

Recommended Operating Conditions

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in figures 36 and 37.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

DD

V

SS

V

IN

T

A

Note 1: Logic operational for VS of -4 to +500V. Logic state held for VS of -4V to -VBS. (Please refer to the Design Tip DT97-3 for more details). Note 2: When V

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High side floating supply absolute voltage VS + 10 VS + 20 High side floating supply offset voltage (IR2110) Note 1 500

(IR2113) Note 1 600 High side floating output voltage V Low side fixed supply voltage 10 20 Low side output voltage 0 VCC Logic supply voltage VSS + 3 VSS + 20 Logic supply offset voltage -5 (Note 2) 5 Logic input voltage (HIN, LIN & SD) V Ambient temperature -40 125 °C

< 5V, the minimum VSS offset is limited to -V

DD

DD.

S

SS

V

B

V

DD

V

IR2110/IR2113 (S)

Dynamic Electrical Characteristics

V

(VCC, VBS, VDD) = 15V, CL = 1000 pF, T

BIAS

electrical characteristics are measured using the test circuit shown in Figure 3.

Symbol Definition Figure Min. Typ. Max. Units Test Conditions

t t t

MT Delay matching, HS & LS turn-on/off — — — 10 Figure 5

Turn-on propagation delay 7 — 120 150 VS = 0V

on

Turn-off propagation delay 8 — 94 125 VS = 500V/600V

off

Shutdown propagation delay 9 — 110 140 VS = 500V/600V

sd

t

Turn-on rise time 10 — 25 35

r

t

Turn-off fall time 11 — 17 25

f

Static Electrical Characteristics

V

(VCC, VBS, VDD) = 15V, T

BIAS

are referenced to V referenced to COM and are applicable to the respective output leads: HO or LO.

and are applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are

SS

Symbol Definition Figure Min. Typ. Max. Units Test Conditions

V

OH

V

OL

I

LK

I

QBS

I

QCC

I

QDD

I

IN+

I

IN-

V

BSUV+VBS

V

BSUV-VBS

V

CCUV+VCC

V

CCUV-

I

O+

I

O-

Logic “1” input voltage 12 9.5 — —

IH

Logic “0” input voltage 13 — — 6.0

IL

High level output voltage, V Low level output voltage, V Offset supply leakage current 16 — — 50 VB=VS = 500V/600V Quiescent VBS supply current 17 — 125 230 V Quiescent VCC supply current 18 — 180 340 VIN = 0V or V Quiescent VDD supply current 19 — 15 30 VIN = 0V or V Logic “1” input bias current 20 — 20 40 VIN = V Logic “0” input bias current 21 — — 1.0 V

supply undervoltage positive going 22 7.5 8.6 9.7

threshold

supply undervoltage negative going 23 7.0 8.2 9.4

threshold

supply undervoltage positive going 24 7.4 8.5 9.6 threshold VCC supply undervoltage negative going 25 7.0 8.2 9.4 threshold Output high short circuit pulsed current 26 2.0 2.5 — VO = 0V, VIN = V

Output low short circuit pulsed current 27 2.0 2.5 — VO = 15V, VIN = 0V

= 25°C and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters

A

BIAS

O

= 25°C and VSS = COM unless otherwise specified. The dynamic

A

ns

µA

V

IN

A

PW ≤ 10 µs

- V

O

14 — — 1.2 IO = 0A 15 — — 0.1 IO = 0A

= 0V or V

DD

= 0V

IN

DD DD DD

DD

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IR2110/IR2113 (S)

Functional Block Diagram

V

DD

HIN

SD

LIN

V

RSQ

SS

VDD/V

LEVEL SHIFT

VDD/V

LEVEL SHIFT

CC

PULSE

GEN

CC

Lead Definitions

Symbol Description

V

DD

HIN Logic input for high side gate driver output (HO), in phase SD Logic input for shutdown LIN Logic input for low side gate driver output (LO), in phase V

SS

V

B

HO High side gate drive output V

S

V

CC

LO Low side gate drive output COM Low side return

Logic supply

Logic ground High side floating supply

High side floating supply return Low side supply

HV LEVEL SHIFT

UV

DETECT

PULSE FILTER

DETECT

UV

DELAY

R Q R S

V

B

HO

V

S

V

CC

LO

COM

Lead Assignments

14 Lead PDIP 16 Lead SOIC (Wide Body)

IR2110/IR2113 IR2110S/IR2113S

Part Number

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IR2110/IR2113 (S)

10% 10%

HOLO

HV =10 to 500V/600V

<50V/ns

Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient Test Circuit

HIN

50%

LIN

(0 to 500V/600V)

t

on

t

r

90% 90%

t

off

t

f

HO LO

Figure 3. Switching Time Test Circuit Figure 4. Switching Time Waveform Definition

50% 50%

LO

10%

MT

HO

MT

90%

SD

HO LO

50%

t

sd

HIN LIN

90%

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Figure 6. Delay Matching Waveform DefinitionsFigure 5. Shutdown Waveform Definitions