Data Sheet No. PD60045-O
IR2103
(S) & ( PbF)
HALF-BRIDGE DRIVER
Features
• Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
• Gate drive supply range from 10 to 20V
• Undervoltage lockout
• 3.3V, 5V and 15V logic compatible
• Cross-conduction prevention logic
• Matched propagation delay for both channels
• Internal set deadtime
• High side output in phase with HIN input
• Low side output out of phase with
LIN
input
• Also available LEAD-FREE
Description
The IR2103(S) are high voltage, high speed power
MOSFET and IGBT drivers with dependent high and low
side referenced output channels. Proprietary HVIC and
latch immune CMOS technologies enable ruggedized
monolithic construction. The logic input is compatible with
standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer
stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel
power MOSFET or IGBT in the high side configuration which operates up to 600 volts.
Product Summary
V
OFFSET
+/- 130 mA / 270 mA
I
O
V
OUT
t
(typ.) 680 & 150 ns
on/off
Deadtime (typ.) 520 ns
600V max.
10 - 20V
Packages
8-Lead SOIC
IR2103S
8-Lead PDIP
IR2103
Typical Connection
up to 600V
V
CC
V
CC
HIN
LIN
(Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.
www.irf.com 1
HIN
LIN
V
HO
V
LOCOM
B
S
TO
LOAD
IR2103
(S) & ( PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol Definition Min. Max. Units
V
B
V
S
V
HO
V
CC
V
LO
V
IN
dVs/dt Allowable offset supply voltage transient — 50 V/ns
P
D
Rth
JA
T
J
T
S
T
L
High side floating absolute voltage -0.3 625
High side floating supply offset voltage VB - 25 VB + 0.3
High side floating output voltage VS - 0.3 V
Low side and logic fixed supply voltage -0.3 25
Low side output voltage -0.3 VCC + 0.3
Logic input voltage (HIN & LIN) -0.3 V
Package power dissipation @ TA ≤ +25°C (8 Lead PDIP) — 1.0
(8 Lead SOIC) — 0.625
Thermal resistance, junction to ambient (8 Lead PDIP) — 125
(8 Lead SOIC) — 200
Junction temperature — 150
Storage temperature -55 150
Lead temperature (soldering, 10 seconds) — 300
CC
B
+ 0.3
+ 0.3
W
°C/W
°C
V
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.
Symbol Definition Min. Max. Units
V
B
V
S
V
HO
V
CC
V
LO
V
IN
T
A
Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
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High side floating supply absolute voltage VS + 10 VS + 20
High side floating supply offset voltage Note 1 600
High side floating output voltage V
Low side and logic fixed supply voltage 10 20
Low side output voltage 0 V
Logic input voltage (HIN &
Ambient temperature -40 125
)0V
LIN
S
V
B
CC
CC
V
°C
IR2103
(S) & ( PbF)
Dynamic Electrical Characteristics
V
(VCC, VBS) = 15V, CL = 1000 pF and TA = 25°C unless otherwise specified.
BIAS
Symbol Definition Min. Typ. Max. Units T est Conditions
t
on
t
off
t
t
DT Deadtime, LS turn-off to HS turn-on & 400 520 650
MT Delay matching, HS & LS turn-on/off — — 60
Turn-on propagation delay — 680 820 VS = 0V
Turn-off propagation delay — 150 220 VS = 600V
Turn-on rise time — 100 170
r
Turn-off fall time — 50 90
f
HS turn-on to LS turn-off
ns
Static Electrical Characteristics
V
(VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to
BIAS
COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol Definition Min. T yp. Max. Units Test Conditions
V
V
V
V
I
LK
I
QBS
I
QCC
I
IN+
I
IN-
V
CCUV+
V
CCUV-
I
O+
I
O-
IH
IL
OH
OL
Logic “1” (HIN) & Logic “0” (
Logic “0” (HIN) & Logic “1” (
High level output voltage, V
Low level output voltage, V
Offset supply leakage current — — 50 VB = VS = 600V
Quiescent VBS supply current — 30 55 V
Quiescent VCC supply current — 150 270 VIN = 0V or 5V
Logic “1” input bias current — 3 10 HIN = 5V,
Logic “0” input bias current — — 1 HIN = 0V,
VCC supply undervoltage positive going 8 8.9 9.8
threshold
VCC supply undervoltage negative going 7.4 8.2 9
threshold
Output high short circuit pulsed current 130 210 — VO = 0V, V
Output low short circuit pulsed current 270 360 — VO = 15V, V
LIN
) input voltage 3 — — VCC = 10V to 20V
LIN
) input voltage — — 0.8 VCC = 10V to 20V
BIAS
O
- V
O
— — 100 IO = 0A
— — 100 IO = 0A
V
mV
µA
V
mA
= 0V or 5V
IN
PW ≤ 10 µs
PW ≤ 10 µs
LIN
LIN
IN
IN
= 0V
= 5V
= V
= V
IH
IL
www.irf.com 3
IR2103
(S) & ( PbF)
Functional Block Diagram
HV
LEVEL
SHIFT
IHN
DEAD TIME &
SHOOT-THROUGH
PREVENTION
VCC
LIN
UV
DETECT
PULSE
GEN
Lead Definitions
Symbol Description
HIN Logic input for high side gate driver output (HO), in phase
LIN
V
B
HO High side gate drive output
V
S
V
CC
LO Low side gate drive output
COM Low side return
Logic input for low side gate driver output (LO), out of phase
High side floating supply
High side floating supply return
Low side and logic fixed supply
PULSE
FILTER
VB
Q
R
S
HO
VS
VCC
LO
COM
Lead Assignments
1
V
CC
2
HIN
3
LIN
4
COM
V
HO
V
LO
1
8
B
7
6
S
5
V
CC
2
HIN
3
LIN
4
COM
8 Lead PDIP 8 Lead SOIC
IR2103 IR2103S
4 www.irf.com
V
HO
V
LO
8
B
7
6
S
5
IR2103
(S) & ( PbF)
HIN
LIN
HO
LO
Figure 1. Input/Output Timing Diagram
HIN
LIN
50% 50%
LIN
50%
t
off
90% 90%
50%
LO
50%
t
on
t
r
10% 10%
50%
HIN
t
on
HO
Figure 2. Switching Time Waveform Definitions
t
r
90% 90%
10% 10%
t
off
t
f
t
f
90%
DT
90%
10%
DT
10%
HO
LO
Figure 4. Deadtime Waveform Definitions
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IR2103
)
(S) & ( PbF)
1400
1200
1000
M ax.
800
600
Typ.
400
200
Turn-On Delay Time (ns)
0
-50 -25 0 25 50 75 100 125
T emperature (oC)
Figure 6A. T urn-On Time vs T emperature
1000
800
600
400
200
Turn-On Delay Time (ns
0
0 2 4 6 8101214161820
Max.
Typ
.
Input Voltage (V)
Figure 6C. T urn-On Time vs Input Voltage
1400
1200
Max.
1000
800
Typ.
600
400
200
Turn-On Delay Time (ns)
0
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 6B. T urn-On Time vs Supply Voltage
500
400
300
M ax.
200
100
Turn-Off Delay T ime (ns)
Typ.
0
-50 -25 0 25 50 75 100 125
T emperature (oC)
Figure 7A. T urn-Off Time vs T emperature
500
400
300
Max.
200
Typ.
100
Turn-Off Delay T ime (ns)
0
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 7B. Turn-Off T ime vs Supply Voltage
1000
800
600
.
400
200
Turn-Off Delay Time (ns
0
02468101214161820
Max
Typ
Input Voltage (V)
Figure 7C. T urn-Off Time vs Input Voltage
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IR2103
(S) & ( PbF)
500
400
300
200
Max.
100
Turn-On Rise T ime (ns)
Typ.
0
-50 -25 0 25 50 75 100 125
T emperature (oC)
Figure 9A. T urn-On Rise Time
vs Temperature
200
150
100
Turn-Off Fall T ime (ns)
Max.
Typ.
50
0
-50 -25 0 25 50 75 100 125
T emperature (oC)
500
400
300
M ax.
200
100
Turn-On Rise T ime (ns)
Typ.
0
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 9B. T urn-On Rise Time
vs Voltage
200
150
M ax.
100
Typ.
50
Turn-Off Fall T ime (ns)
0
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 10A. T urn Off Fall Time
Figure 10B. T urn Off Fall Time vs V oltage
vs T emperature
1400
1200
1000
800
Max.
600
Ty
p.
400
Deadtime (ns)
Min.
200
0
-50-250 255075100125
T emperature (oC)
Figure 11A. Deadtime vs Temperature
1400
1200
1000
Max.
800
Typ.
600
Deadtime (ns)
400
Min.
200
0
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 11B. Deadtime vs Voltage
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IR2103
(S) & ( PbF)
8
7
6
5
4
Min.
3
2
Input Voltage (V)
1
0
-50 -25 0 25 50 75 100 125
T emperature (oC)
T emperature (oC)
Figure12A. Logic "1" (HIN) & Logic "0" (LIN)
Input V oltage vs Temperature
4
3.2
2.4
1.6
M ax.
Input Voltage (V)
0.8
0
-50 -25 0 25 50 75 100 125
T emperature (oC)
8
7
6
5
4
Min.
Min.
3
2
Input Voltage (V)
1
0
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 12B. Logic "1" (HIN) & Logic "0" (LIN)
Input Voltage vs Voltage
4
3.2
2.4
1.6
Max .
Input Voltage (V)
0.8
0
10 12 14 16 18 20
Vcc Supply Voltage (V)
Figure 13A. Logic "0"(HIN) & Logic "1"(LIN)
Input V oltage vs T emperature
1
0.8
0.6
0.4
0.2
M ax.
High Level Output Voltage (V)
0
-50 -25 0 2 5 50 75 100 125
T emperature (oC)
Figure 14A. High Level Output
Figure 13B. Logic "0"(HIN) & Logic "1"(LIN)
Input V oltage vs V oltage
1
0.8
0.6
0.4
0.2
Max.
High Level Output Voltage (V)
0
10 12 14 16 18 20
Vcc Supply Voltage (V)
Figure 14B. High Level Output vs Voltage
vs Temperature
8 www.irf.com
IR2103
(S) & ( PbF)
1
0.8
0.6
0.4
0.2
Low Level Output Voltage (V)
Max.
0
-50 -25 0 25 50 75 100 125
T emperature (oC)
Figure 15A. Low Level Output
vs T emperature
500
400
300
200
100
Max.
0
Offset Supply Leakge Current (µA)
-50 -25 0 25 50 75 100 125
T emperature (oC)
1
0.8
0.6
0.4
0.2
Max .
Low Level Output Voltage (V)
0
10 12 14 16 18 20
Vcc Supply Voltage (V)
Figure 15B. Low Level Output vs V oltage
500
400
300
200
Max.
100
0
Offset Supply Leakge Current (µA)
0 200 400 600 800
VB Boost Voltage (V)
Figure 16A. Offset Supply Current
Figure 16B. Offset Supply Current vs V oltage
vs T emperature
150
120
90
60
Max.
30
VBS Supply Current (µA)
0
Typ.
-50-250 255075100125
T emperature (oC)
Figure 17A. VBS Supply Current
150
120
90
60
Max .
30
VBS Supply Current (µA)
Typ.
0
10 12 14 16 18 20
VBS Floating Supply Voltage (V)
Figure 17B. VBS Supply Current vs V oltage
vs Temperature
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IR2103
(S) & ( PbF)
700
600
500
400
Max.
300
200
100
VCC Supply Current (µA)
Typ.
0
-50-25 0 25 50 75100125
T emperature (oC)
Figure 18A. Vcc Supply Current
vs Temperature
30
25
20
15
Max.
10
Max
5
Typ.
Logic “1” Input Current (µA)
0
-50 -25 0 25 50 75 100 125
T emperature (oC)
700
600
500
400
300
M ax.
200
100
VCC Supply Current (µA)
Typ.
0
10 12 14 16 18 20
Vcc Supply Voltage (V)
Figure 18B. Vcc Supply Current vs Voltage
30
25
20
15
M ax.
10
5
Logic “1” Input Current (µA)
Typ.
0
10 12 14 16 18 20
Vcc Supply Voltage (V)
Figure 19A. Logic "1" Input Current
vs T emperature
5
4
3
2
Max.
1
Logic “0” Input Current (µA)
0
-50 -25 0 25 50 75 100 125
T emperature (oC)
Figure 20A. Logic "0" Input Current
vs T emperature
Figure 19B. Logic "1" Input Current
vs Voltage
5
4
3
2
Max .
1
Logic “0” Input Current (µA)
0
10 12 14 16 18 20
Vcc Supply Voltage (V)
Figure 20B. Logic "0" Input Current
vs V oltage
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IR2103
(S) & ( PbF)
11
Max.
10
Typ.
Typ.
9
Min.
8
7
VCC UVLO Threshold +(V)
6
-50 -25 0 25 50 75 100 125
T emperature (
o
C)
Figure 21A. Vcc Undervoltage Threshold(+)
vs Temperature
500
400
300
200
100
Output Source Current (mA)
Typ.
Min.
0
-50 -25 0 2 5 50 75 100 125
T emperature (oC)
11
10
Max.
9
Typ.
Typ.
8
7
Min.
VCC UVLO Threshold -(V)
6
-50 -25 0 25 50 75 100 125
T emperature (oC)
Figure 21B. Vcc UndervoltageThreshold (-)
vs T emperature
500
400
300
200
Typ.
100
Output Source Current (mA)
0
10 12 14 16 18 20
Min.
VBIAS Supply Voltage (V)
Figure 22A. Output Source Current vs
Temperature
700
600
Typ.
500
400
300
Min.
200
100
Output Sink Current (mA)
0
-50-25 0 255075100125
T emperature (oC)
Figure 23A. Output Sink Current
vs T emperature
Figure 22B. Output Source Current
vs Voltage
700
600
500
400
Typ.
300
200
Min.
100
Output Sink Current (mA)
0
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 23B. Output Sink Current
vs Voltage
www.irf.com 11
IR2103
(S) & ( PbF)
Case outlines
A
E
D B
5
87
6
6X
0.25 [ . 010 ]
65
H
4312
0.25 [ . 010 ] A
e
8X b
e1
A1
A
CAB
NOTES:
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONT ROLLING DIMENSION: MILLIMETER
3. D IMENSIONS ARE SHOW N IN MIL LIMETERS [INCHES] .
4. OUTLINE CONFORMS TO JEDEC OUT LINE MS-012AA.
C
0.10 [ . 004 ]
8-Lead PDIP
6.46 [. 2 55]
3X 1.27 [. 05 0]
y
8-Lead SOIC
01-3003 01
DIM
FOOTPRINT
8X 0.72 [. 02 8]
8X 1.78 [. 07 0]
MIN MAX
.0532
A
A1
b
c .0075 .0098 0.19 0.25
D
E
e
e1
H
K
L
y
.0688
.0040
.0098
.020
.013
.1968
.189
.1574
.1497
.050 BASI C
.025 BASIC 0.635 BASIC
.2284
.2440
.0099
.0196
.016
.050
0°
K x 4 5°
8X L
8X c
7
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXC EED 0.15 [.006].
6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXC EED 0.25 [.010].
7 DIMENSION IS THE LE NGT H OF LEAD FOR SOLD ERING TO
A SUBSTRATE.
01-0021 11
8°
01-6014
(MS-001AB)
MILLIMETERSINC HE S
MIN MAX
1.35
1.75
0.10
0.25
0.33
0.51
4.80
5.00
3.80
4.00
1.27 BASI C
5.80
6.20
0.25
0.50
0.40
1.27
0°
8°
01-6027
(MS-012AA)
12 www.irf.com
IR2103
LEADFREE PART MARKING INFORMATION
(S) & ( PbF)
Part number
Date code
Pin 1
Identifier
?
MARKING CODE
Lead Free Released
P
Non-Lead Free
Released
IRxxxxxx
YWW?
ORDER INFORMATION
Basic Part (Non-Lead Free)
8-Lead PDIP IR2103 order IR2103
8-Lead SOIC IR2103S order IR2103S
IR logo
?XXXX
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
Per SCOP 200-002
Leadfree Part
8-Lead PDIP IR2103 order IR2103PbF
8-Lead SOIC IR2103S order IR2103SPbF
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 4/2/2004
www.irf.com 13
This product has been qualified per industrial level
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