INVENTEC S11D Schematic

5

D D

4

3

2

1

Inventec Corporation
R&D Division

C C

Board name : Mother Board Schematic
Project : S11D (Santa Rosa)

Version : 0.3

B B

A A

5

Initial Date : OCT 27 , 2006

4

3

Inventec Corporation

Inventec Corporation

Inventec Corporation

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

<OrgAddr4>

<OrgAddr4>

<OrgAddr4>

TEL:[phone]

TEL:[phone]

TEL:[phone]

Title

Title

Title

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, May 23, 2007

Wednesday, May 23, 2007

2

Wednesday, May 23, 2007

1

Title

Title

Title

1

1

1

0.3

0.3

0.3

43

43

43

8

7

6

1. Schematic Page Description :

Santa Rosa Schematic Ver : 0.1

5

4

3

2

1

D D

1. Title

2. Schematic Page DESCR

3. Block Diagram

4. Annotations

5. Schematic Modify

6. Timing Diagram

7. DDRII Layout Guideline

8. Merom Processor(1/2)

9. Merom Processor(2/2)

10. CPU Core Power

11. CPU Thermal

12. Crestline Host(1/6)

13. Crestline DMI/Graph(2/6)

C C

14. Crestline DDRII(3/6)

15. Crestline Power(4/6)

16. Crestline Power(5/6)

17. Crestline Ground(6/6)

18. Clock Generator

19. DDRII SDRAM SO-DIMM0

20. DDRII SDRAM SO-DIMM1

21. ICH8M CPU/IDE/SATA(1/4)

22. ICH8M PCI/PCIE/DMI/USB(2/4)

23. ICH8M GPIO(3/4)

24. ICH8M Power/GND(4/4)

25. LCD&CRT

26. TV Connector

27. IDE&SATA

28. I/O Board CN(MB)

29. LAN (88E8055B0)

30. USB&Bluetooth Connector

31. KBC ITE8512F

32. Audio Codec ALC262/AMP

33. Audio Jack

34. DVI Transmitter Sil1364

35. Super I/O

36. Docking Connector

37. Adaptor in/Charge

38. 5VLA/5VA/3VA

39. 3VS/5VS/1.5VS/1.05VS

40. 1.25VS/1.8V

41. GPU_Core

42. Dual Battery

43. WLAN&New Card&USB Board

44. 3G&MDC&Cardreader Board

45. LED&Glide Pad Board

B B

2. PCI & IRQ & DMA Description :

IDSEL
AD17

AD27
AD29

IRQA
IRQB
IRQC
IRQD

BUSMASTER

A A

REQ
REQ0 / GNT0
REQ1 / GNT1
REQ2 / GNT2
REQ3 / GNT3
REQ4 / GNT4

CHIP

CHIPPCIINT

CHIP

Inventec Corporation

Inventec Corporation

Inventec Corporation

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

<OrgAddr4>

<OrgAddr4>

<OrgAddr4>

TEL:[phone]

TEL:[phone]

TEL:[phone]

Title

Title

Title

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Schematic Page DESCR

Schematic Page DESCR

Schematic Page DESCR

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, May 23, 2007

Wednesday, May 23, 2007

8

7

6

5

4

3

2

Wednesday, May 23, 2007

2

2

2

1

0.3

0.3

0.3

43

43

43

8

7

6

5

4

3

2

1

3. Block Diagram :

CPU

D D

LCD

P.25

CRT

P.25

P.11

S-OUT

P.26

Docking

P.36

LVDS

TVO

RGB_CRT RGB

RGB_DOCK

FAN

Thermal

G784

CRT_SW

P.36

Thermal

uFCPGA 478pin

Merom

P.8-9P.11

FSB 1.05V
667/800MHz

MCH

965GM/GML
FCBGA 1299pin

35mmx35mm

Crestline GM

P.12-17

DMI x4

DDR2 1.8V
533/667MHz

DDR2 1.8V
533/667MHz

SODIMM0

P.19

SODIMM1

P.20

PLL

ICS9LPRS365AGLF

P.18

166MHz+/­100MHz+/­48MHz
33MHz
14MHz
27MHz/96MHz+/-

x2
x8
x1
x7
x1
x1

RJ45

ICH

C C

HDD

SATA 150

P.27

ODD

PATA 100

P.27

mBGA 676pin

ICH8M

31mmx31mm

PCI-Express x1 2.5GHz

PCI-Express x1 2.5GHz

PCI-Express x1 2.5GHz

PCI-Express x1 2.5GHz

PCI 3.3V 33MHz

GbE

88E8055

Port#2

P.29

P.29

Express
Card

Port#1

P.43

MiniCard #1

UMTS/Robson

Port#4

P.44

SIM Slot

P.28

MiniCard #2

WLAN/Robson

Port#3

P.43

Cardreader

GL827

PMU&KBC

ITE8512F

P.31

PS/2

Glide Pad

Flash
ROM

P.44

P.28P.44

Docking

P.36

KB

P.31

P.45

P.31

4 IN 1

Slot

P.44

IntMic
Stereo

P.33

Analog In

P.33

Super I/O

IT8305E

4

Out

Out

Serial port

Parallel port

Audio
Codec

ALC262

P.32

Docking

Out

Out

Docking

IN

P.36

IN

80Port

P.43P.35

P.36

3

AMP

P.P32

2

SPK

P.33

Analog Out

P.33

Inventec Corporation

Inventec Corporation

Inventec Corporation

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

<OrgAddr4>

<OrgAddr4>

<OrgAddr4>

TEL:[phone]

TEL:[phone]

TEL:[phone]

Title

Title

Title

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Block Diagram

Block Diagram

Block Diagram

Wednesday, May 23, 2007

Wednesday, May 23, 2007

Wednesday, May 23, 2007

43

3

43

3

43

3

1

0.3

0.3

0.3

USB0USB1USB2USB3

System1System2System3WLAN

P.43P.30P.30P.43

EHCI#1

B B

USB 2.0/1.1

Support
S0~S3 state

USB4USB5

Docking

USB9

Bluetooth

P.30

A A

8

Web Cam

7

UMTS

P.44P.36

USB 2.0/1.1

USB6USB7USB8

New CardCardreader

P.43P.44P.25

6

EHCI#2

Support
S0~S2 state

P.21-24

HDA 24MHz

MDC1.5 RJ11

LPC 3.3V 33MHz

SPI

5

8

7

6

5

4

3

2

1

4. Net name Description :

Voltage Rails

DCIN
+5VLA 5.0V always on power rail by LATCH or ACIN

D D

+3VA 3.3V always on power rail by ECPWON
+5VS

+1.8VS 1.8V switched power rail by SLP_S3#_3R
VCC_CORE

+1.05VS
+1.25VS 1.25V switched power rail by SLP_S3#_3R
+1.5VS

Primary DC system power supply

5.0V always on power rail by ECPWON+5VA

5.0V switched power rail by SLP_S3#_3R

3.3V switched power rail by SLP_S3#_3R+3VS

Core Voltage for CPU

1.05V power rail for AGTL+ termination/Core for GMCH by SLP_S3#_3R

1.5V power rail for CPU PLL/DMI;PCIE;DDRII DLLs for GMCH/Core;PCIE

Power Rail

VCC_CORE

+1.05VS

+1.5VS

for ICH8m by SLP_S3#_3R

+1.8V

0.9VDDT_DDRII

Part Naming Conventions

C
CN

C C

D
F
L
Q
R
RP
U
Y

Capacitor

=
=

Connector
Diode

=
=

Fuse
Inductor

=

Transistor

=

Resistor

=

Resistor Pack

=

Arbitrary Logic Device

=

Crystal and Osc

=

1.8V power rail for DDRII by SLP_S5#_3R

0.9V DDRII Termination Voltage by SLP_S3#_3R

+1.8V

0.9VDDT_DDRII:DDRII Terminator:
+2.5VS

+3VS

Net Name Suffix

#=

Active Low signal

5. Board Stack up Description

PCB Layers

B B

Layer 1
Layer 2
Layer 3

Component Side, Microstrip signal Layer
Ground Plane
Stripline Layer

Power PlaneLayer 4
Layer 5 Stripline Layer
Layer 6
Layer 7
Layer 8

Host Clock
PCI-E Clock
DDR2 CLK

A A

DDR2 Strobe
DMI Bus
PCIE Bus
SDVO
SATA
USB
LVDS
Lan

Differential Impedance for Microstrip(5-mils) Differential Impedance for Stripline(4-mils)

95 ohm +/- 20% 100 ohm +/- 20%
95 ohm +/- 20% 100 ohm +/- 20%
70 ohm +/- 20% 70 ohm +/- 20%
85 ohm +/- 20%

95 ohm +/- 20%
95 ohm +/- 20% 100 ohm +/- 20%
95 ohm +/- 20%
90 ohm +/- 20%

95 ohm +/- 20% 100 ohm +/- 20%

8

Stripline Layer

Ground Plane

Solder Side,Microstrip signal Layer

90 ohm +/- 20%
100 ohm +/- 20%95 ohm +/- 20%
100 ohm +/- 20%

100 ohm +/- 20%
95 ohm +/- 20%
100 ohm +/- 20%

7

6

5

1.8VS DVI: Sil1364

+3VA

+5VS

+5VA USB: x 3 ports

+5VLA

4

Destination

HFM:

Merom

LFM:
Merom: AGTL+ termination
965GM: Core
965GM: AGTL+ termination
ICH8m:
Merom PLL
965GM: PCIE
965GM: LVDS
965GM: TVDAC
965GM: Various PLLS analog supply
965GM: DDR DLLS,DDRII,FSB HSIO 1.885A1.425V~1.5V~1.575V
ICH8m:
ICH8m:
ICH8m:
ICH8m:
Mini Card:
Express Card:
965GM: DDRII System Memory 3.1A
SO-DIMM:

965GM: PCIE analog
965GM: LVDS analog
965GM: LVDS I/O
965GM: CRT DAC

965GM: HV CMOS
965GM: TVDAC analog
ICH8m:
ICH8m:
ICH8m:
ICH8m:
ICH8m:
Mini Card: UMTS
Express Card:
CLK Generator: ICS9LPRS365AGLF 400mA3.135V~3.3V~3.465V
Mini Card: WirelessLan
Bluetooth:
Super I/O: IT8305E
Azalia Codec: ALC262
Azalia MDC:
HDD: SATA

Thermal Sensor:
Lan: Marvell 88E8055B0
Azalia MDC:
EC: ITE8512F
ICH8m: RTC
Flash ROM: BIOS
LCD:
Cardreader: GL827
Azalia Codec: ALC262
FAN:
HDD: SATA
ODD: PATA
Audio AMP: G1432
Woofer AMP: None
Inverter:

Control Power

3

Voltage

1.3319V~1.4375V~1.4591V

0.9221V~0.9625V~0.9739V

0.997V~1.05V~1.102V

1.0V~1.05V~1.1V

0.9475V~1.05V~1.1025V

1.425V~1.5V~1.575V

1.425V~1.5V~1.575V

1.425V~1.5V~1.575V

1.425V~1.5V~1.575V

1.425V~1.5V~1.575V

1.7V~1.8V~1.9V

0.855V~0.9V~0.945V 1.0A

2.32V~2.5V~2.625V

2.375V~2.5V~2.625V

2.375V~2.5V~2.625V

2.32V~2.5V~2.625V

3.135V~3.3V~3.465V

3.135V~3.3V~3.465V

3.0V~3.3V~3.6V

3.0V~3.3V~3.6V 1.0A

3.0V~3.3V~3.6V

4.75V~5.0V~5.25V

4.75V~5.0V~5.25V

5VA 1.5A

2

S0 Current

36A

2.5A

4.6A

1.4A

120mA

1.5A
60mA
24mA
320mA

2mA
10mA
60mA
70mA

40mA
120mA

Max: 1.0A ; R/W: 460mA ; STDBY: 70mA
Max: 1.8A ; R/W: 900mA ; STDBY: 45mA

Inventec Corporation

Inventec Corporation

Inventec Corporation

<OrgAddr4>

<OrgAddr4>

<OrgAddr4>
Title

Title

Title

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, May 23, 2007

Wednesday, May 23, 2007

Wednesday, May 23, 2007

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan
TEL:[phone]

TEL:[phone]

TEL:[phone]

ANNOTATIONS

ANNOTATIONS

ANNOTATIONS

4

4

4

1

0.3

0.3

0.3

43

43

43

5

4

3

2

1

6.Schematic modify Item and History :

0.1 Modify

D D

C C

B B

A A

Inventec Corporation

Inventec Corporation

Inventec Corporation

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

<OrgAddr4>

<OrgAddr4>

<OrgAddr4>

TEL:[phone]

TEL:[phone]

TEL:[phone]

Title

Title

Title

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Schematic Modify

Schematic Modify

Schematic Modify

Wednesday, May 23, 2007

Wednesday, May 23, 2007

Wednesday, May 23, 2007

5

5

1

5

0.3

0.3

0.3

43

43

43

5

4

SYSTEM POWER ON/OFF SEQUENCE

3

2

1

Power on/off sequence AC insert(First)

Power on sequence Power off sequence

SW OFF:

D D

RTCVCC

5VLA

5VAUXON

3VA,5VA

5VA must be powered up before 3VA, or after 3VA within 0.7V

10ms

1.5VA,2.5VA

PWR_SWIN#

SW ON:

RSMRST#

PWR_BTN#

SUSB#

SUSC#

1.8V

5VS,3VS

1.5VS,2.5VS

C C

0.9VS_DIMM

VR_ON

+VCCP

VCCP_PWRGD

VCORE_GD

CPU_PWRGOOD

ALL_SYSPWRGD

PLT_RST#

RTCVCC

3VLA,5VLA

PWR_SWIN#

LATCH_ON

3VA,5VA

1.5VA,2.5VA



MRST#

PWR_BTN#

SUSB#

SUSC#

1.8V

1.5VS,2.5VS

0.9VS_DIMM

VR_ON

+VCCP

VCCP_PWRGD

VCORE_GD

CPU_PWRGOOD

ALL_SYSPWRGD

PLT_RST#

Power on/off sequence AC insert(S4)

Power on sequence Power off sequence

RTCVCC

B B

3VLA,5VLA

5VAUXON

3VA,5VA

PWR_SWIN#

1.5VA,2.5VA

RSMRST#

PWR_BTN#

SUSB#

SUSC#

1.8V

5VS,3VS

1.5VS,2.5VS

0.9VS_DIMM

A A

VR_ON

+VCCP

VCCP_PWRGD

VCORE_GD

CPU_PWRGOOD

ALL_SYSPWRGD

PLT_RST# PLT_RST#

5

4

RTCVCC

3VLA,5VLA

PWR_SWIN#

LATCH_ON

3VA,5VA

1.5VA,2.5VA

RSMRST#

PWR_BTN#

SUSB#

SUSC#

1.8V_DIMM

5VS,3VS

1.5VS,2.5VS

0.9VS_DIMM

VR_ON

+VCCP

VCCP_PWRGD

VCORE_GD

CPU_PWRGOOD

ALL_SYSPWRGD

Battery only Power on/off sequence

Power on sequence Power off sequence

5VS,3VS

Suspend resume sequence(S3)

Power on sequence Power off sequence

3

Inventec Corporation

Inventec Corporation

Inventec Corporation

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

<OrgAddr4>

<OrgAddr4>

<OrgAddr4>

TEL:[phone]

TEL:[phone]

TEL:[phone]

Title

Title

Title

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Timing Diagram

Timing Diagram

Timing Diagram

Wednesday, May 23, 2007

Wednesday, May 23, 2007

Wednesday, May 23, 2007

6

6

1

6

0.3

0.3

0.3

43

43

43

5

8. Layout Guideline :

4

3

2

1

Crestline DDRII Layout Guidelines

DDRII Signal Groups

Group Signal Name

D D

Data

M_A_DQ[63..0]/M_B_DQ[63..0]
M_A_DM[7..0]/M_B_DM[7..0]
M_A_DQS[7..0]/M_A_DQS#[7..0]
M_B_DQS[7..0]/M_B_DQS#[7..0]

M_A_A[13..0]/M_B_A[13..0]Address
M_A_BS[2..0]/M_B_BS[2..0]
M_A_RAS#/M_B_RAS#
M_A_CAS#/M_B_CAS#
M_A_WE#/M_B_WE#

M_CS#[3..0]Control
M_CKE[3..0]
M_ODT[3..0]

Clock M_CLK_DDR[3..0]

M_CLK_DDR#[3..0]
SA_RCVEN#/SB_RCVEN#FeedBack

CLK group : M_CLK_DDR[3..0],M_CLK_DDR#[3..0]

GMCH

P1P1L0L0L1L1L2L2S1

C C

Topology
Reference Plane
Single Ended Trace Impedance
Differential Mode Impedance
Minimum Serpentine Spacing Inner Layer : 12 mils

Package Length Range - P1 350 mils ~ 625 mils
Min. Serpentine Spacing 25 mils
Trace Length Limit - L0 (MS)

Trace Length Limit - L1 (SL)
(Breakout length segment)

B B

Stub Length S1-Stub from via to SO-DIMM Max = 200 mils (Breakin)
MB Length Limits - L0 + L1 + L2 + S1 Min = 500 mils

Maximim Via Count 2 (Per side)
SCK to SCK# Length Matching Match total length to within 5 mils
Clock to Clock Length Match

(Total Length)
Breakout Exceptions (Reduce geometries
for GMCH break-out region)

Breakin Exceptions (Reduce geometries
for SO-DIMM break-in region)

Feedback group :
SA_RCVENIN#],SA_RCVENOUT#,SB_RCVENIN#],SB_RCVENOUT#

These signals are routed internally on the GMCH package and don't require any
routing on the MB. As a result, can be left as NC.

A A

4/4/12 7/4/16 8/5/15

Escape

Breakout Breakin

5

SLMS SL MS

Length Matching and Length Formulas

Signal Group Minimum Length Maximum Length

Control-to-Clock
Command-to-Clock
Strobe-to-Clock
Data-to-Strobe

Clock - 1.0"
Clock - 1.0"
Clock - 0.5"
Strobe - 220mils

SO-DIMM

S1

Differential Pair Point-to-Point
Ground
42 +/- 15%
70 +/- 20%

Outer Layer : 15 mils

Nominal Trace Width : 5mils, 4mils
Length Limit: Max = 50 mils (Escape)
Min. Trace Spacing : 5mils, 4mils
Length Limit: Max = 700 mils
Nominal Trace Width : 4mils
Min. Trace Spacng (pair) : 4mils
Min. Trace Spacng (Other) : 12 mils

Max = 4000 mils
Max = 4500 milsTotal Length - P1 + L0 + L1 + L2 + S1
Total Length for Channel A : X0

Total Length for Channel B : X1

Match Channel A clocks to X0 +/- 20mils
Match Channel A clocks to X1 +/- 20mils

Inner Layer : 4/12 mils to other DDR2
Outer Layer : 5/15 mils to other DDR2

Max. breakout length is 500 mils
CK to CK# spacing rule waived at

connector spacing of 15 mils to
other DDR2

Max. breakin length is 200 mils

Clock - 0.0"
Clock + 1.0"
Clock + 1.0"
Strobe - 180mils

4

Control group : SM_CKE[3..0],SM_CS#[3..0],SM_ODT[3..0]

7/4/16

GMCH

Escape

P1

L0

MS SL/MS

4/4/12

L1

Breakout
SL

8/5/15

L2

L3

SL/MS

S1

MS

Vtt

SO-DIMM

Topology
Reference Plane
Characteristic Trace Impedance
Nominal Trace Width

Minimum CTRL Trace Spacing

Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2
Package Length P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 -

From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 ­From GMCH die to SO-DIMM pad

Parallel Termination Resistor 56 +/- 5%
Maximim Via Count
CTRL to SCK/SCK# Length Matching

(Total Length including package)
Breakout Exceptions (Reduce geometries
for GMCH break-out region)

Command group :
SA_MA[13..0],SB_MA[13..0],SA_BS[2..0],SB_BS[2..0],SA_RAS#,
SB_RAS#,SA_CAS#,SB_CAS#,SA_WE#,SB_WE#

GMCH

P1

Escape

L0

4/4

Breakout

Point-to-Point with parallel termination
Ground
55 +/- 15%
Inner Layer : 4 mils

Outer Layer : 5 mils
Inner Layer : 8 mils

Outer Layer : 10 mils
Inner Layer : 12 mils

Outer Layer : 15 mils
25 mils
750 mils +/- 200 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils

Max = 4500 mils
Max = 5000 mils

Max = 1500 milsTrace Length L3

3
(CLK-1.0") </= CTRL </= (CLK-0.0")

Inner Layer : 4 mils spacing allowed
Outer Layer : 5 mils spacing allowed
Max. breakout length is 500 mils

4/6,5/10

4/6,5/10

L1

L2

SL/MS

SL/MSMS SL

S1

MS

L3

Vtt

SO-DIMM

Topology
Reference Plane
Characteristic Trace Impedance
Nominal Trace Width

Minimum CMD Bus Trace Spacing

Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2
Package Length P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 -

From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 ­From GMCH die to SO-DIMM pad
Trace Length L3

Parallel Termination Resistor
Maximim Via Count
CTRL to SCK/SCK# Length Matching

(Total Length including package)
Breakout Exceptions (Reduce geometries
for GMCH break-out region)

Point-to-Point with parallel termination
Ground
55 +/- 15%
Inner Layer : 4 mils

Outer Layer : 5 mils
Inner Layer : 6 mils

Outer Layer : 10 mils
Inner Layer : 12 mils

Outer Layer : 15 mils
25 mils
750 mils +/- 350 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils

Max = 4500 mils
Max = 5000 mils

Max = 1500 mils
56 +/- 5%
3
(CLK-1.0") </= CMD </= (CLK+1.0")

Inner Layer : 4 mils spacing allowed
Outer Layer : 5 mils spacing allowed
Max. breakout length is 500 mils

3

Data group : SA_DQ[63..0],SB_DQ[63..0],SA_DM[7..0],SB_DM[7..0]

4/4

L1

Breakout

4/6

L2

S1

GMCH

Escape

P1 L0

MS SLSL MS

SO-DIMM

Topology
Reference Plane
Characteristic Trace Impedance
Nominal Trace Width

Minimum DQ Bus Trace Spacing

Minimum Serpentine Spacing Same as DQ-to-DQ routing
Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2
Package Length P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 -

From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 ­From GMCH die to SO-DIMM pad
Trace Length L3

Maximim Via Count
DQ/DM to DQS Length Matching

(Total Length including
package)

Breakout Exceptions (Reduce geometries
for GMCH break-out region)

Point-to-Point
Ground
55 +/- 15%
Inner Layer : 4 mils

Outer Layer : 5 mils
Inner Layer : 6 mils

Outer Layer : 8 mils

Inner Layer : 12 mils
Outer Layer : 15 mils

25 mils
750 mils +/- 350 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils

Max = 4500 mils
Max = 5000 mils

Max = 1500 mils
2
Match DQ/DM to [SDQS - 200mils]

+/- 20mils, per byte lane
Inner Layer : 4 mils spacing allowed

Outer Layer : 5 mils spacing allowed
Max. breakout length is 500 mils

Data Strobe group : SA_DQS[7..0],SA_DQS[7..0]#,SB_DQS[7..0],SB_DQS[7..0]#

SO-DIMM

5/5/10

4/4/12

GMCH

P1
P1

Topology
Reference Plane
Single Ended Trace Impedance
Differential Mode Impedance
Nominal Trace Width

Nominal DQS to DQS# Spacing
(edge to edge)

Minimum Serpentine Spacing

Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2
Package Length Range - P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 -

From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 ­From GMCH die to SO-DIMM pad
Maximim Via Count

DQS to DQS# Length Matching
Clock to Clock Length Match

(Total Length include package)
Breakout Exceptions (Reduce geometries
for GMCH break-out region)

Breakin Exceptions (Reduce geometries
for SO-DIMM break-in region)

Escape

L0
L0

4/4/8

L2

L1

L2

L1

Breakout
SL SL MS

Differential Pair Point-to-Point
Ground
55 +/- 15%
85 +/- 20%
Inner Layer : 4 mils

Outer Layer : 5 mils
Inner Layer : 4 mils

Outer Layer : 5 mils
Inner Layer : 12 milsMinimum DQS to DQ Spacing

Outer Layer : 15 mils
Inner Layer : 8 mils

Outer Layer : 10 mils
Inner Layer : 12 mils

Outer Layer : 15 mils
25 mils
750 mils +/- 350 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils

Max = 4500 mils
Max = 5000 mils

2 (Per side)
Match total length to within 5 mils
(CLK-0.5") </= DQS </= (CLK+1.0")

Inner Layer : 8 mils to other DDR2
Outer Layer : 10 mils to other DDR2
Max. breakout length is 500 mils

DQS to DQS# spacing rule
waived at connector spacing of
10 mils to other DDR2

Max. breakin length is 200 mils

2

S1
S1

Breakin

Inventec Corporation

Inventec Corporation

Inventec Corporation

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

<OrgAddr4>

<OrgAddr4>

<OrgAddr4>

TEL:[phone]

TEL:[phone]

TEL:[phone]

Title

Title

Title

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

DDRII Layout Guideline

DDRII Layout Guideline

DDRII Layout Guideline

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, May 23, 2007

Wednesday, May 23, 2007

Wednesday, May 23, 2007

1

43

7

43

7

43

7

0.3

0.3

0.3

A

CN8A

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14

H_A#[35..3]

H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

4 4

3 3

H_A#[35..3]12

H_ADSTB#012

H_REQ#[4..0]12

H_ADSTB#112

H_A20M#21

H_FERR#21

H_IGNNE#21

H_STPCLK#21

H_INTR21

H_NMI21

H_SMI#21

H_A#[35..3]

H_REQ#[4..0]

H_A#[35..3]12

No stub on H_STPCLK test point

CN8A

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

SCKT CPU 478P PZ4782K-274M-41 FOXCONN

SCKT CPU 478P PZ4782K-274M-41 FOXCONN

6026B0056801

6026B0056801

Rout to TP via and place gnd via w/in 100mils

A#[32-39], APM#[0-1]:Leave escape routing on for future functionality

ADDR GROUP 0 ADDR GROUP 1

ADDR GROUP 0 ADDR GROUP 1

THERMAL

THERMAL

PROCHOT#

THERMTRIP#

ICH

ICH

RESERVED

RESERVED

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

LOCK#

CONTROL

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TRST#

DBR#

XDP/ITP SIGNALS

XDP/ITP SIGNALS

THERMDA
THERMDC

H CLK

H CLK

BCLK[0]
BCLK[1]

INIT#

TDO

B

H1
E2
G5

H5
F21
E1

F1

H_IERR#

D20
B3

H4
C1

F3
F4
G3
G2

G6

HIT#

E4
AD4

AD3
AD1
AC4
AC2
AC1
AC5

TCK

AA6

TDI

AB3
AB5

TMS

AB6
C20

D21
A24
B25

C7

A22
A21

R386 56-5%-1/16W-0402R386 56-5%-1/16W-0402

R390 SHORT-0402-5MILR390 SHORT-0402-5MIL

XDP_BPM#5
XDP_TCK
XDP_TDI

XDP_TMS
XDP_TRST#
XDP_DBRESET#

H_ADS# 12
H_BNR# 12

H_BPRI# 12
H_DEFER# 12

H_DRDY# 12
H_DBSY# 12

H_BREQ#0 12

H_INIT# 21

H_LOCK# 12

H_CPURST# 12
H_RS#0 12
H_RS#1 12
H_RS#2 12
H_TRDY# 12

H_HIT# 12
H_HITM# 12

1.05VS9,12,13,15,16,18,21,24,39

R385

R385
75-1%-1/16W-0402

75-1%-1/16W-0402

H_PROCHOT# 10
H_THERMDA 11
H_THERMDC 11

PM_THRMTRIP# 13,21

CLK_CPU_BCLK 18
CLK_CPU_BCLK# 18

C

1.05VS 9,12,13,15,16,18,21,24,39

D

Topology : FERR#

VCCP

L4

CPU

Rtt

ICH7m

CPU IMVP6

L2+L1 L3 Strip-line

L2

VCCP L1

Rtt

VCCP

Rtt

0.5" - 12"L1

0.5" - 6.5"

L2
0" - 3.0" Micro-strip0.5" - 12"
0" - 3.0"

Topology : PWRGOOD

ICH7m

L1

Transmission Line
Micro-strip

0.5" - 12"

0.5" - 12" Strip-line

CPU

L1

Topology : INTR , NMI , A20M# , DPSLP# , IGNNE# , INIT# , SMI# , STPCLK#

Transmission Line

L1CPU ICH7m

L1

Topology : THERMTRIP#

GMCHL2CPU ICH8m

0.5" - 12" Micro-strip
Strip-line

0.5" - 12"

VCCP

L3

RttL1 L4

Rtt

Rtt Transmission Line
56 +/-5%

Strip-line

56 +/-5%

L3 L4

0.5" - 6.5"

0" - 3.0"
0" - 3.0"

0" - 3.0"
0" - 3.0"

0.5" - 6.5"

Topology : CPUSLP#

Topology : RESET#

L1 L2
1" - 12"
1" - 12" 1" - 6"

L1+L3

1" - 6" 0" - 3.0"

1" - 12"
1" - 12"

Rtt Transmission LineL2L1

70 +/-5%0.5" - 6.5"

GMCH

L3
0" - 3.0"
0" - 3.0"

E

Micro-strip70 +/-5%

Transmission Line

L1CPU

GMCH

0.5" - 12"

L1

L1

Rss
24 +/-5%
24 +/-5%

0.5" - 12"

L1
1" - 6"
1" - 6"

Rtt
56 +/-5%
56 +/-5%

Micro-strip
Strip-line

Transmission LineCPU
Micro-strip
Strip-line

Transmission LineL4
Micro-strip
Strip-line0" - 3.0"

Should be connect to ICH8 and Calistoga without T-ing(no stub)

XDP P/U & P/D

XDP_DBRESET#

XDP_TMS
XDP_TDI
XDP_BPM#5

XDP_TRST#
XDP_TCK

R91 1K-5%-1/16W-0402R91 1K-5%-1/16W-0402

R372 39.2-1%-1/16W-0402R372 39.2-1%-1/16W-0402

R378 150-5%-1/16W-0402R378 150-5%-1/16W-0402

R371 54.9-1%-1/16W-0402R371 54.9-1%-1/16W-0402
R374 649-1%-1/16W-0402R374 649-1%-1/16W-0402

R370 27-5%-1/10W-0603R370 27-5%-1/10W-0603

7/4 MODIFY

3VS 10,11,13,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,34,35,39,40,41

1.05VS 9,12,13,15,16,18,21,24,39

FSB Common Clock Signal Layout Guide :

H_ADS# , H_BNR# , H_BPRI# , H_BR0# , H_DBSY# , H_DEFER# , H_DPWR# , H_DRDY# , H_HIT# , H_HITM# , H_LOCK# ,H_
RS#[2..0] , H_TRDY# , H_CPURST#.

Transmission Line Type Total Trace Length Normal Impedance Spacing (mils)

Strip-line(Int. Layer)

Micro-strip(Ext. Layer)

1.0 ~ 6.5 inch

55+/-15%

W=4 & S=8 mils

W=5 & S=10 mils

H_D#[63..0]12

2 2

H_DSTBN#012

H_DSTBP#012

H_DINV#012

H_D#[63..0]12

1.05VS9,12,13,15,16,18,21,24,39

R379

R379

1K-1%-1/16W-0402

1K-1%-1/16W-0402

R375

R375

2K-1%-1/16W-0402

1 1

2K-1%-1/16W-0402

A

H_DSTBN#112

H_DSTBP#112

H_DINV#112

Zo=55ohm, 0.5" max for GTLREF, Space any other switch
signals away from GTLREF with a minimum of 25mils.

Don't allow the GTLREF routing to create splits or
discontinuities in the reference planes of the FSB signals

H_D#[63..0]

H_D#[63..0]

1K-5%-1/16W-0402_NU

1K-5%-1/16W-0402_NU
R387

R387
R388

R388

1K-5%-1/16W-0402_NU

1K-5%-1/16W-0402_NU
C380

C380

0.1uF 10V 10% 0402 X5R_NU

0.1uF 10V 10% 0402 X5R_NU

CLK_BSEL018

H_TEST2

CN8B

CN8B

H_D#0

E22

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

GTLREF COMP0
H_TEST1

H_TEST4

D[0]#

F24

D[1]#

E26

D[2]#

AD26

AF26

G22

F23

G25

E25

E23

K24

G24

J24

J23
H22
F26
K22
H23

J26
H26
H25

N22
K25
P26
R23
L23

M24

L22

M23

P25
P23
P22
T24
R24
L25
T25
N25
L26

M26

N24

C23
D25
C24

AF1
A26

B22
B23
C21

DATA GRP 0 DATA GRP 1

DATA GRP 0 DATA GRP 1

D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF

MISC

MISC

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

BSEL[0]
BSEL[1]
BSEL[2]

SCKT CPU 478P PZ4782K-274M-41 FOXCONN

SCKT CPU 478P PZ4782K-274M-41 FOXCONN

6026B0056801

6026B0056801

B

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

PSI#

H_D#[63..0]
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#[63..0]
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

R383 27.4-1%-1/16W-0402R383 27.4-1%-1/16W-0402

COMP1

R382 54.9-1%-1/16W-0402R382 54.9-1%-1/16W-0402

COMP2

R373 27.4-1%-1/16W-0402R373 27.4-1%-1/16W-0402

COMP3

R377 54.9-1%-1/16W-0402R377 54.9-1%-1/16W-0402

H_DPRSTP# 10,13,21
H_DPSLP# 21
H_DPWR# 12
H_PWRGD 21
H_CPUSLP# 12
PSI# 10

H_PWRGD rise time :
Max : 15ns

H_D#[63..0] 12

H_DSTBN#2 12
H_DSTBP#2 12
H_DINV#2 12

H_D#[63..0] 12

H_DSTBN#3 12
H_DSTBP#3 12
H_DINV#3 12

Comp0,2 connect with Zo=27.4ohm, make trace
length shorter than 0.5" and width is 18mils.

Comp1,3 connect with Zo=55ohm, make trace
length shorter than 0.5" and width is 5mils

C

FSB Source Synchronous Data Length Variation and Strobe Matching Requirements :

Signals Name

H_D#[15..0] , H_DINV#0
H_D#[31..16] , H_DINV#1 +/- 100 mils
H_D#[47..32] , H_DINV#2
H_D#[63..48] , H_DINV#3

FSB Source Synchronous Data Signal Routing Topology#1 :

Signal Name

H_DINV#[3..0]
H_DATA#[63..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]

FSB Source Synchronous Address Length Variation and Strobe Matching Requirements :

H_A#[16..3] , H_REQ#[4..0]

*** No length matching requirements exist between H_ADSTB#0 and H_ADSTB#1

FSB Source Synchronous Address Signal Routing :

Signal Name

H_A#[35..3]
H_REQ#[4..0]
H_ADSTB#[1..0]

Signals Matching

+/- 100 mils
+/- 100 mils

Transmission Line Type

Strip-line
Strip-line
Strip-line
Strip-line

Signals MatchingSignals Name

+/- 200 mils

Transmission Line Type

Strip-line
Strip-line

D

Strobes associated with the group Strobe-to-Strobe Complement Matching

H_DSTBP#0, H_DSTBN#0
H_DSTBP#1, H_DSTBN#1
H_DSTBP#2, H_DSTBN#2
H_DSTBP#3, H_DSTBN#3

Total Trace Length

0.5 ~ 5.5 inch

0.5 ~ 5.5 inch

0.5 ~ 5.5 inch

0.5 ~ 5.5 inch

Strobes associated with the group

H_ADSTB#0+/- 200 mils
H_ADSTB#1H_A#[35..17]

Total Trace Length Normal Impedance

0.5 ~ 6.5 inch

0.5 ~ 6.5 inch

0.5 ~ 6.5 inch

Normal Impedance

55+/-15%
55+/-15%
55+/-15%
55+/-15%

55+/-15%
55+/-15%
55+/-15%Strip-line

+/- 25 mils+/- 100 mils
+/- 25 mils
+/- 25 mils
+/- 25 mils

Width & Spacing (mils)
Data-to-Data,Strobe-to-strobe Strobe-to-Data

W=4 & S=8 mils
W=4 & S=8 mils
W=4 & S=4 mils
W=4 & S=4 mils

Strobe to Assoc. Address Signal Matching

+/- 200 mils
+/- 200 mils

Width & Spacing (mils)

W=4 & S=8 mils
W=4 & S=8 mils
W=4 & S=12 mils

Inventec Corporation

Inventec Corporation

Inventec Corporation

<OrgAddr4>

<OrgAddr4>

<OrgAddr4>
Title

Title

Title

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, May 23, 2007

Wednesday, May 23, 2007

Wednesday, May 23, 2007

N/A
N/A
W=4 & S=12 mils
W=4 & S=12 mils

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan
TEL:[phone]

TEL:[phone]

TEL:[phone]

Merom Processor(1/2)

Merom Processor(1/2)

Merom Processor(1/2)

E

8

8

8

0.3

0.3

0.3

43

43

43

A

B

C

D

E

Place these inside socket cavity on L8
(North side secondary)

4 4

3 3

VCORE_CPU10

C43

C43

C38

C38

C34

C34

C49

C49

C54

C54

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

Place these inside socket cavity on L1
(North side Primary)

C389 10uF 6.3V 10% 0805 X5RC389 10uF 6.3V 10% 0805 X5R

C409 10uF 6.3V 10% 0805 X5RC409 10uF 6.3V 10% 0805 X5R

C399 10uF 6.3V 10% 0805 X5RC399 10uF 6.3V 10% 0805 X5R

C394 10uF 6.3V 10% 0805 X5RC394 10uF 6.3V 10% 0805 X5R

C405 10uF 6.3V 10% 0805 X5RC405 10uF 6.3V 10% 0805 X5R

North side secondary

C14 T330uF 2V 9m 7343 PANASONIC+C14 T330uF 2V 9m 7343 PANASONIC

C428 T330uF 2V 9m 7343 PANASONIC_NU+C428 T330uF 2V 9m 7343 PANASONIC_NU

C396 T330uF 2V 9m 7343 PANASONIC+C396 T330uF 2V 9m 7343 PANASONIC

+

+

+

2 2

Place these inside socket cavity on
L8 (South side secondary)

C53 10uF 6.3V 10% 0805 X5RC53 10uF 6.3V 10% 0805 X5R

C42 10uF 6.3V 10% 0805 X5RC42 10uF 6.3V 10% 0805 X5R

C33 10uF 6.3V 10% 0805 X5RC33 10uF 6.3V 10% 0805 X5R

C48 10uF 6.3V 10% 0805 X5RC48 10uF 6.3V 10% 0805 X5R

C37 10uF 6.3V 10% 0805 X5RC37 10uF 6.3V 10% 0805 X5R

Place these inside socket cavity on L1
(South side Primary)

C408 10uF 6.3V 10% 0805 X5RC408 10uF 6.3V 10% 0805 X5R

C393 10uF 6.3V 10% 0805 X5RC393 10uF 6.3V 10% 0805 X5R

C388 10uF 6.3V 10% 0805 X5RC388 10uF 6.3V 10% 0805 X5R

C404 10uF 6.3V 10% 0805 X5RC404 10uF 6.3V 10% 0805 X5R

C398 10uF 6.3V 10% 0805 X5RC398 10uF 6.3V 10% 0805 X5R

South side secondary

C429 T330uF 2V 9m 7343 PANASONIC_NU+C429 T330uF 2V 9m 7343 PANASONIC_NU

C350 T330uF 2V 9m 7343 PANASONIC+C350 T330uF 2V 9m 7343 PANASONIC

C351 T330uF 2V 9m 7343 PANASONIC+C351 T330uF 2V 9m 7343 PANASONIC

+

+

+

CN8C

CN8C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

SCKT CPU 478P PZ4782K-274M-41 FOXCONN

SCKT CPU 478P PZ4782K-274M-41 FOXCONN

6026B0056801

6026B0056801

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

C385 0.1uF 10V 10% 0402 X7RC385 0.1uF 10V 10% 0402 X7R

R384 SHORT-0603-PWRR384 SHORT-0603-PWR
R381 SHORT-0603-PWRR381 SHORT-0603-PWR

Close to CPU
pin B26

H_VID0 10
H_VID1 10
H_VID2 10
H_VID3 10
H_VID4 10
H_VID5 10
H_VID6 10

VCORE_CPU10

Route VCCSENSE and VSSSENSE traces
at 27.4 ohms with 50mil spacing.
Place PU and PD within 1 inch of CPU

C392 0.1uF 10V 10% 0402 X7RC392 0.1uF 10V 10% 0402 X7R

C395 0.1uF 10V 10% 0402 X7RC395 0.1uF 10V 10% 0402 X7R

C401 0.1uF 10V 10% 0402 X7RC401 0.1uF 10V 10% 0402 X7R

C402 0.1uF 10V 10% 0402 X7RC402 0.1uF 10V 10% 0402 X7R

C419

C419

0.01uF 16V 10% 0402 X7R

0.01uF 16V 10% 0402 X7R

R16

R16
100-1%-1/16W-0402

100-1%-1/16W-0402

R17

R17
100-1%-1/16W-0402

100-1%-1/16W-0402

160mil

C411 0.1uF 10V 10% 0402 X7RC411 0.1uF 10V 10% 0402 X7R

C443

C443

+

+

T220uF 2V 15m 7343 PANASONIC

T220uF 2V 15m 7343 PANASONIC

1.05VS 8,12,13,15,16,18,21,24,39

Place these inside socket cavity on L8
(North side secondary)

1.5VS16,24,28,39,40

20mil

C418

C418
10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

VCCSENSE 10
VSSSENSE 10

18mil
7mil space

CN8D

CN8D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]

P3

VSS[081]

SCKT CPU 478P PZ4782K-274M-41 FOXCONN

SCKT CPU 478P PZ4782K-274M-41 FOXCONN

6026B0056801

6026B0056801

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

1 1

Inventec Corporation

Inventec Corporation

Inventec Corporation

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

<OrgAddr4>

<OrgAddr4>

<OrgAddr4>

TEL:[phone]

TEL:[phone]

TEL:[phone]

Title

Title

Title

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

A

B

C

D

Date: Sheet of

Merom Processor(2/2)

Merom Processor(2/2)

Merom Processor(2/2)

Wednesday, May 23, 2007

Wednesday, May 23, 2007

Wednesday, May 23, 2007

E

9

9

9

0.3

0.3

0.3

43

43

43

5

D D

2.2K-5%-1/16W-0402

2.2K-5%-1/16W-0402

C C

B B

VCORE_GD23

H_VID09
H_VID19
H_VID29
H_VID39
H_VID49
H_VID59
H_VID69

R339 SHORT-0402-5MILR339 SHORT-0402-5MIL
R333 SHORT-0402-5MILR333 SHORT-0402-5MIL
R332 SHORT-0402-5MILR332 SHORT-0402-5MIL
R328 SHORT-0402-5MILR328 SHORT-0402-5MIL
R324 SHORT-0402-5MILR324 SHORT-0402-5MIL
R321 SHORT-0402-5MILR321 SHORT-0402-5MIL
R313 SHORT-0402-5MILR313 SHORT-0402-5MIL

PSI#8

VR_ON31

H_DPRSTP#8,13,21

PM_DPRSLPVR13,23

8770GND

8770VCC

H_PROCHOT#8

4

2.2uF 10V 10% 0805 X5R

2.2uF 10V 10% 0805 X5R

3VS 8,11,13,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,34,35,39,40,41

R294

R294

R292 0-5%-1/16W-0402R292 0-5%-1/16W-0402
R311 0-5%-1/16W-0402R311 0-5%-1/16W-0402
R304 0-5%-1/16W-0402R304 0-5%-1/16W-0402
R306 0-5%-1/16W-0402R306 0-5%-1/16W-0402

C332

C332

470pF 50V 10% 0402 X7R

470pF 50V 10% 0402 X7R

71.5K 1% 1/10W 0603

71.5K 1% 1/10W 0603
R298

R298

C325

C325

0.22uF 10V 10% 0603 X7R

0.22uF 10V 10% 0603 X7R

R290

R290
10K-5%-1/16W-0402

10K-5%-1/16W-0402

0-5%-1/16W-0402

0-5%-1/16W-0402
R291

R291

TP2TP2

C368

C368

R293

R293

2.2K-5%-1/16W-0402

2.2K-5%-1/16W-0402

8770REF

8770GND

1

R341

R341

10-5%-1/10W-0603

10-5%-1/10W-0603

8770VCC

8770GND

U31

U31

2

PWRGD

1

CLKEN

31

D0

32

D1

33

D2

34

D3

35

D4

36

D5

37

D6

3

PSI

38

SHDN

40

DPRSTP

39

DPRSLPVR

9

CCV

7

TIME

11

REF

18

GND

41

EP

6

THRM

5

VRHOT

4

POUT

MAX8770GTL+ TQFN 40P MAXIM

MAX8770GTL+ TQFN 40P MAXIM

6019B0130201

6019B0130201

8770GND

5VA24,28,30,36,38,39,40,41,43

19

VCC

R363

R363

SHORT-0402-40MIL

SHORT-0402-40MIL

25

TON

VDD

BST1

LX1
DH1
DL1

PGND1

FB

CCI

GNDS

CSN1
CSP1

CSP2
CSN2

DH2
DL2

LX2

BST2

PGND2

C375

C375
10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

R299

R299
200K 1% 1/16W 0402

200K 1% 1/16W 0402

8

R344 2.2-5%-1/10W-0603R344 2.2-5%-1/10W-0603

30
28
29
26
27

12

10K-5%-0603-NTC(NU)

10K-5%-0603-NTC(NU)

5.11K-1%-1/10W-0603(NU)

5.11K-1%-1/10W-0603(NU)
R305

R305

10

C331

C331

470pF 50V 10% 0402 X7R

470pF 50V 10% 0402 X7R

13

8770CSN1

16

8770CSP1

17

8770CSP2

14

8770CSN2

15

21
24
22
20
23

3

R297

R297

3.9K 1% 1/10W 0603

3.9K 1% 1/10W 0603

R301

R301

20K-1%-1/16W-0402

20K-1%-1/16W-0402

R283

R283

8770GND

R343 2.2-5%-1/10W-0603R343 2.2-5%-1/10W-0603

0.22uF 25V 10% 0603 X5R

0.22uF 25V 10% 0603 X5R

0.22uF 25V 10% 0603 X5R

0.22uF 25V 10% 0603 X5R
C370

C370

100-1%-1/16W-0402

100-1%-1/16W-0402
R303

R303

C327

C327
1000pF 50V 10% 0402 X7R

1000pF 50V 10% 0402 X7R

8770GND

R307

R307

100-1%-1/16W-0402

100-1%-1/16W-0402

C342

C342
1000pF 50V 10% 0402 X7R

1000pF 50V 10% 0402 X7R

C369

C369

61

5

789

D

D

4

S

S

2

3

FDMS8690 30V 19.8A 8P

FDMS8690 30V 19.8A 8P

61

5

789

D

D

4

S

S

2

3

VCCSENSE 9

VSSSENSE 9

61

5

789

D

D

4

S

S

2

3

FDMS8690 30V 19.8A 8P

FDMS8690 30V 19.8A 8P

61

5

789

D

D

Q33

Q33

4

S

S

2

3

Q35

Q35

Q38

Q38

FDMS8670S 30V 20A 8P

FDMS8670S 30V 20A 8P

Q31

Q31

FDMS8670S 30V 20A 8P

FDMS8670S 30V 20A 8P

61

5

789

D

D

4

S

S

2

3

FDMS8690 30V 19.8A 8P

FDMS8690 30V 19.8A 8P

61

5

789

D

D

Q37

Q37

4

S

S

2

3

61

5

4

61

5

4

Q36

Q36

0-5%-1/10W-0603_NU

0-5%-1/10W-0603_NU

R606

R606

FDMS8670S 30V 20A 8P

FDMS8670S 30V 20A 8P

C624

C624

8770CSP1
8770CSN1

10UF 25V 10% 1206 X5R

10UF 25V 10% 1206 X5R

789

Q34

Q34

D

D

FDMS8690 30V 19.8A 8P

FDMS8690 30V 19.8A 8P

S

S

2

3

789

R607

R607

D

D

Q32

Q32

FDMS8670S 30V 20A 8P

FDMS8670S 30V 20A 8P

S

S

2

3

C625

C625

2

0.36uH 30A PCMC104T-R36MN

0.36uH 30A PCMC104T-R36MN

R331

R331

2.67K 1% 1/10W 0603

2.67K 1% 1/10W 0603

1000pF 50V 10% 0402 X7R

1000pF 50V 10% 0402 X7R

2.1K 1% 1/10W 0603

2.1K 1% 1/10W 0603

0-5%-1/10W-0603_NU

0-5%-1/10W-0603_NU

1000pF 50V 10% 0402 X7R

1000pF 50V 10% 0402 X7R

8770CSP2
8770CSN2

DCIN

+

C367T5.6uF 25V 100m 3528 SANYO+C367T5.6uF 25V 100m 3528 SANYO

L39

L39

10K-5%-0603-NTC

10K-5%-0603-NTC

R337

R337

C355

C355

0.22uF 10V 10% 0603 X7R

0.22uF 10V 10% 0603 X7R

C329

C329

T5.6uF 25V 100m 3528 SANYO

T5.6uF 25V 100m 3528 SANYO

L37

L37

0.36uH 30A PCMC104T-R36MN

0.36uH 30A PCMC104T-R36MN

R315

R315

2.67K 1% 1/10W 0603

2.67K 1% 1/10W 0603

R314

R314

2.1K 1% 1/10W 0603

2.1K 1% 1/10W 0603

C346

C346

0.22uF 10V 10% 0603 X7R

0.22uF 10V 10% 0603 X7R

R366

R366

DCIN36,37,38,40,41,42,43

C356

C356

10K-5%-0603-NTC

10K-5%-0603-NTC
R365

R365

DCIN36,37,38,40,41,42,43

C344

C344
10UF 25V 10% 1206 X5R

10UF 25V 10% 1206 X5R

+

+

1

VCORE_CPU9

A A

Inventec Corporation

Inventec Corporation

Inventec Corporation

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

<OrgAddr4>

<OrgAddr4>

<OrgAddr4>

TEL:[phone]

TEL:[phone]

TEL:[phone]

Title

Title

Title

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

CPU Core Power

CPU Core Power

CPU Core Power

Wednesday, May 23, 2007

Wednesday, May 23, 2007

Wednesday, May 23, 2007

1

0.3

0.3

0.3

4310

4310

4310

8

D D

7

6

5

4

3

2

1

THERMAL SENSOR

3VS8,10,13,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,34,35,39,40,41

C67

C67

R92

0.1uF 10V 10% 0402 X7R

0.1uF 10V 10% 0402 X7R

10mil

THRM#31

C C

H_THERMDA8

H_THERMDC

H_THERMDC8

R92
10K-5%-1/16W-0402

10K-5%-1/16W-0402

C63

C63

2200pF 50V 5% 0603 C0G

2200pF 50V 5% 0603 C0G

U5

U5

1

VDD

2

DXP

3

DXN

ALERT#

THERM#4GND

G784P81U MSOP 8P

G784P81U MSOP 8P

6019B0221201

6019B0221201

SCLK

SDATA

THRMSCK

8

THRMSDAH_THERMDA

7
6
5

THRMSCK 31
THRMSDA 31

10mil

B B

Fan control

Q4

Q4

FDN338P 20V 1.6A SOT3

FDN338P 20V 1.6A SOT3

5VS24,25,27,28,31,32,33,34,36,39

C96

10uF 10V 10% 0805 X5R

C96

10uF 10V 10% 0805 X5R

0.01uF 16V 10% 0402 X7R

0.01uF 16V 10% 0402 X7R

A A

8

7

6

FANCTL131

S D

S

S

D

C88

C88

1K-5%-1/16W-0402

1K-5%-1/16W-0402

D

G

G

R132

R132

G

R133

R133
0-5%-1/16W-0402

0-5%-1/16W-0402

Q1

Q1

B

NPN PDTC144EU 50V 100mA SOT223

NPN PDTC144EU 50V 100mA SOT223

E C

5

30mil

10-5%-1/16W-0402_NU

10-5%-1/16W-0402_NU

5VS_FAN

R135

R135

CN11

CN11

1

G1

1

G1

2

2

3

FAN_TACH131

C94

3300pF 50V 10% 0402 X7R_NU

C94

3300pF 50V 10% 0402 X7R_NU

C90

1uF 6.3V 10% 0402 X5R_NU

C90

1uF 6.3V 10% 0402 X5R_NU

4

CN 3P 3702-F03C-02R ENTERY

CN 3P 3702-F03C-02R ENTERY

3

6012B0191701

6012B0191701

G2

G2

Inventec Corporation

Inventec Corporation

Inventec Corporation

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

<OrgAddr4>

<OrgAddr4>

<OrgAddr4>

TEL:[phone]

TEL:[phone]

TEL:[phone]

Title

Title

Title

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

3

Date: Sheet of

2

CPU Thermal

CPU Thermal

CPU Thermal

Wednesday, May 23, 2007

Wednesday, May 23, 2007

Wednesday, May 23, 2007

11

11

11

1

0.3

0.3

0.3

43

43

43

10

9

8

7

6

5

4

3

2

1

H H

1.05VS8,9,13,15,16,18,21,24,39

H_A#[35..3]

H_REQ#[4..0]

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_D#[63..0]

H_AVREF

U12A

U12A

H_D#0

E2

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_D#_0

G2

H_D#_1

G7

H_D#_2

M6

H_D#_3

H7

H_D#_4

H3

H_D#_5

G4

H_D#_6

F3

H_D#_7

N8

H_D#_8

H2

H_D#_9

M10

H_D#_10

N12

H_D#_11

N9

H_D#_12

H5

H_D#_13

P13

H_D#_14

K9

H_D#_15

M2

H_D#_16

W10

H_D#_17

Y8

H_D#_18

V4

H_D#_19

M3

H_D#_20

J1

H_D#_21

N5

H_D#_22

N3

H_D#_23

W6

H_D#_24

W9

H_D#_25

N2

H_D#_26

Y7

H_D#_27

Y9

H_D#_28

P4

H_D#_29

W3

H_D#_30

N1

H_D#_31

AD12

H_D#_32

AE3

H_D#_33

AD9

H_D#_34

AC9

H_D#_35

AC7

H_D#_36

AC14

H_D#_37

AD11

H_D#_38

AC11

H_D#_39

AB2

H_D#_40

AD7

H_D#_41

AB1

H_D#_42

Y3

H_D#_43

AC6

H_D#_44

AE2

H_D#_45

AC5

H_D#_46

AG3

H_D#_47

AJ9

H_D#_48

AH8

H_D#_49

AJ14

H_D#_50

AE9

H_D#_51

AE11

H_D#_52

AH12

H_D#_53

AJ5

H_D#_54

AH5

H_D#_55

AJ6

H_D#_56

AE7

H_D#_57

AJ7

H_D#_58

AJ2

H_D#_59

AE5

H_D#_60

AJ3

H_D#_61

AH2

H_D#_62

AH13

H_D#_63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

Crestline FBGA 1299P INTEL 6019B0360601

Crestline FBGA 1299P INTEL 6019B0360601

HOST

HOST

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_ADSTB#_0
H_ADSTB#_1

H_BNR#
H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#
H_HITM#

H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

R128

R128

54.9-1%-1/16W-0402

G G

F F

54.9-1%-1/16W-0402

H_SCOMP#

1.05VS8,9,13,15,16,18,21,24,39 1.05VS8,9,13,15,16,18,21,24,39

R127

R127

54.9-1%-1/16W-0402

54.9-1%-1/16W-0402

H_SCOMP

H_RCOMP

R123

R123

24.9-1%-1/16W-0402

24.9-1%-1/16W-0402

10mil

R418

R418
221-1%-1/16W-0402

221-1%-1/16W-0402

R416

R416
100-1%-1/16W-0402

100-1%-1/16W-0402

10mil

H_SWING

H_D#[63..0]8

C447

C447

0.1uF 10V 10% 0402 X7R

0.1uF 10V 10% 0402 X7R

Trace should be 10-mil wide with 20-mil spacing

E E

D D

H_CPURST#8

1.05VS8,9,13,15,16,18,21,24,39

C C

R420

R420
1K-1%-1/16W-0402

1K-1%-1/16W-0402

H_CPUSLP#8

H_A#[35..3] 8

H_ADS# 8
H_ADSTB#0 8
H_ADSTB#1 8
H_BNR# 8
H_BPRI# 8
H_BREQ#0 8
H_DEFER# 8
H_DBSY# 8
CLK_MCH_BCLK 18
CLK_MCH_BCLK# 18
H_DPWR# 8
H_DRDY# 8
H_HIT# 8
H_HITM# 8
H_LOCK# 8
H_TRDY# 8

H_DINV#0 8
H_DINV#1 8
H_DINV#2 8
H_DINV#3 8

H_DSTBN#0 8
H_DSTBN#1 8
H_DSTBN#2 8
H_DSTBN#3 8

H_DSTBP#0 8
H_DSTBP#1 8
H_DSTBP#2 8
H_DSTBP#3 8
H_REQ#[4..0] 8

H_RS#0 8
H_RS#1 8
H_RS#2 8

10mil

R421

R419

R419
2K-1%-1/16W-0402

2K-1%-1/16W-0402

C457

C457

0.1uF 10V 10% 0402 X7R

0.1uF 10V 10% 0402 X7R

R421
0-5%-1/16W-0402

0-5%-1/16W-0402

H_DVREF

B B

Inventec Corporation

Inventec Corporation

Inventec Corporation

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

A A

10

9

8

7

6

5

4

3

Beitou District, Taipei 11270, Taiwan

<OrgAddr4>

<OrgAddr4>

<OrgAddr4>

TEL:[phone]

TEL:[phone]

TEL:[phone]

Title

Title

Title

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Crestline Host(1/6)

Crestline Host(1/6)

Date: Sheet of

Date: Sheet of

Date: Sheet of

Crestline Host(1/6)

Wednesday, May 23, 2007

Wednesday, May 23, 2007

Wednesday, May 23, 2007

2

43

12

43

12

43

12

1

0.3

0.3

0.3

10

H H

Add for Intel ref design v1.3

G G

F F

E E

PM_BMBUSY#23

H_DPRSTP#8,10,21
PM_EXTTS#019
PM_EXTTS#120

PM_ICH_PWROK23,25

D D

PLT_RST#22
PM_THRMTRIP#8,21
PM_DPRSLPVR10,23

3VS 8,10,11,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,34,35,39,40,41

R461

R461
10K-5%-1/16W-0402

10K-5%-1/16W-0402
R468

R468
10K-5%-1/16W-0402

10K-5%-1/16W-0402

C C

B B

A A

10

R295

R295

1K-5%-1/16W-0402

1K-5%-1/16W-0402

MCH_BSEL018
MCH_BSEL1
MCH_BSEL2

R467 SHORT-0402-5MILR467 SHORT-0402-5MIL

R463 SHORT-0402-5MILR463 SHORT-0402-5MIL

PM_EXTTS#0
PM_EXTTS#1

R431 100-5%-1/16W-0402R431 100-5%-1/16W-0402

R438 SHORT-0402-5MILR438 SHORT-0402-5MIL

PM_EXTTS#0

PM_EXTTS#1

MCH_CFG18
MCH_CFG19
MCH_CFG20

MCH_CFG5
MCH_CFG9
MCH_CFG16
MCH_CFG12
MCH_CFG13

NC_MCH_CFG3
NC_MCH_CFG4
MCH_CFG5
NC_MCH_CFG6
NC_MCH_CFG7
NC_MCH_CFG8
MCH_CFG9
NC_MCH_CFG10
NC_MCH_CFG11
MCH_CFG12
MCH_CFG13
NC_MCH_CFG14
NC_MCH_CFG15
MCH_CFG16
NC_MCH_CFG17
MCH_CFG18
MCH_CFG19
MCH_CFG20

R449 1K-5%-1/16W-0402_NUR449 1K-5%-1/16W-0402_NU
R453 4.02K-1%-1/16W-0402_NUR453 4.02K-1%-1/16W-0402_NU
R464 4.02K-1%-1/16W-0402_NUR464 4.02K-1%-1/16W-0402_NU

R428 4.02K-1%-1/16W-0402_NUR428 4.02K-1%-1/16W-0402_NU
R425 2.2K-5%-1/16W-0402_NUR425 2.2K-5%-1/16W-0402_NU
R427 4.02K-1%-1/16W-0402_NUR427 4.02K-1%-1/16W-0402_NU
R424 4.02K-1%-1/16W-0402_NUR424 4.02K-1%-1/16W-0402_NU
R426 4.02K-1%-1/16W-0402_NUR426 4.02K-1%-1/16W-0402_NU

9

C475

C475

0.1uF 10V 10% 0402 X5R

0.1uF 10V 10% 0402 X5R

1.05VS8,9,12,15,16,18,21,24,39

R316

R316
1K-5%-1/16W-0402

1K-5%-1/16W-0402

R465 SHORT-0402-5MILR465 SHORT-0402-5MIL
R595 SHORT-0402-5MILR595 SHORT-0402-5MIL

9

8

U12B

U12B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

E1

NC_10

A5

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2

NC_16

Crestline FBGA 1299P INTEL 6019B0360601

Crestline FBGA 1299P INTEL 6019B0360601

3VS8,10,11,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,34,35,39,40,41

CRESTLINE (965GM) Strapping:

SM_RCOMP_VOH

SM_RCOMP_VOL

DDR MUXINGCLK

DDR MUXINGCLK

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CFGRSVD

CFGRSVD

DMI

DMI

PM

PM

GRAPHICS VID

GRAPHICS VID

ME

ME

NC

NC

SDVO_CTRL_CLK

SDVO_CTRL_DATA

MISC

MISC

MCH_CFG5

MCH_CFG9 (PCIE Graphic Lane)

MCH_CFG16 (FSB Dynamic ODT)

MCH_CFG18 (VCC Select)
MCH_CFG19 (DMI Lane Reversal)
MCH_CFG20

8

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

SM_CK#_0
SM_CK#_1
SM_CK#_3

SM_CK#_4
SM_CKE_0

SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_VREF_0
SM_VREF_1

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

CLK_REQ#
ICH_SYNC#

TEST_1
TEST_2

7

AV29
BB23
BA25
AV23

AW30
BA23
AW25
AW23

BE29
AY32
BD39
BG37

BG20
BK16
BG16
BE13

BH18
BJ15
BJ14
BE16

BL15
BK14

BK31
BL31

AR49
AW4

B42
C42
H48
H47

K44
K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35
A39
C38
B39
E36

AM49
AK50
AT43
AN49
AM50

H35
K36
G39
G40

A37
R32

M_RCOMP
M_RCOMP#

M_RCOMP_VOH
M_RCOMP_VOL

M_VREF

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

MCH_CLVREF

MCH_TEST1
MCH_TEST2

Low

DMIx2

M_CLK_DDR0 19
M_CLK_DDR1 19
M_CLK_DDR2 20
M_CLK_DDR3 20

M_CLK_DDR#0 19
M_CLK_DDR#1 19
M_CLK_DDR#2 20
M_CLK_DDR#3 20

M_CKE0 19
M_CKE1 19
M_CKE2 20
M_CKE3 20

M_CS#0 19
M_CS#1 19
M_CS#2 20
M_CS#3 20

M_ODT0 19
M_ODT1 19
M_ODT2 20
M_ODT3 20

DREFCLK 18
DREFCLK# 18
DREFSSCLK 18
DREFSSCLK# 18

CLK_PCIE_3GPLL 18
CLK_PCIE_3GPLL# 18

DMI_TXN[3..0]

DMI_TXP[3..0]

DMI_RXN[3..0]

DMI_RXP[3..0]

DFGT_VID_0 41
DFGT_VID_1 41
DFGT_VID_2 41
DFGT_VID_3 41
DFGT_VR_EN

CL_CLK0 23

CL_DATA0 23
ALL_SYSPWRGD 23,31
CL_RST#0 23
MCH_CLVREF

CLK_MCH_OE# 18
MCH_ICH_SYNC# 23

MCH_TEST1
MCH_TEST2

Reverse Lane

Dynamic ODT Disable

1.05V
Normal Lanes Reversed
Only SDVO or PCIE x1 is

operation

7

6

Route M_OCDCMOP 0&1 as short as possible

M_VREF

C454

C454

0.1uF 10V 10% 0402 X7R

0.1uF 10V 10% 0402 X7R

C535

C535

0.1uF 10V 10% 0402 X7R

0.1uF 10V 10% 0402 X7R

20mil

M_VREF 19,20,40

DMI_TXN[3..0] 22

DMI_TXP[3..0] 22

DMI_RXN[3..0] 22

DMI_RXP[3..0] 22

CRT_BLUE36
CRT_GREEN36
CRT_RED36

CRT_DDC_CLK25
CRT_DDC_DATA25
CRT_HSYNC25

CRT_VSYNC25

SDVO_CTRL_CLK 34

SDVO_CTRL_DATA 34

MCH_TEST1 MCH_TEST2

0-5%-1/16W-0402

0-5%-1/16W-0402

High

DMIx4

Place 150ohm termination resistor
close to GMCH

R448

R448

R455

R455

20K-5%-1/16W-0402

20K-5%-1/16W-0402

MCH_CLVREF

0.1uF 10V 10% 0402 X7R

0.1uF 10V 10% 0402 X7R

Normal Operation

Dynamic ODT Enable

1.5V

Only SDVO or PCIE x1
with PEG port

6

1.8V15,16,19,20,34,40,43

10mil

C543

C543

R147

R147

R146

R146

LUMA26
CHROMA26

5

10K-5%-1/16W-0402

10K-5%-1/16W-0402

R470 0-5%-1/16W-0402_NUR470 0-5%-1/16W-0402_NU

INV_PWM25,31

BL_ENA25

LCM_DDCPCLK25
LCM_DDCPDATA25

LVDS_VDDEN25

LVDS_TXCLK_LN25
LVDS_TXCLK_LP25

LVDS_TXOUT_L0N25
LVDS_TXOUT_L1N25
LVDS_TXOUT_L2N25

LVDS_TXOUT_L0P25
LVDS_TXOUT_L1P25
LVDS_TXOUT_L2P25

R436 75-1%-1/16W-0402R436 75-1%-1/16W-0402
R433 120 0.5% 1/16W 0402R433 120 0.5% 1/16W 0402
R434 120 0.5% 1/16W 0402R434 120 0.5% 1/16W 0402

R440 130 0.5% 1/16W 0402R440 130 0.5% 1/16W 0402
R441 130 0.5% 1/16W 0402R441 130 0.5% 1/16W 0402
R439 130 0.5% 1/16W 0402R439 130 0.5% 1/16W 0402

CRT_BLUE
CRT_GREEN
CRT_RED

R446 30.1-0.5%-1/16W-0402R446 30.1-0.5%-1/16W-0402
R451 30.1-0.5%-1/16W-0402R451 30.1-0.5%-1/16W-0402

1.25VM_AXD 16

R478

R478
1K-1%-1/16W-0402

1K-1%-1/16W-0402

R483

R483
392-1%-1/16W-0402

392-1%-1/16W-0402

M_RCOMP

20-1%-1/16W-0402

20-1%-1/16W-0402

20-1%-1/16W-0402

20-1%-1/16W-0402

M_RCOMP#

10mil

5

3VS8,10,11,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,34,35,39,40,41

R454

R454

SHORT-0402-5MIL

SHORT-0402-5MIL

1

TP15TP15

LVDS_TXCLK_LN
LVDS_TXCLK_LP

LVDS_TXOUT_L0N
LVDS_TXOUT_L1N
LVDS_TXOUT_L2N

LVDS_TXOUT_L0P
LVDS_TXOUT_L1P
LVDS_TXOUT_L2P

TP14TP14
TP13TP13

R457

R457
10K-5%-1/16W-0402

10K-5%-1/16W-0402

R462

R462

R4692.37K-1%-1/16W-0402 R4692.37K-1%-1/16W-0402

L_VBG

1
1

REFSET

R443

R443

1.27K 1% 1/16W 0402

1.27K 1% 1/16W 0402

4

U12C

U12C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

C48

LVDSA_DATA#_3

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

D47

LVDSA_DATA_3

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

C32

CRT_TVO_IREF

E33

CRT_VSYNC

Crestline FBGA 1299P INTEL 6019B0360601

Crestline FBGA 1299P INTEL 6019B0360601

As close as possible to GMCH and Minimum
spacing of 20 mils away from any toggle
signals

When the display is completely white , the RGB voltage is
between 665mV to 770mV by VESA Spec

LVDS

LVDS

TV VGA

TV VGA

3

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

If meet , CRT_IREF resistor value is optimal

1.8V 15,16,19,20,34,40,43

R150

R150

1K-1%-1/16W-0402

1K-1%-1/16W-0402

3.01K 1% 1/16 0402

3.01K 1% 1/16 0402

1K-1%-1/16W-0402

1K-1%-1/16W-0402

4

R151

R151

R153

R153

0.01uF 16V 10% 0402 X7R

0.01uF 16V 10% 0402 X7R

M_RCOMP_VOH

C125

C125

C141

C141

2.2uF 10V 10% 0805 X5R

2.2uF 10V 10% 0805 X5R

M_RCOMP_VOL

C131

C131

C136

C136

2.2uF 10V 10% 0805 X5R

2.2uF 10V 10% 0805 X5R

0.01uF 16V 10% 0402 X7R

0.01uF 16V 10% 0402 X7R

3

N43
M43

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

2

VCC_PEG16

R475

R475

24.9-1%-1/16W-0402

24.9-1%-1/16W-0402

PEG_COMP

SDVOB_INT- 34

SDVOB_INT+ 34

C208 0.1uF 10V 10% 0402 X5RC208 0.1uF 10V 10% 0402 X5R
C205 0.1uF 10V 10% 0402 X5RC205 0.1uF 10V 10% 0402 X5R
C210 0.1uF 10V 10% 0402 X5RC210 0.1uF 10V 10% 0402 X5R
C204 0.1uF 10V 10% 0402 X5RC204 0.1uF 10V 10% 0402 X5R

C207 0.1uF 10V 10% 0402 X5RC207 0.1uF 10V 10% 0402 X5R
C206 0.1uF 10V 10% 0402 X5RC206 0.1uF 10V 10% 0402 X5R
C209 0.1uF 10V 10% 0402 X5RC209 0.1uF 10V 10% 0402 X5R
C203 0.1uF 10V 10% 0402 X5RC203 0.1uF 10V 10% 0402 X5R

Inventec Corporation

Inventec Corporation

Inventec Corporation

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road

5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

Beitou District, Taipei 11270, Taiwan

<OrgAddr4>

<OrgAddr4>

<OrgAddr4>

TEL:[phone]

TEL:[phone]

TEL:[phone]

Title

Title

Title

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

S11D (Merom+Crestline+ICH8M)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, May 23, 2007

Wednesday, May 23, 2007

Wednesday, May 23, 2007

2

SDVOB_RED- 34

SDVOB_GREEN- 34

SDVOB_BLUE- 34

SDVOB_CLK- 34

SDVOB_RED+ 34
SDVOB_GREEN+ 34
SDVOB_BLUE+ 34

SDVOB_CLK+ 34

Crestline DMI/Graph2/6)

Crestline DMI/Graph2/6)

Crestline DMI/Graph2/6)

1

0.3

0.3

0.3

43

13

43

13

43

13

1