Inventec RALPH1.1, LV1.1, Lauren Schematics
THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC
CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT
WRITTEN PERMISSION,INVENTEC CORPORATION,2009 ALL RIGHT RESERVED.
8
7 6 5 4 3 2 1
HSF Property:ROHS or Halogen-Free(5L3?)
E
D
RALPH1.1
SI-2 BUILD
2012.1.3
FF
E
D
C
B
A
12-12-2011
DATE CHANGE NO.
8
REV
7 6 5 4 3
DRAWER
DESIGN
CHECK
RESPONSIBLE
SIZE=
FILE NAME:
P/N
David Cheng
POWER
2
C
B
A
DATEDATEEE
VER:
INVENTEC
TITLE
LV1.1_Lauren
Everest Main Board
CODE
SIZE
C
CS
SHEET
DOC.NUMBER REV
1310A24893-0 MTR
of
1
1
AX1
67
8 7
6 5
INDEX
4
3 2 1
D
PAGE
01. PROJECT NAME
02. INDEX
03. BLOCK DIAGRAM
04. POWER PROCEDURE
05. POWER SEQUENCE
06. DC & BATTERY CHARGER
07. BATTERY CONN
08. VRP5V0A & VRP3V3A
09. VRP1V5 & P0V75S
10. VRP1V05S_VCCP
11. VRP1V8S
12. VRPVSA
13. PVCORE & PVAXG
14. PVCORE & PVAXG
15. VRPVCORE_DGPU
16. PVDDCI
B
17. PVPCIE
18. POWER PAD
19. P5V0S & P3V3S & P1V5S
20. CPU
21. CPU-1
22. CPU-2-POWER
23. CPU-3-PCIE-GRAPHICS & DMI & FDI & EDP
24. CPU-4-MEMORY BUS
25. CPU-5-POWER-GRAPHICS
26. CPU-6-VSS & STRAP PIN
27. FAN & LOCAL SHUTDOWN
28. SO-DIMM0
29. SO-DIMM1
30. PCH
31. PCH-1-RTC & IHDA & SPI & LPC & SATA & EEPROM
32. PCH-2-PCIE & CLOCKS & SMBUS
33. PCH-3-DMI & FDI & POWER MANAGEMENT
8
7 6
34. PCH-4-LVDS & CRT & DISPLAY INTERFACE
35. PCH-5-USB30 & USB20 & PCI
36. PCH-6-GPIO & CPU/MISC
37. PCH-7-POWER
38. PCH-8-POWER
39. PCH-9-VSS
40. KBC
41. KEYBOARD CONN & DC-JACK LED & TOUCHPAD CONN
42. DISPLAY PORT
43. HDMI
44. LVDS CONN
45. LAN
46. RJ45
47. USB30 REDRIVER
48. USB30 CONN1 & REAR SPEAKER CONN
49. AU/B CONN & HDD CONN & HD CONN & PBN CONN & ODD REDRIVER
50. WIRELESS AUDIO/B CONN & MUTE BUTTON & LDPS/B CONN
CR/B CONN & JOG DIAL CONN & AU-USB30 CONN
51. WLAN CONN & BLUETOOTH CONN & HARDDRIVE PROTECTION
52. SCREWS
53. GPU
54. GPU-1-PCIE INTERFACE
55. GPU-2-BACO
56. GPU-3-GPIO & THERMAL
57. GPU-4-MEMORY CHANNEL A
58. GPU-5-MEMORY CHANNEL B
59. GPU-6-POWER
60. GPU-7-VSS
61. GPU-8-POWER & GPU LVDS
62. GPU-9-CHANNEL A MEMORY (GDDR5)
63. GPU-10-CHANNEL B MEMORY (GDDR5)
64. CARD READER BOARD
65. ODD/B & WIRELESS AUDIO/B & POWER BUTTON/B
66. TPM
67. EMI
5 4
CHANGE by
David Cheng 12-12-2011
DATE
23
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
DOC.NUMBER
CODE
SIZE
1310A24893-0 MTR
CS
A3
SHEET
of
2
67
1
D
CC
B
AA
REV
AX1
8 7
6 5
4
3 2 1
D
V-RAMX4
GDDR5
64MX32
(1GB)
P62~P63
X32
DGPU
AMD CHELSEA PRO 128BIT
M2 29MM X 29MM
P53~P61
PEGX8
LVDS
PANEL
P44
DISPLAY
PORT
HDMI
PORT
B
P42
P43
SATA2
ODD
SATA0
HDD
P49
P49
MAIN BATT
P07
SYSTEM CHARGER
DC / DC SYSTEM POWER
LVDSX2
DPX2
HDMI
SATA2
SATA0
P06
FRONT SPKR
REAR SPKR
P49
SUB WOOFER
HP JACK X2
IVY BRIDGE
RPGA988B (SOCKET-G2)
37.5MM X 37.5MM
FDI
PANTHER POINT
FCBGA PACKAGE
27 MM X 27 MM
HDA
IDT 92HD91
TPM
SLB 9656
P66
DMI
LPC
ITE IT8572E/AX
SPI ROM
KBC
P20~P26
P30~P39
SPI
BIOS
SPI
P31
P40
AUDIO CODEC
THERMAL SENSOR
TI TMP302
8
P27
MIC JACK
INT DMIC
7 6
P44 P50
KEYBOARD
5 4
TOUCHPAD
P41 P41
USB 2.0
USB 3.0
USB 2.0
PCIE
DDR3
DDR3
DDR3 SO-DIMM 0
DDR3 SO-DIMM 1
USB P0
+
USB 3.0 P1
M/B
P48 P44
USB 3.0 REDRIVER
CARD READER
RTS5229
ALS PROXIMITY
SENSOR CM3633
CHANGE by
David Cheng
1066/1333/1600 MHZ . 16GB MAXIMUM MEMORY
1066/1333/1600 MHZ . 16GB MAXIMUM MEMORY
USB P4
WIRELESS AUDIO
P50
P47
USB P5
WEBCAM
DEBUG ONLY
USB P1
+
USB 3.0 P2
WLAN/WIMAX
P64
MINICARD
P51
P28
P29
USB P10
BLUETOOTH
USB P2
+
USB 3.0 P3
D/B
AR8151
10/100/1000MHZ
RJ45
P46
ACCELEROMETER
P50 P51
ST MICRE HP302DLT8-MBD
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
DOC.NUMBER
CODE
DATE
12-12-2011
23
SIZE
CS
A3
1310A24893-0 MTR
SHEET
of
3
1
D
CC
P51
P50P50D/B
P45
67
REV
AX1
B
AA
8 7
6 5
4
3 2 1
VRP3V3A
FDMC7696
ADAPTER
D
CHARGER
BATT_CLK
BATT_DAT
B
SCL
SDA
BQ24728
ACDET
AC_OK
PVBAT
AON7410
PVPACK
EN_3V_5V
EN_P0V75 S3
DDR3L_SEL
EN_P1V0_VCCP
DGPU_PWR_EN
5/3.3V
TPS51123
S5EN_P1V5
VREF
TPS51216
EN
TPS51219
EN_DEM
RT8208
VO
VO
VO
PG
VO
PG
VO
PG
VRP5V0A
CORE_PWEN#
VRP1V5
P0V75S
CORE_PWEN#
P0V75M_VREF
CORE_PWEN#
P1V5_PG
VRP1V05S_VCCP
VCCIO_PG
VRPVCORE_DGPU
DGPU_PWROK
PVPCIE
P1V0S_VCCPP1V0S_VCCP
P3V3A
EN_P1V8
P5V0A
VCCSA_VID0
VCCSA_VID1
EN_PVCCSA
AO6402AL
AO6402AL
AON7410
EN
AT1530F11U
VID0
VID1
EN
TPS51461
VO
VO
P3V3S
P5V0S
D
P1V5S
VRP1V8S
CC
VRPVSA
B
PVDDCI
VO
EN_VPCIE EN
G9330TB
DGPU_PWROK
PVCORE
EN
VOUT
PVAXG
EN_CORE
VR_SVID_DATA
VR_SVID_ALERT#
VR_SVID_CLK
8
7 6
5 4
VR_ON
SDA
ALERT#
PGOOD
PGOODGSCLK
ISL95836
CHANGE by
David Cheng
CORE_PG
AXG_PG
DATE
12-12-2011
23
VO
G9330TB
INVENTEC
TITLE
LV1.1_Lauren
CODE
SIZE
CS
A3
POWER PROCEDURE
DOC.NUMBER
1310A24893-0 MTR
SHEET
of
67
4
1
REV
AX1
AA
8 7
6 5
Power sequence
4
3 2 1
D
B
D
CC
B
AA
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
David Cheng
DATE
12-12-2011
23
A3
1310A24893-0 MTR
CS
SHEET
of
5
1
DOC.NUMBER
CODE
REV
AX1
67
8 7
PVADPTR
R6015
2_5%_6
2 1
ACDRV
OUT
IN
VADPBL
Q6010
1
2
3
4 5
S
G
NMOS_4D3S
FDMC7696
D
8
7
6
C6018
D
C6020
2 1
0.047UF_25V_2
R6017
C6019
2 1
0.1UF_25V_2
2200PF_50V_2
2 1
RSC_0402_DY
C6031
2 1
2 1
BATDRV
2 1
C6033
1UF_25V_3
IN
6
R6028
2 1
4.3K_5%_2
P1V5S PVADPTR
B
PVADPTR
R6029
2 1
R6030
2 1
D6018
2 1
2 1
1SS355VMTE_17
RSC_0402_DY
OUT
AC_OK
C6022
2 1
RSC_0402_DY
CSC0402_DY
ACDET>0.6V = SMBUS OK
ACDET>1.8V = ADP_PRES HI
ACDET>2.4V = AC_OK TO CHARGE
ACDET>3.15V = AC_OVP
8
R6021
ADP_PRES
2 1
300K_1%_2
35 40
R6049
2 1
47K_1%_2
7
40
40
7
7 6
OUT
40
I_ADP
BI
BI
6 5
KC_FBMA_11_321611_121A60T
KC_FBMA_11_321611_121A60T
L6015
L6016
C6017
2 1
1000PF_50V_2
100pF_50V_2
PVPACK
2 1
C6032
0.01UF_50V_2
OUT
ACDRV
1
S
2
3
4 5
G
NMOS_4D3S
AON7406
1
S
2
3
4 5
G
NMOS_4D3S
AON7406
R6018
2 1
4.3K_5%_2
P3V3AL
TI_BQ24728_QFN_20P
R6024
2 1
10K_5%_2
OUT
C6046
2 1
100PF_50V_2
BATT_DAT
BATT_CLK
21
21
Q6012
Q6011
C6047
4
1
2
C6016
2 1
C6015
2 1
100pF_50V_2
1000PF_50V_2
SEM_SM24_SOT23_3P_DY
D6017
1
2
3
P3V3AL
3
8
D
7
6
PVBAT_R
OUT
8
D
7
6
0.1UF_16V_2
21
C6029
1UF_25V_3
543
ACPRES
6
ACDET
7
IOUT
8
SDA
9
SCL
10
ILIM
BATDRV
P3V3A
R6023
2 1
100K_1%_2
R6046
2 1
2 1
CSC0402_DY
36.5K_1%_2
R6000
0.01_1%_6
C6028
VRPVADPTR_CSP
1
2
ACN
ACP
CMSRC
ACDRV
LODRV
GND
SRN
SRP
1514131211
4.3K_5%_2
VRPVADPTR_CSN
U6000
PHASE
R6043
HIDRV
REGN
21
43
21
BTST
TML
VCC
PVADPTR PVBAT
D5049
C6027
0.047UF_25V_3
2 1
R6026
2.2_5%_2
2 1
D6016
BAT54WS
21
21
OUT
BAT54CW
2 1
C6025
1UF_10V_2
0_5%_2
21
C6030
CSC0402_DY
21
20
19
18
17
16
2 1
R6025
R6020
0_5%_2
BATDRV
21
6
C
3
R6027
2 1
VRPVPACK_HG
VRPVPACK_PH
0.047UF_16V_2
VRPVPACK_LG
A2A1
20_5%_5
C6026
PVBAT
12
PAD6015
2 1
21
678
AON7410
NMOS_4D3S
G
3
21
678
AON7410
NMOS_4D3S
G
3
5 4
3 2 1
JACK6015
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
41
AMBER#
41
WHITE#
D6015
1SS355VMTE_17
IN
IN
R6048
21
21
2 1
C6048
2 1
2 1
9
10
10
PROF_HPW20008_10M100R_10P
1K_1%_2
R6047
12K_1%_2
OUT
0.0015UF_50V_2
POWERPAD_2_0610
IN
PVBAT_CHG
Q6000
D
C6002
C6001
C6000
2 1
S
CSC0805_DY
2 1
2 1
4.7UF_25V_5
10UF_25V_5
214 5
L6000
ETQP3W4R7WFN
Q6001
D
S
214 5
R7600
2 1
RSC_0603_DY
C7600
2 1
CSC0402_DY
21
C6024
2 1
CSC0402_DY
R6001
0.01_1%_6
C6023
0.1UF_16V_2
21
43
21
2 1
VRPVPACK_CSP
VRPVPACK_CSN
SIZE
CHANGE by
David Cheng
DATE
12-12-2011
23
40
ADP_ID
PVPACK
C6010
2 1
10UF_25V_5
2 1
2 1
10UF_25V_5
CSC0805_DY
C6012
C6011
C6021
0.1UF_25V_2
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
DOC.NUMBER
CODE
1310A24893-0 MTR
CS
A3
SHEET
of
67
6
1
D
CC
B
D6019
B0530W_7
2 1
AA
REV
AX1
8 7
6 5
4
3 2 1
D
P3V3AL
12
R6052
2 1
2.2K_5%_2
BATT_CLK
6
40
BI
BATT_DAT
6
40
BI
R6050
2 1
2 1
2.2K_5%_2
C7501
C7500
2 1
100PF_50V_2
100PF_50V_2
R6053
100_5%_2
R6051
100_5%_2
D7504
2 1
PHP_PESD5V0S1BB_SOD523_2P
21
21
12
D7506
2 1
PHP_PESD5V0S1BB_SOD523_2P
PVPACK
BP0206C_B7200B3_9H
CN6050
1
1
2
2
3
3
4
4
5
5
6
6
G1
G
G2
G
D
CC
21
C6050
0.1UF_25V_2
B
B
AA
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
David Cheng
DATE
12-12-2011
23
A3
1310A24893-0 MTR
CS
SHEET
of
7
1
DOC.NUMBER
CODE
REV
AX1
67
8 7
6 5
4
3 2 1
D
OCP=8AMP
3.36V=((R6100/R6101)+1)*2
B
8
OUT
OCP=7AMP
P3V3A
P3V3AL
VBATP
8
19
IN
VRP3V3A
2 1
2 1
2 1
POWERPAD_2_0610
2 1
POWERPAD1X1M
R6100
6.8K_1%_2
R6101
10K_1%_2
PAD6100
PAD6121
C6100
12
12
+
2 1
220UF_6.3V
PVBAT
PAD6110
2 1
C6110
2 1
L6100
ETQP3W3R3WFN
VRP3V3A
VRP3V3A_LDO
EN_3V
12
R6110
2 1
73.2K_1%_2
R6160
POWERPAD_2_0610
EN_5V
ININ
2 1
71.5K_1%_2
2VREF
OUT
PVADPTR
D6999
BAV70W_7_F
3
21
PVBAT
ININ
VRP5V0A_VIN
8
OUT
D
TON=3.3V:300KHZ/375KHZ
21
18
VRP5V0A_PH
678
AON7410
NMOS_4D3S
G
3
214 5
678
AON7702A
G
3
214 5
VRP5V0A_LG
8
8
OUT
8
IN
VBATP
Q6150
C6160
D
2 1
S
D
Q6151
2 1
S
2 1
4.7UF_25V_5_DY
R7615
C7615
IN
C6161
2 1
ETQP3W3R3WFN
RSC_0603_DY
CSC0402_DY
18
10UF_25V_5
L6150
21
19
CC
OCP=8AMP
5.08V=((R6050/R6151)+1)*2
VRP5V0A
R6150
2 1
+
C6150
2 1
220UF_6.3V
R6151
2 1
8
18
OUT
15.4K_1%_2
B
10K_1%_2
5V_PG
OUT
678
D
S
D
S
3
214 5
678
3
214 5
Q6100
NMOS_4D3S
G
C6115
VRP3V3A_HG
VRP3V3A_PH
VRP3V3A_LG
R6114
2.2_5%_30.1UF_16V_2
21
21
Q6101
G
VRP3V3A_LDO
8
OUT
C6121
1UF_6.3V_2
25
5
3
4
TML
TONSEL
TRIP2
VREF
VFB2
7 24
VO2 VO1
8
VREG3
9 22
VBST2
10 21
DRVH2
11 20
LL2
12 19
DRVL2
SKIPSEL
GND
EN0
VIN
16
15618
13
14
TI_TPS51123RGER_QFN_24P
R6113
2 1
2 1
2 1
330K_5%_2_DY
AON7410
C6111
2 1
4.7UF_25V_5_DY
21
10UF_25V_5
AON7702A
R7610
2 1
RSC_0603_DYCSC0402_DY
C7610
2 1
8
IN
C6123
U6100
PGOOD
VBST1
DRVH1
DRVL1
2 1
0.22UF_6.3V_2
R6155
2.2_5%_3
23
LL1
VRP5V0A_HG
VRP5V0A_PH
21
C6155
0.1UF_16V_2
1
2
TRIP1
VFB1
VREG5
ENC
17
VRP5V0A_LDO
41
OUT
C6122
1UF_25V_3
C6120
2 1
10UF_6.3V_3
OCP=7AMP
8
IN
SKIP:OOA=3.3V; PWM=2VREF; AUTO=GND
SKIP_3V_5V
18
IN
EN_3V_5V
19
IN
VRP5V0A_VIN
8
IN
P5V0A
PAD6150
2 1
POWERPAD_2_0610
12
VRP5V0A
8
18
IN
AA
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
DATE
12-12-2011David Cheng
23
CS
A3
1310A24893-0 MTR
SHEET
of
8
1
DOC.NUMBER
CODE
REV
AX1
67
8 7
6 5
4
3 2 1
PVBAT
21
D
P5V0A
1 2
PAD6210
D
POWERPAD_2_0610
P0V75S
678
C6216
2 1
2.2UF_6.3V_3
U6200
EN_P0V75
19
IN
IN
IN
EN_P1V5
DDR3L_SEL
R6200
10K_1%_2
21
19
21
R6201
C6217
B
2 1
52.3K_1%_2
C6218
2 1
0.01UF_50V_2
0.1UF_16V_2
R6203
2 1
100K_5%_2
17
S3
16
S5
6
VREF
8
REFIN
7
GND
19
MODE
18
TRIP
21
TI_TPS51216RUKR_QFN_20P
R6202
66.5K_1%_2
PGOOD
VDDQSNS
VLDOIN
VTTSNS
VTTGND
VTTREF
VBSTV5IN
DRVH
DRVL
PGND
1512
14
13
SW
11
10
20
9
2
3
VTT
1
4
5
21
TML
2.2_5%_3
VRP1V5_HG
VRP1V5_PH
VRP1V5_LG
P0V75M_VREF
C6220
2 1
R6215
10UF_6.3V_5
2 1
21
C6221
C6215
0.1UF_16V_2
0.22UF_6.3V_2
21
FDMC8884
FDMS0310AS
P1V5_PG
Q6200
D
NMOS_4D3S
G
S
3
2145
678
Q6201
D
C6211
2 1
21
R7620
RSC_0603_DY
G
S
3
OUT
2145
19
C7620
2 1
C6210
2 1
4.7UF_25V_5
10UF_25V_5
OCP=16AMP
L6200
21
PCMC104T_1R0MN
43
PAD6220
CSC0402_DY
VRP1V5
21
+
C6200
1 2
2 1
OUT
9
CC
POWERPAD1X1M
330UF_2V_9MR_PANA_-35%
B
1.511V=REFIN=1.8*(R6201/(R6200+R6201))
MODE=100KOHM:TRACKING DISCHARGE
OCP=12AMP
P1V5
PAD6200
2 1
POWERPAD_2_0610
12
VRP1V5
9
IN
AA
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
David Cheng
DATE
12-12-2011
23
A3
1310A24893-0 MTR
CS
SHEET
of
9
1
DOC.NUMBER
CODE
REV
AX1
67
8 7
6 5
4
3 2 1
D
PVBAT
EN_P1V0_VCCP
19
IN
R6303
2 1
MODE=200KHZ:400KHZ
P1V0_VCCP_PG
19
OUT
modify on 09/19
R6306
C6308
2 1
2 1
2.2UF_10V_3
10K_5%_2
R6308
C6320
2 1
2 1
11.3K_1%_2
0.01uF_50V_2
VCCIO_SEL
25
IN
VSS_SENSE_VCCIO
22
IN
VCC_SENSE_VCCIO
22
IN
VOUT=2*11.3/(10+11.3)=1.06V
R6307
21
0_5%_2_DY
TI_TPS51219RTER_QFN_16P
2 1
C6319
0.01UF_50V_2
B
200K_5%_2
678
FDMC7696
D
Q6300
NMOS_4D3S
G
S S
3
2145
678
FDMS0306AS
Q6301
D
G
3
214 5
C6310
2 1
21
2 1
10UF_25V_5
CYN_PCMB063T_R33MS_4P
R7630
RSC_0603_DY
C7630
2 1
CSC0402_DY
21
0.1UF_16V_2
P5V0A
2 1
C6315
21
C6316
2.2UF_6.3V_3
R6315
2.2_5%_3
14
17
16815
U6300
VREF
REFIN
GSNS
VSNS
PWPD
COMP
6
5
1
2
3
4
13
EN
BST
MODE
PGOOD
TRIP
GND
PGND
SW
DH
DL
V5
12
VRP1V05S_VCCP_PH
11
VRP1V05S_VCCP_HG
10
VRP1V05S_VCCP_LG
9
7
R6302
2 1
47.5K_1%_2
21
1 2
PAD6310
POWERPAD_2_0610
C6311
C6312
2 1
L6300
CSC0805_DY
21
21
43
43
VRP1V05S_VCCP
C6300
2 1
22UF_6.3V_5
C6301
OCP=25AMP
10
OUT
+
2 1
4.7UF_25V_5
D
CC
B
330UF_2V_9MR_PANA_-35%
OCP=8AMP
P1V0S_VCCP
OCP=12AMP
P1V05S_VCCP
PAD6300
2 1
POWERPAD_2_0610
POWERPAD_2_0610
POWERPAD_2_0610
12
PAD6301
2 1
12
PAD6400
2 1
12
VRP1V05S_VCCP
P1V0S_VCCP
10
IN
AA
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
David Cheng
DATE
12-12-2011
23
A3
1310A24893-0 MTR
CS
SHEET
of
1
DOC.NUMBER
CODE
REV
AX1
6710
8 7
6 5
4
3 2 1
D
D
P3V3A
P3V3A
C6971
2 1
10UF_6.3V_3
R6970
10_5%_2
2 1
EN_P1V8
19
IN
C6972
2 1
0.1UF_16V_2
B
U6970
GMT_AT1530F11U_SOP8_8P
8
VIN
1
VCC
5
EN
PGNDLXGND
673
TML
VRP1V8S_PH
FB
REF
9
4
2
C6973
2 1
L6970
PAN_ELL5PR2R2N
21
R6973
13K_1%_210K_1%_2
2 1
R6972
2 1
VRP1V8S
C6974
2 1
2 1
CSC0402_DY
0.1UF_16V_2
OCP=4.5AMP
OUT
1.84V=((R6973/R6972)+1)*0.8
C6970
22UF_6.3V_5
OCP=4.5AMP
11
P1V8S
PAD6970
2 1
POWERPAD_2_0610
12
VRP1V8S
11
IN
CC
B
AA
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
David Cheng
DATE
12-12-2011
23
A3
1310A24893-0 MTR
CS
SHEET
of
11
1
DOC.NUMBER
CODE
REV
AX1
67
8 7
6 5
4
3 2 1
D
C6522
VCCSA_SENSE
21
R6502
R6524
0.01UF_50V_2
2 1
C6515
0.1UF_16V_2
21
VCCSA_VID0
21
VCCSA_VID1
21
21
EN_SA
SA_PG
IN
IN
IN
IN
OUT
25
VRPVSA_PH
19
25
25
19
L6500
21
CYN_PCMB063T_R33MS_4P
43
OCP=7AMP
21
43
C6502
2 1
OCP=7AMP
PVSA
POWERPAD_2_0610
2 1
C6500
2 1
C6501
22UF_6.3V_522UF_6.3V_5
VRPVSA
C6503
22UF_6.3V_5_DY22UF_6.3V_5
2 1
PAD6500
2 1
12
VRPVSA
12
12
IN
C6520
2 1
C6521
2 1
P5V0A
PAD6510
1 2
POWERPAD1X1M
12
IN OUT
VRPVCCSA_IN
21
VRPVCCSA_IN
C6511
0.1UF_16V_2
12
OUT
C6510
12
2 1
IN
22uF_6.3V_5
VRPVCCSA_IN
2 1
0.22UF_6.3V_2
25
TML
24
23
VIN
22
VIN
21
PGND
20
PGND
19
PGND
B
C6523
1UF_6.3V_2
C6524
2 1
3300PF_50V_2
R6520
2 1
5.11K_1%_2
1
4
3
2
5
GND
COMP
VREF
VOUT
SLEW
U6500
V5FILT
VID0
VID1
V5DRV
PGOOD
151417
18
16
2 1
1UF_6.3V_2
R6521
6
RSC_0402_DY
MODE
7
SWVIN
8
SW
9
SW
10
SW
11
SW
12
BST
EN
TI_TPS51461RGER_QFN_24P
13
0_5%_2
0_5%_2
R6525
0_5%_2
D
CC
B
AA
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
David Cheng
DATE
12-12-2011
23
A3
1310A24893-0 MTR
CS
SHEET
of
1
DOC.NUMBER
CODE
REV
AX1
6712
8 7
21
C6731
VSUMG-
1314
IN
0.1UF_16V_2
21
D
R6719 NEAR L66710/L6720
R6719
10K_5%_NTC
21
R6720
VSUMG+
14
IN
VSUMG-
1314
IN
2.61K_1%_2
C6733
2 1
ISEN1G
14
IN
ISEN2G
14
IN
27.4K_1%_2
470K_5%_NTC
B
14
IN
14
IN
14
IN
470K_5%_NTC
ISEN3
ISEN2
ISEN1
0.22UF_16V_2
21
R6721
21
R6722
21
R6620
21
R6621
21
C6628
VSUM-
1314
IN
VSUM+
14
IN
R6624 NAER L6610/L6620
VSUM-
1314
IN
0.22UF_16V_2
R6623
2 1
2.61K_1%_2
R6624
2 1
10K_5%_NTC
21
R6718
C6730
11.3K_1%_2
C6732
2 1
0.22UF_16V_2
21
R6723
3.83K_1%_2
R6622
3.83K_1%_227.4K_1%_2
13
22
IN
22
OUT
13
22
BI
21
40
OUT
19
21
IN
R6621 NEAR ONE PH HI SIDE
21
C6627
0.22UF_16V_2
21
R6625
C6630
11.3K_1%_2
2 1
CSC0402_DY
VR_SVID_CLK
VR_SVID_ALERT#
VR_SVID_DATA
CPU_PROCHOT#
EN_CORE
21
2 1
C6629
2 1
0.1UF_16V_2
8
7 6
6 5
R6717
549_1%_2
C6729
2 1
0.22UF_10V_2
1
ISUMPG
ISEN1G
3
ISEN2G
4
NTCG
5
SCKL
6 U6600
ALERT#
7
SDA
8
VR_HOT#
9
10
NTC
41
PAD
C6626
0.22UF_16V_2
C6631
CSC0402_DY
2 1
0.22UF_6.3V_2
P5V0A
R6716
2 1
0_5%_2_DY
ISUMNG
ISEN3_FB2
11
C6728
1000PF_50V_2
39
RTNG
ISEN2
ISEN1 FBG
12213 38
21
COMPG
ISUMP
144015
TP24
1
36
PGOODG
ISUMN
21
INTERSIL_ISL95836HRTZ_T_TQFN_40P
VR_ON
R6626
866_1%_2
21
14
OUT
2 1
330PF_50V_2
14
14
OUT
OUT
GFX_VSS_SENSE
GFX_VCC_SENSE
C6727
14
14
OUT
OUT
IN
IN
2 1
C6726
470PF_50V_2
TP88
VRPVAXG_BOOT1
VRPVAXG_PH1
GPWM2
352833
16
VRPVAXG_HG1
VRPVAXG_LG1
32
34
PWM2G
LGATE1G
FB
RTN
173718
3120
BOOT2
UGATE2
BOOT1GBOOT1
PHASE1G
UGATE1G
PHASE2
LGATE2
VCCP
VDD
PWM3
LGATE1
PHASE1
UGATE1
COMP
PGOOD
19
VRPVCORE_BOOT2
30
VRPVCORE_HG2
29
VRPVCORE_PH2
VRPVCORE_LG2
27
26
25
CPWM3
24
VRPVCORE_LG1
23
VRPVCORE_PH1
22
VRPVCORE_HG1
21
VRPVCORE_BOOT1
2 1
VCCSENSE
2 1
C6633
330PF_50V_2
2 1
C6632
1000PF_50V_2
VSSSENSE
C6634
5 4
4
25
25
R6714
2 1
3.65K_1%_2
CORE_PG
R6627
3.65K_1%_2
2 1
499_1%_2
R6628
499_1%_2470PF_50V_2
21
22
IN
22
IN
R6715
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
3 2 1
2 1
R6712
2K_1%_2
2 1
R6713
267K_1%_2
47PF_50V_2
330PF_50V_2
150PF_50V_2
2 1
C6725
C6723
2 1
C6724
21
2 1
R6711
169K_1%_2
VR_SVID_CLK
13
22
OUT
VR_SVID_DATA
13
22
BI
R6635
2 1
P1V0S_VCCP
R6636
2 1
54.9_1%_2
C6640
130_1%_2
2 1
D
0.1UF_10V_2
P5V0A
0_5%_2
2 1
14
14
14
14
R6633
C6639
2 1
21
R6634
1_5%_2
CC
2.2UF_10V_3
14
14
14
14
14
33
21
47PF_50V_2
2 1
R6629
267K_1%_2
2 1
R6630
2K_1%_2
2 1
C6635
150PF_50V_2
2 1
680PF_50V_2
C6636
C6637
C6638
2 1
1uF_6.3V_2
B
R6631
21
5.76K_1%_2
21
AA
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
CHANGE by
David Cheng
DATE
12-12-2011
23
SIZE
DOC.NUMBER
CODE
1310A24893-0 MTR
CS
A3
SHEET
of
1
REV
AX1
6713
8 7
6 5
4
3 2 1
PVBAT
1
12
+
C6800
C6801
68UF_25V
2 1
2 1
VRPVCORE_BOOT1
13
D
IN
13
IN
13
IN
13
IN
VRPVCORE_BOOT2
13
IN
13
IN
13
IN
13
IN
C6803
C6802
2 1
100UF_25V
100UF_25V
VRPVCORE_HG1
VRPVCORE_PH1
VRPVCORE_LG1
VRPVCORE_HG2
VRPVCORE_PH2
VRPVCORE_LG2
+
15UF_25V
2 1
R6601
R6607
2.2_5%_3
POWERPAD_2_0610
IN
21
0.1UF_16V_22.2_5%_3
21
0.1UF_16V_2
B
PAD6600
VRPVBAT_CPU
C6622
21
C6623
21
2
FDMS7692 FDMS0300S
NMOS_4D3S
G
G
FDMS7692 FDMS0300S
NMOS_4D3S
G
G
+
+
P5V0A
C6625
2 1
1UF_6.3V_2
INTERSIL_ISL6208BCRZ_T_QFN_8P
8
U6630
9
TML
8
PHASE
UGATE
7
FCCM
6
VCC
5 4
LGATE GND
13
IN
CPWM3
BOOT
VRPVCORE_PH3
VRPVCORE_HG3
1
2
3
PWM
R6613
C6624
21
0.1UF_16V_22.2_5%_3
7 6
PVCORE OCP=112A
678
Q6610
D
C6612
2 1
ISEN1
VSUM+
VSUM-
10UF_25V_5
R6602
10K_1%_2
R6603
3.65K_1%_2
R6604
10_1%_2
1
ETQP4LR36AFM
21
21
21
L6610
2
43
470UF_2V
10UF_25V_5
OUT
OUT
OUT
C6615
2 1
ISEN2
VSUM+
VSUM-
10UF_25V_5
R6608
10K_1%_2
R6609
3.65K_1%_2
R6610
10_1%_2
ETQP4LR36AFM
21
21
21
L6620
21
43
470UF_2V
CSC0805_DY
C6617
2 1
10UF_25V_5
L6630
ETQP4LR36AFM
OUT
OUT
OUT
ISEN3
VSUM+
VSUM-
13
1314
1314
R6614
10K_1%_2
R6615
3.65K_1%_2
R6616
10_1%_2
21
21
21
5 4
21
3
214 5
678
3
214 5
678
3
214 5
678
3
214 5
CSC0805_DY
CSC0805_DY
C6616
2 1
CSC0805_DY
R7663
RSC_0603_DY
2 1
C7663
CSC0402_DY
2 1
C6611
2 1
13
1314
1314
C6614
2 1
13
OUT
1314
OUT
1314
OUT
C6610
2 1
S
Q6611
D
R7661
RSC_0603_DY
2 1
C7661
CSC0402_DY
2 1
Q6620
D
C6613
2 1
SS
Q6621
D
R7662
RSC_0603_DY
2 1
S
C7662
CSC0402_DY
2 1
678
FDMS7692
FDMS0300S
Q6630
D
NMOS_4D3S
G
S S
3
214 5
678
Q6631
D
G
3
214 5
C6600
C6602
PVAXG OCP=55A
PAD6700
21
FDMC7696 FDMS0306AS
PVBAT
12
2 1
NMOS_4D3S
G
G
678
3
678
3
Q6710
D
C6710
2 1
S
214 5
Q6711
D
R7671
RSC_0603_DY
2 1
C7671
214 5
CSC0402_DY
2 1
C6711
2 1
10UF_25V_5
10UF_25V_5
L6710
21
ETQP4LR36AFM
OUT
OUT
OUT
ISEN1G
VSUMG+
VSUMG-
13
1314
1314
R6702
10K_1%_2
R6703
3.65K_1%_2
R6704
10_1%_2
21
21
21
43
470UF_2V
C6700
PVCORE
IN
R6701
2.2_5%_3
POWERPAD_2_0610
VRPVBAT_AGX
C6720
21
0.1UF_16V_2
1
1
C6601
+
+
470UF_2V
3
2
3
2
VRPVAXG_BOOT1
13
IN
VRPVAXG_HG1
13
IN
VRPVAXG_PH1
13
IN
VRPVAXG_LG1
13
IN
PVCORE
PVBAT
1
1
470UF_2V
+
+
C6603
3
2
3
2
P5V0A
C6722
2 1
PVCORE
21
43
U6720
9
TML
8
PHASE
1UF_6.3V_2
UGATE
7
FCCM
BOOT
6
VCC
5 4
PWM
LGATE GND
INTERSIL_ISL6208BCRZ_T_QFN_8P
13
IN
GPWM2
1
2
3
R6706
2.2_5%_3
1
21
0.1UF_16V_2
C6721
12
PAD6701
POWERPAD_2_0610
2 1
678
FDMC7696
2
FDMS0306AS
Q6720
D
NMOS_4D3S
G
3
G
214 5
678
3
2145
C6712
2 1
S
Q6721
DS
R7672
RSC_0603_DY
2 1
S
C7672
CSC0402_DY
2 1
C6713
2 1
4.7UF_25V_5_DY
10UF_25V_5
L6720
21
ETQP4LR36AFM
OUT
OUT
OUT
ISEN2G
VSUMG+
VSUMG-
13
1314
1314
R6707
10K_1%_2
R6708
3.65K_1%_2
R6709
10_1%_2
21
21
21
43
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
DOC.NUMBER
CODE
CHANGE by
David Cheng
DATE
12-12-2011
23
SIZE
A3
1310A24893-0 MTR
CS
SHEET
of
6714
1
PVAXG
1
+
2
PVAXG
REV
AX1
D
CC
3
B
AA
8 7
6 5
4
3 2 1
POW_SW0
POW_SW1
191817
16
20
G0G1G2
CS
TON
PHASE
UGATE
D0D1D2S1S2
987
6
10
POW_SW2
R6758
21
49.9K_1%_2
360K_1%_2
P5V0A
10UF_6.3V_3
VRPVCORE_DGPU_LGEN_DGPU
11
GATE
VDD
BOOT
RICH_RT8232AZQW_QFN_20P
R6752
12
13
14
15
VRPVCORE_DGPU_PH
VRPVCORE_DGPU_HG
D
21
U6750
GND
1
18
IN
DGPU_PG
18
IN
R6753
49.9K_1%_2
C6757
2 1
R6754
C6758
0.22UF_10V_2
2 1
1000PF_50V_2
R6757
B
R6760
2K_1%_2
EN_MODE
2
FB
3
PGOOD
4
REFO
5
REFIN
1
2
2 1
34.8K_1%_2
R6756
2K_1%_2
2 1
2 1
2.1K_1%_2
R6759
2.15K_1%
2 1
2 1
R6755
21
C6754
56
IN
56
IN
56
IN
21
21
C6753
0.1UF_16V_22.2_5%_3
PVBAT
678
NMOS_4D3S
678
3
Q6750
D
C6760
2 1
G
S
3
214 5
678
D
S
214 5
FDMS0310AS
D
G
S
3
214 5
C6762
C6761
2 1
2 1
10UF_25V_5
CSC0805_DY
4.7UF_25V_5_DY
L6750
PAN_ETQP4LR36ZFC_4P
Q6752
R7675
2 1
RSC_0603_DY
2 1
C7675
CSC0402_DY
OCP=25AMP
21
43
R6750
0_5%_2
2 1
R6751
VRPVCORE_DGPU
1
+
C6750
470UF_2V
3
2
+
C6751
2 1
OUT
OCP=25AMP
PVCORE_DGPU
15
R6762
0.001_1%_1W
VRPVCORE_DGPU
21
15
IN
2 1
RSC_0402_DY
FDMS7692
21
FDMS0310AS
Q6751
G
D
CC
330UF_2V_9MR_PANA_-35%
B
R6761
2.15K_1%
2 1
AA
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
David Cheng
DATE
12-12-2011
23
A3
1310A24893-0 MTR
CS
SHEET
of
1
DOC.NUMBER
CODE
REV
AX1
6715
8 7
6 5
4
3 2 1
D
D
P1V0S_VCCP
12
PAD6940
2 1
678
POWERPAD_2_0610
FDMC7672
C6945
2 1
4.7UF_6.3V_3
6
5
4
R6940
2 1
C6942
P5V0A
0.1UF_16V_2
2 1
GMT_G9330TB1U_SOT23_6P
U6940
1
DRV
VCC
2
ADJ
GND
3
PGD
EN
2 1
18
VDDCI_PG
OUT
EN_VDDCI
18
IN
B
Q6940
D
NMOS_4D3S
G
S
3
2145
21
C6943
2 1
CSC0402_DY
SSM3K17FU
R6941
90.9_1%_2
S
Q6941
21
R6942
100_1%_2
47_5%_2
C6941
0.033UF_16V_2
21
R6943
806_1%_2
D
D S
G
R6944
G
1K_5%_2
21
VDDCI_SW
PVDDCI
OCP=6AMP
HIGH : 0.908V = 0.5 [ 1 + ( ( R6941//R6943) / R6942 ) ]
C6947
C6940
2 1
2 1
22UF_6.3V_5
22UF_6.3V_5
56
IN
LOW : 0.954V=0.5 ( 1+ R6941/R6942 )
CC
B
C6944
2 1
1000pF_50V_2
AA
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
David Cheng
DATE
12-12-2011
23
A3
1310A24893-0 MTR
CS
SHEET
of
1
DOC.NUMBER
CODE
REV
AX1
6716
8 7
6 5
4
3 2 1
D
OCP=6AMP
0.943V=0.5(1+R6951/R6952)
D
P1V0S_VCCP PVPCIE
678
FDMC7696
D
NMOS_4D3S
C6955
2 1
P5V0A
GMT_G9330TB1U_SOT23_6P
U6950
1
2
3
C6952
2 1
0.1UF_16V_2
18
EN_VPCIE
IN
6
DRV
VCC
5
ADJ
GND
4
PGD
EN
G
4.7UF_6.3V_3
R6950
2 1
2 1
S
3
2145
47_5%_2
R6951
2 1
C6951
R6952
0.033UF_16V_2
2 1
B
12
Q6950
PAD6950
2 1
POWERPAD1X1M
C6950
2 1
90.9_1%_2
22UF_6.3V_5
CC
100_1%_2
B
AA
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
David Cheng
DATE
12-12-2011
23
A3
1310A24893-0 MTR
CS
SHEET
of
1
DOC.NUMBER
CODE
REV
AX1
6717
8 7
6 5
4
3 2 1
EN_VPCIE
17
OUT
2 1
10K_5%_2
D
C6953
2 1
0.1uF_16V_2
R6953
DGPU_PWR_EN
18
IN
32 36 55
8
5V_PG
IN
R6999
100K_5%_2_DY
D
P3V3AL
21
P3V3S P3V3S
R206
10K_5%_2
2 1
DGPU_PWROK
3640
OUT
R754
0_5%_2
21
DGPU_PG
15
IN
16
OUT
VDDCI_PG
R205
10K_5%_2
2 1
CORE_PWEN
19
2540
PAD6135
1 2
POWERPAD1X1M
21
SKIP_3V_5V
OUTIN
8
CC
C3805
2 1
0.1uF_16V_2
IN
D6997
VRP5V0A_LG
B
3
8
IN
VRP5V0A
C6994
2 1
0.1UF_25V_2
2
D3801
B
323655
55
18
PX_MODE
IN
DGPU_PWR_EN
IN
R3808
R3809
0_5%_2
21
8.2K_5%_20_5%_2_DY
21
DIODE-BAT54-TAP-PHP
NC
R3807
21
13
EN_DGPU
OUT
15
P15V0A
C3804
2 1
0.1uF_16V_2
SI 1012
R6945
0_5%_2
21
EN_VDDCI
OUT
16
2 1
C6998
2 1
D6998
BAV99W_7_F
C6996
2 1
0.1UF_25V_2
3
2 1
C6997
0.1UF_25V_20.1UF_25V_2
2 1
BAV99W_7_F
C6995
2 1
0.1UF_25V_2
C6946
2 1
CSC0402_DY
AA
INVENTEC
TITLE
LV1.1_Lauren
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
David Cheng
DATE
12-12-2011
23
A3
1310A24893-0 MTR
CS
SHEET
of
1
DOC.NUMBER
CODE
REV
AX1
6718
8 7
6 5
4
3 2 1
P3V3S
P15V0A
1
R701
1M_5%_2
2
C845
2200PF_50V_2
V3S_R_EN
D
Q90
3
DS
IN
CORE_PWEN#
1921
40
1
SSM3K7002FU
G
1
2
2
P3V3S
1
SSM3K7002FU
1
2
Q36
DS
G
3
2
R362
47_5%_5
I112
B
P5V0S
1
R451
47_5%_5
2
Q49
3
DS
1
SSM3K7002FU
G
2
1921
40
P3V3A P3V3S
1
2
5
OUT
R634
21
0_5%_2
P5V0A
1
2
5
R700
21
0_5%_2
P1V5
8
7
6
R65
21
0_5%_2
CORE_PWEN#
IN
Q81
D
NMOS_4D1S
AO6402AL
49
V3S_EN
Q85
D
NMOS_4D1S
AO6402AL
V5S_EN
Q12
D
NMOS_4D3S
AON7410
4
S
36
G
4
S
36
G
1
S
2
3
45
G
1
SSM3K7002FU
(2.2A)
1
C764
2 1
10uF_6.3V_3
2
C679
CSC0402_DY
P5V0S
(3.5A)
C851
2 1
P1V5S
C842
2 1
0.1UF_16V_2_DY
10UF_6.3V_3
(6A)
C39
10UF_6.3V_3
2 1
2540
2540
Q13
G
R76
100_5%_2
2 1
3
DS
2
1
VBATP
IN
2
8
C682
CSC0402_DY
SA_PG
12
IN
P1V5_PG
9
IN
R624
R52
P3V3AL
SI2 1229
21
R769
2 1
383K_1%_2
C6999
R768
2 1
2 1
100K_1%_2
40
RESUME_PWEN
R6997
2 1
100K_1%_2
R6998
2 1
100K_1%_2
0.1uF_25V_2_DY
R953
1M_1%_2
5
U55
1
+
+
4
OUT
3
-
-
2
ON_LMV331SN3T1G_TSOP_5P
R3800
10K_5%_2
21
R952
0_5%_2
EN_P1V5
C3800
2 1
0.01UF_50V_2
2
D3800
1819
100K_5%_2
R3801
NC
21
DIODE-BAT54-TAP-PHP
13
EN_P0V75CORE_PWEN
C3801
2 1
0.1UF_16V_20.01UF_50V_2
R3802
21
1819
CORE_PWEN
IN OUT
10K_5%_2
EN_P1V0_VCCP
C3802
2 1
21
OUTIN
2540
OUTIN
100_5%_2
21
100_5%_2
21
SI 1012
EN_3V_5V
8
OUT
ALWAYS_PW_EN
40
IN
9
CORE_PWEN
1819
9
P1V0_VCCP_PG
10
10
40
IN OUT
21
2 1
CPU_PWEN
R688
10K_5%_2
C829
1000PF_50V_2
10K_5%_2
ALL_PWRGD_IN
R3803
21
R3805
21
0_5%_2
R3806
0_5%_2
C3803
2 1
P3V3S
21
R3804
C900
2 1
EN_P1V8
0.01UF_50V_2
10K_5%_2
CSC0402_DY
21
EN_CORE
OUT
EN_SA
D
21
40
CC
11
OUTIN
B
12
OUTIN
AA
13
INVENTEC
TITLE
LV1.1_Lauren
+V5S & +V3S
SIZE
8
7 6
5 4
CHANGE by
David Cheng
DATE
12-12-2011
23
A3
1310A24893-0 MTR
CS
SHEET
of
19 67
1
DOC.NUMBER
CODE
REV
AX1
8 7
6 5
4
3 2 1
D
D
CC
CPU
B
B
AA
INVENTEC
TITLE
LV1.1_Lauren
BLANK
SIZE
8
7 6
5 4
CHANGE by
David Cheng
DATE
12-12-2011
23
A3
1310A24893-0 MTR
CS
SHEET
of
1
DOC.NUMBER
CODE
REV
AX1
6720
8 7
6 5
4
3 2 1
P1V8S P1V8S
C26
AN34
AL33
AN33
AL32
AN32
AM34
AP33
AR33
CN19
A28
PROC_SELECT#
SKTOCC#
CATERR#
PECI
CLOCKS
BCLK
BCLK#
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
MISCDDR3
PROCHOT#
THERMTRIP#
PM_SYNC
UNCOREPWRGOOD
V8
SM_DRAMPWROK
RESET#
JTAG & BPM
PWR MANAGEMENT THERMAL MISC
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PRDY#
PREQ#
TRST#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
DBR#
TCK
TMS
TDI
TDO
CLK_DMI_PCH_R
A27
CLK_DMI_PCH#_R
A16
CLK_DP_P_R
A15
CLK_DP_N_R
R8
DDR3_DRAMRST#_CPU
AK1
R119
A5
R484
A4
R480
AP29
AP27
XDP_PREQ#
AR26
XDP_TCLK
AR27
XDP_TMS
AP30
XDP_TRST#
AR28
XDP_TDI_R
AP26
XDP_TDO
AL35
XDP_DBRESET#
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
21
21
21
R544
R541
R508
R506
R704
R705
140_1%_2
25.5_1%_2
200_1%_2
TP24
TP21
TP17
TP20
TP28
TP27
TP18
TP40
TP26
TP22
TP32
TP30
TP37
TP35
TP36
TP38
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
21
21
21
21
1K_5%_2_DY
21
21
1K_5%_2_DY
OUT
0_5%_2
0_5%_2
0_5%_2
0_5%_2
21
CLK_DMI_PCH
CLK_DMI_PCH#
CLK_DP_P
CLK_DP_N
32
IN
32
IN
32
IN
32
IN
P1V0S_VCCP
D
P3V3S
XDP_DBRESET#
TP24
TP24
TP24
TP24
TP24
TP24
TP24
TP24
TP24
TP24
TP24
TP24
TP24
TP24
TP24
TP24
IN
IN
IN
IN
IN
OUT
OUT
XDP_TDO
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TCLK
XDP_TRST#
R222
R225
R227
R226
R213
R556
R558
21
21
21
21
21
21
21
1K_5%_2
51_5%_2
51_5%_2
51_5%_2
51_5%_2_DY
51_5%_2
51_5%_2
CC
P1V0S_VCCP
B
R711
1K_5%_2_DY
NV_CLE
36
OUT
D
2 1
1K_5%_2
R529
21
2 1
R531
2.2K_5%_2
P1V0S_VCCP
13
40
21
CPU_PROCHOT#
IN
IN
R561
62_5%_2
2 1
C693
47PF_50V_2
2 1
PM_DRAM_PWRGD_CPU
36
40
36
10K_5%_2
36
OUT
OUT
R203
IN
H_PECI
R562
56_5%_2
PM_THRMTRIP#
33
BI
21
H_PWRGD
R482
130_1%_2
51
35
40
66
IN
BUF_PLT_RST#
R217
1.5K_5%_2
B
21
21
21
R559
43_5%_2
H_PM_SYNC
2 1
21
R218
750_1%_2
P1V5
FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER
CPU SOCKET PN: 6026B0222201
P3V3A
SI 1201
R118
1K_5%_2
2 1
U6
OUT
PM_DRAM_PWRGD
ALL_PWRGD_IN
33
19
40
1
2
3
NXP_74AHC1G09GV_SOT753_5P
P3V3A P1V5S
5
VCC
B
4
Y
A
GND
2 1
3
DS
2
R116
200_5%_2
2 1
PM_DRAM_PWRGD_CPU
R117
RSC_0402_DY
1
G
Q18
CORE_PWEN#
R488
0_5%_2
C588
21
BSS138
2 1
2532
21
OUTIN
21
19
40
IN
PCH_DDR_RST
IN
DDR3_DRAMRST#_CPU
IN
3300PF_50V_2
SSM3K7002FU_DY
R479
2 1
1K_1%_2
Q55
3
DS
1
G
2
R486
21
0_5%_2_DY
R487
4.99K_1%_2
2 1
R485
1K_5%_2
21
DDR3_DRAMRST#
OUT
28 29
AA
INVENTEC
TITLE
LV1.1_Lauren
CPU-1
SIZE
8
7 6
5 4
CHANGE by
David Cheng
DATE
12-12-2011
23
A3
1310A24893-0 MTR
CS
SHEET
of
21
1
DOC.NUMBER
CODE
REV
AX1
67
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