Inventec RALPH1.1, LV1.1, Lauren Schematics

THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC
CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT
WRITTEN PERMISSION,INVENTEC CORPORATION,2009 ALL RIGHT RESERVED.

8

7 6 5 4 3 2 1

HSF Property:ROHS or Halogen-Free(5L3?)

E

D

RALPH1.1

SI-2 BUILD

2012.1.3

FF

E

D

C

B

A

12-12-2011

DATE CHANGE NO.

8

REV

7 6 5 4 3

DRAWER

DESIGN

CHECK

RESPONSIBLE

SIZE=
FILE NAME:
P/N

David Cheng

POWER

2

C

B

A

DATEDATEEE

VER:

INVENTEC

TITLE

LV1.1_Lauren

Everest Main Board

CODE

SIZE

C

CS

SHEET

DOC.NUMBER REV

1310A24893-0 MTR

of

1

1

AX1

67

8 7

6 5

INDEX

4

3 2 1

D

PAGE

01. PROJECT NAME

02. INDEX

03. BLOCK DIAGRAM

04. POWER PROCEDURE

05. POWER SEQUENCE

06. DC & BATTERY CHARGER

07. BATTERY CONN

08. VRP5V0A & VRP3V3A

09. VRP1V5 & P0V75S

10. VRP1V05S_VCCP

11. VRP1V8S

12. VRPVSA

13. PVCORE & PVAXG

14. PVCORE & PVAXG

15. VRPVCORE_DGPU

16. PVDDCI

B

17. PVPCIE

18. POWER PAD

19. P5V0S & P3V3S & P1V5S

20. CPU

21. CPU-1

22. CPU-2-POWER

23. CPU-3-PCIE-GRAPHICS & DMI & FDI & EDP

24. CPU-4-MEMORY BUS

25. CPU-5-POWER-GRAPHICS

26. CPU-6-VSS & STRAP PIN

27. FAN & LOCAL SHUTDOWN

28. SO-DIMM0

29. SO-DIMM1

30. PCH

31. PCH-1-RTC & IHDA & SPI & LPC & SATA & EEPROM

32. PCH-2-PCIE & CLOCKS & SMBUS

33. PCH-3-DMI & FDI & POWER MANAGEMENT

8

7 6

34. PCH-4-LVDS & CRT & DISPLAY INTERFACE

35. PCH-5-USB30 & USB20 & PCI

36. PCH-6-GPIO & CPU/MISC

37. PCH-7-POWER

38. PCH-8-POWER

39. PCH-9-VSS

40. KBC

41. KEYBOARD CONN & DC-JACK LED & TOUCHPAD CONN

42. DISPLAY PORT

43. HDMI

44. LVDS CONN

45. LAN

46. RJ45

47. USB30 REDRIVER

48. USB30 CONN1 & REAR SPEAKER CONN

49. AU/B CONN & HDD CONN & HD CONN & PBN CONN & ODD REDRIVER

50. WIRELESS AUDIO/B CONN & MUTE BUTTON & LDPS/B CONN
CR/B CONN & JOG DIAL CONN & AU-USB30 CONN

51. WLAN CONN & BLUETOOTH CONN & HARDDRIVE PROTECTION

52. SCREWS

53. GPU

54. GPU-1-PCIE INTERFACE

55. GPU-2-BACO

56. GPU-3-GPIO & THERMAL

57. GPU-4-MEMORY CHANNEL A

58. GPU-5-MEMORY CHANNEL B

59. GPU-6-POWER

60. GPU-7-VSS

61. GPU-8-POWER & GPU LVDS

62. GPU-9-CHANNEL A MEMORY (GDDR5)

63. GPU-10-CHANNEL B MEMORY (GDDR5)

64. CARD READER BOARD

65. ODD/B & WIRELESS AUDIO/B & POWER BUTTON/B

66. TPM

67. EMI

5 4

CHANGE by

David Cheng 12-12-2011

DATE

23

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

DOC.NUMBER

CODE

SIZE

1310A24893-0 MTR

CS

A3

SHEET

of

2

67

1

D

CC

B

AA

REV

AX1

8 7

6 5

4

3 2 1

D

V-RAMX4

GDDR5

64MX32

(1GB)

P62~P63

X32

DGPU

AMD CHELSEA PRO 128BIT

M2 29MM X 29MM

P53~P61

PEGX8

LVDS

PANEL

P44

DISPLAY

PORT

HDMI
PORT

B

P42

P43

SATA2

ODD

SATA0

HDD

P49

P49

MAIN BATT

P07

SYSTEM CHARGER

DC / DC SYSTEM POWER

LVDSX2

DPX2
HDMI

SATA2
SATA0

P06

FRONT SPKR
REAR SPKR

P49

SUB WOOFER

HP JACK X2

IVY BRIDGE

RPGA988B (SOCKET-G2)

37.5MM X 37.5MM

FDI

PANTHER POINT

FCBGA PACKAGE

27 MM X 27 MM

HDA

IDT 92HD91

TPM

SLB 9656

P66

DMI

LPC

ITE IT8572E/AX

SPI ROM

KBC

P20~P26

P30~P39

SPI

BIOS

SPI

P31

P40

AUDIO CODEC

THERMAL SENSOR

TI TMP302

8

P27

MIC JACK

INT DMIC

7 6

P44 P50

KEYBOARD

5 4

TOUCHPAD

P41 P41

USB 2.0

USB 3.0
USB 2.0

PCIE

DDR3

DDR3

DDR3 SO-DIMM 0
DDR3 SO-DIMM 1

USB P0

+

USB 3.0 P1

M/B

P48 P44

USB 3.0 REDRIVER

CARD READER

RTS5229

ALS PROXIMITY

SENSOR CM3633

CHANGE by

David Cheng

1066/1333/1600 MHZ . 16GB MAXIMUM MEMORY

1066/1333/1600 MHZ . 16GB MAXIMUM MEMORY

USB P4

WIRELESS AUDIO

P50

P47

USB P5

WEBCAM

DEBUG ONLY

USB P1

+

USB 3.0 P2

WLAN/WIMAX

P64

MINICARD

P51

P28

P29

USB P10

BLUETOOTH

USB P2

+

USB 3.0 P3

D/B

AR8151

10/100/1000MHZ

RJ45

P46

ACCELEROMETER

P50 P51

ST MICRE HP302DLT8-MBD

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

DOC.NUMBER

CODE

DATE

12-12-2011

23

SIZE

CS

A3

1310A24893-0 MTR

SHEET

of

3

1

D

CC

P51

P50P50D/B

P45

67

REV

AX1

B

AA

8 7

6 5

4

3 2 1

VRP3V3A

FDMC7696

ADAPTER

D

CHARGER

BATT_CLK

BATT_DAT

B

SCL

SDA

BQ24728

ACDET

AC_OK

PVBAT

AON7410

PVPACK

EN_3V_5V

EN_P0V75 S3

DDR3L_SEL

EN_P1V0_VCCP

DGPU_PWR_EN

5/3.3V

TPS51123

S5EN_P1V5
VREF

TPS51216

EN

TPS51219

EN_DEM

RT8208

VO
VO
VO
PG

VO

PG

VO

PG

VRP5V0A

CORE_PWEN#

VRP1V5

P0V75S

CORE_PWEN#

P0V75M_VREF

CORE_PWEN#

P1V5_PG

VRP1V05S_VCCP

VCCIO_PG

VRPVCORE_DGPU

DGPU_PWROK

PVPCIE

P1V0S_VCCPP1V0S_VCCP

P3V3A

EN_P1V8

P5V0A

VCCSA_VID0
VCCSA_VID1
EN_PVCCSA

AO6402AL

AO6402AL

AON7410

EN

AT1530F11U

VID0
VID1
EN

TPS51461

VO

VO

P3V3S

P5V0S

D

P1V5S

VRP1V8S

CC

VRPVSA

B

PVDDCI

VO

EN_VPCIE EN

G9330TB

DGPU_PWROK

PVCORE

EN

VOUT

PVAXG

EN_CORE

VR_SVID_DATA

VR_SVID_ALERT#

VR_SVID_CLK

8

7 6

5 4

VR_ON
SDA

ALERT#

PGOOD

PGOODGSCLK

ISL95836

CHANGE by

David Cheng

CORE_PG
AXG_PG

DATE

12-12-2011

23

VO

G9330TB

INVENTEC

TITLE

LV1.1_Lauren

CODE

SIZE

CS

A3

POWER PROCEDURE

DOC.NUMBER

1310A24893-0 MTR

SHEET

of

67

4

1

REV

AX1

AA

8 7

6 5

Power sequence

4

3 2 1

D

B

D

CC

B

AA

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

5

1

DOC.NUMBER

CODE

REV

AX1

67

8 7

PVADPTR

R6015

2_5%_6

2 1

ACDRV

OUT

IN

VADPBL

Q6010
1
2
3
4 5

S

G

NMOS_4D3S

FDMC7696

D

8
7
6

C6018

D

C6020

2 1

0.047UF_25V_2

R6017

C6019

2 1

0.1UF_25V_2

2200PF_50V_2

2 1

RSC_0402_DY

C6031

2 1

2 1

BATDRV

2 1

C6033

1UF_25V_3

IN

6

R6028

2 1

4.3K_5%_2

P1V5S PVADPTR

B

PVADPTR

R6029

2 1

R6030

2 1

D6018

2 1

2 1

1SS355VMTE_17

RSC_0402_DY

OUT

AC_OK

C6022

2 1

RSC_0402_DY

CSC0402_DY

ACDET>0.6V = SMBUS OK
ACDET>1.8V = ADP_PRES HI
ACDET>2.4V = AC_OK TO CHARGE
ACDET>3.15V = AC_OVP

8

R6021

ADP_PRES

2 1

300K_1%_2

35 40

R6049

2 1

47K_1%_2

7

40

40
7

7 6

OUT

40

I_ADP

BI
BI

6 5

KC_FBMA_11_321611_121A60T
KC_FBMA_11_321611_121A60T

L6015

L6016

C6017

2 1

1000PF_50V_2

100pF_50V_2

PVPACK

2 1

C6032

0.01UF_50V_2

OUT

ACDRV

1

S

2
3
4 5

G

NMOS_4D3S

AON7406

1

S

2
3
4 5

G

NMOS_4D3S

AON7406

R6018

2 1

4.3K_5%_2

P3V3AL

TI_BQ24728_QFN_20P

R6024

2 1

10K_5%_2

OUT

C6046

2 1

100PF_50V_2

BATT_DAT

BATT_CLK

21
21

Q6012

Q6011

C6047

4

1

2

C6016

2 1

C6015

2 1

100pF_50V_2

1000PF_50V_2

SEM_SM24_SOT23_3P_DY

D6017

1

2

3

P3V3AL

3

8

D

7
6

PVBAT_R

OUT

8

D

7
6

0.1UF_16V_2

21

C6029

1UF_25V_3

543

ACPRES

6

ACDET

7

IOUT

8

SDA

9

SCL

10

ILIM

BATDRV

P3V3A

R6023

2 1

100K_1%_2

R6046

2 1

2 1

CSC0402_DY

36.5K_1%_2

R6000

0.01_1%_6

C6028

VRPVADPTR_CSP

1

2

ACN

ACP

CMSRC

ACDRV

LODRV

GND

SRN

SRP

1514131211

4.3K_5%_2

VRPVADPTR_CSN

U6000

PHASE

R6043

HIDRV

REGN

21
43

21

BTST

TML

VCC

PVADPTR PVBAT

D5049

C6027

0.047UF_25V_3

2 1

R6026

2.2_5%_2

2 1

D6016

BAT54WS

21

21

OUT

BAT54CW

2 1

C6025

1UF_10V_2

0_5%_2

21

C6030

CSC0402_DY

21
20

19
18
17
16

2 1

R6025

R6020

0_5%_2

BATDRV

21

6

C

3

R6027

2 1

VRPVPACK_HG

VRPVPACK_PH

0.047UF_16V_2

VRPVPACK_LG

A2A1

20_5%_5

C6026

PVBAT

12

PAD6015

2 1

21

678

AON7410

NMOS_4D3S

G

3

21

678

AON7410

NMOS_4D3S

G

3

5 4

3 2 1

JACK6015

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

41

AMBER#

41

WHITE#

D6015

1SS355VMTE_17

IN
IN

R6048

21

21

2 1

C6048

2 1

2 1

9

10

10

PROF_HPW20008_10M100R_10P

1K_1%_2

R6047

12K_1%_2

OUT

0.0015UF_50V_2

POWERPAD_2_0610

IN

PVBAT_CHG

Q6000

D

C6002

C6001

C6000

2 1

S

CSC0805_DY

2 1

2 1

4.7UF_25V_5

10UF_25V_5

214 5

L6000

ETQP3W4R7WFN

Q6001

D

S

214 5

R7600

2 1

RSC_0603_DY

C7600

2 1

CSC0402_DY

21

C6024

2 1

CSC0402_DY

R6001

0.01_1%_6

C6023

0.1UF_16V_2

21
43

21

2 1

VRPVPACK_CSP

VRPVPACK_CSN

SIZE

CHANGE by

David Cheng

DATE

12-12-2011

23

40

ADP_ID

PVPACK

C6010

2 1

10UF_25V_5

2 1

2 1

10UF_25V_5

CSC0805_DY

C6012

C6011

C6021

0.1UF_25V_2

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

DOC.NUMBER

CODE

1310A24893-0 MTR

CS

A3

SHEET

of

67

6

1

D

CC

B

D6019

B0530W_7

2 1

AA

REV

AX1

8 7

6 5

4

3 2 1

D

P3V3AL

12

R6052

2 1

2.2K_5%_2

BATT_CLK

6

40

BI

BATT_DAT

6

40

BI

R6050

2 1

2 1

2.2K_5%_2

C7501

C7500

2 1

100PF_50V_2

100PF_50V_2

R6053

100_5%_2

R6051

100_5%_2

D7504

2 1

PHP_PESD5V0S1BB_SOD523_2P

21
21

12

D7506

2 1

PHP_PESD5V0S1BB_SOD523_2P

PVPACK

BP0206C_B7200B3_9H

CN6050

1

1

2

2

3

3

4

4

5

5

6

6

G1

G

G2

G

D

CC

21

C6050

0.1UF_25V_2

B

B

AA

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

7

1

DOC.NUMBER

CODE

REV

AX1

67

8 7

6 5

4

3 2 1

D

OCP=8AMP

3.36V=((R6100/R6101)+1)*2

B

8

OUT

OCP=7AMP

P3V3A

P3V3AL

VBATP

8

19

IN

VRP3V3A

2 1

2 1

2 1

POWERPAD_2_0610

2 1

POWERPAD1X1M

R6100

6.8K_1%_2

R6101

10K_1%_2

PAD6100

PAD6121

C6100

12

12

+

2 1

220UF_6.3V

PVBAT

PAD6110

2 1

C6110

2 1

L6100

ETQP3W3R3WFN

VRP3V3A

VRP3V3A_LDO

EN_3V

12

R6110

2 1

73.2K_1%_2

R6160

POWERPAD_2_0610

EN_5V

ININ

2 1

71.5K_1%_2

2VREF

OUT

PVADPTR

D6999

BAV70W_7_F

3

21

PVBAT

ININ

VRP5V0A_VIN

8

OUT

D

TON=3.3V:300KHZ/375KHZ

21

18

VRP5V0A_PH

678

AON7410

NMOS_4D3S

G

3

214 5

678

AON7702A

G

3

214 5

VRP5V0A_LG

8

8

OUT

8

IN

VBATP

Q6150

C6160

D

2 1

S

D

Q6151

2 1

S

2 1

4.7UF_25V_5_DY

R7615

C7615

IN

C6161

2 1

ETQP3W3R3WFN

RSC_0603_DY

CSC0402_DY

18

10UF_25V_5

L6150

21

19

CC

OCP=8AMP

5.08V=((R6050/R6151)+1)*2

VRP5V0A

R6150

2 1

+

C6150

2 1

220UF_6.3V

R6151

2 1

8

18

OUT

15.4K_1%_2

B

10K_1%_2

5V_PG

OUT

678

D

S

D

S

3

214 5

678

3

214 5

Q6100

NMOS_4D3S

G

C6115

VRP3V3A_HG
VRP3V3A_PH
VRP3V3A_LG

R6114

2.2_5%_30.1UF_16V_2

21

21

Q6101

G

VRP3V3A_LDO

8

OUT

C6121

1UF_6.3V_2

25

5

3

4

TML

TONSEL

TRIP2

VREF

VFB2

7 24

VO2 VO1

8

VREG3

9 22

VBST2

10 21

DRVH2

11 20

LL2

12 19

DRVL2

SKIPSEL

GND

EN0

VIN

16

15618

13

14

TI_TPS51123RGER_QFN_24P

R6113

2 1

2 1

2 1

330K_5%_2_DY

AON7410

C6111

2 1

4.7UF_25V_5_DY

21

10UF_25V_5

AON7702A

R7610

2 1

RSC_0603_DYCSC0402_DY

C7610

2 1

8

IN

C6123

U6100

PGOOD

VBST1

DRVH1

DRVL1

2 1

0.22UF_6.3V_2

R6155

2.2_5%_3

23

LL1

VRP5V0A_HG
VRP5V0A_PH

21

C6155

0.1UF_16V_2

1

2

TRIP1

VFB1

VREG5

ENC

17

VRP5V0A_LDO

41

OUT

C6122

1UF_25V_3

C6120

2 1

10UF_6.3V_3

OCP=7AMP

8

IN

SKIP:OOA=3.3V; PWM=2VREF; AUTO=GND

SKIP_3V_5V

18

IN

EN_3V_5V

19

IN

VRP5V0A_VIN

8

IN

P5V0A

PAD6150

2 1

POWERPAD_2_0610

12

VRP5V0A

8

18

IN

AA

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

SIZE

8

7 6

5 4

CHANGE by

DATE

12-12-2011David Cheng

23

CS

A3

1310A24893-0 MTR

SHEET

of

8

1

DOC.NUMBER

CODE

REV

AX1

67

8 7

6 5

4

3 2 1

PVBAT

21

D

P5V0A

1 2

PAD6210

D

POWERPAD_2_0610

P0V75S

678

C6216

2 1

2.2UF_6.3V_3

U6200

EN_P0V75

19

IN
IN

IN

EN_P1V5

DDR3L_SEL

R6200

10K_1%_2

21

19

21

R6201

C6217

B

2 1

52.3K_1%_2

C6218

2 1

0.01UF_50V_2

0.1UF_16V_2

R6203

2 1

100K_5%_2

17

S3

16

S5

6

VREF

8

REFIN

7

GND

19

MODE

18

TRIP

21

TI_TPS51216RUKR_QFN_20P

R6202

66.5K_1%_2

PGOOD

VDDQSNS

VLDOIN

VTTSNS

VTTGND

VTTREF

VBSTV5IN

DRVH

DRVL

PGND

1512
14
13

SW

11

10
20
9
2
3

VTT

1

4
5
21

TML

2.2_5%_3

VRP1V5_HG

VRP1V5_PH

VRP1V5_LG

P0V75M_VREF

C6220

2 1

R6215

10UF_6.3V_5

2 1

21

C6221

C6215

0.1UF_16V_2

0.22UF_6.3V_2

21

FDMC8884

FDMS0310AS

P1V5_PG

Q6200

D

NMOS_4D3S

G

S

3

2145

678

Q6201

D

C6211

2 1

21

R7620

RSC_0603_DY

G

S

3

OUT

2145

19

C7620

2 1

C6210

2 1

4.7UF_25V_5

10UF_25V_5

OCP=16AMP

L6200

21

PCMC104T_1R0MN

43

PAD6220

CSC0402_DY

VRP1V5

21

+

C6200

1 2

2 1

OUT

9

CC

POWERPAD1X1M

330UF_2V_9MR_PANA_-35%

B

1.511V=REFIN=1.8*(R6201/(R6200+R6201))
MODE=100KOHM:TRACKING DISCHARGE

OCP=12AMP

P1V5

PAD6200

2 1

POWERPAD_2_0610

12

VRP1V5

9

IN

AA

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

9

1

DOC.NUMBER

CODE

REV

AX1

67

8 7

6 5

4

3 2 1

D

PVBAT

EN_P1V0_VCCP

19

IN

R6303

2 1

MODE=200KHZ:400KHZ

P1V0_VCCP_PG

19

OUT

modify on 09/19

R6306

C6308

2 1

2 1

2.2UF_10V_3

10K_5%_2

R6308

C6320

2 1

2 1

11.3K_1%_2

0.01uF_50V_2

VCCIO_SEL

25

IN

VSS_SENSE_VCCIO

22

IN

VCC_SENSE_VCCIO

22

IN

VOUT=2*11.3/(10+11.3)=1.06V

R6307

21

0_5%_2_DY

TI_TPS51219RTER_QFN_16P

2 1

C6319

0.01UF_50V_2

B

200K_5%_2

678

FDMC7696

D

Q6300

NMOS_4D3S

G

S S

3

2145

678

FDMS0306AS

Q6301

D

G

3

214 5

C6310

2 1

21

2 1

10UF_25V_5

CYN_PCMB063T_R33MS_4P

R7630

RSC_0603_DY

C7630

2 1

CSC0402_DY

21

0.1UF_16V_2

P5V0A

2 1

C6315

21

C6316

2.2UF_6.3V_3

R6315

2.2_5%_3

14

17

16815

U6300

VREF

REFIN

GSNS

VSNS

PWPD

COMP

6

5

1
2
3
4

13

EN

BST

MODE

PGOOD

TRIP

GND

PGND

SW

DH

DL

V5

12

VRP1V05S_VCCP_PH

11

VRP1V05S_VCCP_HG

10

VRP1V05S_VCCP_LG

9

7

R6302

2 1

47.5K_1%_2

21

1 2

PAD6310

POWERPAD_2_0610

C6311

C6312

2 1

L6300

CSC0805_DY

21

21

43

43

VRP1V05S_VCCP

C6300

2 1

22UF_6.3V_5

C6301

OCP=25AMP

10

OUT

+

2 1

4.7UF_25V_5

D

CC

B

330UF_2V_9MR_PANA_-35%

OCP=8AMP

P1V0S_VCCP

OCP=12AMP

P1V05S_VCCP

PAD6300

2 1

POWERPAD_2_0610

POWERPAD_2_0610

POWERPAD_2_0610

12

PAD6301

2 1

12

PAD6400

2 1

12

VRP1V05S_VCCP

P1V0S_VCCP

10

IN

AA

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6710

8 7

6 5

4

3 2 1

D

D

P3V3A

P3V3A

C6971

2 1

10UF_6.3V_3

R6970

10_5%_2

2 1

EN_P1V8

19

IN

C6972

2 1

0.1UF_16V_2

B

U6970

GMT_AT1530F11U_SOP8_8P

8

VIN

1

VCC

5

EN

PGNDLXGND

673

TML

VRP1V8S_PH

FB

REF

9

4

2

C6973

2 1

L6970

PAN_ELL5PR2R2N

21

R6973

13K_1%_210K_1%_2

2 1

R6972

2 1

VRP1V8S

C6974

2 1

2 1

CSC0402_DY

0.1UF_16V_2

OCP=4.5AMP

OUT

1.84V=((R6973/R6972)+1)*0.8

C6970

22UF_6.3V_5

OCP=4.5AMP

11

P1V8S

PAD6970

2 1

POWERPAD_2_0610

12

VRP1V8S

11

IN

CC

B

AA

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

11

1

DOC.NUMBER

CODE

REV

AX1

67

8 7

6 5

4

3 2 1

D

C6522

VCCSA_SENSE

21

R6502

R6524

0.01UF_50V_2

2 1

C6515

0.1UF_16V_2

21

VCCSA_VID0

21

VCCSA_VID1

21

21

EN_SA

SA_PG

IN

IN

IN

IN

OUT

25

VRPVSA_PH

19

25

25

19

L6500

21

CYN_PCMB063T_R33MS_4P

43

OCP=7AMP

21
43

C6502

2 1

OCP=7AMP

PVSA

POWERPAD_2_0610

2 1

C6500

2 1

C6501

22UF_6.3V_522UF_6.3V_5

VRPVSA

C6503

22UF_6.3V_5_DY22UF_6.3V_5

2 1

PAD6500

2 1

12

VRPVSA

12

12

IN

C6520

2 1

C6521

2 1

P5V0A

PAD6510

1 2

POWERPAD1X1M

12

IN OUT

VRPVCCSA_IN

21

VRPVCCSA_IN

C6511

0.1UF_16V_2

12

OUT

C6510

12

2 1

IN

22uF_6.3V_5

VRPVCCSA_IN

2 1

0.22UF_6.3V_2

25

TML

24
23

VIN

22

VIN

21

PGND

20

PGND

19

PGND

B

C6523

1UF_6.3V_2

C6524

2 1

3300PF_50V_2

R6520

2 1

5.11K_1%_2

1

4

3

2

5

GND

COMP

VREF

VOUT

SLEW

U6500

V5FILT

VID0

VID1

V5DRV

PGOOD

151417

18

16

2 1

1UF_6.3V_2

R6521

6

RSC_0402_DY

MODE

7

SWVIN

8

SW

9

SW

10

SW

11

SW

12

BST

EN

TI_TPS51461RGER_QFN_24P

13

0_5%_2

0_5%_2

R6525

0_5%_2

D

CC

B

AA

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6712

8 7

21

C6731

VSUMG-

1314

IN

0.1UF_16V_2

21

D

R6719 NEAR L66710/L6720

R6719

10K_5%_NTC

21

R6720

VSUMG+

14

IN

VSUMG-

1314

IN

2.61K_1%_2

C6733

2 1

ISEN1G

14

IN

ISEN2G

14

IN

27.4K_1%_2

470K_5%_NTC

B

14

IN

14

IN

14

IN

470K_5%_NTC

ISEN3

ISEN2

ISEN1

0.22UF_16V_2

21

R6721

21

R6722

21

R6620

21

R6621

21

C6628

VSUM-

1314

IN

VSUM+

14

IN

R6624 NAER L6610/L6620

VSUM-

1314

IN

0.22UF_16V_2

R6623

2 1

2.61K_1%_2

R6624

2 1

10K_5%_NTC

21

R6718

C6730

11.3K_1%_2

C6732

2 1

0.22UF_16V_2

21

R6723

3.83K_1%_2

R6622

3.83K_1%_227.4K_1%_2

13

22

IN

22

OUT

13

22

BI

21

40

OUT

19

21

IN

R6621 NEAR ONE PH HI SIDE

21

C6627

0.22UF_16V_2

21

R6625

C6630

11.3K_1%_2

2 1

CSC0402_DY

VR_SVID_CLK

VR_SVID_ALERT#

VR_SVID_DATA

CPU_PROCHOT#

EN_CORE

21

2 1

C6629

2 1

0.1UF_16V_2

8

7 6

6 5

R6717

549_1%_2

C6729

2 1

0.22UF_10V_2

1

ISUMPG

ISEN1G

3

ISEN2G

4

NTCG

5

SCKL

6 U6600

ALERT#

7

SDA

8

VR_HOT#

9

10

NTC

41

PAD

C6626

0.22UF_16V_2

C6631

CSC0402_DY

2 1

0.22UF_6.3V_2

P5V0A

R6716

2 1

0_5%_2_DY

ISUMNG

ISEN3_FB2

11

C6728

1000PF_50V_2

39

RTNG

ISEN2

ISEN1 FBG

12213 38

21

COMPG

ISUMP

144015

TP24

1
36

PGOODG

ISUMN

21

INTERSIL_ISL95836HRTZ_T_TQFN_40P

VR_ON

R6626

866_1%_2

21

14

OUT

2 1

330PF_50V_2

14

14

OUT

OUT

GFX_VSS_SENSE

GFX_VCC_SENSE

C6727

14

14

OUT

OUT

IN
IN

2 1

C6726

470PF_50V_2

TP88

VRPVAXG_BOOT1

VRPVAXG_PH1

GPWM2

352833

16

VRPVAXG_HG1

VRPVAXG_LG1

32

34

PWM2G

LGATE1G

FB

RTN

173718

3120

BOOT2

UGATE2

BOOT1GBOOT1

PHASE1G

UGATE1G

PHASE2

LGATE2

VCCP

VDD

PWM3

LGATE1

PHASE1

UGATE1

COMP

PGOOD

19

VRPVCORE_BOOT2

30

VRPVCORE_HG2

29

VRPVCORE_PH2

VRPVCORE_LG2

27
26
25

CPWM3

24

VRPVCORE_LG1

23

VRPVCORE_PH1

22

VRPVCORE_HG1

21

VRPVCORE_BOOT1

2 1

VCCSENSE

2 1

C6633

330PF_50V_2

2 1

C6632

1000PF_50V_2

VSSSENSE

C6634

5 4

4

25

25

R6714

2 1

3.65K_1%_2

CORE_PG

R6627

3.65K_1%_2

2 1

499_1%_2

R6628

499_1%_2470PF_50V_2

21

22

IN

22

IN

R6715

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT

3 2 1

2 1

R6712

2K_1%_2

2 1

R6713

267K_1%_2

47PF_50V_2

330PF_50V_2

150PF_50V_2

2 1

C6725

C6723

2 1

C6724

21

2 1

R6711

169K_1%_2

VR_SVID_CLK

13

22

OUT

VR_SVID_DATA

13

22

BI

R6635

2 1

P1V0S_VCCP

R6636

2 1

54.9_1%_2

C6640

130_1%_2

2 1

D

0.1UF_10V_2

P5V0A

0_5%_2

2 1

14

14

14

14

R6633

C6639

2 1

21

R6634

1_5%_2

CC

2.2UF_10V_3

14

14

14

14

14

33

21

47PF_50V_2

2 1

R6629

267K_1%_2

2 1

R6630

2K_1%_2

2 1

C6635

150PF_50V_2

2 1

680PF_50V_2

C6636

C6637

C6638

2 1

1uF_6.3V_2

B

R6631

21

5.76K_1%_2

21

AA

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

CHANGE by

David Cheng

DATE

12-12-2011

23

SIZE

DOC.NUMBER

CODE

1310A24893-0 MTR

CS

A3

SHEET

of

1

REV

AX1

6713

8 7

6 5

4

3 2 1

PVBAT

1

12

+

C6800

C6801

68UF_25V

2 1

2 1

VRPVCORE_BOOT1

13

D

IN

13

IN

13

IN

13

IN

VRPVCORE_BOOT2

13

IN

13

IN

13

IN

13

IN

C6803

C6802

2 1

100UF_25V

100UF_25V

VRPVCORE_HG1

VRPVCORE_PH1

VRPVCORE_LG1

VRPVCORE_HG2

VRPVCORE_PH2

VRPVCORE_LG2

+

15UF_25V

2 1

R6601

R6607

2.2_5%_3

POWERPAD_2_0610

IN

21

0.1UF_16V_22.2_5%_3

21

0.1UF_16V_2

B

PAD6600

VRPVBAT_CPU

C6622

21

C6623

21

2

FDMS7692 FDMS0300S

NMOS_4D3S

G

G

FDMS7692 FDMS0300S

NMOS_4D3S

G

G

+

+

P5V0A

C6625

2 1

1UF_6.3V_2

INTERSIL_ISL6208BCRZ_T_QFN_8P

8

U6630

9

TML

8

PHASE

UGATE

7

FCCM

6

VCC

5 4

LGATE GND

13

IN

CPWM3

BOOT

VRPVCORE_PH3

VRPVCORE_HG3

1
2
3

PWM

R6613

C6624

21

0.1UF_16V_22.2_5%_3

7 6

PVCORE OCP=112A

678

Q6610

D

C6612

2 1

ISEN1

VSUM+

VSUM-

10UF_25V_5

R6602

10K_1%_2

R6603

3.65K_1%_2

R6604

10_1%_2

1

ETQP4LR36AFM

21

21

21

L6610

2
43

470UF_2V

10UF_25V_5

OUT

OUT

OUT

C6615

2 1

ISEN2

VSUM+

VSUM-

10UF_25V_5

R6608

10K_1%_2

R6609

3.65K_1%_2

R6610

10_1%_2

ETQP4LR36AFM

21

21

21

L6620

21
43

470UF_2V

CSC0805_DY

C6617

2 1

10UF_25V_5

L6630

ETQP4LR36AFM

OUT

OUT

OUT

ISEN3

VSUM+

VSUM-

13

1314

1314

R6614

10K_1%_2

R6615

3.65K_1%_2

R6616

10_1%_2

21

21

21

5 4

21

3

214 5

678

3

214 5

678

3

214 5

678

3

214 5

CSC0805_DY

CSC0805_DY

C6616

2 1

CSC0805_DY

R7663

RSC_0603_DY

2 1

C7663

CSC0402_DY

2 1

C6611

2 1

13

1314

1314

C6614

2 1

13

OUT

1314

OUT

1314

OUT

C6610

2 1

S

Q6611

D

R7661

RSC_0603_DY

2 1

C7661

CSC0402_DY

2 1

Q6620

D

C6613

2 1

SS

Q6621

D

R7662

RSC_0603_DY

2 1

S

C7662

CSC0402_DY

2 1

678

FDMS7692

FDMS0300S

Q6630

D

NMOS_4D3S

G

S S

3

214 5

678

Q6631

D

G

3

214 5

C6600

C6602

PVAXG OCP=55A

PAD6700

21

FDMC7696 FDMS0306AS

PVBAT

12

2 1

NMOS_4D3S

G

G

678

3

678

3

Q6710

D

C6710

2 1

S

214 5

Q6711

D

R7671

RSC_0603_DY

2 1

C7671

214 5

CSC0402_DY

2 1

C6711

2 1

10UF_25V_5

10UF_25V_5

L6710

21

ETQP4LR36AFM

OUT

OUT

OUT

ISEN1G

VSUMG+

VSUMG-

13

1314

1314

R6702

10K_1%_2

R6703

3.65K_1%_2

R6704

10_1%_2

21

21

21

43

470UF_2V

C6700

PVCORE

IN

R6701

2.2_5%_3

POWERPAD_2_0610

VRPVBAT_AGX

C6720

21

0.1UF_16V_2

1

1

C6601

+

+

470UF_2V

3

2

3

2

VRPVAXG_BOOT1

13

IN

VRPVAXG_HG1

13

IN

VRPVAXG_PH1

13

IN

VRPVAXG_LG1

13

IN

PVCORE

PVBAT

1

1

470UF_2V

+

+

C6603

3

2

3

2

P5V0A

C6722

2 1

PVCORE

21
43

U6720

9

TML

8

PHASE

1UF_6.3V_2

UGATE

7

FCCM

BOOT

6

VCC

5 4

PWM

LGATE GND

INTERSIL_ISL6208BCRZ_T_QFN_8P

13

IN

GPWM2

1
2
3

R6706

2.2_5%_3

1

21

0.1UF_16V_2

C6721

12

PAD6701

POWERPAD_2_0610

2 1

678

FDMC7696

2

FDMS0306AS

Q6720

D

NMOS_4D3S

G

3

G

214 5

678

3

2145

C6712

2 1

S

Q6721

DS

R7672

RSC_0603_DY

2 1

S

C7672

CSC0402_DY

2 1

C6713

2 1

4.7UF_25V_5_DY

10UF_25V_5

L6720

21

ETQP4LR36AFM

OUT

OUT

OUT

ISEN2G

VSUMG+

VSUMG-

13

1314

1314

R6707

10K_1%_2

R6708

3.65K_1%_2

R6709

10_1%_2

21

21

21

43

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

DOC.NUMBER

CODE

CHANGE by

David Cheng

DATE

12-12-2011

23

SIZE

A3

1310A24893-0 MTR

CS

SHEET

of

6714

1

PVAXG

1

+

2

PVAXG

REV

AX1

D

CC

3

B

AA

8 7

6 5

4

3 2 1

POW_SW0

POW_SW1

191817

16

20

G0G1G2

CS

TON

PHASE
UGATE

D0D1D2S1S2

987

6

10

POW_SW2

R6758

21

49.9K_1%_2

360K_1%_2

P5V0A

10UF_6.3V_3

VRPVCORE_DGPU_LGEN_DGPU

11

GATE

VDD

BOOT

RICH_RT8232AZQW_QFN_20P

R6752
12
13
14
15

VRPVCORE_DGPU_PH
VRPVCORE_DGPU_HG

D

21

U6750

GND

1

18

IN

DGPU_PG

18

IN

R6753

49.9K_1%_2

C6757

2 1

R6754

C6758

0.22UF_10V_2

2 1

1000PF_50V_2

R6757

B

R6760

2K_1%_2

EN_MODE

2

FB

3

PGOOD

4

REFO

5

REFIN

1

2

2 1

34.8K_1%_2

R6756

2K_1%_2

2 1

2 1

2.1K_1%_2

R6759

2.15K_1%

2 1

2 1

R6755

21

C6754

56

IN

56

IN

56

IN

21

21

C6753

0.1UF_16V_22.2_5%_3

PVBAT

678

NMOS_4D3S

678

3

Q6750

D

C6760

2 1

G

S

3

214 5

678

D

S

214 5

FDMS0310AS

D

G

S

3

214 5

C6762

C6761

2 1

2 1

10UF_25V_5

CSC0805_DY

4.7UF_25V_5_DY

L6750

PAN_ETQP4LR36ZFC_4P

Q6752

R7675

2 1

RSC_0603_DY

2 1

C7675

CSC0402_DY

OCP=25AMP

21
43

R6750

0_5%_2

2 1

R6751

VRPVCORE_DGPU

1

+

C6750

470UF_2V

3

2

+

C6751

2 1

OUT

OCP=25AMP

PVCORE_DGPU

15

R6762

0.001_1%_1W

VRPVCORE_DGPU

21

15

IN

2 1

RSC_0402_DY

FDMS7692

21

FDMS0310AS

Q6751

G

D

CC

330UF_2V_9MR_PANA_-35%

B

R6761

2.15K_1%

2 1

AA

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6715

8 7

6 5

4

3 2 1

D

D

P1V0S_VCCP

12

PAD6940

2 1

678

POWERPAD_2_0610

FDMC7672

C6945

2 1

4.7UF_6.3V_3

6
5
4

R6940

2 1

C6942

P5V0A

0.1UF_16V_2

2 1

GMT_G9330TB1U_SOT23_6P

U6940

1

DRV

VCC

2

ADJ

GND

3

PGD

EN

2 1

18

VDDCI_PG

OUT

EN_VDDCI

18

IN

B

Q6940

D

NMOS_4D3S

G

S

3

2145

21

C6943

2 1

CSC0402_DY

SSM3K17FU

R6941

90.9_1%_2

S

Q6941

21

R6942

100_1%_2

47_5%_2

C6941

0.033UF_16V_2

21

R6943

806_1%_2

D

D S

G

R6944

G

1K_5%_2

21

VDDCI_SW

PVDDCI

OCP=6AMP

HIGH : 0.908V = 0.5 [ 1 + ( ( R6941//R6943) / R6942 ) ]

C6947

C6940

2 1

2 1

22UF_6.3V_5

22UF_6.3V_5

56

IN

LOW : 0.954V=0.5 ( 1+ R6941/R6942 )

CC

B

C6944

2 1

1000pF_50V_2

AA

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6716

8 7

6 5

4

3 2 1

D

OCP=6AMP

0.943V=0.5(1+R6951/R6952)

D

P1V0S_VCCP PVPCIE

678

FDMC7696

D

NMOS_4D3S

C6955

2 1

P5V0A

GMT_G9330TB1U_SOT23_6P

U6950

1

2
3

C6952

2 1

0.1UF_16V_2

18

EN_VPCIE

IN

6

DRV

VCC

5

ADJ

GND

4

PGD

EN

G

4.7UF_6.3V_3

R6950

2 1

2 1

S

3

2145

47_5%_2

R6951

2 1

C6951

R6952

0.033UF_16V_2

2 1

B

12

Q6950

PAD6950

2 1

POWERPAD1X1M

C6950

2 1

90.9_1%_2

22UF_6.3V_5

CC

100_1%_2

B

AA

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6717

8 7

6 5

4

3 2 1

EN_VPCIE

17

OUT

2 1

10K_5%_2

D

C6953

2 1

0.1uF_16V_2

R6953

DGPU_PWR_EN

18

IN

32 36 55

8

5V_PG

IN

R6999

100K_5%_2_DY

D

P3V3AL

21

P3V3S P3V3S

R206

10K_5%_2

2 1

DGPU_PWROK

3640

OUT

R754

0_5%_2

21

DGPU_PG

15

IN

16

OUT

VDDCI_PG

R205

10K_5%_2

2 1

CORE_PWEN

19

2540

PAD6135

1 2

POWERPAD1X1M

21

SKIP_3V_5V

OUTIN

8

CC

C3805

2 1

0.1uF_16V_2

IN

D6997

VRP5V0A_LG

B

3

8

IN

VRP5V0A

C6994

2 1

0.1UF_25V_2

2

D3801

B

323655

55

18

PX_MODE

IN

DGPU_PWR_EN

IN

R3808

R3809

0_5%_2

21

8.2K_5%_20_5%_2_DY

21

DIODE-BAT54-TAP-PHP

NC

R3807

21

13

EN_DGPU

OUT

15

P15V0A

C3804

2 1

0.1uF_16V_2

SI 1012

R6945

0_5%_2

21

EN_VDDCI

OUT

16

2 1

C6998

2 1

D6998

BAV99W_7_F

C6996

2 1

0.1UF_25V_2

3

2 1

C6997

0.1UF_25V_20.1UF_25V_2

2 1

BAV99W_7_F

C6995

2 1

0.1UF_25V_2

C6946

2 1

CSC0402_DY

AA

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6718

8 7

6 5

4

3 2 1

P3V3S

P15V0A

1

R701

1M_5%_2

2

C845

2200PF_50V_2

V3S_R_EN

D

Q90

3

DS

IN

CORE_PWEN#

1921

40

1

SSM3K7002FU

G

1

2

2

P3V3S

1

SSM3K7002FU

1

2

Q36

DS

G

3

2

R362

47_5%_5

I112

B

P5V0S

1

R451

47_5%_5

2

Q49

3

DS

1

SSM3K7002FU

G

2

1921

40

P3V3A P3V3S

1
2
5

OUT

R634

21

0_5%_2

P5V0A

1
2
5

R700

21

0_5%_2

P1V5

8
7
6

R65

21

0_5%_2

CORE_PWEN#

IN

Q81

D

NMOS_4D1S

AO6402AL

49

V3S_EN

Q85

D

NMOS_4D1S

AO6402AL

V5S_EN

Q12

D

NMOS_4D3S

AON7410

4

S

36

G

4

S

36

G

1

S

2
3
45

G

1

SSM3K7002FU

(2.2A)

1

C764

2 1

10uF_6.3V_3

2

C679

CSC0402_DY

P5V0S

(3.5A)

C851

2 1

P1V5S

C842

2 1

0.1UF_16V_2_DY

10UF_6.3V_3

(6A)

C39

10UF_6.3V_3

2 1

2540

2540

Q13

G

R76

100_5%_2

2 1

3

DS

2

1

VBATP

IN

2

8

C682

CSC0402_DY

SA_PG

12

IN

P1V5_PG

9

IN

R624

R52

P3V3AL

SI2 1229

21

R769

2 1

383K_1%_2

C6999

R768

2 1

2 1

100K_1%_2

40

RESUME_PWEN

R6997

2 1

100K_1%_2

R6998

2 1

100K_1%_2

0.1uF_25V_2_DY

R953

1M_1%_2

5

U55

1

+

+

4

OUT

3

-

-

2

ON_LMV331SN3T1G_TSOP_5P

R3800

10K_5%_2

21

R952

0_5%_2

EN_P1V5

C3800

2 1

0.01UF_50V_2

2

D3800

1819

100K_5%_2

R3801

NC

21

DIODE-BAT54-TAP-PHP

13

EN_P0V75CORE_PWEN

C3801

2 1

0.1UF_16V_20.01UF_50V_2

R3802

21

1819

CORE_PWEN

IN OUT

10K_5%_2

EN_P1V0_VCCP

C3802

2 1

21

OUTIN

2540

OUTIN

100_5%_2

21

100_5%_2

21

SI 1012

EN_3V_5V

8

OUT

ALWAYS_PW_EN

40

IN

9

CORE_PWEN

1819

9

P1V0_VCCP_PG

10

10

40

IN OUT

21

2 1

CPU_PWEN

R688

10K_5%_2

C829

1000PF_50V_2

10K_5%_2

ALL_PWRGD_IN

R3803

21

R3805

21

0_5%_2

R3806

0_5%_2

C3803

2 1

P3V3S

21

R3804

C900

2 1

EN_P1V8

0.01UF_50V_2

10K_5%_2

CSC0402_DY

21

EN_CORE

OUT

EN_SA

D

21

40

CC

11

OUTIN

B

12

OUTIN

AA

13

INVENTEC

TITLE

LV1.1_Lauren

+V5S & +V3S

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

19 67

1

DOC.NUMBER

CODE

REV

AX1

8 7

6 5

4

3 2 1

D

D

CC

CPU

B

B

AA

INVENTEC

TITLE

LV1.1_Lauren

BLANK

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6720

8 7

6 5

4

3 2 1

P1V8S P1V8S

C26

AN34

AL33

AN33

AL32

AN32

AM34

AP33

AR33

CN19

A28

PROC_SELECT#

SKTOCC#

CATERR#

PECI

CLOCKS

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

MISCDDR3

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

V8

SM_DRAMPWROK

RESET#

JTAG & BPM

PWR MANAGEMENT THERMAL MISC

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PRDY#
PREQ#

TRST#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

DBR#

TCK
TMS

TDI

TDO

CLK_DMI_PCH_R

A27

CLK_DMI_PCH#_R

A16

CLK_DP_P_R

A15

CLK_DP_N_R

R8

DDR3_DRAMRST#_CPU

AK1

R119

A5

R484

A4

R480

AP29
AP27

XDP_PREQ#

AR26

XDP_TCLK

AR27

XDP_TMS

AP30

XDP_TRST#

AR28

XDP_TDI_R

AP26

XDP_TDO

AL35

XDP_DBRESET#

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

21
21
21

R544
R541

R508
R506

R704
R705

140_1%_2

25.5_1%_2
200_1%_2

TP24
TP21

TP17
TP20
TP28

TP27
TP18

TP40

TP26
TP22
TP32
TP30
TP37
TP35
TP36
TP38

1
1

1
1
1

1
1

1

1
1
1
1
1
1
1
1

21
21

21
21

1K_5%_2_DY

21
21

1K_5%_2_DY

OUT

0_5%_2
0_5%_2

0_5%_2
0_5%_2

21

CLK_DMI_PCH
CLK_DMI_PCH#

CLK_DP_P
CLK_DP_N

32

IN

32

IN

32

IN

32

IN

P1V0S_VCCP

D

P3V3S

XDP_DBRESET#

TP24

TP24

TP24

TP24

TP24

TP24

TP24

TP24

TP24

TP24

TP24

TP24

TP24

TP24

TP24

TP24

IN

IN
IN
IN

IN
OUT
OUT

XDP_TDO

XDP_TMS

XDP_TDI_R

XDP_PREQ#

XDP_TCLK

XDP_TRST#

R222

R225
R227
R226
R213
R556
R558

21

21
21
21
21
21
21

1K_5%_2

51_5%_2

51_5%_2

51_5%_2

51_5%_2_DY

51_5%_2

51_5%_2

CC

P1V0S_VCCP

B

R711

1K_5%_2_DY

NV_CLE

36

OUT

D

2 1

1K_5%_2

R529

21

2 1

R531

2.2K_5%_2

P1V0S_VCCP

13
40

21

CPU_PROCHOT#

IN

IN

R561

62_5%_2

2 1

C693

47PF_50V_2

2 1

PM_DRAM_PWRGD_CPU

36
40

36

10K_5%_2

36

OUT

OUT

R203

IN

H_PECI

R562

56_5%_2

PM_THRMTRIP#

33

BI

21

H_PWRGD

R482

130_1%_2

51
35
40
66

IN

BUF_PLT_RST#

R217

1.5K_5%_2

B

21

21

21

R559

43_5%_2

H_PM_SYNC

2 1

21

R218

750_1%_2

P1V5

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

CPU SOCKET PN: 6026B0222201

P3V3A

SI 1201

R118

1K_5%_2

2 1

U6

OUT

PM_DRAM_PWRGD
ALL_PWRGD_IN

33

19

40

1
2

3

NXP_74AHC1G09GV_SOT753_5P

P3V3A P1V5S

5

VCC

B

4

Y

A

GND

2 1

3

DS

2

R116

200_5%_2

2 1

PM_DRAM_PWRGD_CPU

R117

RSC_0402_DY

1

G

Q18

CORE_PWEN#

R488

0_5%_2

C588

21

BSS138

2 1

2532

21

OUTIN

21

19

40

IN

PCH_DDR_RST

IN

DDR3_DRAMRST#_CPU

IN

3300PF_50V_2

SSM3K7002FU_DY

R479

2 1

1K_1%_2

Q55

3

DS

1

G

2

R486

21

0_5%_2_DY

R487

4.99K_1%_2

2 1

R485

1K_5%_2

21

DDR3_DRAMRST#

OUT

28 29

AA

INVENTEC

TITLE

LV1.1_Lauren

CPU-1

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

21

1

DOC.NUMBER

CODE

REV

AX1

67

8 7

C164

2 1

C156

2 1

10UF_6.3V_310UF_6.3V_3

C165

10UF_6.3V_3

C151

2 1

2 1

10UF_6.3V_3

C145

2 1

10UF_6.3V_3

D

C158

2 1

C653

2 1

C332

2 1

C153

2 1

C325

2 1

22UF_6.3V_522UF_6.3V_5

C652

2 1

C172

10UF_6.3V_3

C303

22UF_6.3V_5

C646

22UF_6.3V_5

C171

2 1

2 1

10UF_6.3V_3

C618

2 1

2 1

22UF_6.3V_5

C635

2 1

2 1

22UF_6.3V_5

C126

2 1

10UF_6.3V_3

C308

2 1

22UF_6.3V_5

C655

2 1

22UF_6.3V_5

B

8

7 6

6 5

PVCORE

(94A)

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28

10UF_6.3V_3

10UF_6.3V_3

22UF_6.3V_5

22UF_6.3V_5

AG27
AG26

AF35
AF34
AF33
AF32

AF31

AF30
AF29
AF28
AF27

AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26

Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

CN19

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

POWER

PEG AND DDR

CORE SUPPLY

SVIDSENSE LINES

VSS_SENSE_VCCIO

5 4

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

4

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

3 2 1

P1V0S_VCCP

(8.5A)

C643

C607

C624

2 1

22UF_6.3V_5

C131

2 1

22UF_6.3V_5

C118

2 1

22UF_6.3V_5

C608

2 1

22UF_6.3V_5

C117

2 1

22UF_6.3V_5

C614

2 1

22UF_6.3V_5

C124

2 1

22UF_6.3V_5

C606

2 1

22UF_6.3V_5

C605

2 1

2 1

22UF_6.3V_5

22UF_6.3V_5

C127

2 1

2 1

22UF_6.3V_5

22UF_6.3V_5

D

CC

J23

P1V0S_VCCP

54.9_1%_2

CLOSE TO VR

R224

130_1%_2

2 1

VR_SVID_ALERT#
VR_SVID_CLK
VR_SVID_DATA

OUT
OUT
OUT

13
13
13

B

AJ29
AJ30
AJ28

R230

130_1%_2

2 1

R212 CLOSE TO CPU

R212
R250
R223

43_5%_2

21
21
21

0_5%_2
0_5%_2

21

R211

R239

75_1%_2

2 1

PVCORE

21

R199

21

100_1%_2

R200

100_1%_2

VCCSENSE
VSSSENSE

OUT
OUT

13
13

AA

P1V0S_VCCP

AJ35
AJ34

B10
A10

2 1

2 1

R495

10_5%_2

R491

10_5%_2

CHANGE by

VCC_SENSE_VCCIO
VSS_SENSE_VCCIO

David Cheng

OUT
OUT

DATE

10
10

12-12-2011

23

INVENTEC

TITLE

LV1.1_Lauren

CPU-2

DOC.NUMBER

CODE

SIZE

A3

1310A24893-0 MTR

CS

SHEET

of

67

22

1

REV

AX1

8 7

6 5

4

3 2 1

24.9_1%_2

P1V0S_VCCP

54

IN

54

IN

54

IN

54

IN

54

ININ

54

IN

54

IN

54

IN

54

IN

54

IN

54

IN

54

IN

54

IN

54

IN

54

IN

54

IN

23

OUT

23

OUT

23

OUT

23

OUT

23

OUT

23

OUT

23

OUT

23

OUT

23

OUT

23

OUT

23

OUT

23

OUT

23

OUT

23

OUT

23

OUT

23

OUT

CLOSED TO CPU

23

23

23

23

23

23

23

23

PEG_TXN0

PEG_TXN1

PEG_TXN2

IN

PEG_TXN3

IN

PEG_TXN4

IN

PEG_TXN5

IN

PEG_TXN6

IN

PEG_TXN7

IN

C742
C740
C736
C731
C725
C715
C709
C702

C IS 0402

23

23

23

23

23

23

23

23

PEG_TXP0

IN OUT

PEG_TXP1

IN

PEG_TXP2

IN

PEG_TXP3

IN

PEG_TXP4

IN

PEG_TXP5

IN

PEG_TXP6

IN

PEG_TXP7

C741
C738
C733
C727
C720
C711
C706
C697

C IS 0402

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

PEG_C_TXN0

PEG_C_TXN1

PEG_C_TXN2

PEG_C_TXN3

PEG_C_TXN4

PEG_C_TXN5

PEG_C_TXN6

PEG_C_TXN7

PEG_C_TXP0

PEG_C_TXP1

PEG_C_TXP2

PEG_C_TXP3

PEG_C_TXP4

PEG_C_TXP5

PEG_C_TXP6

PEG_C_TXP7

OUTIN
OUTIN
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUTIN

D

54

54

54

54

54

54

54

54

54

54

54

54

54

54

54

54

CC

B

AA

CN19

PEG_ICOMPI

PCI EXPRESS* - GRAPHICS

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

D

33
33
33
33

33
33
33
33

33
33
33
33

33
33
33
33

33
33
33
33
33
33
33
33

33
33
33
33
33
33
33
33

B

P1V0S_VCCP

44

44
44

44
44

44
44

IN
IN
IN
IN

IN
IN

IN

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

33
33

33

33
33

IN

IN
IN

IN
IN

IN
IN

DMI_TXN(0)
DMI_TXN(1)
DMI_TXN(2)
DMI_TXN(3)

DMI_TXP(0)
DMI_TXP(1)
DMI_TXP(2)
DMI_TXP(3)

DMI_RXN(0)
DMI_RXN(1)
DMI_RXN(2)
DMI_RXN(3)

DMI_RXP(0)
DMI_RXP(1)
DMI_RXP(2)
DMI_RXP(3)

FDI_TXN(0)
FDI_TXN(1)
FDI_TXN(2)
FDI_TXN(3)
FDI_TXN(4)
FDI_TXN(5)
FDI_TXN(6)
FDI_TXN(7)

FDI_TXP(0)
FDI_TXP(1)
FDI_TXP(2)
FDI_TXP(3)
FDI_TXP(4)
FDI_TXP(5)
FDI_TXP(6)
FDI_TXP(7)

OUT
OUT

OUT
OUT

OUT

NB_EDP_HPD#

NB_EDP_AUX_DP
NB_EDP_AUX_DN

NB_EDP_TX0_DP
NB_EDP_TX1_DP

NB_EDP_TX0_DN
NB_EDP_TX1_DN

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

24.9_1%_2

R517

21

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HDP#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

eDP Intel(R) FDI DMI

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

R148

PEG_C_RXN0
PEG_C_RXN1
PEG_C_RXN2
PEG_C_RXN3
PEG_C_RXN4
PEG_C_RXN5
PEG_C_RXN6
PEG_C_RXN7

PEG_C_RXP0
PEG_C_RXP1
PEG_C_RXP2
PEG_C_RXP3
PEG_C_RXP4
PEG_C_RXP5
PEG_C_RXP6
PEG_C_RXP7

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7

21

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

INVENTEC

TITLE

LV1.1_Lauren

CPU-3

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

23

1

DOC.NUMBER

CODE

REV

AX1

67

8 7

6 5

4

3 2 1

CN19

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT

OUT
OUT
OUT

M_B_DQ(0)
M_B_DQ(1)
M_B_DQ(2)
M_B_DQ(3)
M_B_DQ(4)
M_B_DQ(5)
M_B_DQ(6)
M_B_DQ(7)
M_B_DQ(8)
M_B_DQ(9)
M_B_DQ(10)
M_B_DQ(11)
M_B_DQ(12)
M_B_DQ(13)
M_B_DQ(14)
M_B_DQ(15)
M_B_DQ(16)
M_B_DQ(17)
M_B_DQ(18)
M_B_DQ(19)
M_B_DQ(20)
M_B_DQ(21)
M_B_DQ(22)
M_B_DQ(23)
M_B_DQ(24)
M_B_DQ(25)
M_B_DQ(26)
M_B_DQ(27)
M_B_DQ(28)
M_B_DQ(29)
M_B_DQ(30)
M_B_DQ(31)
M_B_DQ(32)
M_B_DQ(33)
M_B_DQ(34)
M_B_DQ(35)
M_B_DQ(36)
M_B_DQ(37)
M_B_DQ(38)
M_B_DQ(39)
M_B_DQ(40)
M_B_DQ(41)
M_B_DQ(42)
M_B_DQ(43)
M_B_DQ(44)
M_B_DQ(45)
M_B_DQ(46)
M_B_DQ(47)
M_B_DQ(48)
M_B_DQ(49)
M_B_DQ(50)
M_B_DQ(51)
M_B_DQ(52)
M_B_DQ(53)
M_B_DQ(54)
M_B_DQ(55)
M_B_DQ(56)
M_B_DQ(57)
M_B_DQ(58)
M_B_DQ(59)
M_B_DQ(60)
M_B_DQ(61)
M_B_DQ(62)
M_B_DQ(63)

M_B_BS0
M_B_BS1
M_B_BS2

M_B_CAS#
M_B_RAS#
M_B_WE#

AH11

AB6

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

SA_CS#[0]

SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

SA_ODT[0]

SA_ODT[1]
RSVD_TP[9]

RSVD_TP[10]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AP11
AN11

AL12
AM12
AM11

AL11

AP12
AN12

AJ14

AH14

AL15

AK15

AL14

AK14

AJ15

AH15

AE10

AF10

M10

AG6
AG5

AH5
AH6

AH8
AH9

AD9

C5

SA_DQ[0]

D5

SA_DQ[1]

D3

SA_DQ[2]

D2

SA_DQ[3]

D6

SA_DQ[4]

C6

SA_DQ[5]

C2

SA_DQ[6]

C3

SA_DQ[7]

F10

SA_DQ[8]

F8

SA_DQ[9]

G10

SA_DQ[10]

G9

SA_DQ[11]

F9

SA_DQ[12]

F7

SA_DQ[13]

G8

SA_DQ[14]

G7

SA_DQ[15]

K4

SA_DQ[16]

K5

SA_DQ[17]

K1

SA_DQ[18]

J1

SA_DQ[19]

J5

SA_DQ[20]

J4

SA_DQ[21]

J2

SA_DQ[22]

K2

SA_DQ[23]

M8

SA_DQ[24]

N10

SA_DQ[25]

N8

SA_DQ[26]

N7

SA_DQ[27]
SA_DQ[28]

M9

SA_DQ[29]

N9

SA_DQ[30]

M7

SA_DQ[31]
SA_DQ[32]
SA_DQ[33]

AK6

SA_DQ[34]

AK5

SA_DQ[35]
SA_DQ[36]
SA_DQ[37]

AJ5

SA_DQ[38]

AJ6

SA_DQ[39]

AJ8

SA_DQ[40]

AK8

SA_DQ[41]

AJ9

SA_DQ[42]

AK9

SA_DQ[43]
SA_DQ[44]
SA_DQ[45]

AL9

SA_DQ[46]

AL8

SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]

V6

SA_BS[2]

AE8

SA_CAS#
SA_RAS#

AF9

SA_WE#

DDR SYSTEM MEMORY A

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT

OUT
OUT
OUT

M_A_DQ(0)
M_A_DQ(1)
M_A_DQ(2)
M_A_DQ(3)
M_A_DQ(4)
M_A_DQ(5)
M_A_DQ(6)
M_A_DQ(7)
M_A_DQ(8)
M_A_DQ(9)
M_A_DQ(10)
M_A_DQ(11)
M_A_DQ(12)
M_A_DQ(13)
M_A_DQ(14)
M_A_DQ(15)
M_A_DQ(16)
M_A_DQ(17)
M_A_DQ(18)
M_A_DQ(19)
M_A_DQ(20)
M_A_DQ(21)
M_A_DQ(22)
M_A_DQ(23)
M_A_DQ(24)
M_A_DQ(25)
M_A_DQ(26)
M_A_DQ(27)
M_A_DQ(28)
M_A_DQ(29)
M_A_DQ(30)
M_A_DQ(31)
M_A_DQ(32)
M_A_DQ(33)
M_A_DQ(34)
M_A_DQ(35)
M_A_DQ(36)
M_A_DQ(37)
M_A_DQ(38)
M_A_DQ(39)
M_A_DQ(40)
M_A_DQ(41)
M_A_DQ(42)
M_A_DQ(43)
M_A_DQ(44)
M_A_DQ(45)
M_A_DQ(46)
M_A_DQ(47)
M_A_DQ(48)
M_A_DQ(49)
M_A_DQ(50)
M_A_DQ(51)
M_A_DQ(52)
M_A_DQ(53)
M_A_DQ(54)
M_A_DQ(55)
M_A_DQ(56)
M_A_DQ(57)
M_A_DQ(58)
M_A_DQ(59)
M_A_DQ(60)
M_A_DQ(61)
M_A_DQ(62)
M_A_DQ(63)

M_A_BS0
M_A_BS1
M_A_BS2

M_A_CAS#
M_A_RAS#
M_A_WE#

28
28

D

B

28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28

28
28
28

28
28
28

AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

M_CLK_DDR0
M_CLK_DDR#0
M_CKE0

M_CLK_DDR1
M_CLK_DDR#1
M_CKE1

M_CS#0
M_CS#1

M_ODT0
M_ODT1

M_A_DQS#(0)
M_A_DQS#(1)
M_A_DQS#(2)
M_A_DQS#(3)
M_A_DQS#(4)
M_A_DQS#(5)
M_A_DQS#(6)
M_A_DQS#(7)

M_A_DQS(0)
M_A_DQS(1)
M_A_DQS(2)
M_A_DQS(3)
M_A_DQS(4)
M_A_DQS(5)
M_A_DQS(6)
M_A_DQS(7)

M_A_A(0)
M_A_A(1)
M_A_A(2)
M_A_A(3)
M_A_A(4)
M_A_A(5)
M_A_A(6)
M_A_A(7)
M_A_A(8)
M_A_A(9)
M_A_A(10)
M_A_A(11)
M_A_A(12)
M_A_A(13)
M_A_A(14)
M_A_A(15)

OUT
OUT
OUT

OUT
OUT
OUT

OUTBI
OUT

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

28
28
28

28
28
28

28
28

28
28

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28

29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29

28

29

28

29

28

29

28

29

28

29

28

29

28

29

28

29
29
29
29
29

28

29

28

29

28

29

28

29

28

29

28

29

28

29

28

29
29
29
29
29

29
29
29

29
29
29

CN19

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]

AM5

SB_DQ[32]

AM6

SB_DQ[33]

AR3

SB_DQ[34]

AP3

SB_DQ[35]

AN3

SB_DQ[36]

AN2

SB_DQ[37]

AN1

SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]

AN9

SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]

AN8

SB_DQ[45]

AR6

SB_DQ[46]

AR5

SB_DQ[47]

AR9

SB_DQ[48]

AJ11

SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]
SB_DQ[52]

AR8

SB_DQ[53]

AJ12

SB_DQ[54]

AH12

SB_DQ[55]

AT11

SB_DQ[56]

AN14

SB_DQ[57]

AR14

SB_DQ[58]

AT14

SB_DQ[59]

AT12

SB_DQ[60]

AN15

SB_DQ[61]

AR15

SB_DQ[62]

AT15

SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

AA10

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

DDR SYSTEM MEMORY B

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

SB_CS#[0]

SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

SB_ODT[0]

SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AE2
AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

M_CLK_DDR2
M_CLK_DDR#2
M_CKE2

M_CLK_DDR3
M_CLK_DDR#3
M_CKE3

M_CS#2
M_CS#3

M_ODT2
M_ODT3

M_B_DQS#(0)
M_B_DQS#(1)
M_B_DQS#(2)
M_B_DQS#(3)
M_B_DQS#(4)
M_B_DQS#(5)
M_B_DQS#(6)
M_B_DQS#(7)

M_B_DQS(0)
M_B_DQS(1)
M_B_DQS(2)
M_B_DQS(3)
M_B_DQS(4)
M_B_DQS(5)
M_B_DQS(6)
M_B_DQS(7)

M_B_A(0)
M_B_A(1)
M_B_A(2)
M_B_A(3)
M_B_A(4)
M_B_A(5)
M_B_A(6)
M_B_A(7)
M_B_A(8)
M_B_A(9)
M_B_A(10)
M_B_A(11)
M_B_A(12)
M_B_A(13)
M_B_A(14)
M_B_A(15)

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

29
29
29

29
29
29

29
29

29
29

29

BI

29

BI

29

BI

29

BI

29

BI

29

BI

29

BI

29

BI

29

BI

29

BI

29

BI

29

BI

29

BI

29

BI

29

BI

29

BI

29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29

D

CC

B

AA

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

INVENTEC

TITLE

LV1.1_Lauren

CPU-4

DOC.NUMBER

CODE

SIZE

A3

1310A24893-0 MTR

CS

SHEET

of

24 67

1

REV

AX1

8 7

6 5

4

3 2 1

21

3

D S

Q1

AM2302N

PCH_DDR_RST

C148

C161

2 1

22UF_6.3V_5

C160

C157

2 1

22UF_6.3V_5

C601

2 1

1UF_6.3V_2

CPUDDR_WR_VREF1_M

21

IN

C149

2 1

2 1

22UF_6.3V_5

22UF_6.3V_5

C146

2 1

2 1

C596

22UF_6.3V_5

22UF_6.3V_5

C609

2 1

2 1

10UF_6.3V_3

10UF_6.3V_3

25 32

IN

DDR_WR_VREF02

2 1

R111

25

1K_5%_2_DY

SB MOUNT

CN19

AT24

VAXG1 VAXG_SENSE

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

POWER

LINES

GRAPHICS

1.8V RAIL

5 4

R110

0_5%_2_DY

IN

DDR_WR_VREF01

25

R109

D

PVAXG PVAXG

+

SI 1102

C637

470uF_2V

2 1

2

G

1

2 1

1K_5%_2_DY

SB OPENSB MOUNT

(26A)

C159

2 1

22UF_6.3V_5

C147

2 1

22UF_6.3V_5

B

P1V8S

(1.2A)

C610

2 1

1UF_6.3V_2

8

7 6

0_5%_2_DY

2

SB OPEN

SENSE

DDR3 -1.5V RAILS

MISC VREFSA RAIL

R112

D S

G

1

PCH_DDR_RST

21

3

Q5

AM2302N

VSSAXG_SENSE

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

VCCIO_SEL

SM_VREF

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VDDQ11

VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1

VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

CPUDDR_WR_VREF2_M

21

25 32

IN

PVAXG

21

R201

AK35
AK34

AL1

B4
D1

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

M27
M26
L26
J26
J25
J24
H26
H25

H23

C22
C24
A19

100_1%_2

21

R202

100_1%_2

DDR_WR_VREF01
DDR_WR_VREF02

VCCSA_SENSE

VCCSA_VID0
VCCSA_VID1
VCCIO_SEL

R526

2 1

10K_5%_2_DY

For IB

GFX_VCC_SENSE
GFX_VSS_SENSE

OUT
OUT

C115

2 1

10UF_6.3V_3

OUT

CHANGE by

Q1 R109

Stuff

NAFor SB

25

C116

2 1

10UF_6.3V_3

PVSA

100_1%_2

R240

2 1

10

R6523

David Cheng

R111Q5

NA

Stuff

OUT
OUT

2.2UF_6.3V_2_DY

C112

2 1

10UF_6.3V_3

12

OUT

OUT

10K_5%_2

2 1

P0V75M_VREF

Q51

3

CORE_PWEN

1819

40

IN

PCH_DDR_RST

21

2532

IN

13
13

IVYB MOUNT R483

SB MOUNT R490

P0V75M_VREF_H

10UF_6.3V_3

C94

0.1UF_16V_2_DY

2 1

P1V5S

(10A)

C114

2 1

10UF_6.3V_3

C93

2 1

C113

C111

2 1

2 1

10UF_6.3V_3

P0V75M_VREF_H P1V5S

2

DS

G

AM2302N

1

R483

2 1

0_5%_2

R490

21

0_5%_2_DY

R478

2 1

C587

2 1

3300PF_50V_2

R481

2 1

1K_1%_2_DY

1K_1%_2_DY

D

CC

B

PVSA

(6A)

C167

C166

2 1

10uF_6.3V_3

C654

2 1

2 1

10uF_6.3V_3

10uF_6.3V_3

AA

12

12

R6522

10K_5%_2

2 1

DATE

12-12-2011

23

OUT

INVENTEC

TITLE

LV1.1_Lauren

CPU-5

DOC.NUMBER

CODE

SIZE

A3

1310A24893-0 MTR

CS

SHEET

of

6725

1

REV

AX1

8 7

6 5

4

3 2 1

CN19

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13 AJ2

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

D

B

AR22
AR19
AR16
AR13
AR10

AR7
AR4

AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10

AP7

AP4

AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AN7

AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10

AM7
AM4
AM3
AM2
AM1

AL34

AL31

AL28
AL25
AL22
AL19
AL16
AL13
AL10

AL7

AL4

AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AK7

AK4

AJ25

VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96

VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3

AJ1
AH35
AH34
AH32
AH30
AH29
AH28

AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

CN19

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

AK28
AK29
AL26
AL27
AK26
AL29
AL30

AJ31
AJ33

AJ26

D24
G25
G24

D23
C30
A31

D30
B31

C29

CN19

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10
RSVD11
RSVD12
RSVD13

E23

RSVD14
RSVD15
RSVD16
RSVD17

B30

RSVD18

B29

RSVD19
RSVD20
RSVD21

A30

RSVD22
RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

RESERVED

VCC_DIE_SENSE
VSS_DIE_SENSE

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9

RSVD_NCTF10

BCLK_ITP

BCLK_ITP#

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

RSVD28
RSVD29
RSVD30

RSVD31

RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD51

RSVD52

L7
AG7
AE7
AK2
W8

AT26
AM33
AJ27

AH27
AH26

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AN35
AM35

AT2
AT1
AR1

B1

KEY

SB MOUNT

R233

0_5%_2_DY

21

D

CC

B

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

26
26
26
26
26
26

SI 1115

IN
IN
IN
IN
IN
IN

SI 1115

CFG(2)
CFG(3)
CFG(4)
CFG(5)
CFG(6)
CFG(7)

AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29

AH31
AH33

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

PEG X4 LANE REVERSAL

PEGX16 STATIC LAN REVERSAL

DISPLAY PORT PRESENCE STRAP

PCIE PORT BIFURCATION STRAP

PEG DEFER TRAINING

CFG(3)

IN

CFG(2)

IN

CFG(4)

IN

26

26

26

CFG(5)

IN

CFG(6)

IN

CFG(7)

IN

R554

R540

R543

R546

R555

R557

21

21

21

21

21

21

1K_1%_2_DY

1K_5%_2_DY

1K_5%_2

1K_5%_2

1K_5%_2

1K_1%_2_DY

AA

STRAP PIN

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

INVENTEC

TITLE

LV1.1_Lauren

CPU-6

DOC.NUMBER

CODE

SIZE

A3

1310A24893-0 MTR

CS

SHEET

of

6726

1

REV

AX1

8 7

6 5

FAN CONN

4

3 2 1

D

4.7K_5%_2

40

OUT

40

IN

TACH0
CPUFAN1_ON

100PF_50V_2_DY

R474

C583

P3V3S

2 1

2 1

CN17

1

1

2

2

3

3

4

ACES_50273_0047N_001_4P

GG4

PN: 6012A0081607

P5V0S

C578

4.7UF_6.3V_3

G1
G2

C577

0.01UF_50V_2

2 1

2 1

D

CC

P3V3S

P3V3S

P3V3S

B

R534

10K_5%_2

R535

10K_5%_2_DY

R533

100_5%_2

2 1

2 1

U33

2
3 4

TI_TMP302BDRLR_SOT_6P

PN: 6019B0843501

TRIPSET1TRIPSET0
GND
OUT# HYSTSET

VS

61
5

R706

10K_5%_2

2 1

2 1

C662

2 1

2.2uF_6.3V_3

R3

10K_5%_2

2 1

THRMTRIP#

OUT

40 54 56

B

AA

INVENTEC

TITLE

LV1.1_Lauren

FAN

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6727

8 7

6 5

4

3 2 1

CN15

BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
OUT
OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

M_A_A(0)
M_A_A(1)
M_A_A(2)
M_A_A(3)
M_A_A(4)
M_A_A(5)
M_A_A(6)
M_A_A(7)
M_A_A(8)
M_A_A(9)
M_A_A(10)
M_A_A(11)
M_A_A(12)
M_A_A(13)
M_A_A(14)
M_A_A(15)

M_A_BS0
M_A_BS1
M_A_BS2
M_CS#0
M_CS#1
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
M_CKE0
M_CKE1
M_A_CAS#
M_A_RAS#
M_A_WE#
SA0_DIM0
SA1_DIM0
PCH_3S_SMCLK
PCH_3S_SMDATA

M_ODT0
M_ODT1

M_A_DQS(0)
M_A_DQS(1)
M_A_DQS(2)
M_A_DQS(3)
M_A_DQS(4)
M_A_DQS(5)
M_A_DQS(6)
M_A_DQS(7)
M_A_DQS#(0)
M_A_DQS#(1)
M_A_DQS#(2)
M_A_DQS#(3)
M_A_DQS#(4)
M_A_DQS#(5)
M_A_DQS#(6)
M_A_DQS#(7)

24
24
24
24
24
24
24
24
24
24
24
24

D

B

24
24
24
24

24
24
24
24
24
24

24
24
24
24
24
24

24
28
28
2932

2932

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10_AP

84

A11

83

A12

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS#0

27

DQS#1

45

DQS#2

62

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

DDR3_FOX_204_RV_800_3

DDR3 SOCKET (RV_800) PN: 6026B0221101

5

DQ0

7

DQ1

DQ2
DQ3

4

DQ4

6

DQ5
DQ6
DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

M_A_DQ(0)
M_A_DQ(1)

15

M_A_DQ(2)

17

M_A_DQ(3)
M_A_DQ(4)
M_A_DQ(5)

16

M_A_DQ(6)

18

M_A_DQ(7)
M_A_DQ(8)
M_A_DQ(9)
M_A_DQ(10)
M_A_DQ(11)
M_A_DQ(12)
M_A_DQ(13)
M_A_DQ(14)
M_A_DQ(15)
M_A_DQ(16)
M_A_DQ(17)
M_A_DQ(18)
M_A_DQ(19)
M_A_DQ(20)
M_A_DQ(21)
M_A_DQ(22)
M_A_DQ(23)
M_A_DQ(24)
M_A_DQ(25)
M_A_DQ(26)
M_A_DQ(27)
M_A_DQ(28)
M_A_DQ(29)
M_A_DQ(30)
M_A_DQ(31)

129

M_A_DQ(32)

131

M_A_DQ(33)

141

M_A_DQ(34)

143

M_A_DQ(35)

130

M_A_DQ(36)

132

M_A_DQ(37)

140

M_A_DQ(38)

142

M_A_DQ(39)

147

M_A_DQ(40)

149

M_A_DQ(41)

157

M_A_DQ(42)

159

M_A_DQ(43)

146

M_A_DQ(44)

148

M_A_DQ(45)

158

M_A_DQ(46)

160

M_A_DQ(47)

163

M_A_DQ(48)

165

M_A_DQ(49)

175

M_A_DQ(50)

177

M_A_DQ(51)

164

M_A_DQ(52)

166

M_A_DQ(53)

174

M_A_DQ(54)

176

M_A_DQ(55)

181

M_A_DQ(56)

183

M_A_DQ(57)

191

M_A_DQ(58)

193

M_A_DQ(59)

180

M_A_DQ(60)

182

M_A_DQ(61)

192

M_A_DQ(62)

194

M_A_DQ(63)

24

BI

24

BI

24

BI

24

BIBI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

2424

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

P1V5

C75

2 1

P3V3S

2 1

(4.32A)

0.1UF_16V_2

C68

0.1UF_16V_2

C77

C60

2 1

0.1UF_16V_2

C88

2 1

0.1UF_16V_2

P0V75S_DIMM0_VREF_DQ

C65

C63

2 1

2 1

0.1UF_16V_2

2.2uF_6.3V_3

P0V75S_DIMM0_VREF_CA

C83

C86

2 1

2 1

0.1UF_16V_2

2.2uF_6.3V_3

C62

C87

2 1

2 1

22UF_6.3V_5

0.1UF_16V_2

21

29

OUT

C72

2 1

2 1

22UF_6.3V_5

DDR3_DRAMRST#

DDR3 SO-DIMM 0

CN15

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

22UF_6.3V_5

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

DDR3_FOX_204_RV_800_3

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

203

VTT1

204

VTT2

G1

G1
G2

SI2 1230

G2

C44

2 1

1UF_6.3V_2

D

CC

P0V75S

(1A)

B

C78

C66

C49

2 1

1UF_6.3V_2

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

NOTE:

IF SA0_DIM0=0 , SA1_DIM0=0
SO-DIMMA SPD ADDRESS IS 0XA0
SO-DIMMA TS ADDRESS IS 0X30

IF SA0_DIM0=1 , SA1_DIM0=0
SO-DIMMA SPD ADDRESS IS 0XA2
SO-DIMMA TS ADDRESS IS 0X32

8

P3V3S

10K_5%_2_DY

R87

10K_5%_2

R85

2 1

2 1

R181

10K_5%_2_DY

2 1

R81

10K_5%_2

2 1

7 6

SA0_DIM0

SA1_DIM0

P0V75S_DIMM0_VREF_DQ

P1V5

R91

2 1

28

IN

28

IN

1K_1%_2_DY1K_1%_2_DY

0_5%_2

R92

2 1

0_5%_2

SB OPEN

5 4

P0V75M_VREF

R95

21

CPUDDR_WR_VREF1_M

R94

21

CHANGE by

P1V5

R113

R114

David Cheng

P0V75S_DIMM0_VREF_CA P0V75M_VREF

2 1

1K_1%_2_DY1K_1%_2_DY

R115

0_5%_2

21

2 1

INVENTEC

TITLE

SIZE

DATE

12-12-2011

23

A3

LV1.1_Lauren

DDR3-1

DOC.NUMBER

CODE

1310A24893-0 MTR

CS

SHEET

AA

REV

of

AX1

6728

1

8 7

6 5

4

3 2 1

CN14

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
OUT
OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

M_B_A(0)
M_B_A(1)
M_B_A(2)
M_B_A(3)
M_B_A(4)
M_B_A(5)
M_B_A(6)
M_B_A(7)
M_B_A(8)
M_B_A(9)
M_B_A(10)
M_B_A(11)
M_B_A(12)
M_B_A(13)
M_B_A(14)
M_B_A(15)

M_B_BS0
M_B_BS1
M_B_BS2
M_CS#2

M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR3
M_CLK_DDR#3
M_CKE2
M_CKE3
M_B_CAS#
M_B_RAS#
M_B_WE#
SA0_DIM1
SA1_DIM1
PCH_3S_SMCLK
PCH_3S_SMDATA

M_ODT2
M_ODT3

M_B_DQS(0)
M_B_DQS(1)
M_B_DQS(2)
M_B_DQS(3)
M_B_DQS(4)
M_B_DQS(5)
M_B_DQS(6)
M_B_DQS(7)
M_B_DQS#(0)
M_B_DQS#(1)
M_B_DQS#(2)
M_B_DQS#(3)
M_B_DQS#(4)
M_B_DQS#(5)
M_B_DQS#(6)
M_B_DQS#(7)

1

TP24

24
24
24
24
24
24
24
24
24
24
24
24

D

B

24
24
24
24

24
24
24
24

24
24
24
24
24
24
24
24
24

29

29
2832
2832

24
24

24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10_AP

84

A11

83

A12

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

TP5

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS#0

27

DQS#1

45

DQS#2

62

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

DDR3_FOX_204_RV_400

DDR3 SOCKET (RV_400) PN: 6026B0221601

5
7

15

17
4
6

16

18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70

129

131

141

143

130

132

140

142

147

149

157

159

146

148

158

160

163

165

175

177

164

166

174

176

181

183

191

193

180

182

192

194

M_B_DQ(0)
M_B_DQ(1)
M_B_DQ(2)
M_B_DQ(3)
M_B_DQ(4)
M_B_DQ(5)
M_B_DQ(6)
M_B_DQ(7)
M_B_DQ(8)
M_B_DQ(9)
M_B_DQ(10)
M_B_DQ(11)
M_B_DQ(12)
M_B_DQ(13)
M_B_DQ(14)
M_B_DQ(15)
M_B_DQ(16)
M_B_DQ(17)
M_B_DQ(18)
M_B_DQ(19)
M_B_DQ(20)
M_B_DQ(21)M_CS#3
M_B_DQ(22)
M_B_DQ(23)
M_B_DQ(24)
M_B_DQ(25)
M_B_DQ(26)
M_B_DQ(27)
M_B_DQ(28)
M_B_DQ(29)
M_B_DQ(30)
M_B_DQ(31)
M_B_DQ(32)
M_B_DQ(33)
M_B_DQ(34)
M_B_DQ(35)
M_B_DQ(36)
M_B_DQ(37)
M_B_DQ(38)
M_B_DQ(39)
M_B_DQ(40)
M_B_DQ(41)
M_B_DQ(42)
M_B_DQ(43)
M_B_DQ(44)
M_B_DQ(45)
M_B_DQ(46)
M_B_DQ(47)
M_B_DQ(48)
M_B_DQ(49)
M_B_DQ(50)
M_B_DQ(51)
M_B_DQ(52)
M_B_DQ(53)
M_B_DQ(54)
M_B_DQ(55)
M_B_DQ(56)
M_B_DQ(57)
M_B_DQ(58)
M_B_DQ(59)
M_B_DQ(60)
M_B_DQ(61)
M_B_DQ(62)
M_B_DQ(63)

DQ0

DQ1

DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

2424

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

P1V5

C40

2 1

P3V3S

C37

2 1

C45

2 1

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2
P0V75S_DIMM1_VREF_DQ

C55

2 1

2.2uF_6.3V_3

P0V75S_DIMM1_VREF_CA

C59

2 1

2.2uF_6.3V_3

C52

2 1

2 1

2 1

0.1UF_16V_2

22UF_6.3V_5

0.1UF_16V_2

21

28

OUT

2 1

22UF_6.3V_5

DDR3_DRAMRST#

2 1

C53

C47

C50

C57

C56

2 1

0.1UF_16V_2

C64

2 1

0.1UF_16V_2

DDR3 SO-DIMM 1

CN14

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

22UF_6.3V_5

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

DDR3_FOX_204_RV_400

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

203

VTT1

204

VTT2

G1

G1
G2

SI2 1230

G2

C61

2 1

1UF_6.3V_2

D

CC

P0V75S

B

C51

C84

C46

2 1

1UF_6.3V_2

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

NOTE:
SO-DIMMB SPD ADDRESS IS 0XA4
SO-DIMMB TS ADDRESS IS 0X34

8

P3V3S

R79

10K_5%_2

R186

10K_5%_2_DY

2 1

2 1

R204

10K_5%_2_DY

2 1

R77

10K_5%_2

2 1

7 6

SA1_DIM1

SA0_DIM1

P1V5

29

IN

29

IN

R88

R86

5 4

P0V75S_DIMM1_VREF_DQ

2 1

1K_1%_2_DY1K_1%_2_DY

2 1

P0V75M_VREF

R89

21

0_5%_2

CPUDDR_WR_VREF2_M

R84

21

0_5%_2

SB OPEN

CHANGE by

P1V5

R144

R166

P0V75S_DIMM1_VREF_CA P0V75M_VREF

2 1

1K_1%_2_DY

R167

21

0_5%_2

2 1

1K_1%_2_DY

AA

INVENTEC

TITLE

LV1.1_Lauren

DDR3-2

DATE

SIZE

12-12-2011David Cheng

23

CS

A3

1310A24893-0 MTR

SHEET

of

29

1

DOC.NUMBER

CODE

REV

AX1

67

8 7

6 5

4

3 2 1

D

D

CC

PCH

B

B

AA

INVENTEC

TITLE

LV1.1_Lauren

BLANK

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6730

8 7

6 5

4

3 2 1

P3V3AL P3V3_RTC

21

A2A1

3

C

D

BAT54C_30V_0.2A

P3V3AL_RTC_BAT

D20

1K_5%_2

R434

2 1

R642

330K_5%_2

2 1

R636

0_5%_2_DY

50

50

2 1

BI

1M_5%_2

OUT

22PF_50V_2

B

P3V3A

R273
R276

31

BI

31

BI

10K_5%_2_DY

21

3.3K_5%_2

21

PCH_SPI_CS0#

PCH_SPI_SO

CHECK SPI POWER NET

CLOSE TO PCH

U14

1

CS#

2

SO_SIO1

3

WP#

4

GND

MXIC_MX25L6406EM2I_12G_SOP_8P

*BOM(8MB)
MX25L6406EM2I-12G: 6019B0813101

W25Q64CVSSIG: 6019B0871001

8

C510

1UF_6.3V_2

2 1

R388

21

20K_5%_2

C483

2 1

R397

21

20K_5%_2

C484

R398

1M_5%_2

2 1

1UF_6.3V_2

2 1

INTVRMEN_R

P5V0S

1

Q45

SSM3K7002FU

HDA_SYNC

R703

21

SSM3K7002FU

HDA_SDOUT

C779

VCC

HOLD#

SCLK

SI_SIO0

2 1

8
7
6
5

G

2

P5V0S

1

Q78

G

2

P3V3A

R216

PCH_SPI_CLK

PCH_SPI_SI

3

DS

3

DS

31

31

IN

IN

10K_5%_2

21

7 6

POWERPAD1X1M_DY

C485

CSC0805_DY1UF_6.3V_2

2 1

50

49

50

50

R648

HDA_SDO_R

GPIO13

R314

21

3.3K_5%_2

BI
BI

0.1UF_16V_2

PAD10

1 2

15pF_50V_2

15pF_50V_2

BI

OUT
OUT

IN

P3V3A

31

31

C254

SI 1115

C766

SI 1115

C770

HDA_BITCLK

PCSPKR

HDA_RST#

HDA_SDIN0

22PF_50V_2

33_5%_2

21

2 1

21

P3V3A

P3V3AL_RTC_BAT

21

4

32

X5

32.768KHZ

1

21

R389

R313
R390

R361

C429

2 1

HDA_SDO_R

1K_5%_2_DY

R615

21

CLOSE TO PCH

51_5%_2

TP81

TP24

BI
BI

BI
BI

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_SI

PCH_SPI_SO

31

31

31

31

CN24

1

1

2

2

ACES_50228_0024N_001_2P

PN: 6012B0025303

R645

10M_5%_2

2 1

1K_5%_2

21

33_5%_2

21

33_5%_2

21

33_5%_2

21

R649

21

1

TP57

TP24

TP52

TP24

TP82

TP24

G1

3

G2

4

SI 0919

U36

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN#/GPIO33

N32

HDA_DOCK_RST#/GPIO13

J3

JTAG_TCK

1

H7

JTAG_TMS

1

K5

JTAG_TDI

1

H1

JTAG_TDO

T3

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

ITL_PANTHERPOINT_FCBGA_989P

R219
R274

R229
R275

HDA_BCLK

SPI_CLK

RTC BATY CNTR

PCH PN: 6019B0960401

21

0_5%_2

21

0_5%_2

21

0_5%_2

21

0_5%_2

5 4

RTC

IHDA

JTAG

SPI

SPI_CLK

SPI_CS0#

SPI_SI

SPI_SO

D

SI 1201

C38

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LPC

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN

SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN

SATA1TXP

SATA 6G

SATA2RXN
SATA2RXP
SATA2TXN

SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN

SATA3TXP

SATA4RXN
SATA4RXP

SATA

SATA4TXN

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

40

BI

40

BI

40

BI

40

BI

31

LPC_AD(0)

A38

LPC_AD(1)

B37

LPC_AD(2)

C37

LPC_AD(3)

D36

LPC_FRAME#

E36

1

K36
V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11
Y10

AB12
AB13

AH1

P3
V14
P1

OUT IN

TP61

TP24

SATA_A_RX0N
SATA_A_RX0P
SATA_A_TX0N
SATA_A_TX0P

SATA_ODD_RX2N
SATA_ODD_RX2P
SATA_ODD_TX2N
SATA_ODD_TX2P

37.4_1%_2

49.9_1%_2

R570

21

750_1%_2

CLOSE TO PCH

1

TP85

TP24

1

TP47

TP24

HDA_SDO_R

1K_5%_2

R263

R280

FLASH DESCRIPTOR SECURITY OVERIDE

HDA_SDO_R

CHANGE by

David Cheng

BI
BI
BI
BI

405166

OUT

P1V05S_VCCP

21

P1V05S_VCCP

21

R268

10K_5%_2_DY

R647

21

ME_FLASH_EN

HIGH:ENABLE
LOW:DISABLE

405166
405166
405166
405166

21

DATE

P3V3S

IN

IN
OUT
OUT

IN

IN
OUT
OUT

P3V3S

R584

10K_5%_2

2 1

P3V3S

12-12-2011

23

R286

10K_5%_2

2 1

SERIRQ

49
49
49

SATA HDD A

49

49
49

SATA ODD

49
49

LED_3S_SATA#

40

40 66

BI

50

OUT

INVENTEC

TITLE

LV1.1_Lauren

PCH-1

DOC.NUMBER

CODE

SIZE

A3

1310A24893-0 MTR

CS

SHEET

of

6731

1

REV

AX1

CC

B

AA

8

7 6 5 4 3 2 1

P3V3A

21

R407
R631
R623

SI 1111

R406
R304
R403
R404
R606
R401

P3V3S

R595
R283

RA

R600

RB

R603

2829

RA MOUNT IS UMA
RB MOUNT IS DGPU

PCH_3S_SMCLK

BI

E

D

PCH_3A_SMCLK

32

41

BI

PCH_3A_SMDATA

32

41

BI

PCH_3S_SMDATA

2829

BI

STUFF FOR INTEGRATED CLK

C

32

32

32

32

32

32

32

32

32

CLKIN_DMI_PCH#

IN

CLKIN_DMI_PCH

IN

CLKIN_BUF_DOT96#

IN

CLKIN_BUF_DOT96

IN

CLKIN_PCH14

IN

CLKIN_SATA

IN

CLKIN_SATA#

IN

CLKIN_BUF_CPYCLK

IN

CLKIN_BUF_CPYCLK#

IN

B

SMB_ALERT#

10K_5%_2

21

PCH_DDR_RST

1K_5%_2

21

PCH_3M_SMCLK

2.2K_5%_2_DY

21

PCH_3M_SMDATA

2.2K_5%_2_DY

21

USB30_PEG8_CLKRQ#

10K_5%_2_DY

21

GPIO46

10K_5%_2_DY

21

USB30_PEG7_B_CLKRQ#

10K_5%_2_DY

21

CLKREQ_WLAN#

10K_5%_2

21

CLKREQ_LAN#

10K_5%_2

21
21

21
21

10K_5%_2

10K_5%_2

10K_5%_2_DY

10K_5%_2

USB3_PWR_ON

CLKREQ_CR#

DGPU_PRSNT#

DGPU_PRSNT#

P3V3S P3V3A

R413

2.2K_5%_2

2 1

R193

R192

R399

R400

R309

R245

R255

32

IN

21

25 32

IN

32

IN

32

IN

32

IN

32

IN

32

IN

32

51

IN

32 45

IN

WLAN

CARD READER

32

IN

32 50

IN

32

IN

32

IN

R377

R428

2 1

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

R548

10K_5%_2

21

R549

10K_5%_2

21

R427

2.2K_5%_22.2K_5%_22.2K_5%_2

2 1

2 1

2

Q44

G

DS

SSM3K7002FU

3

3

Q43

DS

G

SSM3K7002FU

2

P3V3S

1

1

CLKREQ_GPU#

32

IN

55

DGPU_PWR_EN

18

IN

36

P3V3A

R627
R334

R446
R449

SSM3K7002FU

LAN

R323

R681

Q33

1

G

51
51
51

OUT

51

OUT

50

OUT

50

OUT

45
45
45
45

10K_5%_2_DY

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2_DY

21

2 1

CLKREQ_GPU#

3

DS

2

PCIE_C_RXN_WLAN

IN

PCIE_C_RXP_WLAN

IN

PCIE_C_TXN_WLAN
PCIE_C_TXP_WLAN

PCIE_C_RXN_CR

IN

PCIE_C_RXP_CR

IN

PCIE_C_TXN_CR
PCIE_C_TXP_CR

PCIE_C_RXN_LAN

IN

PCIE_C_RXP_LAN

IN

PCIE_C_TXN_LAN

IN

PCIE_C_TXP_LAN

IN

10K_5%_2

21

0_5%_2_DY

BUILD_ID0

BUILD_ID1

P3V3A

OUT

21

C192
C191

C203
C204

C193
C194

32

0.1UF_16V_2

21

0.1UF_16V_2

21
21

21

0.1UF_16V_2

21

0.1UF_16V_2

51

32

51

32

50
50

3250

32

IN

32

IN

32

32

45
45

3245

32

32

32

0.1UF_16V_2

0.1UF_16V_2

OUT
OUT

IN

OUT

OUT
OUT

OUT

OUT

OUT

OUT
OUT

IN

USB30_PEG8_CLKRQ#

OUT

USB30_PEG7_B_CLKRQ#

OUT

GPIO46

OUT

PCIE_TXN_WLAN
PCIE_TXP_WLAN

PCIE_TXN_CR
PCIE_TXP_CR

PCIE_TXN_LAN
PCIE_TXP_LAN

CLK_PCIE_WLAN#
CLK_PCIE_WLAN

CLKREQ_WLAN#

USB3_PWR_ON

CLK_PCIE_CR#
CLK_PCIE_CR

CLKREQ_CR#

BUILD_ID0

BUILD_ID1

CLK_PCIE_LAN#
CLK_PCIE_LAN

CLKREQ_LAN#

AW38

BG34

BJ34
AV32

AU32

BE34
BF34
BB32
AY32

BG36

BJ36
AV34

AU34

BF36
BE36
AY34
BB34

BG37
BH37

AY36
BB36

BJ38
BG38
AU36

AV36
BG40

BJ40

AY40

BB40

BE38
BC38

AY38

Y40
Y39

J2

AB49

AB47

M1

AA48

AA47

V10

Y37
Y36

A8

Y43
Y45

L12

V45
V46

L14

AB42

AB40

E6

V40
V42

T13
V38

V37
K12

AK14

AK13

U36

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6
PERP6
PETN6
PETP6

PERN7
PERP7
PETN7
PETP7

PERN8
PERP8
PETN8
PETP8

CLKOUT_PCIE0N
CLKOUT_PCIE0P

PCIECLKRQ0#/GPIO73

CLKOUT_PCIE1N
CLKOUT_PCIE1P

PCIECLKRQ1#/GPIO18

CLKOUT_PCIE2N
CLKOUT_PCIE2P

PCIECLKRQ2#/GPIO20

CLKOUT_PCIE3N
CLKOUT_PCIE3P

PCIECLKRQ3#/GPIO25

CLKOUT_PCIE4N
CLKOUT_PCIE4P

PCIECLKRQ4#/GPIO26

CLKOUT_PCIE5N
CLKOUT_PCIE5P

PCIECLKRQ5#/GPIO44

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

PEG_B_CLKRQ#/GPIO56

CLKOUT_PCIE6N
CLKOUT_PCIE6P

PCIECLKRQ6#/GPIO45

CLKOUT_PCIE7N
CLKOUT_PCIE7P

PCIECLKRQ7#/GPIO46

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

ITL_PANTHERPOINT_FCBGA_989P

PCI-E*

E12

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SMBUS

Link

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1ALERT#/PCHHOT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

SMB_ALERT#

H14

PCH_3A_SMCLK

C9

PCH_3A_SMDATA

A12

PCH_DDR_RST

C8

PCH_3M_SMCLK

G12

PCH_3M_SMDATA

C13
E14
M16

M7

T11

P10

R635

1

TP86

TP24

1

TP87

TP24

21

IN
BI
BI

OUT

BI
BI

10K_5%_2

32

32

41

32

41

21

25 32

32

32

P3V3A

Controller

M10

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N

CLOCKS

CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

FLEX CLOCKS

CLKREQ_GPU#

AB37

CLK_PEG#

AB38

CLK_PEG

AV22

CLK_DMI_PCH#

AU22

CLK_DMI_PCH

AM12

CLK_DP_N

AM13

CLK_DP_P

BF18

CLKIN_DMI_PCH#

BE18

CLKIN_DMI_PCH

BJ30

CLKIN_BUF_CPYCLK#

BG30

CLKIN_BUF_CPYCLK

G24

CLKIN_BUF_DOT96#

E24

CLKIN_BUF_DOT96

AK7

CLKIN_SATA#

AK5

CLKIN_SATA

K45

CLKIN_PCH14

H45

CLK_R3S_PCH_FB

V47
V49

Y47

K43
F47
H47
K49

P1V05S_VCCP

R594

21

90.9_1%_2

1

TP51

TP24

AS PER INTEL ME FW RELEASED,
CLKOUTFLEX0 IS BY DEFAULT 33MHZ

DGPU_PRSNT#

OUT

OUT
OUT

OUT
OUT

OUT
OUT

15PF_50V_2

32

32

IN

54
54

21
21

21
21

32

IN

32

IN

32

IN

32

IN

32

IN

32

IN

32

IN

32

IN

32

IN

35

IN

R296

21

1M_5%_2

X3

1
432

C400

25MHZ

2 1

2 1

C435

15PF_50V_2

FF

E

D

C

B

A

INVENTEC

TITLE

LV1.1_Lauren

PCH-2

DOC.NUMBER

CODE

SIZE

1310A24893-0 MTR

CS

CHANGE by

8

7 6 5 4 3

David Cheng 12-12-2011

DATE

2 1

C

SHEET

of

32 67

A

REV

AX1

8 7

NOTE:1.SLP_SUS AND SUSACK# ARE NC IF DSW IS NOT SUPPORTED

2.DPWROK SHOULD CONNECT TO RSMRST# IF DSW NOT SUPPORTED

IN
IN
IN
IN

IN
IN
IN
IN

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

DMI_RXN(0)
DMI_RXN(1)
DMI_RXN(2)
DMI_RXN(3)

DMI_RXP(0)
DMI_RXP(1)
DMI_RXP(2)
DMI_RXP(3)

DMI_TXN(0)
DMI_TXN(1)
DMI_TXN(2)
DMI_TXN(3)

DMI_TXP(0)
DMI_TXP(1)
DMI_TXP(2)
DMI_TXP(3)

23
23
23
23

23
23
23

D

P1V05S_VCCP

1

R550

49.9_1%_2

2

23

23
23
23
23

23
23
23
23

P3V3S

21

OUT

BI

SUS_PWR_DN_ACK

IN

CORE_PG

IN

SB_PWRGD

IN

PM_DRAM_PWRGD

RSMRST#

IN

SUS_PWR_DN_ACK

SB_PWRBTN#

IN

SI 1201

GPIO31

IN

BATLOW#

IN

PM_RI#

IN

33

21

R207

10K_5%_2

B

13

40

3340

33

40

33

33

33

C474

R632

R601

R353
R359

6 5

BC24
BE20
BG18
BG20

BE24
BC20

BJ18
BJ20

AW24
AW20

BB18
AV18

AY24
AY20
AY18

AU18

BJ24

R551

750_1%_2

21

0.1UF_16V_2_DY

21

0_5%_2_DY

21

10K_5%_2

21

0_5%_2

21

0_5%_2_DY

21

BG25
BH21

C12

P12

L22

L10

B13

C21

K16

E20

H20

E10

A10

U36

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

SUSACK#

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SUSPW RDNACK/GPIO30

PWRBTN#

ACPRESENT/GPIO31

BATLOW#/GPIO72

RI#

ITL_PANTHERPOINT_FCBGA_989P

DMI

4

FDI_INT

WAKE#

SLP_A#

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16
AV12
BC10
AV14
BB10

A18

E22

B9K3

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

R358

0_5%_2

1

TP64

TP24

1

TP49

TP24

1

TP62

TP24

1

TP54

TP24

1

TP53

TP24

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3

FDI

FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

System Power Management

SLP_SUS#

PMSYNCH

SLP_LAN#/GPIO29

3 2 1

FDI_TXN(0)
FDI_TXN(1)
FDI_TXN(2)
FDI_TXN(3)
FDI_TXN(4)
FDI_TXN(5)
FDI_TXN(6)
FDI_TXN(7)

FDI_TXP(0)
FDI_TXP(1)
FDI_TXP(2)
FDI_TXP(3)
FDI_TXP(4)
FDI_TXP(5)
FDI_TXP(6)
FDI_TXP(7)

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

OUT
OUT
OUT
OUT
OUT

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

23

23

23

23

23

P3V3_RTC

R644

330K_5%_2

2 1

21

RSMRST#

PCIE_WAKE#

PCI_CLKRUN#

IN

IN

BI

33 40

33 45 48 49

33

R646

330K_5%_2_DY

2 1

(LPC_PD#)

PCH_SUSCLK

SLP_S4#

SLP_S3#

H_PM_SYNC

OUT

OUT

OUT

BI

40

40 49

40 48 49

21

D

CC

B

DATE

P3V3A

12-12-2011

23

INVENTEC

TITLE

LV1.1_Lauren

PCH-3

DOC.NUMBER

CODE

SIZE

A3

1310A24893-0 MTR

CS

SHEET

of

6733

1

REV

AX1

AA

P3V3S

21

10K_5%_2_DY

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

CHANGE by

R281

R633

R628

R661

R365

R405

David Cheng

R591

33

8

PCI_CLKRUN#

IN

7 6

8.2K_5%_2

21

IN
IN

BI

IN

OUT

PM_RI#

PCIE_WAKE#

SUS_PWR_DN_ACK

SI 1201

GPIO31

BATLOW#

33

33454849

33

33

33

5 4

8 7

6 5

P3V3S

4

3 2 1

D

AWAY FROM ANY TOGGLING SIGNALS
MINIMUM SPACING OF 20 MILS

B

CLOSE TO PCH

R271

2.37K_1%_2

2 1

R282

R288

2.2K_5%_22.2K_5%_2

2 1

2 1

2 1

M45

AF37
AF36

AE48
AE47

AK39
AK40

AN48
AM47
AK47

AJ48

AN47
AM49
AK49

AJ47

AF40
AF39

AH45
AH47

AF49
AF45

AH43
AH49

AF47
AF43

N48

M40

M47
M49

U36

J47

L_BKLTEN
L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

LVD_IBG
LVD_VBG

LVD_VREFH
LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

ITL_PANTHERPOINT_FCBGA_989P

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_INTN

SDVO_INTP

SDVO_CTRLCLK
SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

LVDS

CRT

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_CTRLCLK
DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P

Digital Display Interface

DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_CTRLCLK
DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

P3V3S

20K_5%_2_DY

R265

2 1

R302

20K_5%_2_DY

2 1

UNMOUNT - FOR PORT B NOT DETECTED

NB_DPA_DDCCLK
NB_DPA_DDCDATA

NB_DPA_AUX_DN
NB_DPA_AUX_DP
NB_DPA_HPD

NB_DPA_TX0_DN
NB_DPA_TX0_DP
NB_DPA_TX1_DN
NB_DPA_TX1_DP
NB_DPA_TX2_DN
NB_DPA_TX2_DP
NB_DPA_TX3_DN
NB_DPA_TX3_DP

NB_HDMI_DDCCLK
NB_HDMI_DDCDATA

NB_HDMI_HPD

NB_HDMI_TX2_DN
NB_HDMI_TX2_DP
NB_HDMI_TX1_DN
NB_HDMI_TX1_DP
NB_HDMI_TX0_DN
NB_HDMI_TX0_DP
NB_HDMI_TXC_DN
NB_HDMI_TXC_DP

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

42
42

42

BI

42

BI

42

IN

42
42
42
42
42
42
42
42

43
43

43

IN

43
43
43
43
43
43
43
43

D

CC

B

AA

R272

44
44

44

44
44

44
44

44
44
44

44
44
44

44
44

44
44
44

44
44
44

NB_LCM_BLEN

OUT

NB_LCM_VCC_EN

OUT

NB_LCM_PWM

OUT

NB_LCM_CLK

OUT

NB_LCM_DATA

OUT

NB_LCM_L1_TXCL_DN

OUT

NB_LCM_L1_TXCL_DP

OUT

NB_LCM_L1_TXDL0_DN

OUT

NB_LCM_L1_TXDL1_DN

OUT

NB_LCM_L1_TXDL2_DN

OUT

NB_LCM_L1_TXDL0_DP

OUT

NB_LCM_L1_TXDL1_DP

OUT

NB_LCM_L1_TXDL2_DP

OUT

NB_LCM_L2_TXCL_DN

OUT

NB_LCM_L2_TXCL_DP

OUT

NB_LCM_L2_TXDL0_DN

OUT

NB_LCM_L2_TXDL1_DN

OUT

NB_LCM_L2_TXDL2_DN

OUT

NB_LCM_L2_TXDL0_DP

OUT

NB_LCM_L2_TXDL1_DP

OUT

NB_LCM_L2_TXDL2_DP

OUT

1K_5%_2

CLOSE TO PCH

INVENTEC

TITLE

LV1.1_Lauren

PCH-4

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6734

8 7

6 5

4

3 2 1

P3V3A

D

0
0

of

6735

1

REV

AX1

CC

B

AA

BG26

BJ26

BH25

BJ16
BG16
AH38
AH37
AK43
AK45

C18
N30

H3

AH12

AM4
AM5

Y13

K24

L24
AB46
AB45

B21
M20

AY16

BG46

BE28
BC30
BE32

BJ32
BC28
BE30

BF32
BG32
AV26
BB26
AU28

AY30
AU26

AY26
AV28

AW30

K40
K38
H38
G38

C46
C44
E40

D47
E42

F46

G42
G40
C42
D44

K10

C6

H49
H43

J48
K42
H40

OUT

OUT

3

D S

G

SSM3K7002FU

1

0_5%_2

U36

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18

40

6

R892

TP19
TP20

TP21
TP22
TP23
TP24

USB3RN1
USB3RN2
USB3RN3
USB3RN4
USB3RP1
USB3RP2
USB3RP3
USB3RP4
USB3TN1
USB3TN2
USB3TN3
USB3TN4
USB3TP1
USB3TP2
USB3TP3
USB3TP4

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54

GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

PME#

PLTRST#

40

RSVD

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4 OC7#/GPIO14

ITL_PANTHERPOINT_FCBGA_989P

R251

10K_5%_2_DY

21

NVRAM

PCI

USB

P3V3A

21

PME#

OUT

35

RSVD1
RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8
RSVD9

RSVD10

RSVD11

RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

RSVD21

RSVD22

RSVD23

RSVD24

RSVD25

RSVD26
RSVD27

RSVD28
RSVD29

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

USBP5P

USBP6N

USBP6P

USBP7N

USBP7P

USBP8N

USBP8P

USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59
OC1#/GPIO40

OC2#/GPIO41

OC3#/GPIO42
OC4#/GPIO43

OC5#/GPIO9

OC6#/GPIO10

AY7
AV7
AU3
BG4

AT10
BC8

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

1

AV5

TP24

AV10
AT8
AY5

BA2
AT12

BF3

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

C33

B33

A14

2ND_WLAN_RF_OFF#

K20

BOARD_ID0

B17

BOARD_ID1

C16

BOARD_ID2

L16

BOARD_ID3

A16

BOARD_ID4

D14

BOARD_ID5

C14

AOAC_LED

CHANGE by

TP43

CHECK ??

USB_0N
USB_0P
USB_1N
USB_1P
USB_2N
USB_2P

USB_4N
USB_4P
USB_5N
USB_5P

USB_8N
USB_8P

USB_10N
USB_10P

David Cheng

35

35

51

22.6_1%_2

IN

35

OUT

35

OUT

35

OUT

35

OUT

35

OUT

35

OUT

35

OUT

2ND_WLAN_RF_OFF#

IN

35

OUT

35

OUT

35

OUT

35

OUT

35

OUT

35

OUT

48

BI

48

BI

50

BI

50

BI

50

BI

50

BI

50

BI

50

BI

44

BI

44

BI

51

BI

51

BI

51

BI

51

BI

CLOSE TO PCH

R650

21

IN
IN
IN
IN
IN
IN
IN

OUT

AOAC_LED

BOARD_ID0

BOARD_ID1

BOARD_ID2

BOARD_ID3

BOARD_ID4

BOARD_ID5

AOAC_LED

BOARD_ID0

BOARD_ID1

BOARD_ID2

BOARD_ID3

BOARD_ID4

BOARD_ID5

DIS
UMA

DEFAULT: DIS

PORT0 (TO MB)
PORT1 (TO DB) DEBUG
PORT2 (TO DB)

WIRELESS AUDIO
WEBCAM

WLAN+BT

BLUETOOTH

35

51
35
35
35
35
35
35
35

SSM3K7002FU

DATE

560K_1%_2

1

12-12-2011

23

P15V0A

R660

Q94

G

R364
R643
R639
R394
R637
R409
R629
R630

R396
R641
R640
R395
R638
R408

ID1ID0BOARD ID

ID2

0

0

1
0 0 1

2 1

AOAC_DIN_LED#

3

DS

2

INVENTEC

TITLE

LV1.1_Lauren

CODE

SIZE

CS

A3

21

10K_5%_2

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2

21

10K_5%_2_DY

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2_DY

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2_DY

21

10K_5%_2

ID4ID3 ID5

1

0
00

44 50

OUT

PCH-5

DOC.NUMBER

1310A24893-0 MTR

SHEET

P3V3S

RS2

8

1
2
3

8.2K_5%

D

8.2K_5%_2_DY

1
2
3

8.2K_5%

10K_5%_2

10K_5%_2

10K_5%_2

10K_5%_2

BBSTRAP1

0
0

1

35

B

51
21

BI

40
66

OUT

PCI_GNT#3
LOW- A16 SWAP OVERRIDE
/ TOP-BLOCK SWAP OVERRIDE ENABLED

455054

PLT_RST#

BI

BUF_PLT_RST#

R416

100K_5%_2

8

7
6
54

R758

21

RS1

8
7
6
54

R392

21

R414

21

R651

21

R393

21

PCI_GNT#3

4

2 1

USB30_SMI#7
PCI_INTC#
PCI_INTA#
USB30_SMI#8

ACCEL_INT#

PCI_INTB#
PCI_SERR#
PCI_INTD#

PCI_INTF#

DGPU_SELECT#

SI 1013

DGPU_HOLD_RST#

DGPU_PWR_EN#

BBSTRAP0

0

1

0

11

R343

1K_5%_2_DY

P3V3A

5

+

1
2

-

U24

TC7SZ08FU

3

35

BI

35

BI

35

BI

35

BI

35

51

BI

35

BI

36 40

BI

35

BI

35

BI

35

IN

35 54

IN

35 36 56

IN

BOOT BIOS LOCATION

LPC
RESERVED(NAND)
PCI
SPI

21

40

OUT

32

OUT

66

OUT

51

OUT

C482

21

0.1UF_16V_2

51

40

7 6

LPC_CLK

CLK_R3S_PCH_FB

CLK_TPM

LPC_CLK1

10pF_50V_2_DY

10pF_50V_2_DY

SI 1122

10pF_50V_2_DY

WLAN_WAKE#

IN

AOAC_WAKE

IN

35
35
35
35

3554
35
353656

35

35
35
35
35

51

35

C1000

33pF_50V_2

PV 1219

C1003

2 1

C1001

2 1

C1002

2 1

48
47
47

48
47
47

48
47
47

48
47
47

BI
BI
BI
BI

OUT
OUT
OUT

OUT

BI
BI
BI
BI

IN

BI
BI
BI

BI
BI
BI

BI
BI
BI

BI
BI
BI

SI 1122

21

USB3.0

USB30_SSRX1­USB30_SSRX2­USB30_SSRX3-

USB30_SSRX1+
USB30_SSRX2+
USB30_SSRX3+

USB30_SSTX1­USB30_SSTX2­USB30_SSTX3-

USB30_SSTX1+
USB30_SSTX2+
USB30_SSTX3+

PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#

DGPU_HOLD_RST#
DGPU_SELECT#
DGPU_PWR_EN#

PCI_GNT#3

USB30_SMI#8
PCI_INTF#
USB30_SMI#7
ACCEL_INT#

PME#

R608

21

22_5%_2

21

22_5%_2

R324

21

22_5%_2

R903
R331

21

22_5%_2

R890

0_5%_2

R891

0_5%_2_DY

SI 1014

0_5%_2

TP58
TP63

LPC_CLK_R
CLK_PCH_FB

CLK_TPM_R

TP50

CLK_DEBUG

21

ADP_EN2

21

R387

21

TP24

1
1

TP24

TP24

1

AC_OK

Q110

2

OPEN

5 4

8 7

6 5

4

3 2 1

P3V3A

SI 1201

WLAN_RF_OFF#

36

51

OUT

WLAN_POWER_OFF

36

51

OUT

R402
R751

10K_5%_2

21

10K_5%_2

21

P3V3S

D

SI 1013

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

200K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2_DY

21

10K_5%_2

21

10K_5%_2_DY

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

WWAN_POWER_OFF

3650

IN

DGPU_HPD_INTR#

36

IN

EC_SCI#

3640

IN

ODD_PRSNT#

36

IN

BIOS_REC

36

IN

STP_PCI#

36

IN

GPIO37

36

IN

RF_SEL2

3650

IN

HDD_LOCK_LED#

3650

IN

TEMP_ALERT#

36

IN

KB_RST#

3640

IN

3650

RF_SEL1

BI

R350
R385
R391
R298
R306
R604
R346
R588
R277
R580
R329
R598

P3V3S

3540

40

36

3640

51

51

3650

18

40

36

36

51

36

3650

36

36

3650

3650

3650

36

36

51

21

R344

10K_5%_2

DGPU_PWR_EN

3

Q42

DS

IN

IN
IN

DGPU_PWR_EN#

GPIO37

SMSC_RST#

B

3556

36

3650

1

SSM3K7002FU

R349
R368

G

2

100K_5%_2

21

10K_5%_2_DY

21

OUT

18

32 55

OUT

IN
IN
IN

IN
OUT
OUT

IN

BI
BI

OUT

IN
OUT
OUT
OUT

IN
BI
OUT
OUT

IN

SI 1201

PCI_SERR#

EC_SMI#

DGPU_HPD_INTR#

EC_SCI#

INTE_CLOCK_EN

TP65

BTOFF

WWAN_RF_OFF#

WWAN_POWER_OFF

DGPU_PWROK

BIOS_REC

SI 1115

WLAN_POWER_OFF

TP48

STP_PCI#

SMSC_RST#

ODD_PRSNT#

GPIO37

RF_SEL2

RF_SEL1

HDD_LOCK_LED#

TEMP_ALERT#

WLAN_RF_OFF#

TP24

TP24

1

1

T7

A42

H36

E38

C10

C4
G2

U2

D40

T5

E8

E16

P8
K1
K4
V8

M5

N2

M3

V13

V3
D6

A4

A45
A46

A5
A6
B3

B47

BD1

BD49

BE1

BE49

BF1

BF49

U36

BMBUSY#/GPIO0

TACH1/GPIO1

TACH2/GPIO6

TACH3/GPIO7

GPIO8

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

SATA4GP/GPIO16

TACH0/GPIO17

SCLOCK/GPIO22

GPIO24

GPIO27

GPIO28

STP_PCI#/GPIO34

GPIO35

SATA2GP/GPIO36

SATA3GP/GPIO37

SLOAD/GPIO38

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

SATA5GP/GPIO49/TEMP_ALERT#

GPIO57

VSS_NCTF_1

VSS_NCTF_2

VSS_NCTF_3

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

VSS_NCTF_8

VSS_NCTF_9

VSS_NCTF_10

VSS_NCTF_11

VSS_NCTF_12

VSS_NCTF_13

VSS_NCTF_14

ITL_PANTHERPOINT_FCBGA_989P

GPIO

RCIN#

DF_TVS

C40
B41
C41
A40

GPIO71

P4
AU16

PECI

P5
AY11
AY10
T14

AY1

NV_CLE

AH8
AK11
AH10
AK10
P37

NC_1

BG2
BG48
BH3
BH47
BJ4
BJ44A44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49

R232

0_5%_2_DY

R652

10K_5%_2

21

BI

21

21

A20GATE

H_PECI

KB_RST#

H_PWRGD

P3V3S

390_5%_2

OUT

OUT

CHECK

40

R228

21
40

36 40

21

21

P1V05S_VCCP

R220

56_5%_2_DY

2 1

PM_THRMTRIP#

OUT

IN

IN

D

21

CC

B

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

A20GATE

PROCPWRGD

THRMTRIP#

INIT3_3V#

CPU/MISC

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

NCTF

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

AA

INVENTEC

TITLE

LV1.1_Lauren

PCH-6

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6736

8 7

6 5

4

3 2 1

P1V05S_VCCP

(1.3A)

C367

10UF_6.3V_3

2 1

D

P1V05S_VCCP

C306

10UF_6.3V_3

2 1

C326

2 1

C327

2 1

2 1

C392

P1V05S_VCCP

2 1

C353

1UF_6.3V_21UF_6.3V_21UF_6.3V_2

C384

2 1

R755

0_5%_3_DY

0.1UF_16V_2_DY

2 1

21

C349

1UF_6.3V_2

P3V3S

1UF_6.3V_21UF_6.3V_21UF_6.3V_2

2 1

P1V05S_VCCP

C668

C363

3.8A

2 1

178mA

C205

0.1UF_16V_2

B

P1V05S_VCCP

P1V05S_VCCP

P1V5S

147mA

2 1

R553

0_5%_2_DY

P1V05S_VCCP

21

47mA

C305

0.1UF_16V_2

2 1

U36

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3] VCCDFTERM[2]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

ITL_PANTHERPOINT_FCBGA_989P

POWER

VCC CORE

VCCIO

FDI

VCCADAC

VSSADAC

U48

U47

CRT

VCCALVDS

VSSALVDS

VCCTX_LVDS[1]

VCCTX_LVDS[2]

LVDS

VCCTX_LVDS[3]

VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

AK36
AK37

AM37
AM38
AP36
AP37

V33

V34

AT16

AT20

VCCTX_LVDS

DMI HVCMOS

VCCSPI

AB36

AG16

AG17

AJ16

AJ17

V1

VCCCLKDMI

VCCDFTERM[1]

VCCDFTERM[3]

VCCDFTERM[4]

NAND / SPI

P1V5S

P3V3S

P3V3S

2 1

147mA

63mA

(0.001A)

C301

2 1

2 1

C342

0.1UF_16V_2

C713

1UF_6.3V_2

C302

0.1UF_16V_20.01UF_50V_2

2 1

C415

0.1UF_16V_2

2 1

P1V05S_VCCP

C395

2 1

1UF_6.3V_2

FBM_11_160808_181A15T

C318

2 1

10uF_6.3V_3

P3V3S

178mA

75mA

47mA

L16

2 1

C323

1UF_6.3V_2

P1V8S

21

40mA

CHECK POWER NET

P1V05S_VCCP

P1V8S

(0.19A)

CHECK POWER NET

P3V3A

(0.02A)

D

CC

B

AA

INVENTEC

TITLE

LV1.1_Lauren

PCH-7

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6737

8

7 6 5 4 3 2 1

C701

C397

3.8A

(0.01A)

P3V3A

65mA

C433

0.1UF_16V_2

2 1

10UF_6.3V_3_DY

21

21

P3V3A

2 1

P1V05S_VCCP

C378

1UF_6.3V_2

2 1

P3V3A

2 1

0.1UF_16V_2

21

C430

0.1UF_16V_2

(0.266A)

C438

1UF_6.3V_2

P1V05S_VCCP

65mA

65mA

C344

1UF_6.3V_2

2 1

P3V3A

2 1

P1V05S_VCCP

(0.16A)

803mA

C432

0.1UF_16V_2

P3V3A

65mA

P3V3S

21

P1V5S

P1V05S_VCCP

2 1

178mA

C328

0.1UF_16V_2

C402

1UF_6.3V_2

P3V3S

21

C717

0.1UF_16V_2

P1V05S_VCCP

2 1

178mA

3.8A

C389

1UF_6.3V_2

DIODE-BAT54-TAP-PHP

C523

0.1UF_16V_2

2 1

DIODE-BAT54-TAP-PHP

C521

1UF_6.3V_2

2 1

D21

R430

10_5%_2

D22

R435

10_5%_2

FF

2

P3V3A

13

P5V0A

21

2

NC NC

13

(0.001A)

E

P3V3S

P5V0S

21

(0.001A)

D

C

P3V3A

(1.01A)

P1V05S_VCCP

803mA

P3V3S

MLZ1608M100WT

C360

22UF_6.3V_5

2 1

L17

1UF_6.3V_2

178mA

21

C398

2 1

C413

10UF_6.3V_3

2 1

C372

2 1

C416

1UF_6.3V_222UF_6.3V_5

2 1

0.1UF_16V_2

C377

1UF_6.3V_2

2 1

C425

2 1

P1V05S_VCCP

C322

1UF_6.3V_2

2 1

E

P1V05S_VCCP

C772

2 1

P1V05S_VCCP

(0.08A)

2 1

MLZ1608M100WT

D

(0.08A)

MLZ1608M100WT

P1V05S_VCCP

C

C778

2.2UF_6.3V_22.2UF_6.3V_2

(0.055A)

(0.095A)

P1V0S_VCCP

C276

22UF_6.3V_5

2 1

C215

22UF_6.3V_5

2 1

C364

1UF_6.3V_2

2 1

C380

1UF_6.3V_2

2 1

C359

1UF_6.3V_2

2 1

C771

2.2UF_6.3V_22.2UF_6.3V_2

2 1

C785

2 1

L15

21

L13

21

C266

2.2UF_6.3V_2

2 1

C219

2.2UF_6.3V_2

2 1

C784

2 1

+V1.05S_VCCA_A_DPL

+V1.05S_VCCA_B_DPL

CHECK POWE NET

C265

0.1UF_16V_2

2 1

C220

0.1UF_16V_2

2 1

P1V05S_VCCP

(0.001A)

C670

4.7UF_6.3V_3

2 1

C774

2.2UF_6.3V_22.2UF_6.3V_2

2 1

P1V5S

P1V05S_VCCP

C674

0.1UF_16V_2

2 1

(0.003A)

0.1UF_16V_2

147mA

P1V05S_VCCP

C437

2 1

R303
C417

0_5%_3_DY

0.1UF_16V_2_DY

0_5%_2_DY

0.1UF_16V_2_DY

2 1

C418

2 1

0.1UF_16V_2

1UF_6.3V_2_DY

C676

0.1UF_16V_2

C431

R756

C350

R583

21

21

21

21

0_5%_2_DY

21

21

AD49

T16

V12

T38

BH23

AL29

AL24

AA19
AA21
AA24
AA26
AA27
AA29
AA31
AC26
AC27
AC29
AC31
AD29
AD31

W21
W23
W24
W26
W29
W31
W33

N16

Y49

BD47

BF47

AF17
AF33
AF34

AG34

AG33

V16

T17

V19

BJ8

A22

U36

VCCACLK

POWER

VCCDSW3_3

DCPSUSBYP

VCC3_3[5]

VCCAPLLDMI2

VCCIO[14]

DCPSUS[3]

VCCASW[1]

VCCASW[2]

VCCASW[3]

VCCASW[4]

VCCASW[5]

VCCASW[6]

VCCASW[7]

VCCASW[8]

VCCASW[9]

VCCASW[10]

VCCASW[11]

VCCASW[12]

VCCASW[13]

VCCASW[14]

VCCASW[15]

VCCASW[16]

VCCASW[17]

VCCASW[18]

VCCASW[19]

VCCASW[20]

DCPRTC

VCCVRM[4]

VCCADPLLA

VCCADPLLB

VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

VCCSSC

DCPSST

DCPSUS[1]
DCPSUS[2]

V_PROC_IO

VCCRTC

ITL_PANTHERPOINT_FCBGA_989P

Clock and Miscellaneous

CPU

RTC

N26

VCCIO[29]

P26

VCCIO[30]

P28

VCCIO[31]

T27

VCCIO[32]

T29

VCCIO[33]

T23

VCCSUS3_3[7]

T24

VCCSUS3_3[8]

V23

VCCSUS3_3[9]

USB

PCI/GPIO/LPCMISC

SATA

HDA

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCAPLLSATA

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

V24
P24

T26
M26

C331

AN23
AN24

P34

V5REF

N20
N22
P20
P22

AA16
W16
T34

AJ2
AF13

AH13
AH14

AF14
AK1

AF11

AC16
AC17
AD17

T21

V21

T19

P32

P3V3S

0.1UF_16V_2_DY

P3V3_RTC

(0.000006A)

C768

0.1UF_16V_2

B

2 1

C767

1UF_6.3V_2

2 1

C769

0.1UF_16V_2

2 1

B

A

INVENTEC

TITLE

LV1.1_Lauren

PCH-8

DOC.NUMBER

CODE

SIZE

1310A24893-0 MTR

CS

CHANGE by

8

7 6 5 4 3

David Cheng 12-12-2011

DATE

2 1

C

SHEET

of

38 67

A

REV

AX1

8 7

6 5

4

3 2 1

U36

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38

BB46
BC14
BC18

BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46

BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28

BF30
BF38
BF40

BG17

BG21

BG33
BG44

BH11
BH15
BH17
BH19

BH27
BH31
BH33
BH35
BH39
BH43

BC2

BD5

BD3

BG8

BH7

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

BB4

VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]

BF8

VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]

H10

VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

U36

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

D

B

AB4

AB43

AB5
AB7

AC19

AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39

AD4
AD40
AD42
AD43
AD45
AD46

AD8

AE2

AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38

AF4
AF42
AF46

AF5

AF7

AF8
AG19

AG2
AG31
AG48
AH11

AH3
AH36
AH39
AH40
AH42
AH46

AH7

AJ19

AJ21

AJ24
AJ33
AJ34

AK12

AK3

VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

ITL_PANTHERPOINT_FCBGA_989P

ITL_PANTHERPOINT_FCBGA_989P

8

7 6

5 4

CHANGE by

David Cheng

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

DATE

12-12-2011

23

INVENTEC

TITLE

LV1.1_Lauren

PCH-9

DOC.NUMBER

CODE

SIZE

A3

1310A24893-0 MTR

CS

SHEET

of

6739

1

REV

AX1

D

CC

B

AA

8

7 6 5 4 3 2 1

P3V3AL

(0.02A)

C21

2 1

C22

2.2uF_6.3V_3

2 1

2.2uF_6.3V_3_DY

E

A20GATE

36

OUT

EC_SMI#

36

IN

EC_SCI#

36

OUT

DIODE-BAT54-TAP-PHP

JD_BUTTON#

EC_PWRBTN#

P3V3AL

P3V3AL

1

2

5

U50

I0

O

I1

GND VCC

TOSHIBA_TC7SZ32FU_SSOP_5P

DIODE-BAT54-TAP-PHP

100K_5%_2

4

D

4050

IN

4049

IN

3

C

ACDC_OCP

40

BI

CPU_PROCHOT#

1321

40

B

OUT

3

DS

G

Q99

2

SSM3K7002FU_DY

1

FBM_11_160808_121T

R48

2

NC

D5

1 3

2

NC

D6

13

R74

21

P3V3A

L3

21

P3V3S

66

R45

10K_5%_210K_5%_2

2 1

2 1

DIODE-BAT54-TAP-PHP

C27

0.1UF_16V_2

2 1

50
50

R366
R415

40

4849

P3V3A

R443

10K_5%_2_DY

2 1
3

DS

G

Q98

2

SSM3K7002FU_DY

1

BI
OUT

OUT
OUT

2 1

213551

21

10K_5%_2

21

10K_5%_2

ADP_PRES

C14

0.1UF_16V_2

ACDC_OCP

USB_SW_EN

1 3

0.1UF_16V_2_DY

BUF_PLT_RST#

IN

2

NC

D4

PCH_SMDAT_THM
PCH_SMCLK_THM

C1

2 1

C30

66

0_5%_2_DY

IN

66

36

35
40

21

35
3151

41

31

36
41

4050
19

18
56
334849
19
50
49
45
41

35
6
6
6
41

R505

R504

0_5%_2

6

40

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN

OUT

IN
IN

IN

IN

IN
IN

IN
IN

IN
IN
IN
IN

21

21

C28

0.1UF_16V_20.1UF_16V_2

2 1

(0.002A)

66
66
66
66

LPC_CLK
LPC_FRAME#

KB_BL_PWREN

SERIRQ

EC_RST#
KB_RST#
CHG_LED

MUTE_BTN#
RESUME_PWEN

DGPU_PWROK
GPU_THROT#
SLP_S3#
ALWAYS_PW_EN
VO_DN_B
ODD_PW_EN#
WOL_PWEN#

TP_OFF_LED#

ADP_EN2

I_ADP
AC_OK
ADP_PRES
LED_ROW2
USB_CHGER_EN

41

OUT

3536

OUT

41

OUT

41

OUT

41

OUT

41

OUT

41

OUT

41

OUT

41

OUT

41

OUT

41

OUT

41

OUT

41

OUT

41

OUT

41

OUT

41

OUT

41

OUT

41

OUT

41

IN

41

IN

41

IN

41

IN

41

IN

41

IN

41

IN

41

IN

2 1

P3V3S

FBM_11_160808_121T

3151

BI

3151

BI

3151

BI

3151

BI

SI 1014

TP67
TP73

31

OUT

31

OUT

31

OUT

31

IN

LED_F5

PCI_SERR#

SCAN_OUT(0)
SCAN_OUT(1)
SCAN_OUT(2)
SCAN_OUT(3)
SCAN_OUT(4)
SCAN_OUT(5)
SCAN_OUT(6)
SCAN_OUT(7)
SCAN_OUT(8)
SCAN_OUT(9)
SCAN_OUT(10)
SCAN_OUT(11)
SCAN_OUT(12)
SCAN_OUT(13)
SCAN_OUT(14)
SCAN_OUT(15)

SCAN_IN(0)

SCAN_IN(1)

SCAN_IN(2)

SCAN_IN(3)

SCAN_IN(4)

SCAN_IN(5)

SCAN_IN(6)

SCAN_IN(7)

C20

0.1UF_16V_2

TP24

TP24

TP24

TP24
TP24

TP4

TP24

TP1

TP24

TP3

L4

21

0.1UF_16V_2

LPC_AD(0)
LPC_AD(1)
LPC_AD(2)
LPC_AD(3)

TP70

TP31

SPI_CLK
SPI_CS0#
SPI_SI
SPI_SO

SI 1115

TP24

TP24

FF

R1

21

220_5%_2

SI 1017

LID_SW#

SB_PWRBTN#

USBPWR_EN

CPU_PROCHOT#

+VCC_EC

C24

2 1

11

26

10

LAD0-GPM0

26

9

LAD1-GPM1

VCC

8

LAD2-GPM2

7

LAD3-GPM3

22

LPCRST#-WUI4-GPD2

13

LPCCCLK-GPM4

6

LFRAME#-GPM5

17

LPCPD#-WUI6-GPE6

126

GA20-GPB5

LPC

5

SERIRQ-GPM6

15

ECSMI#-GPD4

23

ECSCI#-GPD3

14

WRST#

4

KBRST#-GPB6

16

1

1

1
1

1
1
1

PWUREQ#-BBO-GPC7

119

GPC0

CIR

123

TMA0-GPB2

80

DAC4-DCD0#-GPJ4

104

DSR0#-GPG6

33

GINT-CTS0#-GPD5

88

PS2DAT1-RTS0#-GPF3

81

DAC5-RIG0#-GPJ5

87

PS2CLK1-DTR0#-GPF2

109

TXD-SOUT0-GPB1

108

RXD-SIN0-GPB0

71

ADC5-DCD1#-WUI29-GPI5

72

ADC6-DSR1#-WUI30-GPI6

73

ADC7-CTS1#-WUI31-GPI7

35

RTS1#-WUI5-GPE5

34

PWM7-RIG1#-GPA7

107

DTR1#-SBUSY-GPG1-ID7

95

WUI18-SOUT1-GPH2-SMDAT3-ID2

94

WUI17-SIN1-SMCLK3-GPH1-ID1

105

FSCK

101

FSCE#

102

EXTERNAL SERIAL FLASH

FMOSI

103

FMISO

56

KSO16-SMOSI-GPC3

57

KSO17-SMISO-GPC5

32

TP71

PWM6-SSCK-GPA6

1

100

SSCE0#-GPG2

106

TP46

SSCE1#-GPG0

1

36

KSO0-PD0

37

KSO1-PD1

38

KSO2-PD2

39

KSO3-PD3

40

KSO4-PD4

41

KSO5-PD5

42

KSO6-PD6

43

KSO7-PD7

44

KSO8-ACK#

45

KSO9-BUSY

46

KSO10-PE

51

KSO11-ERR#

52

KSO12-SLCT

53

KSO13

54

KSO14

55

KSO15

KSI1-AFD#

KSI0-STB#

121

114

3

929150

929150

NC

114

121

U2

ITE_IT8572E_AX_LQFP_128P

6019B0830601

UART port

KBMX

KSI7

KSI6

KSI5

KSI4

KSI3-SLIN#

KSI2-INIT#

656463

6261605958

127

74

127

AVCC

19

20

838482

EGAD-WUI25-GPE1

EGCS#-WUI26-GPE2

EGCLK-WUI27-GPE3

L80HLAT-BAO-WUI24-GPE0

GPIO

13

122

1

AVSS

49

27

1

75

49

27

113

122

CAPS_LED#

TP9002

TP24

1

RF_WHITE_LED

RF_AMBER_LED

CORE_PWEN

SB_PWRGD

R680

2 1

0_5%_2

96

999897

93

GPH6-ID6

GPH5-ID5

GPH4-ID4

SM BUS

PECI-SMCLK2-WUI22-GPF6

PECIRQT#-WUI23-GPF7

WUI19-GPH3-ID3

L80LLAT-WUI7-GPE7

PS2CLK2-WUI20-GPF4

CLKRUN#-WUI16-GPH0-ID0

PS/2

PS2DAT2-WUI21-GPF5

PWM

TACH1-TMA1-GPD7

TMRI0-WUI2-GPC4
TMRI1-WUI3-GPC6

WAKE UP

RING#-PWRFAIL#-CK32KOUT-LPCRST#-GPB7

RI1#-WUI0-GPD0
RI2#-WUI1-GPD1

ADC4-WUI28-GPI4

A/D D/A

DAC2-TACH0B-GPJ2
DAC3-TACH1B-GPJ3

CLOCK

VCORE

12

C26

0.01UF_50V_2

2 1

AMP_EN

R689

2 1

100K_5%_2

SMCLK0-GPB3
SMDAT0-GPB4
SMCLK1-GPC1
SMDAT1-GPC2

TMB0-GPF0

TMB1-GPF1

PWM0-GPA0

PWM1-GPA1

PWM2-GPA2
PWM3-GPA3
PWM4-GPA4
PWM5-GPA5

TACH0-GPD6

PWRSW-GPE4

ADC0-GPI0
ADC1-GPI1
ADC2-GPI2
ADC3-GPI3

TACH2-GPJ0

CK32KE

44 49

IN

33

OUT

48 49

OUT

13 21

40

OUT

41

OUT

49

IN

41

OUT

41

OUT

18 19

25

OUT

33

OUT

R33
R23

110
111
115
116
117

TP44

1

118

TP24

TP69

1

TP24

85
86

1

89
90

24
25
28
29
30
31

1

47
48

120
124

125
18

21

112

66
67
68
69
70

76
77

GPJ1

78
79

2

128

CK32K

21

R6

100_5%_2

TP24

TP66

TP75

1

TP24

TP72

1

TP24

TP74

TP24

C18

0.1UF_16V_2

R141

10K_5%_2

1

21

21

SI 1115

TP2

1

TP24

EC_CLK32E
EC_CLK32

R55

R53

0_5%_2_DY0_5%_2_DY

2 1

2 1

21

4.7K_5%_2

21

4.7K_5%_2

TP68

SI 1014

TP24

HP_IN
ALL_PWRGD_IN
THRMTRIP#
ADP_ID

ODD_MD#
JD_BUTTON#
ACC_PWR_EN
AOAC_WAKE

18PF_50V_2

P3V3AL

THM_CLK
THM_DAT
BATT_CLK
BATT_DAT
H_PECI
AC_LED

CORE_PWEN#

WLAN_IND#

PWR_LED#
LED_ROW0
LED_ROW1
LCM_BL_PWM
CPUFAN1_ON
GPUFAN2_ON

TACH0
TACH1

ME_FLASH_EN
CPU_PWEN

EC_PWRBTN#
VO_UP_A
SLP_S4#

RSMRST#

C38

2 1

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT

OUT

OUT

R143

0_5%_2_DY

X6

32.768KHZ

P3V3S

P3V3A

495156

BI

495156

BI

6 7

BI

6 7

BI

21

36

IN

41

19 21

51

IN

49 50
41
41
44
27
56

27

IN

56

IN

31

19

40 49

IN

50

IN

33 49

IN

33

49

IN

19 21

IN

27 54 56
6

IN

40 49
40 50

IN

51

IN

35

IN

21

PCH_SUSCLK

21

C42

18PF_50V_2

2 1

10K_5%_2

10K_5%_2

R2

21

ODD_MD#

R63

21

MUTE_BTN#

21

R4

21

R5

TP_CLK
TP_DAT

10K_5%_2

10K_5%_2

BI
BI

40 49

OUT

40 50

IN

P3V3A

41
41

E

D

C

33

OUT

B

A

INVENTEC

TITLE

LV1.1_Lauren

KBC

DOC.NUMBER

CODE

SIZE

1310A24893-0 MTR

C

CHANGE by

8

7 6 5 4 3

David Cheng 12-12-2011

DATE

2 1

CS

SHEET

of

40 67

A

REV

AX1

8

7 6 5 4 3 2 1

DC-JACK LED

VRP5V0A_LDO

8

41

E

P5V0A

R59

470_5%_2_DY

3

Q11

DS

OUT
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN

1

SSM3K7002FU

1

SSM3K7002FU

SCAN_IN(1)
SCAN_IN(7)
SCAN_IN(6)
SCAN_OUT(9)
SCAN_IN(4)
SCAN_IN(5)
SCAN_OUT(0)
SCAN_IN(2)
SCAN_IN(3)
SCAN_OUT(5)
SCAN_OUT(1)
SCAN_IN(0)
SCAN_OUT(2)
SCAN_OUT(4)
SCAN_OUT(7)
SCAN_OUT(8)
SCAN_OUT(6)
SCAN_OUT(3)
SCAN_OUT(12)
SCAN_OUT(13)
SCAN_OUT(14)
SCAN_OUT(11)
SCAN_OUT(10)
SCAN_OUT(15)

RF_WHITE_LED#
RF_AMBER_LED#

CAPS_LED#

G

2

3

Q10

DS

G

220_5%_2_DY

P5V0A

R67

2

21

R49

150_5%_2

21

R51

150_5%_2

21

R41

100_5%_2

CHG_LED

40

IN

D

AC_LED

40

IN

C

B

P3V3S

R66

100_5%_2

0_5%_2_DY

21

KEYBOARD CONN

40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40

P5V0S

40

41

R47

41

40

2 1

2 1

41

(0.02A)

2 1

ACES_50690_0324N_001_32P

IN

R300

470_5%_2

VRP5V0A_LDO

8

IN

R301

220_5%_2

CN4

32

32

31

31

30

30

29

29

28

28

27

27

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

6012B0372601

2 1

2 1

G
G

SI 1201

AMBER#

SI 1201

WHITE#

G1
G2

OUT

OUT

6

6

RF_WHITE_LED

40

IN

RF_AMBER_LED

40

IN

41

OUT

41

OUT

41

OUT

41

OUT

1K_5%_2

SSM3K7002FU

1K_5%_2

SSM3K7002FU

LED_F5_CN#

LED_ROW0_CN#

LED_ROW1_CN#

LED_ROW2_CN#

R43

Q3

1

G

R44

Q6

1

G

P5V0A

2 1
3

DS

2

P5V0A

2 1
3

DS

2

40

IN

40

IN

40

IN

40

IN

RF_WHITE_LED#

RF_AMBER_LED#

R50

806_1%_2

LED_F5

R56

22_5%_2

LED_ROW0

R64

22_5%_2

LED_ROW1

R46

22_5%_2

LED_ROW2

2

21

Q100

1

G

CN6

12

12

11

11

10

G

10

9

9

G

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_50592_0120N_001_12P

6012B0133908

3

SD

Q101

G

AO3409

1

3

DS

2

G2
G1

P5V0S_KBL

21

21

21

21

2

3

DS

G

Q7

SSM3K7002FU

1

2

3

DS

G

Q8

SSM3K7002FU

1

2

3

DS

G

Q9

SSM3K7002FU

1

2

3

DS

G

Q4

SSM3K7002FU

1

41

41

41

41

IN

IN
IN
IN

C169

10PF_50V_2

40

IN

LED_F5_CN#

LED_ROW2_CN#

LED_ROW1_CN#

LED_ROW0_CN#

P5V0A

21

KB_BL_PWREN

R142

100K_5%_2

SSM3K7002FU

TOUCHPAD MODULE CONN

CN28

G2

OUT

OUT

41

41

0.1UF_16V_2

(0.003A)

C566

P3V3A

SI 1111

PCH_3A_SMCLK

32

BI

PCH_3A_SMDATA

32

BI

TP_CLK

40

BI

TP_DAT

40

BI

2 1

D53

SI 1017

TP_OFF_LED#

40

IN

121212

2 1

PHP_PESD5V0S1BB_SOD523_2P_DY

D51

P3V3A

D52

2 1

2 1

PHP_PESD5V0S1BB_SOD523_2P_DY

PHP_PESD5V0S1BB_SOD523_2P_DY

R454

G2

1

1

2

2

3

3

4

4

5

5

6

6

G1

ACES_50505_0064N_001_6P

6012B0317701

ENTERY_3800K_F02N_00R_2P

330_5%_2

21

1

G1

CN13

2

GG2

1

6012B0226310

G2
G1

P5V0S_KBL

FF

E

D

C

B

A

INVENTEC

TITLE

LV1.1_Lauren

KEYBOARD & TOUCHPAD

DOC.NUMBER

CODE

SIZE

1310A24893-0 MTR

CS

CHANGE by

8

7 6 5 4 3

David Cheng 12-12-2011

DATE

2 1

C

SHEET

of

41

A

REV

AX1

67

8 7

6 5

4

3 2 1

DISPLAY PORT

P3V3S

D

34

34

42

34

34

NB_DPA_DDCCLK

IN

NB_DPA_DDCDATA

IN

DPAUX_EN

IN

NB_DPA_AUX_DN

IN

NB_DPA_AUX_DP

IN

B

21

R372

2.2K_5%_2

C726

2 1

0.1UF_16V_2

C729

2 1

0.1UF_16V_2

21

R373

SSM3K7002FU

2.2K_5%_2

1

3

DS

Q40

SSM3K7002FU

1

2

Q66

2

SSM3K7002FU

G

G

Q41

SSM3K7002FU

DS

1

G

DPDDC_EN

2

3

3

DS

1

G

Q67

2

3

DS

R328

2 1

42

IN

100K_5%_2

P3V3S_DPP

R345

2 1

DP_AUXP_CN

DP_AUXN_CN

100K_5%_2

OUT

OUT

42

42

42

IN

42

IN

42

IN

42

OUT

34

IN

34

IN

34

IN

34

IN

34

IN

34

IN

34

IN

34

IN

P3V3S

C504

2 1

DPA_HPD_CN
DP_AUXN_CN

DP_AUXP_CN

DPDDC_EN_CN
NB_DPA_TX3_DN

NB_DPA_TX3_DP

NB_DPA_TX2_DN

NB_DPA_TX2_DP

NB_DPA_TX1_DN

NB_DPA_TX1_DP

NB_DPA_TX0_DN

NB_DPA_TX0_DP

NUVO_NCT3521U_SOT23_5P

U21

4 3

DIS EN

1UF_6.3V_2

100_5%_2

C426
C414

C403
C390

C376
C365

C356
C339

R452

P5V0A

OUTIN
GND

15

2

21

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

P3V3S_DPP

C478

2 1

22UF_6.3V_5

DPA_TX3N_C

DPA_TX3P_C

DPA_TX2N_C

DPA_TX2P_C
DPA_TX1N_C

DPA_TX1P_C

DPA_TX0N_C

DPA_TX0P_C

PN:6012B0416401

20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

R305

R310

1M_5%_2

1M_5%_2

2 1

2 1

G4

G4

20

G3

G3

19

G2

G2

18

G1

G1

17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

CN23

FOX_3V11211_RBAHH_8H_20P

D

CC

B

P3V3S

R616

21

1M_5%_2

OUT

NB_DPA_HPD

34

SSM3K7002FU

1

G

Q68

2

3

DS

DPA_HPD_CN

42

IN

OUT

DPDDC_EN

P3V3S_DPP

R333

2 1

100K_5%_2

2

D32

3

BAV99_DY

1

R657

10K_5%_2

2 1
3

Q74

DS

1

G

C761

2 1

0.1UF_16V_2

SSM3K7002FU

2

R658

2 1
3

DS

SSM3K7002FU

2

10K_5%_2

Q75

1

G

DPAUX_EN

DPDDC_EN_CN

OUT

IN

4242

42

P3V3S_DPP

2

3

D34

BAV99_DY

1

AA

INVENTEC

TITLE

LV1.1_Lauren

DISPLAY PORT CONN

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

SIZE

CS

A3

1310A24893-0 MTR

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6742

8 7

6 5

4

3 2 1

P5V0S

HDMI

2

DS

SSM3K7002FU

3

Q28

1

G

D

R180

750_1%_2

750_1%_2

2 1

2 1

R183

2 1

3

D10

BAV99_DY

34

34
34

34
34

34
34

34

P5V0S

IN
IN

IN
IN

IN
IN

IN
IN

NB_HDMI_TX2_DP

NB_HDMI_TX2_DN

NB_HDMI_TX1_DP

NB_HDMI_TX1_DN

NB_HDMI_TX0_DP

NB_HDMI_TX0_DN

NB_HDMI_TXC_DP

NB_HDMI_TXC_DN

C162
C163

C168
C170

C175
C178

C181
C182

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

CN_HDMI_C_TX2P

CN_HDMI_C_TX2N

CN_HDMI_C_TX1P

CN_HDMI_C_TX1N

CN_HDMI_C_TX0P

CN_HDMI_C_TX0N
CN_HDMI_C_TXCP

CN_HDMI_C_TXCN

R150

R151

750_1%_2

2 1

43
43

43

R152

750_1%_2

2 1

BI
BI

IN

R155

R161

750_1%_2

750_1%_2

2 1

2 1

2 1

HDMI_CN_DDCCLK
HDMI_CN_DDCDATA

HDMI_HPD_CN

R173

R163

750_1%_2

750_1%_2

2 1

2 1

P5V0S_HDMI P5V0S_HDMI

NUVO_NCT3521U_SOT23_5P

C268

2 1

B

1UF_6.3V_2

U13

OUTIN
GND

4 3

DIS EN

R197

21

100_5%_2

15
2

C224

2 1

10UF_6.3V_3

P5V0S

3

BAT54A

D9

21

D

2K_5%_2

R187

2K_5%_2

2 1

CN21

1

1

2
3
4
5
6
7
8
9

10

11

12
13
14
15
16
17
18
19

FOX_QJ11A2L-NSHA-7H_19P

G1

GND

2

G2

GND

3

G3

GND

4

G4

GND

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

CC

PN:6012B0417901

B

P3V3S

R175

2 1

10K_5%_2

SSM3K7002FU

SSM3K7002FU

R158

2 1

10K_5%_2

1

G

Q29

2
2

Q27

DS

D S

G

1

3

HDMI_CN_DDCDATA

3

HDMI_CN_DDCCLK

P3V3S

43

43

BIBI

AA

OUT

R188

1M_5%_2

SSM3K7002FU

P3V3S

21

1

G

Q30

2

3

DS

HDMI_HPD_CNNB_HDMI_HPD

R189

2 1

100K_5%_2

4334

IN

34

34

NB_HDMI_DDCDATA

BI BI

NB_HDMI_DDCCLK

INVENTEC

TITLE

LV1.1_Lauren

HDMI CONN

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6743

8

7 6 5 4 3 2 1

LCM CONN

E

D

P1V0S_VCCP

R512

10K_5%_2

NB_EDP_HPD#

23

IN

C

SSM3K7002FU_DY

2 1

3

DS

G

Q2

2

C2

P3V3S_LCDVDD

R36

1

C13

21

100K_5%_2

2 1

0.47UF_16V_2

MOUNT FOR EDP PANEL

P3V3S

2 1

(0.7A)

1UF_6.3V_2

C35

2 1

NUVO_NCT3521U_SOT23_5P

4 3

CSC0402_DY

P3V3S

C11

C10

21

2 1

CSC0402_DY

44

44

2344
2344

DIS EN

100_5%_2

0.1UF_16V_2

OUT
OUT

U1

R11

BI
BI

15

OUTIN

2

GND

21

CN_LCM_CLK
CN_LCM_DATA

NB_EDP_AUX_DP
NB_EDP_AUX_DN

4049

IN

44

IN

3550

P3V3S_LCDVDD

IN

R35

2 1

R470

C571

LID_SW#

DIODE-BAT54-TAP-PHP

CN_LCM_BLEN

AOAC_DIN_LED#

CN_LCM_VCC_EN

100K_5%_2

21

R465

4.7K_5%_2

2 1

10PF_50V_2

D2

P5V0S

SI 1201

L2

P5V0S_CAM

R38

2 1

21

CN2

JAE_FI_G40SB_VF25_R2000_DT_40P

40

40

39

39

38

38

37

37

36

36

35

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

USB_5P

USB_5N

OUT

IN

BI
BI

IN

NB_EDP_TX0_DP

NB_EDP_TX0_DN

NB_EDP_TX1_DP

NB_EDP_TX1_DN

CN_LCM_L1_TXDL0_DP

CN_LCM_L1_TXDL0_DN

CN_LCM_L1_TXDL1_DP

CN_LCM_L1_TXDL1_DN

CN_LCM_L1_TXDL2_DP

CN_LCM_L1_TXDL2_DN

CN_LCM_L1_TXCL_DP

CN_LCM_L1_TXCL_DN

NB_LCM_L2_TXDL0_DP

NB_LCM_L2_TXDL0_DN

NB_LCM_L2_TXDL1_DP

NB_LCM_L2_TXDL1_DN

NB_LCM_L2_TXDL2_DP

NB_LCM_L2_TXDL2_DN

NB_LCM_L2_TXCL_DP

NB_LCM_L2_TXCL_DN

CN_LCM_PWM

SI2 0102

L20

WCM_2012_900T

DMIC_CLK

DMIC_DAT

21
34

23

23

23

23

44

44

44

44

44

44

44

44

34

34

34

34

34

34

100_1%_2

34

44

35
35

49

49

D1

2 1

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

USB_5P_L

USB_5N_L

12

12

D3

2 1

PHP_PESD5V0S1BB_SOD523_2P

2 1
2 1
2 1
2 1

R34

21

33_5%_2

PVBAT

PHP_PESD5V0S1BB_SOD523_2P

C4

2 1C52 1

4.7UF_25V_5

2200PF_50V_2

35

C6
C7
C8
C9

34

34

33

33

32

32

31

31

30

30

29

29

28

28

27

27

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

P/N:6012B0308402

G9

G9

G8

G8

G7

G7

G6

G6

G5

G5

G4

G4

G3

G3

G2

G2

G1

G1

C34

C12

2 1

CSC0402_DY

KC_FBM_11_160808_101_T_2P_DY

2 1

4.7UF_6.3V_3

IN

21

4.7K_5%_2

C573
C572

21

R469
R468

0_5%_2

21

0_5%_2

21

0.1UF_16V_2_DY

21

0.1UF_16V_2_DY

2

NC

13

R10

3K_5%_2

P3V3S

21

R9

2 1

100K_5%_2

P5V0S_CAM

DS

2

3

Q95

G

SSM3K7002FU

1

FF

E

D

C

B

NB_LCM_BLEN

34

OUT

NB_LCM_VCC_EN

34

OUT

NB_LCM_PWM

34

OUT OUT

NB_LCM_CLK

34

OUT

NB_LCM_DATA

34

OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

NB_LCM_L1_TXDL0_DP
NB_LCM_L1_TXDL0_DN

NB_LCM_L1_TXDL1_DP

NB_LCM_L1_TXDL1_DN
NB_LCM_L1_TXDL2_DP

NB_LCM_L1_TXDL2_DN
NB_LCM_L1_TXCL_DP
NB_LCM_L1_TXCL_DN

34
34
34

NB_EDP_AUX_DN

2344

IN

NB_EDP_AUX_DP

2344

IN

21

R463
R462

100K_5%_2_DY

21

100K_5%_2_DY

P3V3S

34
34
34
34
34

21

R24
R37
R21
R466
R467

R13
R22
R15
R16
R17
R18
R19
R12

21
21
21
21

21
21
21
21
21
21
21
21

0_5%_1
0_5%_1
0_5%_1_DY
0_5%_1
0_5%_1

0_5%_1
0_5%_1
0_5%_1
0_5%_1
0_5%_1
0_5%_1
0_5%_1
0_5%_1

CN_LCM_BLEN
CN_LCM_VCC_EN
CN_LCM_PWM
CN_LCM_CLK
CN_LCM_DATA

CN_LCM_L1_TXDL0_DP
CN_LCM_L1_TXDL0_DN
CN_LCM_L1_TXDL1_DP
CN_LCM_L1_TXDL1_DN
CN_LCM_L1_TXDL2_DP

CN_LCM_L1_TXDL2_DN
CN_LCM_L1_TXCL_DP

CN_LCM_L1_TXCL_DN

OUT
OUT

OUT
OUT

44
44
44
44
44

61

44

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

61

44

OUT

61

44

OUT

61

44

OUT

61

44

OUT

61

44

OUT

61

44

OUT

61

44

OUT

LCM_BL_PWM

40

OUT

GPU_LCM_PWM

61

OUT

GPU_LCM_BLEN

56

OUT

GPU_LCM_VCC_EN

61

OUT

GPU_LCM_CLK

56

OUT

GPU_LCM_DAT

56

OUT

GPU_LCM_L1_TXDL0_DP
GPU_LCM_L1_TXDL0_DN
GPU_LCM_L1_TXDL1_DP
GPU_LCM_L1_TXDL1_DN
GPU_LCM_L1_TXDL2_DP

GPU_LCM_L1_TXDL2_DN
GPU_LCM_L1_TXCL_DP
GPU_LCM_L1_TXCL_DN

21

R70

R20
R32
R40
R461
R464

R25
R26
R14
R27
R28
R29
R30
R31

21
21
21
21
21

21
21
21
21
21
21
21
21

0_5%_1

0_5%_1_DY
0_5%_1_DY
0_5%_1_DY
0_5%_1_DY
0_5%_1_DY

0_5%_1_DY
0_5%_1_DY
0_5%_1_DY
0_5%_1_DY
0_5%_1_DY
0_5%_1_DY
0_5%_1_DY
0_5%_1_DY

CN_LCM_PWM
CN_LCM_BLEN

CN_LCM_VCC_EN
CN_LCM_CLK
CN_LCM_DATA

CN_LCM_L1_TXDL0_DP
CN_LCM_L1_TXDL0_DN
CN_LCM_L1_TXDL1_DP

CN_LCM_L1_TXDL1_DN

CN_LCM_L1_TXDL2_DP

CN_LCM_L1_TXDL2_DN
CN_LCM_L1_TXCL_DP

CN_LCM_L1_TXCL_DN

OUT
OUT
OUT
OUT
OUT

44
44
44
44
44

44

OUT

44

OUT

44

OUT

44

OUT

44

OUT

44

OUT

44

OUT

44

OUT

B

0201 RESISTOR

A

INVENTEC

TITLE

LV1.1_Lauren

LVDS

DOC.NUMBER

CODE

SIZE

1310A24893-0 MTR

C

8

7 6 5 4 3

CHANGE by

DATE

12-12-2011David Cheng

2 1

CS

SHEET

of

44

A

REV

AX1

67

8 7

6 5

4

3 2 1

PAVDDL_LAN

LAN

D

R524

40

IN

2 1

220K_5%_2

(0.169A)

P3V3A P3V3A_LAN

SD

2

G

AM2321P

Q61

1

WOL_PWEN#_RCWOL_PWEN#

C656

2 1

0.1UF_16V_2

1

SSM3K7002FU_DY

3

R528

2 1

3

DS

G

2

TRACE WIDTH >= 30MIL

L9

21

SWF2520CF_4R7K_M

C133

C123

2 1

2 1

10UF_6.3V_3

0.1UF_16V_2

LX

45

IN

IN

BI

OUT

PLT_RST#
PCIE_WAKE#
CLKREQ_LAN#

355054
334849
32

PVDDCT_LAN

CLOSE TO PIN40

B

C625

OUT

LED_LANRXACT

4546

IF NOT OVERCLOCKING, MOUNT R139

OUT

LED_LANLINK#

IF SWITCH REQULATOR APPLIED, NO MOUNT R149
IF LDO APPLIED, MOUNT R149

4546

8

21

470PF_50V_2

R139

21

5.1K_5%_2

C152

R149

21

21

470PF_50V_2

5.1K_5%_2_DY

7 6

I MAX = 0.2A

TRACE WIDTH >= 30MIL

PIN1

C621

2 1

10UF_6.3V_3_DY

200_5%_2

PIN1

PIN1

C620

C641

2 1

10UF_6.3V_3

PLACED NEAR LAN CONTROLLER

Q62

C121

X1

3

1
4

2

25MHZ

C110

2 1

18PF_50V_2

0.1UF_16V_2

21

C108

2 1

4546

OUT

4546

OUT

45

OUT

PAVDDL_LAN

20MIL

PAVDDH_LAN

18PF_50V_2

PIN1

C634

2 1

2 1

1UF_6.3V_2

0.1UF_16V_2

LED_LANRXACT
LED_LANLINK#

LX

TRACE WIDTH >= 30MIL

P3V3A_LAN

PVDDCT_LAN

10

20MIL

R489

2 1

C106

C595

2 1

2 1

1UF_6.3V_2

0.1UF_16V_2

IN
IN

OUT
OUT

IN
IN

OUT
OUT

TRD0P
TRD0N

TRD1P
TRD1N

TRD2P
TRD2N

TRD3P
TRD3N

46
46

46
46

46
46

46
46

5 4

CLOSE TO PIN37

PDVDDL_LAN

C150

34

31

353633

4023393841

LX

GND

1 30

2
3
4
5
6
7
8

LED_1

VDD33 TX_P
PERSTN
WAKEN
CLKREQN
VDDCT
AVDDL_REG
XTLO
XTLI
AVDDH_REG
RBIAS

TRXP0

TRXN0

12

13916

11

2.37K_1%_2

32

37

RX*

RX_P

LED_0

AVDDL

AVDDL

REFCLK*

REFCLK_P

DVDDL_REG

U9

TRXP1

TRXN1

AVDDL

14

15

TX*

NC1

TESTMODE

SMDATA

SMCLK

DVDDL
LED_2

AVDDH

TRXN3

TRXP3

TRXP2

TRXN2

AVDDH

AVDDL

ATHEROS_AR8151_BL1A_R_QFN_40P

20

17

18

19

C134

2 1

2 1

1UF_6.3V_2

PCIE_C_TXN_LAN
PCIE_C_TXP_LAN

CLK_PCIE_LAN

CLK_PCIE_LAN#

PAVDDL_LAN

PCIE_RXP_C_LAN

29

PCIE_RXN_C_LAN

28
27

1

26

TP7

1

25

TP6

24
22

21

PAVDDH_LAN

0.1UF_16V_2

TESTMODE

TP24
TP24

PAVDDH_LAN

PAVDDL_LAN

R128
R127

R126
R125

R124
R123

R122
R121

CHANGE by

32

IN

32

IN

32

BI

32

BI

0.1UF_16V_2

0.1UF_16V_2

PDVDDL_LAN

20MIL

C109

2 1

0.1UF_16V_2

CLOSE TO LAN CHIP

21

49.9_1%_2

21

49.9_1%_2

21

49.9_1%_2

21

49.9_1%_2

21

49.9_1%_2

21

49.9_1%_2

21

49.9_1%_2

21

49.9_1%_2

AR8151 MOUNT ; AR8161 NO MOUNT

David Cheng

PLACED NEAR LAN CONTROLLER

20MIL

PIN13 PIN31 PIN6

C135

C136

2 1

0.1UF_16V_2

PIN34PIN19

C137

C102

2 1

2 1

0.1UF_16V_2

2 1

0.1UF_16V_2

PAVDDH_LAN

20MIL

PIN16

PIN22

C592

C107

2 1

2 1

0.1UF_16V_2

0.1UF_16V_2

2 1
2 1

C104
C103

C101
C100

C98
C99

C96
C97

C125
C122

21
21

21
21

21
21

21
21

PCIE_C_RXP_LAN
PCIE_C_RXN_LAN

1000PF_50V_2

0.1UF_16V_2

1000PF_50V_2

0.1UF_16V_2

1000PF_50V_2

0.1UF_16V_2

1000PF_50V_2

0.1UF_16V_2

INVENTEC

TITLE

CODE

SIZE

CS

DATE

12-12-2011

23

A3

PIN6

C105

2 1

1UF_6.3V_2

0.1UF_16V_2

OUT
OUT

LV1.1_Lauren

LAN

DOC.NUMBER

1310A24893-0 MTR

SHEET

C594

2 1

0.1UF_16V_2

D

CC

32
32

B

AA

REV

of

AX1

6745

1

8 7

RJ45

6 5

4

3 2 1

D

D

PVDDCT_LAN

L38

BLM18BD601SN1D

21

C58

2 1

1UF_10V_2

U31

1

TCT1

OUT
OUT

IN
IN

OUT
OUT

IN
IN

TRD0N
TRD0P

TRD1N
TRD1P

TRD2N
TRD2P

TRD3N
TRD3P

45
45

45
45

45
45

45
45

C920

B

2 1

C902

C901

2 1

2 1

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

3

TD1-

2

TD1+

4

TCT2

6

TD2-

5

TD2+

7

TCT3

9

TD3-

8

TD3+

10

TCT4

12

TD4-

11

TD4+

BOTH_GST5009_SOP_24P

24

MCT1

22

MX1-

23

MX1+

21

MCT2

19

MX2-

20

MX2+

18

MCT3

16

MX3-

17

MX3+

15

MCT4

13

MX4-

14

MX4+

C81

C76

C73

C67

2 1

2 1

0.01UF_100V_3

R97

R98

75_5%_2

2 1

2 1

2 1

2 1

0.01UF_100V_3

0.01UF_100V_3

0.01UF_100V_3

R106

R102

75_5%_2

75_5%_2

75_5%_2

2 1

2 1

RD­RD+

TD­TD+

RD1­RD1+

TD1­TD1+

OUT
OUT

OUT
OUT

46

IN

46

IN

46
46

45

46

IN

46

IN

46
46

46

46

46

46

46
46
46
46

IN
OUT
OUT

IN
OUT
OUT

IN

IN

IN

LED_LANRXACT

RD+
RD­TD+
RD1+
RD1­TD­TD1+
TD1-

P3V3A_LAN

1

2
3
4
5
6
7
8

JACK1

AMBER

B2B1

B2B1
TX+
TX-

G1

RX+

G1
P4
P5

G2

RX-

G2
P7
P8

A2A1

A2A1

WHITE

FOX_JM3611_N2720C3_7H_12P

R101

100_5%_2

R99

330_5%_2

21

21

LED_LANLINK#

45

IN

CC

B

SI 1122

C576

2 1

100PF_3000V

LAYOUT NOTE : PLACE TERMINATION RESISTORS AND CAPS AS CLOSE TO LAN CONTROLLER AS POSSIBLE

INVENTEC

TITLE

SIZE

CHANGE by

8

7 6

5 4

David Cheng

DATE

12-12-2011

23

A3

LV1.1_Lauren

RJ-45

DOC.NUMBER

CODE

1310A24893-0 MTR

CS

SHEET

AA

REV

of

AX1

6746

1

8 7

6 5

4

3 2 1

USB30_REDRIVER_PORT2

P3V3A

R2600

0_5%_3

D

USB30_SSTX2-

35

IN

USB30_SSTX2+

35

IN

OUT
OUT

USB30_SSRX2­USB30_SSRX2+

35
35

USB30_REDRIVER_PORT3

B

35
35

USB30_SSTX3-

IN

USB30_SSTX3+

IN

USB30_SSRX3-

35

OUT

USB30_SSRX3+

35

OUT

8

21

P3V3S_USB30

C2601

2 1

21

C2629

21

C2630
C2603

21

C2602

21

2.2UF_6.3V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.01UF_50V_2

21

C2631

21

C2632
C2623

21

C2620

21

6

U2604

GND

7

NC

EN_RXD

P3V3S_USB30

2 1

8

RX-

9

RX+

10

GND

11

TX2-

12

TX2+

OS2 OS1

EQ2 EQ1

DE2 DE1

CM

VCC

13

15 4

17 2516 3

14

PCIE_EQ2_A

PCIE_DE2_A

USB30_SSTX2-_C

USB30_SSTX2+_C

USB30_SSRX2-_C

USB30_SSRX2+_C

C2622

PCIE_OS2_A

PCIE_CM_A

0.01UF_50V_2

USB30_SSTX3-_C

USB30_SSTX3+_C

USB30_SSRX3-_C

USB30_SSRX3+_C

P3V3S_USB30

C2624

10
11
12

2 1

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

7 6

PCIE_EN_RXD_A

PCIE_OS1_A

PCIE_DE1_A

PCIE_EQ1_A

P3V3S_USB30

C2605

0.1UF_16V_2

2 1

USB30_SSTX2-_R

USB30_SSTX2+_R

0.1UF_16V_2

25

TML

24

NC

23

TX1-

22

TX1+

21

GND

20

RX2-

19

RX2+

GND VCC

TI_SN65LVPE502CPRGER_QFN_24P

18 1

47

IN

47

IN

47

IN

47

IN

PCIE_EN_RXD_B

PCIE_OS1_B

PCIE_DE1_B

PCIE_EQ1_B

6

U2625

TML

GND

7

NC

8

RX-

9

RX+
GND
TX2­TX2+

13

NC

EN_RXD

TX1-

TX1+

GND
RX2-

RX2+

VCC

OS2 OS1

EQ2 EQ1

DE2 DE1

CM

GND VCC

TI_SN65LVPE502CPRGER_QFN_24P

15 4

17 2516 3

14

18 1

PCIE_EQ2_B

PCIE_DE2_B

PCIE_OS2_B

PCIE_CM_B

C2606

2 1

25
24
23
22
21
20

19

2 1

0.1UF_16V_2

P3V3S_USB30

C2626

2 1

USB30_SSTX3-_R

USB30_SSTX3+_R

IN
IN
IN
IN

47

IN

47

IN

47

IN

47

IN

C2607

0.1UF_16V_2

C2627

0.1UF_16V_2

2 1

47

47

47

47

0.1UF_16V_2

USB30_SSTX2-_CN
USB30_SSTX2+_CN

USB30_SSRX2-_CN
USB30_SSRX2+_CN

47

IN

47

IN

47

IN

47

IN

2 1

C2628

USB30_SSTX3-_CN
USB30_SSTX3+_CN

USB30_SSRX3-_CN
USB30_SSRX3+_CN

5 4

SI 1109

SI 1109

OUT
OUT

IN
IN

P3V3S_USB30

R2616

21

PCIE_CM_A

4.7K_5%_2_DY

P3V3S_USB30

PCIE_EQ2_A

R2629

21

4.7K_5%_2_DY

P3V3S_USB30

4.7K_5%_2_DY

PCIE_DE2_A

R2617

21

4.7K_5%_2_DY

50
50

50
50

P3V3S_USB30

R2630

4.7K_5%_2_DY

4.7K_5%_2_DY

PCIE_OS2_A

21

4.7K_5%_2_DY

R2635

R2618

R2636

47

47

IN

21

47

IN

21

47

IN

21

R2640

4.7K_5%_2_DY

P3V3S_USB30

4.7K_5%_2_DY

P3V3S_USB30

4.7K_5%_2_DY

P3V3S_USB30

4.7K_5%_2_DY

21

PCIE_EN_RXD_A

R2641

21

R2642

21

R2643

21

PCIE_EQ1_A

R2648

4.7K_5%_2_DY

PCIE_DE1_A

R2649

4.7K_5%_2_DY

PCIE_OS1_A

4.7K_5%_2_DY

R2650

47

ININ

47

IN

21

47

IN

21

47

IN

21

D

CC

P3V3S_USB30

OUT
OUT

R2631

21

PCIE_CM_B

4.7K_5%_2_DY

P3V3S_USB30

PCIE_EQ2_B

R2632

21

4.7K_5%_2_DY

P3V3S_USB30

4.7K_5%_2_DY

PCIE_DE2_B

R2633

21

4.7K_5%_2_DY

50
50

50

IN

50

IN

P3V3S_USB30

R2634

4.7K_5%_2_DY

4.7K_5%_2_DY

21

4.7K_5%_2_DY

R2637

R2638

R2639

IN

47

IN

21

47

IN

21

47

IN

21

R2644

4.7K_5%_2_DY

P3V3S_USB30

4.7K_5%_2_DY

P3V3S_USB30

4.7K_5%_2_DY

P3V3S_USB30

4.7K_5%_2_DY

21

PCIE_EN_RXD_B

PCIE_EQ1_B

R2645

21

PCIE_DE1_B

R2646

21

PCIE_OS1_BPCIE_OS2_B

R2647

21

R2651

4.7K_5%_2_DY

R2652

4.7K_5%_2_DY

R2653

4.7K_5%_2_DY

4747

IN

B

47

IN

21

47

IN

21

47

IN

21

AA

INVENTEC

TITLE

LV1.1_Lauren

USB30_REDRIVER

CHANGE by

David Cheng

DATE

12-12-2011

23

SIZE

DOC.NUMBER

CODE

1310A24893-0 MTR

CS

A3

SHEET

of

47

1

REV

AX1

67

8 7

P5V0A

6 5

4

3 2 1

USB 3.0

C17

C16

2 1

2 1

D

3548
3548

USB_SW_EN

4049

IN

USB_0N

BI

USB_0P

BI

R845
R846

R844

21

21

0_5%_2

21

0_5%_2

0_5%_2

P5V0A

151614

13

17

GND

ILIM0

ILIM1

PwPd

P5V0A

4049

IN

B

3340

BI

49

USBPWR_EN

SLP_S3#

3548
3548

BI
BI

R104

10K_5%_2

R103

10K_5%_2_DY

R73

0_5%_2

USB_0N
USB_0P

21

21

R753

0_5%_2

21

1

2 11
3 10

21

IN
DM_OUT
DP_OUT
LILM_SEL

FAULT#

DM_IN

DP_IN

CTL3

CTL2

CTL1

EN

876

5

22UF_6.3V_5

0.01UF_50V_2

USB_0N_R
USB_0P_R

R847
R848

U42

1

GND

2

IN

3

IN

4

EN

GMT_G547E1P81U_MSOP_8P

21

0_5%_2

21

0_5%_2

P5V0A_USB1

R96

21

0_5%_2_DY

R105

21

22.1K_1%_2

12

OUT

94

NC

U3

TI_TPS2540_QFN_16P

CO-LAY WITH TPS2543

100K_5%_2

10K_5%_2

10K_5%_2

R108

0_5%_2_DY

R72

R100

R241

21

21

21

21

USB_0N_L
USB_0P_L
PCIE_WAKE#

P5V0A

BOM OPEN

OUT
OUT
OUT
OC#

8
7
6
5

USB_0N_L
USB_0P_L

USB30_SSRX1-

35
35

USB30_SSRX1+

35
35

IN

USB30_SSTX1-

USB30_SSTX1+

BI
BI

BI
BI

BI
BI

33
45
49

0.1UF_16V_2

P5V0A_USB1

C815

2 1

22UF_6.3V_5

WCM_2012_900T

C800

2 1

C525

2 1

L39

21
34

USB30_SSTX1-_C

2 1

0.1UF_16V_2

+

C507

2 1

100UF_6.3V

0.1UF_16V_2

USB_0N_CN
USB_0P_CN

WCM_1210HS_600T

C801

USB30_SSTX1+_C

WCM_1210HS_600T

P5V0A_USB1

L40

L41

D

P5V0A_USB1

U27

VccGND

1

1

IO

2

PHP_PRTR5V0U2X_SOT143_4P_DY

USB30_SSRX1-_CN
USB30_SSRX1+_CN

32
41

32
41

USB30_SSTX1-_CN
USB30_SSTX1+_CN

D80

54

7 6

8

SEMTECH_RCLAMP0524P.TCT_SLP2510P8_10P_DY

4

4

IO

32

3

CN26

1

VBUS

2

D-

3

D+

4

PGND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

FOX_UEA111AC_RABHA_8H_9P

USB LEFT SIDE

D80

2

1

9

10

SEMTECH_RCLAMP0524P.TCT_SLP2510P8_10P_DY

3

CC

G1

G

G2

G

G3

G

G4

G

G5

G

G6

G

B

REAR SPEAKER

CN651

IN
IN
IN
IN

SPK_OUT_R+
SPK_OUT_R­SPK_OUT_L­SPK_OUT_L+

C508

2 1

220PF_50V_2

2 1

2 1

220PF_50V_2

220PF_50V_2

C515

C514

C509

5 4

49
49
49
49

8

7 6

1

1

2

2

3
4

2 1

220PF_50V_2

G1

3

G2

GG4

ACES_50281_00401_001_4P

PN : 6012B0096202

CHANGE by

David Cheng

USB CONN01

INVENTEC

TITLE

LV1.1_Lauren

USB3.0 CONN

DOC.NUMBER

CODE

DATE

12-12-2011

23

SIZE

A3

1310A24893-0 MTR

CS

SHEET

AA

REV

of

48

AX1

67

1

8

7 6 5 4 3 2 1

AUDIO BOARD CNTR

AU BOARD CN ON MB

PVBAT

Q105

SD

213

G

C686

R697

2 1

2 1

100K_5%_2

0.01UF_50V_2_DY

E

P5V0S

1

SSM3K7002FU

D

AU BOARD CN ON MB
(FFC)

R698

47K_5%_2

2 1

3

DS

G

334048

2

Q104

405156
405156

ANALOG_AM2329P_SOT23_3P

USB_SW_EN

4048

IN

PCIE_WAKE#

334548

IN

SLP_S4#

3340

IN

AMP_EN

40

IN

USBPWR_EN

4048

IN

SLP_S3#

BI

MUTE_LED#

50

OUT

PCSPKR

31

OUT

HP_IN

40

OUT

THM_DAT

BI

THM_CLK

BI

C561

R694
R693

44

IN

44

IN

48

IN

48

IN

48

IN

2 1

48

IN

8.2PF_50V_2

EMI

POWER FFC CNTR

PBN CABLE CN ON MB

P5V0A P3V3S P5V0S

21

0_5%_2

21

0_5%_2_DY

DMIC_CLK
DMIC_DAT

SPK_OUT_L+
SPK_OUT_L-

SPK_OUT_R+
SPK_OUT_R-

PN : 6012B0218428

+VBATR_AMP

CN10

ACES_50501_0404N_001_40P

40

40

39

39

G

38

G2

G

37

G1

36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20

19
18
17
16
15
14
13
12
11
10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

31
31

31
31

SI 1014

38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

SATA HDD CONN A

P5V0S

(1A)

C563

2 1

OUT
OUT

IN
IN

SATA_A_RX0P
SATA_A_RX0N

SATA_A_TX0N
SATA_A_TX0P

21

C844

0.01UF_50V_2

21

C841

0.01UF_50V_2

21

C832

0.01UF_50V_2

21

C833

0.01UF_50V_2

CLOSE TO HDD CONN A

SATA_A_RX0P_C
SATA_A_RX0N_C

SATA_A_TX0N_C
SATA_A_TX0P_C

SATA ODD FFC CONN ON MB

SSM3K7002FU_DY

40

49
49

49
49

OUT
OUT

P15V0A

1

G

Q57

IN

IN
IN

R492

2 1

RSC_0402_DY

3

DS

C619

2 1

2

0.1UF_16V_2_DY

ODD_MD#

SATA_RX1P_RD_C
SATA_RX1N_RD_C

SATA_TX1N_RD_C
SATA_TX1P_RD_C

P5V0A

Q60

DGS

NMOS_4D1S

AO6402AL

V3S_R_EN

68PF_50V_2

10
11
12
13
14
15
16

1
2
3
4
5
6
7
8
9

4

+V5A_ODD_MB

36

CN8

C642

1

2

2 1

3
4
5
6
7
8
9

10
11
12
13
14
15
16

PLAST_FZ26_16WK_60_H_16P

10UF_6.3V_3

G1

G

G2

G

C623

2 1

1

2
5

19

IN

C617

2 1

FF

0.1UF_16V_2

E

D

OPEN

IF R492 SHOUL BE MOUNT
PN: 6013B0027203 (560K_1%_2)

CN27

1

1

2

2

3

3

4

4

C562

C564

2 1

10UF_6.3V_3

5

5

6

6

2 1

7

10UF_6.3V_3

CSC0402_DY

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

G

17

18

G

18

19

G

19

20

G

20

FOX_GS12201_1011_9H_20P

G1
G2
G3
G4

ODD_PW_EN#

40

IN

C

P3V3S

C

P3V3A

C447

C434

21

21

C36

68PF_50V_2

SATA_TX1P_RD_C

49

OUT

CN5

G2

G2

1

B

PWR_LED#

4050

IN

EC_PWRBTN#

40

OUT

LID_SW#

4044

OUT

P3V3AL

ACES_50505_0064N_001_6P

R80

C43

2 1

2 1

100K_5%_2

1000PF_50V_2

C41

2 1

0.1UF_16V_2

1

2

2

3

3

4

4

5

5

6

6

G1

G1

49

49
49

OUT

IN
IN

SATA_TX1N_RD_C

SATA_RX1N_RD_C
SATA_RX1P_RD_C

21

C404

0.01UF_50V_2

21

C406

0.01UF_50V_2

21

C405

0.01UF_50V_2

21

C408

0.01UF_50V_2

P3V3S

R597

2 1

R593

2 1

SATA_TX1P_RD
SATA_TX1N_RD

SATA_RX1N_RD
SATA_RX1P_RD

R599

0_5%_2

2 1

R602

2 1

0_5%_2_DY

0_5%_2

0_5%_2_DY

15
14
13 3
12
11

A

8

7 6 5 4 3

2 1

0.1UF_16V_2

0.01UF_50V_2

21

20

16 10

191817

TML

VCC

GND

GND

GND

VCC

1

TX_0P
TX_0N
GND

U19

RX_1N
RX_1P

VCC

VCC

EN

D1

D0

789

6

SATA_TX1P_CN

RX_0P

2

SATA_TX1N_CN

RX_0N

GND

4

SATA_RX1N_CN

TX_1N

5

SATA_RX1P_CN

TX_1P

TI_SN75LVCP412RTJR_QFN_20P

P3V3S

21

R325

1K_5%_2

0.01UF_50V_2

0.01UF_50V_2

0.01UF_50V_2

0.01UF_50V_2

2 1
2 1

2 1
2 1

C354
C336

C462
C458

SATA_ODD_TX2P
SATA_ODD_TX2N

SATA_ODD_RX2N
SATA_ODD_RX2P

OUT
OUT

31

IN

31

IN

31
31

B

A

INVENTEC

TITLE

LV1.1_Lauren

AUDIO, PWB, ODD BOARD& HDD CONN

DOC.NUMBER

CHANGE by

SIZE

DATE

12-12-2011David Cheng

2 1

C

CODE

CS

1310A24893-0 MTR

SHEET

REV

AX1

of

67

49

8

7 6 5 4 3 2 1

WIRELESS AUDIO BOARD CN ON MB

MUTE BUTTON

MUTE BUTTON SWITCH

MUTE_BTN#

40

OUT

T3
T4

DIP_TMG_533_Q_T_R_4P

LDPS BOARD CN ON MB

SW1

T1
G2G1
T2

P3V3S

CN12

1

1

WWAN_POWER_OFF

36

IN

SMSC_RST#

36

IN

USB_4N

35

BI

USB_4P

35

BI

E

W_AU_LED#

51

OUT

RF_SEL1

36

IN

RF_SEL2

36

OUT

TP831TP84

TP24

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

1

TP24

13

14

14

15

G

15

16

G

16

PLAST_FZ26_16WK_60_H_16P

G1
G2

SI 1201

50

354450

49

MUTE_LED#_AOAC

IN

IN

IN

AOAC_DIN_LED#

MUTE_LED#

D7

HT_F196UD

21

Q93

2

SSM3K7002FU

1

G

DS

R136

47_5%_2

3

21

P3V3S

MUTE_LED#_AOAC

OUT

PCH_SMCLK_THM

40

OUT

PCH_SMDAT_THM

40

OUT

50

P3V3A

PN : 6012B0073304

D

CR BOARD CN ON MB AU-USB30 CN ON MB

C

PLT_RST#

354554

IN

CLKREQ_CR#

32

OUT

PWR_LED#

4049

IN

HDD_LOCK_LED#_CN

50

IN

LED_3S_SATA#_CN

50

IN

CLK_PCIE_CR

32

IN

CLK_PCIE_CR#

32

IN

PCIE_C_RXP_CR

32

OUT

PCIE_C_RXN_CR

32

OUT

PCIE_C_TXN_CR

32

IN

PCIE_C_TXP_CR

32

IN

B

PN : 6012B0354701

AOAC_DIN_LED#

354450

IN

HDD_LOCK_LED#

36

IN

P3V3A P3V3S

Q91

2

SSM3K7002FU

CN11

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

ACES_50501_0184N_001_18P

GG18

1

G

3

DS

G1
G2

HDD_LOCK_LED#_CN

OUT

50

JOG DIAL CN ON MB

P3V3SP3V3AL

R527

R523

R520

2 1

VO_UP_A

40

OUT

VO_DN_B

40

OUT

JD_BUTTON#

40

OUT

12

D502

2 1

10K_5%_2

10K_5%_2

2 1

12

D501

2 1

PHP_PESD5V0S1BB_SOD523_2P

10K_5%_2

2 1

12

PN: ?

D500

2 1

PHP_PESD5V0S1BB_SOD523_2P

PHP_PESD5V0S1BB_SOD523_2P

SI2 0103

CN20

G2G17

G2

7

6

G1

6

5

5

4

4

3

3

2

2

1

1

ENTERY_6705K_Q07N_00R_7P

(WIRE OR COXIAL)

HDA_BITCLK

31

IN

HDA_SDIN0

31

IN

HDA_SDOUT

31

IN

HDA_SYNC

31

IN

HDA_RST#

31

IN

USB_1N

35

IN

USB_1P

35

IN

USB30_SSRX2-_CN

47

OUT

USB30_SSRX2+_CN

47

OUT

USB30_SSTX2-_CN

47

IN

USB30_SSTX2+_CN

47

IN

USB_2N

35

IN

USB_2P

35

IN

USB30_SSRX3-_CN

47

OUT

USB30_SSRX3+_CN

47

OUT

USB30_SSTX3-_CN

47

IN

USB30_SSTX3+_CN

47

IN

1

G

Q92

2

3

LED_3S_SATA#

31

A

IN OUT

SSM3K7002FU

DS

8

LED_3S_SATA#_CN

50

7 6 5 4 3

CHANGE by

David Cheng 12-12-2011

DATE

P5V0A

CN7

1

1

2

2

G1

3

G

3

G2

4

G

4

5

5

6

6

ACES_88460_0601_6P

CN9

G1

G

1

1

2

2

G2

3

G

3

4

4

5

5

6

6

7

7

8

8

9

9

10
11
12
13
14
15
16
17
18
19
20

FOX_GS12207_11141_9H_20P

TITLE

SIZE

2 1

G3

G

10
11
12
13
14
15
16
17

G4

G

18
19
20

G5

G

INVENTEC

LV1.1_Lauren

WIRELESS AUDIO,LDPS,CR,JOG,USB CONN

CODE

1310A24893-0 MTR

C

CS

SHEET

DOC.NUMBER

50 67

FF

E

D

C

B

A

REV

AX1

of

8

7 6 5 4 3 2 1

E

D

ATHEROS

BROADCOM

RALINK

REALTEK

INTEL

(RAINBOW PEAK)

PIN 5

V

(RESERVED)

V

(RESERVED)

V

(RESERVED)

PIN 19 PIN 51

V

(ES2 SAMPLE / WW27)

35

OUT

36

51

IN

32

OUT

32

IN

32

IN

21

35405166

IN

35

IN

32

OUT

32

P3V3S_WLAN

35

IN

OUT

32

IN

32

IN

2ND_WLAN_RF_OFF#

(QS SAMPLE / WW42)

WLAN_WAKE#

BTOFF
CLKREQ_WLAN#

CLK_PCIE_WLAN#
CLK_PCIE_WLAN

BUF_PLT_RST#
LPC_CLK1

PCIE_C_RXN_WLAN

PCIE_C_RXP_WLAN

PCIE_C_TXN_WLAN

PCIE_C_TXP_WLAN

V

(RESERVED)

V

R596
R539

R538

R537
R536

P3V3S

12

C255

PAD200

2 1

2 1

POWERPAD1X1M_DY

0.1UF_16V_2_DY

P3V3S_WLAN

TP24

TP24

R863

0_5%_2

0_5%_2_DY

21

2 1

0_5%_2

10K_5%_2

TP781TP77

1

1

3
5
7
9

11

13

19

21

23
25

29

31

33
35
37
39

41

43
45

49

CN22

WAKE#
Reserved
Reserved
CLKREQ#
GND
REFCLK­REFCLK+

Reserved
GND
PERN0
PERP0

GND
PETN0
PETP0
GND
Reserved
Reserved
Reserved
Reserved
Reserved

Reserved

FOX_AS0B226_S40Q_7H_52P

SI 1014

21

0_5%_2_DY

21

0_5%_2

21
21

PN:6026B0221501

Reserved
Reserved
Reserved
Reserved
ReservedGND

Reserved

PERST#

+3.3VAUX

SMB_CLK

SMB_DATA

USB_D­USB_D+

LED_WWAN#

LED_WLAN#

LED_WPAN#

P3V3A

WLAN CONN (MINICARD)

Q80

D

PMOS_4D1S

AM3423P

4

S

36

G

1

2
5

12

PAD201

2 1

POWERPAD1X1M

FF

P3V3A

R620

C256

2 1

(1.5A)

2

3.3V

4

GND

6

1.5V

8
10
12
14
1615
1817

GNDReserved

20
22
24
26

GND

2827

1.5VGND

30
32
34

GND

36
38
40

GND

42
44
46
4847

1.5VReserved

50

GND

5251

3.3VReserved

G2G1

GG

0.1UF_16V_2

R750

220K_5%_2

C253

2 1

WLAN_POWER_OFF

21

C260

2 1

1UF_6.3V_2

LPC_FRAME#

LPC_AD(3)
LPC_AD(2)
LPC_AD(1)
LPC_AD(0)

BUF_PLT_RST#

USB_8N
USB_8P

36

IN

C231

C661

21

2 1

0.1UF_16V_2

4.7UF_6.3V_3

2.2UF_6.3V_2

BI
BI
BI
BI
BI

IN

BI
BI

36

IN

51

IN

31

40 66

31

40 66

31

40 66

2

31

40 66

D11

31

40 66

NC

1 3

21

35 40

51

66

DIODE-BAT54-TAP-PHP

35

2

35

D196

NC

DIODE-BAT54-TAP-PHP

SSM3K7002FU_DY

WWAN_RF_OFF#

BT_IND

13

P3V3S

R196

2 1

3

DS

Q97

2

1K_5%_2

2 1

100K_5%_2

WLAN_RF_OFF#

4.7K_5%_2

1

G

21

R61

WLAN_IND#

W_AU_LED#

OUT

P1V5S

R195

0_5%_2

2 1

(1.5A)

C218

2 1

36

40

50

3

Q123

DS

G

SSM3K7002FU

2

CSC0603_DY

BT_IND

1

51

ININ

IN

E

D

R682

2 1

C751

C570

2 1

2 1

0.1UF_16V_2

P3V3A P15V0A

3

Q102

DS

1

G

SSM3K7002FU

0_5%_2_DY

2

R610

220_5%_3

3

2 1

Q106

DS

1

G

SSM3K7002FU

2

10UF_6.3V_3

51

BI

51

BI

CHANGE by

David Cheng 12-12-2011

R683

2 1

3

DS

2

1M_5%_2

Q103

1

G

SSM3K7002FU

51

BI

404956

BI

404956

BI

51

BI

ACC_PWR_EN

40

IN

SMBUS

G-SENSOR_V

51

IN

R459

R458

2 1

2 1

2.2K_5%_2

G_SEN_CLK

THM_CLK

THM_DAT

G_SEN_DAT

DATE

2 1

2.2K_5%_2

TITLE

SIZE

C

G-SENSOR_V

51

IN

2

Q107

1

G

DS

SSM3K7002FU

3
3

Q108

DS

1

G

SSM3K7002FU

2

INVENTEC

LV1.1_Lauren

WLAN & HDD PROTECTION

DOC.NUMBER

CODE

1310A24893-0 MTR

CS

SHEET

of

51

C

B

A

REV

AX1

67

BLUETOOTH CONN

(SOFTBREEZE)

C

P3V3S_BT

CN3

1

1

2

2

G1

USB_10P

35

BI

USB_10N

35

BI

BT_IND

51

OUT

3

G

3

4

G

4

5

5

6

6

ACES_88460_0601_6P

G2

PN : 612B0073304

B

36

51

IN

A

8

BTOFF

P3V3A

R75

2 1

(0.07A)

10K_5%_2

2 1

220K_5%_2

R78

SI 1013

SD

2

G

Q14

1

AM2321P

C33

2 1

0.01uF_50V_2

P3V3S_BT

3

R69

C31

2 1

4.7K_5%_2

2 1

10UF_6.3V_3

7 6 5 4 3

HARDDRIVE PROTECTION

G-SENSOR_V

51

51

OUT

G-SENSOR_V

51

IN

14

16

1

G

SSM3K7002FU_DY

2

R455

0_5%_2

3

DS

Q96

21

R456

2 1

10K_5%_2_DY

ACCEL_INT#

35

BI

PN:6019B0914201

SMBUS ADDRESS IS "001100XB"

IF SA0 PAD IS CONNECTED TO VOLTAGE, LSB IS "1"
IF SA0 PAD IS CONNECTED TO GND, LSB IS "0"

15

U30

13

RES

RES

VDD

VDD_IO

RES

12

GND

11

INT1

10

RES

SCL_SPC

9

INT2

CS

SDO_SA0

SDA_SDI_SDO

7

6

8

G-SENSOR_V

1
2

NC1

3

NC1

4
5

GND

ST_HP3DC2TR_LGA_16P

G_SEN_CLK

G_SEN_DAT

8 7

6 5

4

3 2 1

D

CPU SCREWS

S6

S11

1

SCREW330_600_1P

S10

1

SCREW330_600_1P

S5

1

1

SCREW330_600_1P

SCREW330_600_1P

VGA SCREWS

S8

B

1

S13

1

SCREW320_520_1P

SCREW320_520_1P

WWAN SCREWS

1.6mm

ST15

STDPAD_1.15_6-TOP

1

RALPH (STDPAD_1.15_6-BOT)
6052B0103501-BOT

FIX1

1

FIX_MASKFIX_ MASK

FIX3

FIX2

1

FIX_MASKFIX_ MASK

1.6mm

ST14

STDPAD_1.15_6-TOP

1

FIX4

1

1

FIX_MASKFIX_ MASK

FIX_MASKFIX_ MASK

S16

1

SCREW280_550_1P

S17

1

SCREW280_550_1P

S1

1

SCREW350_700_1P

S4

1

SCREW320_700_800_ 1P

S18

S19

1

1

SCREW280_550_700_1P

SCREW280_550_1P

S2

S20

1

1

SCREW240_500_NP_1P

SCREW350_700_1P

S7

S3

1

1

SCREW340_620_1P

SCREW280_550_1P

S9

1

SCREW320_700_1P

D

CC

B

FIX5

FIX6

FIX7

FAN SCREWS

S12

1

SCREW340_620_1P

1

1

FIX8

1

1

AA

INVENTEC

TITLE

LV1.1_Lauren

EMI CAP. & SCREW

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6752

8 7

6 5

4

3 2 1

D

D

CC

GPU

B

B

AA

INVENTEC

TITLE

LV1.1_Lauren

BLANK

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6753

8 7

U34

PART 1 0F 9

AA38

PCIE_RX0P

Y37

PCIE_RX0N

Y35

PCIE_RX1P

W36

PCIE_RX1N

W38

PCIE_RX2P

D

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

B

BI

23

BI

23

BI

23

BI

23

BI

32

BI

32

BI

FOR PARK AND CAPILANO
THE PWRGOOD BALL MUST
BE CONNNECCTED TO GND

5456

BI

PEG_C_TXP7
PEG_C_TXN7

PEG_C_TXP6
PEG_C_TXN6

PEG_C_TXP5
PEG_C_TXN5

PEG_C_TXP4
PEG_C_TXN4

PEG_C_TXP3
PEG_C_TXN3

PEG_C_TXP2
PEG_C_TXN2

PEG_C_TXP1
PEG_C_TXN1

PEG_C_TXP0
PEG_C_TXN0

CLK_PEG
CLK_PEG#

R179

1K_5%_2

PEG_PLT_RST#

35

BI

354550

BI

21

8

V37

PCIE_RX2N

V35

PCIE_RX3P

U36

PCIE_RX3N

U38

PCIE_RX4P

T37

PCIE_RX4N

T35

PCIE_RX5P

R36

PCIE_RX5N

R38

PCIE_RX6P

P37

PCIE_RX6N

P35

PCIE_RX7P

N36

PCIE_RX7N

N38

PCIE_RX8P

M37

PCIE_RX8N

M35

PCIE_RX9P

L36

PCIE_RX9N

L38

PCIE_RX10P

K37

PCIE_RX10N

K35

PCIE_RX11P

J36

PCIE_RX11N

J38

PCIE_RX12P

H37

PCIE_RX12N

H35

PCIE_RX13P

G36

PCIE_RX13N

G38

PCIE_RX14P

F37

PCIE_RX14N

F35

PCIE_RX15P

E37

PCIE_RX15N

CLOCK

AB35

PCIE_REFCLKP

AA36

PCIE_REFCLKN

AH16

AA30

PERSTB

AMD_216_0834002_00_FCBGA_962P

DGPU_HOLD_RST#

21

R457

100K_5%_2

PLT_RST#

7 6

PCI EXPRESS INTERFACE

P3V3S_DGPU

5

+

1

2

-

3

U29

TC7SZ08FU

6 5

Y33

PCIE_TX0P

Y32

PCIE_TX0N

W33

PCIE_TX1P

W32

PCIE_TX1N

U33

PCIE_TX2P

U32

PCIE_TX2N

U30

PCIE_TX3P

U29

PCIE_TX3N

T33

PCIE_TX4P

T32

PCIE_TX4N

T30

PCIE_TX5P

T29

PCIE_TX5N

P33

PCIE_TX6P

P32

PCIE_TX6N

P30

PCIE_TX7P

P29

PCIE_TX7N

N33

21

PEG_RXP7

N32

PEG_RXN7

N30

PEG_RXP6

N29

PEG_RXN6

L33

PEG_RXP5

L32

PEG_RXN5

L30

PEG_RXP4

L29

PEG_RXN4

K33

PEG_RXP3

K32

PEG_RXN3

J33

PEG_RXP2

J32

PEG_RXN2

K30

PEG_RXP1

K29

PEG_RXN1

H33

PEG_RXP0

H32

PEG_RXN0

HEATHROW/CHELSEA
THAMES/WHISTLER/SEYMOUR

Y30
Y29

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RXTEST_PG

C550

0.1UF_16V_2

4

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

PEG_PLT_RST#

R236

1.69K_1%_2

R215
R214

54 56

BI

21

R215
OPEN
MOUNT

1.27K_1%_2_DY

21
21

1K_5%_2

54

IN

54

IN

54

IN

54

IN

54

IN

54

IN

54

IN

54

IN

54

IN

54

IN

54

IN

54

IN

54

IN

54

BI

54

BI

54

BI

54

BI

54

BI

54

BI

54

BI

54

BI

54

BI

54

BI

54

BI

54

BI

54

BI

54

BI

54

BI

54

BI

PVPCIE

PVPCIE

54

IN

54

IN

54

IN

R236
HEATHROW/CHELSEA
THAMES/WHISTLER/SEYMOUR

56 56
56
27

40
56

MOUNT

OPEN

GPU_THRM_DPLUS

IN

GPU_THRM_DMINUS

IN
IN

SMBus Address is 1001100Xb

5 4

4

CLOSE TO GPU

PEG_RXN0

PEG_RXN1

PEG_RXN2

PEG_RXN3

PEG_RXN4

PEG_RXN5

PEG_RXN6

PEG_RXN7

PEG_RXP0

PEG_RXP1

PEG_RXP2

PEG_RXP3

PEG_RXP4

PEG_RXP5

PEG_RXP6

PEG_RXP7

THRMTRIP#

BOM CHANGE TO MOUNT

C409
C422
C385
C369
C351
C330
C288
C290

C394
C411
C371
C357
C335
C317
C280
C310

C IS 0402

10K_5%_2_DY

SI 1123

2200pF_50V_2

SI 1108

C848

R709

21

0_5%_2_DY

SI2 0103

3 2 1

WHISTLER M2 PRO

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

0.1uF_16V_2

21

P3V3S_DGPU

C849

2 1

2 1

R954

21

WINB_W83L771AWG_TSSOP_8P

PN:6019B0582601

CHANGE by

0.1uF_16V_2

U43

1

VDD

2

D+

3

D­T_CRIT_A#

David Cheng

PEG_C_RXN0

PEG_C_RXN1

PEG_C_RXN2

PEG_C_RXN3

PEG_C_RXN4

PEG_C_RXN5

PEG_C_RXN6

PEG_C_RXN7

PEG_C_RXP0

PEG_C_RXP1

PEG_C_RXP2

PEG_C_RXP3

PEG_C_RXP4

PEG_C_RXP5

PEG_C_RXP6

PEG_C_RXP7

8

TI_THM_CLK

SCL

7

TI_THM_DAT

SDA

6

ALERT

54

GND

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

DATE

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

BI
BI

12-12-2011

23

56

INVENTEC

TITLE

SIZE

A3

LV1.1_Lauren

GPU-1

DOC.NUMBER

CODE

1310A24893-0 MTR

CS

SHEET

D

CC

B

AA

REV

of

AX1

6754

1

8 7

6 5

4

3 2 1

D

MOUNT FOR BACO MODE

P3V3A

R130

21

100K_5%_2

SSM3K7002FU

3

1

SSM3K7002FU

21

Q20

G

R132

DS

2

MOUNT
OPEN

P3V3A

C651

2 1

SI 1129

Q56

D

NMOS_4D1S

AO6402AL

100K_5%_2

P1V8S_DGPU

4

S

36

G

C500

2 1

0.1uF_25V_2_DY

R518

(1.3A)

21

Q59

1

G

SSM3K7002FU

SI 1130

0_5%_2

SSM3K7002FU

3

DS

2

1

R500

P15V0A

21

Q58

G

55

21

R494

560K_1%_2

3

DS

2

(7A)

IN

C119

0_5%_2

SI 1011

2 1

0.1uF_25V_2

PX_MODE

R135

18

P1V8S

1
2
5

68PF_50V_2

32

18

3655

DGPU_PWR_EN

IN

B

21

R131

330K_1%_2

3

Q19

DS

1

G

D

2

P1V5S_DGPU P1V5 P1V5

OPEN

0_5%_2

R132

21

1

2
3
4 5

W/O BACOBACO

S

G

NMOS_4D3S

TPCA8057_H

Q21

8

D

7
6

C593

C591

2 1

C599

C597

2 1

2 1

2 1

C604

C602

2 1

2 1

2.2UF_6.3V_2

CC

OPEN
MOUNTR135

C120

0.01UF_50V_2

2 1

2.2UF_6.3V_2

2.2UF_6.3V_2

2.2UF_6.3V_2

2.2UF_6.3V_2

2.2UF_6.3V_2

B

P3V3S

P15V0A

DGPU_PWR_EN

18

32

IN

3655

56

PX_EN=0, FOR NORMAL MODE
PX_EN=1, FOR BACO MODE

PX_EN

IN

1

Q26

G

21

R120

10K_5%_2

PX_EN#

3

DS

SSM3K7002FU

2

1

2

R129

P3V3S

1000PF_50V_2

5

U7

+

-

TC7SET08FU

3

C95

21

PX_MODE

4

OUT

PX_MODE=0, FOR BACO MODE
PX_MODE=1, FOR NORMAL MODE

OPEN

0_5%_2

21

R129 OPEN FOR BACO MODE

18

55

AA

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6755

8

GPU_THM_CLK

56

BI

GPU_THM_DAT

56

E

D

BI

54

54

TI_THM_CLK

BI

TI_THM_DAT

BI

DGPU_PWR_EN#

3536

IN

IF GPIO_22_EN = 0 , THEN GPIO[13:11] DEFINES THE PRIMARY MEMORY APERTURE SIZE.

00

1

1

GPU_GPIO0

56

IN

GPU_GPIO1

56

IN

GPU_GPIO9

56

IN

GPU_GPIO11

56

C

THRMTRIP#

274054

B

OUT

IN

GPU_GPIO12

56

IN

GPU_GPIO13

56

IN

GPU_GPIO23

56

IN

AUD_0

56

OUT

AUD_1

56

OUT

GPU_GPIO2

56

IN

GPU_LCM_BLEN

4456

IN

CTF

56

IN

POW_SW0

15

56

OUT

POW_SW1

15

56

IN

POW_SW2

15

56

IN

SI2 1227

21

R855

0_5%_2_DY

Q35

3

10K_5%_2_DY

DS

SSM3K7002FU_DY

1

G

2

21

R856

C300

2 1

0.1UF_10V_2_DY

A

8

7 6 5 4 3 2 1

P3V3S_DGPU

21

SI2 1227

10K_5%_2_DY

R951

GENLK_VSYNC

OUT

P3V3S_DGPU

10K_5%_2

GPU_THROT#

P3V3S_DGPU

R184

10K_5%_2

CLOSE TO GPU

GPU_VREFG

C186

0.1UF_16V_2

P3V3S_DGPU

10K_5%_2_DY

54
54

I=8MA

TSVDD

21

C190

2 1

10UF_6.3V_3

P1V8S_DGPU

21

21

R514

R507

10K_5%_2_DY

10K_5%_2_DY

56
56

SYSTEM BORAD PULL UP

44
44

R172

21

56
56
56

16

4456

56

56

21

56
56

15

56

15

56

56

15

56

56

R156

10K_5%_2_DY

R169

10K_5%_2_DY

GPU_THRM_DPLUS

OUT

GPU_THRM_DMINUS

OUT

C197

C198

2 1

2 1

1UF_6.3V_2

21

R510

OUT
OUT

OUT
OUT

OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

IN
IN

55

21

21

GPIO27_TMS

0.1UF_16V_2

21

R497

10K_5%_2

GPU_LCM_CLK
GPU_LCM_DAT

VDDCI_SW
GPU_LCM_BLEN

GPU_GPIO9

GPU_GPIO11
GPU_GPIO12
GPU_GPIO13

POW_SW0
POW_SW2

GPU_GPIO23

VR_TT#

OUT

I572

10K_5%_2_DY

MEM_ID0
MEM_ID1
MEM_ID2
MEM_ID3

GPU_THM_CLK
GPU_THM_DAT

GPU_GPIO0
GPU_GPIO1
GPU_GPIO2

SI 1115
SI2 1227

SI 1115

CTF
POW_SW1

TP34

1

TP24

TP24

1

TP33

SI 1115

SI 1115

PX_EN

5.1K_1%_2

2 1

R162

I574

GPIO24_TRSTB

1

TP13

TP60

1

TP15

TP80

TP79

TP24

TP24

TP24

TP24

MEM_ID3

0
0
0
0

0

R707

0_5%_2

R708

0_5%_2

SI 1201

1K_5%_2

GPIO_11GPIO_12GPIO_13

DIODE-BAT54-TAP-PHP_DY

R857

10K_5%_2_DY

21

R858

20K_5%_2_DY

MEM_ID2 MEM_ID1

0
0
0
0

1

21
21

P3V3S

21

R684

C816

1uF_10V_3

2 1

R679

21

MEMORY APERTURE SIZE
2GB / 1GB1

0

RESERVED

R182
R171
R185

SI 1014

R177
R165
R159
R145
R552
R547

R160
R170
R154
R515
R107
R950

2

D100

NC

1 3

21

1 1

1

0

R695

R699

2

10K_5%_2

SSM3K7002FU

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

3K_5%_2

21

3K_5%_2

21

3K_5%_2

PEG_PLT_RST#

IN

CTF

IN

MEM_ID0

10
0
0

00

10K_5%_2

21

10K_5%_2

21

2

2

P3V3S_DGPU

SD

Q84

G

AM2321P

1

1

(DEFAULT)

P3V3S_DGPU

54

56

VENDOR
HYNIX (1GB)

(H5GQ1H24BFR-T2C)

SAMSUNG(1GB)

(K4G10325FG-HC04)

HYNIX (2GB)

(H5GQ2H24MFR-T2C)

SAMSUNG(2GB)(DEFAULT)

(K4G20325FC-HC04)

ALPIDA (2GB)

R710

21

R696

21

1

Q88

G

SSM3K7002FU

3

THM_CLK

DS

3

THM_DAT

D S

Q89

SSM3K7002FU

G

1

3

21

R675

200_5%_2

3

Q82

DS

G

2

P1V8S_DGPU

P3V3S_DGPU

P1V8S_DGPU

P3V3S_DGPU P3V3S

0_5%_2

0_5%_2_DY

40 49

51

BI

40 49

51

BI

40

OUT

GPUTHERM_INT#

OUT

VR_TT#: REGULTOR HOT INPUT OPTION - NOT CURRENTLY QUALIFIED

GPIO_29, GPIO30 ARE NC ON THAMES/WHISTLER/SEYMOUR

499_1%_2

R164

2 1
21

R178

249_1%_2

2 1

R190

21

1K_5%_2

21

R191

P3V3S_DGPU

DISABLE MLPS

R850

21

10K_5%_2_DY

R851

21

10K_5%_2

ENABLE MLPS

L12

BLM18EG601SN1D

THAMES/WHISTLER/SEYMOUR ONLY
DO NOT INSTALL FOR HEATHROW/CHELSEA

NC_TSVSSQ SHOULD BE TIED TO GND ON THAMES/WHISTLER/SEYMOUR

PS_0 SHOULD BE TIED TO GND ON THAMES/WHISTLER/SEYMOUR

7 6 5 4 3

U34

PART 2 0F 9

MUTI GFX

AD29

GENLK_CLK

AC29

GENLK_VSYNC

AJ21

SWAPLOCKA

AK21

SWAPLOCKB

AR8

DVPCNTL_MVP_0

AU8

DVPCNTL_MVP_1

AP8

DVPCNTL_0

AW8

DVPCNTL_1

AR3

DVPCNTL_2

AR1

DVPCLK

AU1

DVPDATA_0

AU3

DVPDATA_1

AW3

DVPDATA_2

AP6

DVPDATA_3

AW5

DVPDATA_4

AU5

DVPDATA_5

AR6

DVPDATA_6

AW6

DVPDATA_7

AU6

DVPDATA_8

AT7

DVPDATA_9

AV7

DVPDATA_10

AN7

DVPDATA_11

AV9

DVPDATA_12

AT9

DVPDATA_13

AR10

DVPDATA_14

AW10

DVPDATA_15

AU10

DVPDATA_16

AP10

DVPDATA_17

AV11

DVPDATA_18

AT11

DVPDATA_19

AR12

DVPDATA_20

AW12

DVPDATA_21

AU12

DVPDATA_22

AP12

DVPDATA_23

AJ23

SMBCLK

AH23

SMBDATA

AK26

SCL

AJ26

SDA

GENERAL PURPOSE I/O

AH20

GPIO_0

AH18

GPIO_1

AN16

GPIO_2

AH17

GPIO_5_AC_BATT

AJ17

GPIO_6

AK17

GPIO_7_BLON

AJ13

GPIO_8_ROMSO

AH15

GPIO_9_ROMSI

AJ16

GPIO_10_ROMSCK

AK16

GPIO_11

AL16

GPIO_12

AM16

GPIO_13

AM14

GPIO_14_HPD2

AM13

GPIO_15_PWRCNTL_0

AK14

GPIO_16

AG30

GPIO_17_THERMAL_INT

AN14

GPIO_18_HPD3

AM17

GPIO_19_CTF

AL13

GPIO_20_PWRCNTL_1

AJ14

GPIO_21

AK13

GPIO_22_ROMCSB

AN13

CLKREQB

AG32

GPIO_29

AG33

GPIO_30

AJ19

GENERICA

AK19

GENERICB

AJ20

GENERICC

AK20

GENERICD

AJ24

GENERICE_HPD4

AH26

GENERICF_HPD5

AH24

GENERICG_HPD6

AC30

CEC_1

AK24

HPD1

AH13

VREFG

AL21 AD33

PX_EN

DEBUG

AD28

TESTEN

AM23

JTAG_TRSTB

AN23

JTAG_TDI

TP24

AK23

1

JTAG_TCK

AL24

JTAG_TMS

AM24

JTAG_TDO

1

1

THERMAL

AF29

DPLUS

AG29

DMINUS

AK32

GPIO_28_FDO

AL31

TS_A

AJ32

TSVDD

AJ33

TSVSS

AMD_216_0834002_00_FCBGA_962P

DPA

DPB

DPC

DPD

SMBus

I2C

DAC1

MLPS

BACO

DDC/AUX

AU24

TXCAP_DPA3P

AV23

TXCAM_DPA3N

AT25

TX0P_DPA2P

AR24

TX0M_DPA2N

AU26

TX1P_DPA1P

AV25

TX1M_DPA1N

AT27

TX2P_DPA0P

AR26

TX2M_DPA0N

AR30

TXCBP_DPB3P

AT29

TXCBM_DPB3N

AV31

TX3P_DPB2P

AU30

TX3M_DPB2N

AR32

TX4P_DPB1P

AT31

TX4M_DPB1N

AT33

TX5P_DPB0P

AU32

TX5M_DPB0N

AU14

TXCCP_DPC3P

AV13

TXCCM_DPC3N

AT15

TX0P_DPC2P

AR14

TX0M_DPC2N

AU16

TX1P_DPC1P

AV15

TX1M_DPC1N

AT17

TX2P_DPC0P

AR16

TX2M_DPC0N

AU20

TXCDP_DPD3P

AT19

TXCDM_DPD3N

AT21

TX3P_DPD2P

AR20

TX3M_DPD2N

AU22

TX4P_DPD1P

AV21

TX4M_DPD1N

AT23

TX5P_DPD0P

AR22

TX5M_DPD0N

AD39

GPU_R

R

AD37

AVSSN#1

AE36

GPU_G

G

AD35

AVSSN#2

AF37

GPU_B

B

AE38

AVSSN#3

AC36

AUD_1

HSYNC

AC38

AUD_0

VSYNC

R209

AB34

RSET

499_1%_2

AD34

AVDD

AE34

AVSSQ

AC33

VDD1DI

AC34

VSS1DI

V13

NC#1

U13

NC#2

AC31

NC#3

AD30

NC#4

AC32

NC#5

AD32

NC#6

AF32

NC#7

AA29

NC#8

AG21

NC#9

AF33

NC_TSVSSQ

DDC1CLK

DDC1DATA

DDC2CLK

DDC2DATA

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX5P

DDCDATA_AUX5N

DDCCLK_AUX6P

DDCDATA_AUX6N

DDCVGACLK

DDCVGADATA

R238

NC_TSVSSQ SHOULD BE TIED TO GND ON THAMES/WHISTLER/SEYMOUR

AM34

PS_0

AD31

PS_1

TP25

1

AG31

PS_2

TP24

TP39

1

PS_3

TP24

AM26
AN26

AM27

AUX1P

AL27

AUX1N

AM19
AL19

AN20

AUX2P

AM20

AUX2N

AL30
AM30

AL29
AM29

AN21
AM21

AK30
AK29

GPU_CLK

1

AJ30

1

AJ31

GPU_DATA

TP24

1

TP24

1

TP24

1

TP24

1

TP24

1

21

1

TP24

TP95
TP96

TP24

TP90

TP91

TP92

TP93

OUT

TP94

OUT

R237

21

0_5%_2_DY

HEATHROW/CHELSEA
THAMES/WHISTLER/SEYMOUR

2

0_5%_2_DY

R290
R291
R292
R293

SI 1111

TP24

1

TP14

TP24

1

TP16

CHANGE by

56
56

I=125MA

P1V8S_DGPU

OPEN
MOUNT

21

0_5%_1_DY

21

0_5%_1_DY

21

0_5%_1_DY

21

0_5%_1_DY

FAN CONN

40

IN

40

IN

100PF_50V_2_DY

PS_0

PS_1

PS_2

PS_3

VDDC_CT

56

IN

PS_0

56

OUT

VDDC_CT

56

IN

PS_1

OUT

THERMAL FAN CNTR

P3V3S P5V0S

4.7K_5%_2

R473

2 1

TACH1
GPUFAN2_ON

C579

ACES_50273_0047N_001_4P

PN: 6012A0081607

2 1

56

IN

PS0_0 Bits[5:1]: 11|001

56

IN

PS0_1 Bits[5:1]: 11|000

56

IN

PS0_2 Bits[5:1]: 00|000

56

IN

PS0_3 Bits[5:1]: 11|000

R800

PS_2

2 1

8.45K_1%_2

56

OUT

C501

R801

2K_1%_2

2 1

2 1

CSC0402_DY

82n

R802

PS_3

2 1

0_5%_2_DY

5656

OUT

SI 1207

C503

R803

2 1

2 1

4.75K_1%_2
CSC0402_DY

NC

DATE

12-12-2011David Cheng

2 1

CN16

1

1

2

2

G1

3

3

G2

4

GG4

MULTI LEVEL PIN STRAP (MLPS)

FOR R_PU_X AND R_PD_X AND C_X, SELECTION
REFER TO AN_MGEN_X1
PARTS FOR MLPS SHOULD BE PLACED CLOSE TO ASIC
THE TOTAL RESISTANCE OF TRACE SHOULD BE LESS THAN 3 OHM

R804

0_5%_2_DY

2 1

C505

R805

2 1

2 1

4.75K_1%_2

0.68uF_10V_2

680n

R806

2 1

0_5%_2_DY

C512

R807

2 1

2 1

4.75K_1%_2
CSC0402_DY

NC

INVENTEC

TITLE

LV1.1_Lauren

GPU-2

CODE

SIZE

CS

C

C581

C580

2 1

2 1

4.7UF_6.3V_3

DOC.NUMBER

1310A24893-0 MTR

SHEET

FF

E

0.01UF_50V_2

D

C

B

A

REV

AX1

of

6756

8 7

6 5

4

3 2 1

U34

AG12

AH12

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13

H11
G10

K10

N12

M12
M27

J13

G8
K9

G9
A8
C8
E8
A6
C6
E6
A5

L18
L20

L27

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

MVREFDA
MVREFSA

NC_MEM_CALRN0
NC_MEM_CALRN1
NC_MEM_CALRN2

NC_MEM_CALRP1
MEM_CALRP0
MEM_CALRP2

21
21
21

21
21
21

DQA0(0)
DQA0(1)
DQA0(2)
DQA0(3)
DQA0(4)
DQA0(5)
DQA0(6)
DQA0(7)
DQA0(8)
DQA0(9)
DQA0(10)
DQA0(11)
DQA0(12)
DQA0(13)
DQA0(14)
DQA0(15)
DQA0(16)
DQA0(17)
DQA0(18)
DQA0(19)
DQA0(20)
DQA0(21)
DQA0(22)
DQA0(23)
DQA0(24)
DQA0(25)
DQA0(26)
DQA0(27)
DQA0(28)
DQA0(29)
DQA0(30)
DQA0(31)
DQA1(0)
DQA1(1)
DQA1(2)
DQA1(3)
DQA1(4)
DQA1(5)
DQA1(6)
DQA1(7)
DQA1(8)
DQA1(9)
DQA1(10)
DQA1(11)
DQA1(12)
DQA1(13)
DQA1(14)
DQA1(15)
DQA1(16)
DQA1(17)
DQA1(18)
DQA1(19)
DQA1(20)
DQA1(21)
DQA1(22)
DQA1(23)
DQA1(24)
DQA1(25)
DQA1(26)
DQA1(27)
DQA1(28)
DQA1(29)
DQA1(30)
DQA1(31)

RSC_0402_DY
RSC_0402_DY
RSC_0402_DY

RSC_0402_DY
120_1%_2
120_1%_2

62

BI

62

BI

62

BI

62

BI

62

BI

62

R258
R249
R146

R244
R254
R147

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

D

CHANNEL A

DDR3/GDDR3MEMORY STUFF OPTION

MVDDQ
RA
RB

R247

40.2_1%_2

R248

100_1%_2

R259

40.2_1%_2

P1V5S_DGPU

21

21

C321

2 1

P1V5S_DGPU

21

B

RA

RB

RA

1.5V

40.2R
100R

1UF_6.3V_2

GDDR3GDDR5

1.8V/1.5V

40.2R
100R

MVREFDA_GPU
MVREFSA_GPU

DDR3

1.5V

40.2R
100R

P1V5S_DGPU

21

RB

R260

100_1%_2

C355

2 1

1UF_6.3V_2

FOR M97,BROADWAY,MADISO AND PARK ONLY

IF R258,R249,R146,R244 SHOULD BE MOUNT,

P/N 6013A0087806 (243OHM,1%)

AMD_216_0834002_00_FCBGA_962P

PART 3 0F 9

GDDR5/DDR3

MEMORY INTERFACE A

MAA0_0/MAA_0

MAA0_1/MAA_1

MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8

MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12

MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
MAA1_7/MAA_BA1

WCKA0_0/DQMA_0

WCKA0B_0/DQMA_1

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

EDCA0_0/QSA_0
EDCA0_1/QSA_1
EDCA0_2/QSA_2
EDCA0_3/QSA_3
EDCA1_0/QSA_4
EDCA1_1/QSA_5
EDCA1_2/QSA_6
EDCA1_3/QSA_7

DDBIA0_0/QSA_0B
DDBIA0_1/QSA_1B
DDBIA0_2/QSA_2B
DDBIA0_3/QSA_3B
DDBIA1_0/QSA_4B
DDBIA1_1/QSA_5B
DDBIA1_2/QSA_6B
DDBIA1_3/QSA_7B

ADBIA0/ODTA0

ADBIA1/ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B
RASA1B

CASA0B
CASA1B

CSA0B_0

CSA0B_1

CSA1B_0

CSA1B_1

CKEA0
CKEA1

WEA0B
WEA1B

MAA0_8/MAA_13
MAA1_8/MAA_14
MAA0_9/MAA_15

MAA1_9/RSVD

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

A32
C32
D23
E22
C14
A14
E10
D9

C34
D29
D25
E20
E16
E12
J10
D7

A34
E30
E26
C20
C16
C12
J11
F8

J21
G19

H27
G27

J14
H14

K23
K19

K20
K17

K24
K27

M13
K16

K21
J20

K26
L15

H23
J19
M21
M20

MAA0(0)
MAA0(1)
MAA0(2)
MAA0(3)
MAA0(4)
MAA0(5)
MAA0(6)
MAA0(7)
MAA1(0)
MAA1(1)
MAA1(2)
MAA1(3)
MAA1(4)
MAA1(5)
MAA1(6)
MAA1(7)

WCKA0_0
WCKA0_0#
WCKA0_1
WCKA0_1#
WCKA1_0
WCKA1_0#
WCKA1_1
WCKA1_1#

EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3
EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3

DBIA0_0
DBIA0_1
DBIA0_2
DBIA0_3
DBIA1_0
DBIA1_1
DBIA1_2
DBIA1_3

ADBIA0#
ADBIA1#

CLKA0
CLKA0#

CLKA1
CLKA1#

RASA0#
RASA1#

CASA0#
CASA1#

CSA0#

CSA1#

CKEA0
CKEA1

WEA0#
WEA1#

MAA0(8)
MAA1(8)

TP24

1

TP45

TP24

1

TP8

M96/92 ONLY

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT

OUT
OUT

OUT
OUT

62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62

62
62
62
62
62
62
62
62

62
62
62
62
62
62
62
62

62
62
62
62
62
62
62
62

62
62

62
62

62
62

62
62

62
62

62

62

62
62

62
62

62

BI

62

BI

D

CC

B

AA

INVENTEC

TITLE

LV1.1_Lauren

GPU-3

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6757

8 7

6 5

4

3 2 1

U34

AM1

AA12

AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6

AK3
AF8
AF9
AG8
AG7
AK9

AM8
AM7
AK1

AM6
AN4

AP3
AP1
AP5

C5

DQB0_0

C3

DQB0_1

E3

DQB0_2

E1

DQB0_3

F1

DQB0_4

F3

DQB0_5

F5

DQB0_6

G4

DQB0_7

H5

DQB0_8

H6

DQB0_9

J4

DQB0_10

K6

DQB0_11

K5

DQB0_12

L4

DQB0_13

M6

DQB0_14

M1

DQB0_15

M3

DQB0_16

M5

DQB0_17

N4

DQB0_18

P6

DQB0_19

P5

DQB0_20

R4

DQB0_21

T6

DQB0_22

T1

DQB0_23

U4

DQB0_24

V6

DQB0_25

V1

DQB0_26

V3

DQB0_27

Y6

DQB0_28

Y1

DQB0_29

Y3

DQB0_30

Y5

DQB0_31
DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13

AJ4

DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20

AL7

DQB1_21
DQB1_22
DQB1_23
DQB1_24

AL4

DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31

Y12

MVREFDB
MVREFSB

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

D

CHANNEL B

DDR3/GDDR3MEMORY STUFF OPTION

B

MVDDQ

RB

GDDR5

GDDR3

1.8V/1.5V

1.5V

40.2RRA

40.2R

100R 100R

100R

DDR3

1.5V

40.2R

R221

40.2_1%_2

R210

100_1%_2

P1V5S_DGPU

21

21

C273

2 1

1UF_6.3V_2

MVREFDB_GPU
MVREFSB_GPU

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

DQB0(0)
DQB0(1)
DQB0(2)
DQB0(3)
DQB0(4)
DQB0(5)
DQB0(6)
DQB0(7)
DQB0(8)
DQB0(9)
DQB0(10)
DQB0(11)
DQB0(12)
DQB0(13)
DQB0(14)
DQB0(15)
DQB0(16)
DQB0(17)
DQB0(18)
DQB0(19)
DQB0(20)
DQB0(21)
DQB0(22)
DQB0(23)
DQB0(24)
DQB0(25)
DQB0(26)
DQB0(27)
DQB0(28)
DQB0(29)
DQB0(30)
DQB0(31)
DQB1(0)
DQB1(1)
DQB1(2)
DQB1(3)
DQB1(4)
DQB1(5)
DQB1(6)
DQB1(7)
DQB1(8)
DQB1(9)
DQB1(10)
DQB1(11)
DQB1(12)
DQB1(13)
DQB1(14)
DQB1(15)
DQB1(16)
DQB1(17)
DQB1(18)
DQB1(19)
DQB1(20)
DQB1(21)
DQB1(22)
DQB1(23)
DQB1(24)
DQB1(25)
DQB1(26)
DQB1(27)
DQB1(28)
DQB1(29)
DQB1(30)
DQB1(31)

P1V5S_DGPU

21

R194

40.2_1%_2

21

R198

100_1%_2

8

7 6

C233

2 1

1UF_6.3V_2

5 4

AMD_216_0834002_00_FCBGA_962P

PART 4 0F 9

GDDR5/DDR3

MEMORY INTERFACE B

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8

MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12

MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

WCKB0_0/DQMB_0

WCKB0B_0/DQMB_1

WCKB0_1/DQMB_2

WCKB0B_1/DQMB_3

WCKB1_0/DQMB_4

WCKB1B_0/DQMB_5

WCKB1_1/DQMB_6

WCKB1B_1/DQMB_7

EDCB0_0/QSB_0

EDCB0_1/QSB_1

EDCB0_2/QSB_2
EDCB0_3/QSB_3
EDCB1_0/QSB_4
EDCB1_1/QSB_5
EDCB1_2/QSB_6
EDCB1_3/QSB_7

DDBIB0_0/QSB_0B
DDBIB0_1/QSB_1B
DDBIB0_2/QSB_2B
DDBIB0_3/QSB_3B
DDBIB1_0/QSB_4B
DDBIB1_1/QSB_5B
DDBIB1_2/QSB_6B
DDBIB1_3/QSB_7B

ADBIB0/ODTB0

ADBIB1/ODTB1

CLKB0

CLKB0B

CLKB1

CLKB1B

RASB0B
RASB1B

CASB0B
CASB1B

CSB0B_0
CSB0B_1

CSB1B_0
CSB1B_1

CKEB0
CKEB1

WEB0B
WEB1B

MAB0_8/MAB_13
MAB1_8/MAB_14
MAB0_9/MAB_15

MAB1_9/RSVD

DRAM_RST

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

H3
H1
T3
T5
AE4
AF5
AK6
AK5

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

T7
W7

L9
L8

AD8
AD7

T10
Y10

W10
AA10

P10
L10

AD10
AC10

U10
AA11

N10
AB11

T8
W8
U12
V12

AH11

MAB0(0)
MAB0(1)
MAB0(2)
MAB0(3)
MAB0(4)
MAB0(5)
MAB0(6)
MAB0(7)
MAB1(0)
MAB1(1)
MAB1(2)
MAB1(3)
MAB1(4)
MAB1(5)
MAB1(6)
MAB1(7)

WCKB0_0
WCKB0_0#
WCKB0_1
WCKB0_1#
WCKB1_0
WCKB1_0#
WCKB1_1
WCKB1_1#

EDCB0_0
EDCB0_1
EDCB0_2
EDCB0_3
EDCB1_0
EDCB1_1
EDCB1_2
EDCB1_3

DBIB0_0
DBIB0_1
DBIB0_2
DBIB0_3
DBIB1_0
DBIB1_1
DBIB1_2
DBIB1_3

ADBIB0#
ADBIB1#

CLKB0
CLKB0#

CLKB1
CLKB1#

RASB0#
RASB1#

CASB0#
CASB1#

CSB0#

CSB1#

CKEB0
CKEB1

WEB0#
WEB1#

MAB0(8)
MAB1(8)

21

R513

CHANGE by

R509

10_5%_2

4.99K_1%_2

TP24

1

TP42

TP24

1

TP41

M96/92 ONLY

21

C639

2 1

David Cheng

R496

51_1%_2

120PF_50V_2

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT

OUT
OUT

OUT
OUT

BI
BI

63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63

63
63
63
63
63
63
63
63

63
63
63
63
63
63
63
63

63
63
63
63
63
63
63
63

63
63

63
63

63
63

63
63

63
63

63

63

63
63

63
63

21

VM_RST#

D

CC

B

63
63

AA

62 63

IN

INVENTEC

TITLE

LV1.1_Lauren

GPU-4

DATE

12-12-2011

23

SIZE

DOC.NUMBER

CODE

1310A24893-0 MTR

CS

A3

SHEET

of

1

REV

AX1

6758

8

7 6 5 4 3 2 1

FF

HEATHROW/CHELSEA

THAMES/WHISTLER/SEYMOUR

0.935V

PCIE_VDDC
VDDCI

0.95V

U34

P1V5S_DGPU

+

C598

220UF_2V

E

2 1

D

P1V8S_DGPU

C

P1V5S_DGPU

P1V8S_DGPU

FBM_11_160808_121T

P3V3S_DGPU

I=3.4A

FOR DDR3,MVDDQ=1.5V

C337

C217

2 1

22UF_6.3V_5

C311

2 1

2.2UF_6.3V_2

C340

2 1

1UF_6.3V_2

C381

2 1

0.1UF_16V_2

I=250MA

C130

2 1

I=60MA

C184

2 1

L23

BLM18PG600SN1D

10UF_6.3V_3

10UF_6.3V_3

C347

10UF_6.3V_3

C391

2.2UF_6.3V_2

C272

1UF_6.3V_2

C201

0.1UF_16V_2

C189

2 1

C210

I=300MA

21

2 1

10UF_6.3V_3

C214

2 1

2 1

2.2UF_6.3V_2

2.2UF_6.3V_2

C366

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

C721

2 1

2 1

0.1UF_16V_2

0.1UF_16V_2

VDDC_CT

C200

2 1

1UF_6.3V_2

0.1UF_16V_2

M96 FOR +V1.8S_VGA

2 1

1UF_6.3V_2

VDDR4

C615

C616

2 1

2 1

1UF_6.3V_2

0.1UF_16V_2

2 1

C286

2 1

C324

2 1

C379

2 1

L7

21

AC7

AD11

AF7

AG10

AJ7

AK8

AL9
G11
G14
G17
G20
G23
G26
G29
H10

J7
J9

K11

K13

K8
L12
L16
L21
L23
L26

L7

M11

N11

P7

R11
U11

U7

Y11

Y7

AF26
AF27
AG26
AG27

AF23
AF24
AG23
AG24

AD12
AF11
AF12
AF13

AF15

AG11

AG13
AG15

MEM I/O

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34

LEVEL

TRANSLATION

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

I/O

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

DVP

VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#4

VDDR4#5
VDDR4#6
VDDR4#7
VDDR4#8

PART 5 0F 9

NC_PCIE_VDDR#1
NC_PCIE_VDDR#2
NC_PCIE_VDDR#3
NC_PCIE_VDDR#4
NC_PCIE_VDDR#5
NC_PCIE_VDDR#6

NC_BIF_VDDC#1
NC_BIF_VDDC#2

PCIE

PCIE_VDDC#1

PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8

PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

BACO

CORE

B

VOLTAGE

SI 1115

SI 1115

SENESE

AF28

FB_VDDC

AG28

FB_VDDCI

AH29

FB_GND

AMD_216_0834002_00_FCBGA_962P

ISOLATED

CORE I/O

PCIE_PVDD

BIF_VDDC#1
BIF_VDDC#2

VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26

VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
VDDCI#9
VDDCI#10

VDDCI#11

VDDCI#12
VDDCI#13
VDDCI#14
VDDCI#15
VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20

VDDCI#21

VDDCI#22

1V
1V

21

SI 1013

R860

0_5%_2_DY

AA31
AA32
AA33
AA34
W30
Y31
V28
W29
AB37

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

N27
T27

AA15

VDDC#1

AA17

VDDC#2

AA20

VDDC#3

AA22

VDDC#4

AA24

VDDC#5

AA27

VDDC#6

AB16

VDDC#7

AB18

VDDC#8

AB21

VDDC#9

AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18

AH22
AH27
AH28
M26
N24
R18
R21
R23
R26
T17
T20
T22
T24
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

1.8V 440MA PCIE_VDDR

C232

0.1UF_16V_2

R208

0_5%_2_DY

SI 1011

C259

2 1

2 1

2 1

10UF_6.3V_3

1UF_6.3V_2

1UF_6.3V_2

R231

L14

R208

OPEN

OPEN
OPEN

MOUNT

21

C258

21

R231

0_5%_2_DY

C229

2 1

0.1UF_16V_2

HEATHROW/CHELSEA
THAMES/WHISTLER/SEYMOUR

2 1

PVPCIE

I=1.2A

R861

21

0_5%_2

SI 1014

R862

21

0_5%_2_DY

C247

C261

C207

C213

C242

C209

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

C227

C226

2 1

2 1

1UF_6.3V_2

1UF_6.3V_22.2UF_6.3V_2

C243

C222

2 1

2 1

2.2UF_6.3V_2

C188

C315

2 1

2 1

10UF_6.3V_3

10UF_6.3V_3

C223

C278

2 1

2 1

2 1

2 1

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

C221

C208

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

C277

C225

2 1

2 1

2.2UF_6.3V_2

2.2UF_6.3V_2

C257

C180

2 1

2 1

10UF_6.3V_3

10UF_6.3V_3

VDDCI AND VDDC SHOULD HAVE REGULATORS WITH A MERGE OPTION ON PVB

PEAK=4A VDDCI

C293

C274

2 1

2.2UF_6.3V_2

C297

C294

2 1

1UF_6.3V_2

C295

C296

2 1

2 1

2 1

2 1

2.2UF_6.3V_2

2.2UF_6.3V_2

C239

C206

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

BLM18PG121SN1

C264

C282

C240

1UF_6.3V_2

C244

1UF_6.3V_2

C245

2.2UF_6.3V_2

C216

10UF_6.3V_3

C298

2.2UF_6.3V_2

C211

1UF_6.3V_2

2 1

2 1

2 1

2 1

2 1

2 1

2 1

L14

SI 1011

PVPCIE

2.2uF_6.3V_2

(27.2A)

1UF_6.3V_2

1UF_6.3V_2

2.2UF_6.3V_2

22UF_6.3V_5

2.2UF_6.3V_2

22UF_6.3V_5

P1V8S_DGPU

21

C299

2 1

1UF_6.3V_2

C246

2 1

1UF_6.3V_2

C279

2 1

1UF_6.3V_2

C241

2 1

2.2UF_6.3V_2

C285

2 1

22UF_6.3V_5

C291

2 1

2.2UF_6.3V_2

C284

2 1

22UF_6.3V_5

C370

2 1

1UF_6.3V_2

PVCORE_DGPU

PVDDCI

I=3.6A~6A

C289

2 1

I=33A

E

PVPCIE

I=2.5A

C281

C307

2 1

2 1

1UF_6.3V_2

10UF_6.3V_3

2.2uF_6.3V_2

D

C

B

A

INVENTEC

TITLE

LV1.1_Lauren

GPU-5

DOC.NUMBER

CODE

SIZE

1310A24893-0 MTR

CS

CHANGE by

8

7 6 5 4 3

David Cheng 12-12-2011

DATE

2 1

C

SHEET

of

59 67

A

REV

AX1

8 7

6 5

4

3 2 1

D

D

CC

AW39

AW1

A3

GND#83

GND#82

GND#80

GND#79

GND#78

GND#77

GND#76

GND#75

GND#84

GND#81

GND#90

GND#89

GND#88

GND#87

GND#86

GND#85

GND#91

GND#98

GND#97

GND#96

GND#95

GND#94

GND#93

GND#92

AD22

AD20

AD17

AD15

AC6

AC28

GND#99

GND#105

GND#104

GND#103

GND#102

GND#100

GND#101

AF16

AF10

AE6F7AE2

AD9

AD27

AD24

GND#110

GND#109

GND#108

GND#107

GND#106

GND#111

AG22

AG20

AG2

AG17

AF21

AF18

GND#117

GND#116

GND#115

GND#114

GND#113

GND#112

AJ2

AJ11

AJ10

AH21

AG9F9AG6

GND#124

GND#123

GND#122

GND#120

GND#119

GND#118

GND#121

AL14

AL11G2AK7

AK31

AK11

AJ6

AJ28

GND#130

GND#129

GND#128

GND#127

GND#126

GND#125

AL26

AL23

AL20

AL2

AL17

GND#135

GND#134

GND#133

GND#132

GND#131

AM9

AM31

AM11G6AL8

AL6

AL32

GND#140

GND#139

GND#138

GND#137

GND#136

GND#141

AP11

AN8

AN6

AN30

AN2

AN11

GND#149

GND#148

GND#147

GND#146

GND#145

GND#144

GND#143

GND#142

B19

B17

B15

B13

B11

AR5

AP9H9AP7

GND#155

GND#154

GND#153

GND#152

GND#150

GND#151

B31

B29

B27J2B25

B23

B21

GND#160

GND#159

GND#158

GND#157

GND#156

GND#164

GND#163

GND#162

GND#161

F13

F11

E5

E35

C39C1B9B7B33

GND#170

GND#169

GND#168

GND#167

GND#166

GND#165

GND#171

AC26

AC23

AC21

AC2

AC18

AC16

AC13

AC11

AB27

AB24

AB22

AB20

AB17

AB15

AB12

AA6

AA28

AA26

AA23

AA21

AA2

AA18

AA16

A37

A39

VSS_MECH#3

VSS_MECH#2

VSS_MECH#1

GND

PART 6 0F 9

GND#74

GND#73

GND#72

GND#71

GND#70

GND#69

GND#68

GND#67

GND#66

GND#65

GND#64

GND#63

GND#62

GND#61

GND#60

GND#59

GND#58

GND#57

GND#56

GND#55

GND#54

GND#53

GND#52

GND#51

GND#50

GND#49

GND#48

GND#47

GND#46

GND#45

GND#44

GND#43

GND#42

GND#41

GND#40

GND#39

GND#38

GND#37

GND#36

GND#35

GND#34

GND#33

GND#32

GND#31

GND#30

GND#29

GND#28

GND#27

GND#26

GND#25

GND#24

GND#23

GND#22

GND#21

GND#20

GND#19

GND#18

GND#17

GND#16

GND#15

GND#14

GND#13

GND#12

GND#11

GND#10

GND#9

GND#8

GND#7

GND#6

GND#5

GND#4

GND#3

GND#2

PCIE_VSS#9

PCIE_VSS#8

PCIE_VSS#7

PCIE_VSS#6

PCIE_VSS#5

PCIE_VSS#4

PCIE_VSS#3

PCIE_VSS#2

B

PCIE_VSS#1

U34

F34

F39

E39

AB39

PCIE_VSS#10

J31

H39

H34

G34

G33

H31

PCIE_VSS#16

PCIE_VSS#15

PCIE_VSS#14

PCIE_VSS#13

PCIE_VSS#12

PCIE_VSS#11

J34

L34

L31

K39

K34

K31

PCIE_VSS#22

PCIE_VSS#21

PCIE_VSS#20

PCIE_VSS#19

PCIE_VSS#18

PCIE_VSS#17

P39

P34

N34

P31

N31

M39

M34

PCIE_VSS#29

PCIE_VSS#28

PCIE_VSS#27

PCIE_VSS#26

PCIE_VSS#25

PCIE_VSS#24

PCIE_VSS#23

T39

T34

T31

U34

R34

U31

PCIE_VSS#35

PCIE_VSS#34

PCIE_VSS#33

PCIE_VSS#32

PCIE_VSS#31

PCIE_VSS#30

V39

V34

Y39

Y34

W34

W31

GND#1

J8

J6

K7

F29

F15

F19

F17

F21

F33

F25

F23

F27

F31

J27

K14

L6

L24

L22L2L17

L11

N2

N18

N16

M24

M22

M17

R17

R15N6N26

N23

N21

R6

R2

T11

R27

R24

R22

R20

T26

T23

T18

T16

T13

T21

U15

U6

V16

U27

U24

U22

U20U2U17

V11

W6

W2

Y20

Y17

Y15

V26

V23

V18

V21

AMD_216_0834002_00_FCBGA_962P

Y27

Y24

Y22

B

AA

INVENTEC

TITLE

LV1.1_Lauren

GPU-6

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6760

8

7 6 5 4 3 2 1

FF

U34

E

D

AMD_216_0834002_00_FCBGA_962P

C

B

PART 7 0F 9

LVDS CONTROL

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

P1V8S_DGPU

PVPCIE

VARY_BL

TXOUT_U3P
TXOUT_U3N

TXOUT_L3P
TXOUT_L3N

DIGON

R176
R168

AK27

GPU_LCM_PWM

AJ27

GPU_LCM_VCC_EN

AK35
AL36

AJ38
AK37

AH35
AJ36

AG38
AH37

AF35
AG36

AP34

GPU_LCM_L1_TXCL_DP

AR34

GPU_LCM_L1_TXCL_DN

AW37

GPU_LCM_L1_TXDL0_DP

AU35

GPU_LCM_L1_TXDL0_DN

AR37

GPU_LCM_L1_TXDL1_DP

AU39

GPU_LCM_L1_TXDL1_DN

AP35

GPU_LCM_L1_TXDL2_DP

AR35

GPU_LCM_L1_TXDL2_DN

AN36
AP37

L11

BLM18PG600SN1D

L10

BLM18PG600SN1D

I=500MA

21

10K_5%_2

21

10K_5%_2

SI 1115

21

21

TP19

1

C195

C183

CHECK POWER NET

BACK LIGHT BRIGHTNESS MODULATE
NO CONNECTOR

TP24

44

OUT

44

OUT

BACK LIGHT POWER CONTORL

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

P1V8S_DPE_VDD18

I=237MA

C199

2 1

2 1

10UF_6.3V_3

0.1UF_16V_2

P1V0S_DGPU_DPEF_VDD

I=222MA

C187

2 1

2 1

10UF_6.3V_3

0.1UF_16V_2

I=237MA

44
44

44
44

44
44

44
44

P1V8S_DPE_VDD18

R516

21

150_1%_2

R511

21

150_1%_2

R545

21

150_1%_2

U34

DP_VDDR DP_VDDC

AN24

DP_VDDR#1

AP24

DP_VDDR#2

AP25

DP_VDDR#3

AP26

DP_VDDR#4

AU28

DP_VDDR#5

AV29

DP_VDDR#6

AP20

DP_VDDR#7

AP21

DP_VDDR#8

AP22

DP_VDDR#9

AP23

DP_VDDR#10

AU18

DP_VDDR#11

AV19

DP_VDDR#12

AH34

DP_VDDR#13

AJ34

DP_VDDR#14

AF34

DP_VDDR#15

AG34

DP_VDDR#16

AM37

DP_VDDR#17

AL38

DP_VDDR#18

CALIBRATION

AW28

DPAB_CALR

AW18

DPCD_CALR

AM39

DPEF_CALR

AMD_216_0834002_00_FCBGA_962P

PART 8 0F 9

DP GND

CHECK POWER NET

AP31

DP_VDDC#1

AP32

DP_VDDC#2

AN33

DP_VDDC#3

AP33

DP_VDDC#4

AP13

DP_VDDC#5

AT13

DP_VDDC#6

AP14

DP_VDDC#7

AP15

DP_VDDC#8

AL33

DP_VDDC#9

AM33

DP_VDDC#10

AK33

DP_VDDC#11

AK34

DP_VDDC#12

AN27

DP_VSSR#1

AP27

DP_VSSR#2

AP28

DP_VSSR#3

AW24

DP_VSSR#4

AW26

DP_VSSR#5

AN29

DP_VSSR#6

AP29

DP_VSSR#7

AP30

DP_VSSR#8

AW30

DP_VSSR#9

AW32

DP_VSSR#10

AN17

DP_VSSR#11

AP16

DP_VSSR#12

AP17

DP_VSSR#13

AW14

DP_VSSR#14

AW16

DP_VSSR#15

AN19

DP_VSSR#16

AP18

DP_VSSR#17

AP19

DP_VSSR#18

AW20

DP_VSSR#19

AW22

DP_VSSR#20

AN34

DP_VSSR#21

AP39

DP_VSSR#22

AR39

DP_VSSR#23

AU37

DP_VSSR#24

AF39

DP_VSSR#25

AH39

DP_VSSR#26

AK39

DP_VSSR#27

AL34

DP_VSSR#28

AV27

DP_VSSR#29

AR28

DP_VSSR#30

AV17

DP_VSSR#31

AR18

DP_VSSR#32

AN38

DP_VSSR#33

AM35

DP_VSSR#34

P1V0S_DGPU_DPEF_VDD

PVPCIE

P1V8S_DGPU

PVPCIE

P1V8S_DGPU

I=222MA

FBM_11_160808_121T

FBM_11_160808_121T

1.8V 150MA MPV18

L6

FBM_11_160808_121T

1.8V 75MA SPV18

L5

FBM_11_160808_121T

150MA SPV10

L25

FBM_11_160808_121T

P3V3S_DGPU

FBM_11_160808_121T

HEATHROW/CHELSEA
DP_VDDC
DPLL_VDDC
SPLL_VDDC

I=75MA

DPLL_PVDD

21

L21

C631

C612

2 1

I=140MA

21

L1

C638

2 1

21

MPV18

C143

C129

2 1

10UF_6.3V_3

21

SPV18

2 1C32 1

1UF_6.3V_2

10UF_6.3V_3

0.1UF_16V_2

DPLL_VDDC

C648

C645

2 1

2 1

1UF_6.3V_2

10UF_6.3V_3

2 1

0.1UF_16V_2

0.1UF_16V_2

21

C128

C144

2 1

2 1

10UF_6.3V_3

0.1UF_16V_2

21

SPV10

C647

C644

10UF_6.3V_3

0.1UF_16V_2

2 1

2 1

R235

HEATHROW/CHELSEA
THAMES/WHISTLER/SEYMOUR

P3V3S_DGPU

21

21

R760

L27

21

C179

2 1

2.2UF_6.3V_2

R157

5.1K_5%_2

21

C154

21

C176

2 1

2 1

R761

R153

0.01UF_50V_2

0.01UF_50V_2

5.1K_5%_2

U34

AM32

DPLL_PVDD

AN31

DPLL_VDDC

AN32

DPLL_PVSS

H7

MPLL_PVDD#1

H8

MPLL_PVDD#2

AM10

SPLL_PVDD

AN9

SPLL_VDDC

AN10

SPLL_PVSS

AF30

NC_XTAL_PVDD CLKTESTB

AF31

NC_XTAL_PVSS

AMD_216_0834002_00_FCBGA_962P

0_5%_2_DY

OPEN
MOUNT

SI 1107

C650

6018B0052601

X4

2 1

1

10pF_50V_2

432

27MHZ

R521

1M_5%_2

U10

5.1K_5%_2_DY

4

VDD_100M

8

VDD_27M

7

S0

3

S1

6

GND_PLL

2

GND_27M

IDT_6V40088_DFN_10P

0_5%_2

21

X2X1_ICLK

100M

27M

TML

THAMES/WHISTLER/SEYMOUR

0.935V 1V

PART 9 0F 9

PLLS/XTAL

C658

2 1

10pF_50V_2

101

R519

33_5%_2

21

5

R525

33_5%_2

21

9

11

AV33

XTALIN

AU34

XTALOUT

AW34

XO_IN

AW35

XO_IN2

AK10

CLKTESTA

AL10

GPU_XOIN2_100M

GPU_XOIN_27M

1

TP12

TP24

1

TP9

TP24

GPU_XOIN_27M

GPU_XOIN2_100M

OUT

OUT

E

61

IN

61

IN

D

C

61

61

B

A

INVENTEC

TITLE

LV1.1_Lauren

GPU-7

DOC.NUMBER

CODE

SIZE

1310A24893-0 MTR

CS

8

7 6 5 4 3

CHANGE by

DATE

12-12-2011David Cheng

2 1

C

SHEET

of

61

A

REV

AX1

67

E

D

C

B

5762

IN

5762

IN

P1V5S_DGPU

C826
R685
R686
C821

8

CLKA0

CLKA0#

21

P1V5S_DGPU

P1V5S_DGPU

1UF_6.3V_2_DY

21
21
21

R424
R421

2.37K_1%_2

5.49K_1%_2

1UF_6.3V_2

C782
R662
R653
C776

C808
R678
R677
C802

P1V5S_DGPU

60.4_1%_2

21
21

60.4_1%_2

R670
R5500

P1V5S_DGPU

21

1UF_6.3V_2_DY

21

2.37K_1%_2

21

5.49K_1%_2

21

1UF_6.3V_2

21

1UF_6.3V_2_DY

21

2.37K_1%_2

21

5.49K_1%_2

21

1UF_6.3V_2

7 6 5 4 3 2 1

21

1K_5%_2

M2
M4
N2
N4

M13
M11

N13

N11

T13
T11
V13

V11

F13
F11
E13

E11

B13

B11

A13

A11

K10

K11

H10

H11

H5
H4

D4
D5

R2
R13
C13

C2

P13
D13

D2

G3

J11
J12

G12

L12

J13
J10

A10
V10

J14

U40

DQ31|DQ7
DQ30|DQ6
DQ29|DQ5
DQ28|DQ4

T2

DQ27|DQ3

T4

DQ26|DQ2

V2

DQ25|DQ1

V4

DQ24|DQ0
DQ23|DQ15
DQ22|DQ14
DQ21|DQ13
DQ20|DQ12
DQ19|DQ11
DQ18|DQ10
DQ17|DQ9
DQ16|DQ8
DQ15|DQ23
DQ14|DQ22
DQ13|DQ21
DQ12|DQ20
DQ11|DQ19
DQ10|DQ18
DQ9|DQ17
DQ8|DQ16

F2

DQ7|DQ31

F4

DQ6|DQ30

E2

DQ5|DQ29

E4

DQ4|DQ28

B2

DQ3|DQ27

B4

DQ2|DQ26

A2

DQ1|DQ25

A4

DQ0|DQ24

J5

RFU/A12/NC

K4

A7/A8|A0/A10

K5

A6/A11|A1/A9
A5/BA1|A3/BA3
A4/BA2|A2/BA0
A3/BA3|A5/BA1
A2/BA0|A4/BA2
A1/A9|A6/A11
A0/A10|A7/A8

WCK01|WCK23
WCK01#|WCK23#

P4

WCK23|WCK01

P5

WCK23#|WCK01#

EDC3|EDC0
EDC2|EDC1
EDC1|EDC2
EDC0|EDC3

P2

DBI3#|DBI0#
DBI2#|DBI1#
DBI1#|DBI2#
DBI0#|DBI3#

RAS#|CAS#

L3

CAS#|RAS#

J3

CKE#
CK#
CK

CS#|WE#
WE#|CS#

ZQ
SEN

J2

RESET#

J1

MF

A5

Vpp,NC

V5

Vpp,NC1

VREFD1
VREFD2

VREFC

J4

ABI#

SAM_K4G10325FE_HC04_FBGA_170P

VDDQ-B1

VDDQ-B3
VDDQ-B12
VDDQ-B14

VDDQ-D1

VDDQ-D3
VDDQ-D12
VDDQ-D14

VDDQ-E5
VDDQ-E10

VDDQ-F1

VDDQ-F3
VDDQ-F12
VDDQ-F14

VDDQ-G2
VDDQ-G13

VDDQ-H3
VDDQ-H12

VDDQ-K3
VDDQ-K12

VDDQ-L2
VDDQ-L13

VDDQ-M1

VDDQ-M3
VDDQ-M12
VDDQ-M14

VDDQ-N5
VDDQ-N10

VDDQ-P1

VDDQ-P3
VDDQ-P12
VDDQ-P14

VDDQ-T1

VDDQ-T3
VDDQ-T12
VDDQ-T14

VDD-C10

VDD-D11

VDD-G11

VDD-G14

VDD-L11

VDD-L14

VDD-P11

VDD-R10

VSSQ-A1

VSSQ-A3
VSSQ-A12
VSSQ-A14

VSSQ-C1

VSSQ-C3

VSSQ-C4
VSSQ-C11
VSSQ-C12
VSSQ-C14

VSSQ-E1

VSSQ-E3
VSSQ-E12
VSSQ-E14

VSSQ-F5
VSSQ-F10

VSSQ-H2
VSSQ-H13

VSSQ-K2
VSSQ-K13

VSSQ-M5
VSSQ-M10

VSSQ-N1

VSSQ-N3
VSSQ-N12
VSSQ-N14

VSSQ-R1

VSSQ-R3

VSSQ-R4
VSSQ-R11
VSSQ-R12
VSSQ-R14

VSSQ-V1

VSSQ-V3
VSSQ-V12
VSSQ-V14

VSS-B10

VSS-D10

VSS-G10

VSS-H14

VSS-K14

VSS-P10

VDD-C5

VDD-G1
VDD-G4

VDD-L1
VDD-L4

VDD-R5

VSS-B5

VSS-G5

VSS-H1

VSS-K1

VSS-L5

VSS-L10

VSS-T5

VSS-T10

U39

M2

DQA0(7)

57

BI

DQA0(0)

57

BI

DQA0(6)

57

BI

DQA0(2)

57

BI

DQA0(4)

57

BI

DQA0(1)

57

BI

DQA0(5)

57

BI

DQA0(3)

57

BI

DQA0(9)

57

BI

DQA0(10)

57

BI

DQA0(8)

57

BI

DQA0(11)

57

BI

DQA0(12)

57

BI

DQA0(14)

57

BI

DQA0(15)

57

BI

DQA0(13)

57

BI

DQA0(24)

57

BI

DQA0(25)

57

BI

DQA0(29)

57

BI

DQA0(27)

57

BI

DQA0(26)

57

BI

DQA0(28)

57

BI

DQA0(31)

57

BI

DQA0(30)

57

BI

DQA0(22)

57

BI

DQA0(21)

57

BI

DQA0(23)

57

BI

DQA0(20)

57

BI

DQA0(17)

57

BI

DQA0(19)

57

BI

DQA0(18)

57

BI

DQA0(16)

57

BI

57
57

57
57

57
57
57
57

57
57

57
5762
5762

57
57

586263

BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN

IN
IN

OUT
OUT
OUT
OUT

BI
BI
BI
BI

IN
IN

IN
BI
BI

IN
IN

120_1%_2

1K_5%_2

IN

21

ADBIA0#

VM_RST#

1K_5%_2

MAA0(8)
MAA0(0)
MAA0(1)
MAA0(3)
MAA0(2)
MAA0(5)
MAA0(4)
MAA0(6)
MAA0(7)

WCKA0_1
WCKA0_1#

WCKA0_0
WCKA0_0#

EDCA0_0
EDCA0_1
EDCA0_3
EDCA0_2

DBIA0_0
DBIA0_1
DBIA0_3
DBIA0_2

CASA0#
RASA0#

CKEA0
CLKA0#
CLKA0

WEA0#
CSA0#

57
57
57
57
57
57
57
57
57

57
57
57
57

21
21

R5501

57

IN

DQ31|DQ7

M4

DQ30|DQ6

N2

DQ29|DQ5

N4

DQ28|DQ4

T2

DQ27|DQ3

T4

DQ26|DQ2

V2

DQ25|DQ1

V4

DQ24|DQ0

M13

DQ23|DQ15

M11

DQ22|DQ14

N13

DQ21|DQ13

N11

DQ20|DQ12

T13

DQ19|DQ11

T11

DQ18|DQ10

V13

DQ17|DQ9

V11

DQ16|DQ8

F13

DQ15|DQ23

F11

DQ14|DQ22

E13

DQ13|DQ21

E11

DQ12|DQ20

B13

DQ11|DQ19

B11

DQ10|DQ18

A13

DQ9|DQ17

A11

DQ8|DQ16

F2

DQ7|DQ31

F4

DQ6|DQ30

E2

DQ5|DQ29

E4

DQ4|DQ28

B2

DQ3|DQ27

B4

DQ2|DQ26

A2

DQ1|DQ25

A4

DQ0|DQ24

J5

RFU/A12/NC

K4

A7/A8|A0/A10

K5

A6/A11|A1/A9

K10

A5/BA1|A3/BA3

K11

A4/BA2|A2/BA0

H10

A3/BA3|A5/BA1

H11

A2/BA0|A4/BA2

H5

A1/A9|A6/A11

H4

A0/A10|A7/A8

D4

WCK01|WCK23

D5

WCK01#|WCK23#

P4

WCK23|WCK01

P5

WCK23#|WCK01#

R2

EDC3|EDC0

R13

EDC2|EDC1

C13

EDC1|EDC2

C2

EDC0|EDC3

P2

DBI3#|DBI0#

P13

DBI2#|DBI1#

D13

DBI1#|DBI2#

D2

DBI0#|DBI3#

G3

RAS#|CAS#

L3

CAS#|RAS#

J3

CKE#

J11

CK#

J12

CK

G12

CS#|WE#

L12

WE#|CS#

J13

ZQ

J10

SEN

J2

RESET#

J1

MF

A5

Vpp,NC

V5

Vpp,NC1

A10

VREFD1

V10

VREFD2

J14

VREFC

J4

ABI#

SAM_K4G10325FE_HC04_FBGA_170P

VDDQ-B1

VDDQ-B3
VDDQ-B12
VDDQ-B14

VDDQ-D1

VDDQ-D3
VDDQ-D12
VDDQ-D14

VDDQ-E5
VDDQ-E10

VDDQ-F1

VDDQ-F3
VDDQ-F12
VDDQ-F14

VDDQ-G2
VDDQ-G13

VDDQ-H3
VDDQ-H12

VDDQ-K3
VDDQ-K12

VDDQ-L2
VDDQ-L13

VDDQ-M1

VDDQ-M3
VDDQ-M12
VDDQ-M14

VDDQ-N5
VDDQ-N10

VDDQ-P1

VDDQ-P3
VDDQ-P12
VDDQ-P14

VDDQ-T1

VDDQ-T3
VDDQ-T12
VDDQ-T14

VDD-C10

VDD-D11

VDD-G11

VDD-G14

VDD-L11
VDD-L14

VDD-P11

VDD-R10

VSSQ-A1

VSSQ-A3
VSSQ-A12
VSSQ-A14

VSSQ-C1

VSSQ-C3

VSSQ-C4
VSSQ-C11
VSSQ-C12
VSSQ-C14

VSSQ-E1

VSSQ-E3
VSSQ-E12
VSSQ-E14

VSSQ-F5
VSSQ-F10

VSSQ-H2
VSSQ-H13

VSSQ-K2
VSSQ-K13

VSSQ-M5
VSSQ-M10

VSSQ-N1

VSSQ-N3
VSSQ-N12
VSSQ-N14

VSSQ-R1

VSSQ-R3

VSSQ-R4
VSSQ-R11
VSSQ-R12
VSSQ-R14

VSSQ-V1

VSSQ-V3
VSSQ-V12
VSSQ-V14

VSS-D10

VSS-G10

VSS-H14

VSS-K14

VSS-L10
VSS-P10

VSS-T10

VDD-C5

VDD-G1
VDD-G4

VDD-L1
VDD-L4

VDD-R5

VSS-B5
VSS-B10

VSS-G5

VSS-H1

VSS-K1

VSS-L5

VSS-T5

P1V5S_DGPU

R663
R5502

1UF_6.3V_2_DY

2.37K_1%_2

5.49K_1%_2

1UF_6.3V_2

1UF_6.3V_2_DY

2.37K_1%_2

5.49K_1%_2

1UF_6.3V_2

57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57

57
57
57
57
57
57
57
57
57

57
57

57
57

57
57
57
57

57

BI

57

BI

57

BI

57

BI

57
57

57
5762
5762

57
57

586263

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

CHANNEL A MEMORY

VENDER

SAMSUNG

HYNIX

SAMSUNG

HYNIX

32MX32
32MX32
64MX32
64MX32

VENDER PNDENSITY
K4G10325FG-HC04
H5GQ1H24BFR-T2C
K4G20325FC-HC04
H5GQ2H24MFR-T2C

5762
5762

IN
IN

IEC PN
6019B0889201
6019B0866701
6019B0842201
6019B0843001

CLKA1

R431

CLKA1#

R426

P1V5S_DGPU

C765
R655
R625
C759

P1V5S_DGPU

C831
R691
R687
C828

P1V5S_DGPU

60.4_1%_2

21
21

60.4_1%_2

21
21
21
21

21
21
21
21

21
21

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN

IN
IN

OUT
OUT
OUT
OUT

IN
IN

IN

BI
BI

IN
IN

120_1%_2
1K_5%_2

IN

DBIA1_3
DBIA1_2
DBIA1_0
DBIA1_1

R5503

DQA1(25)
DQA1(29)
DQA1(27)
DQA1(28)
DQA1(26)
DQA1(31)
DQA1(24)
DQA1(30)
DQA1(21)
DQA1(20)
DQA1(22)
DQA1(23)
DQA1(19)
DQA1(16)
DQA1(18)
DQA1(17)
DQA1(5)
DQA1(7)
DQA1(6)
DQA1(2)
DQA1(3)
DQA1(1)
DQA1(4)
DQA1(0)
DQA1(8)
DQA1(9)
DQA1(10)
DQA1(11)
DQA1(15)
DQA1(13)
DQA1(12)
DQA1(14)

MAA1(8)
MAA1(7)
MAA1(6)
MAA1(5)
MAA1(4)
MAA1(3)
MAA1(2)
MAA1(1)
MAA1(0)

WCKA1_0
WCKA1_0#

WCKA1_1
WCKA1_1#

EDCA1_3
EDCA1_2
EDCA1_0
EDCA1_1

RASA1#
CASA1#

CKEA1
CLKA1#
CLKA1

CSA1#
WEA1#

VM_RST#

P1V5S_DGPU

21

C788
R665
R669
C796

1UF_6.3V_2_DY

21

2.37K_1%_2

21

5.49K_1%_2

21

1UF_6.3V_2

ADBIA1#

57

IN

P1V5S_DGPU

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

FF

E

D

C

B

P1V5S_DGPU

C551

C811

C810

C790

C780

2 1

2 1

2 1

2 1

10UF_6.3V_3

A

0.1UF_16V_2

2 1

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

8

C791

C823

C827

2 1

2 1

0.1UF_16V_2

2.2UF_6.3V_2

7 6 5 4 3

C775

C803

C789

2 1

2 1

2.2UF_6.3V_2

2.2UF_6.3V_2

C795

2 1

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

P1V5S_DGPU

C450

2 1

C819

C822

C805

C794

C758

C781

C792

2 1

2 1

2 1

2 1

10UF_6.3V_3

0.1UF_16V_2

0.1UF_16V_2

2 1

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

2 1

2 1

2.2UF_6.3V_2

2.2UF_6.3V_2

CHANGE by

David Cheng 12-12-2011

C825

2 1

C755

C804

2 1

2.2UF_6.3V_2

C820

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

TITLE

SIZE

DATE

2 1

C

INVENTEC

LV1.1_Lauren

VRAM1 & VRAM2

DOC.NUMBER

CODE

1310A24893-0 MTR

CS

SHEET

of

62 67

A

REV

AX1

8

CLKB0

5863

IN

CLKB0#

5863

IN

E

D

P1V5S_DGPU

P1V5S_DGPU

21

C730

C

R581
R589
C737

21
21
21

1UF_6.3V_2_DY

2.37K_1%_2

5.49K_1%_2

1UF_6.3V_2

P1V5S_DGPU

P1V5S_DGPU

B

7 6 5 4 3 2 1

21

1K_5%_2

U32

M2

DQ31|DQ7

M4

DQ30|DQ6

N2

DQ29|DQ5

N4

DQ28|DQ4

T2

DQ27|DQ3

T4

DQ26|DQ2

V2

DQ25|DQ1

V4

DQ24|DQ0

M13

DQ23|DQ15

M11

DQ22|DQ14

N13

DQ21|DQ13

N11

DQ20|DQ12

T13

DQ19|DQ11

T11

DQ18|DQ10

V13

DQ17|DQ9

V11

DQ16|DQ8

F13

DQ15|DQ23

F11

DQ14|DQ22

E13

DQ13|DQ21

E11

DQ12|DQ20

B13

DQ11|DQ19

B11

DQ10|DQ18

A13

DQ9|DQ17

A11

DQ8|DQ16

F2

DQ7|DQ31

F4

DQ6|DQ30

E2

DQ5|DQ29

E4

DQ4|DQ28

B2

DQ3|DQ27

B4

DQ2|DQ26

A2

DQ1|DQ25

A4

DQ0|DQ24

J5

RFU/A12/NC

K4

A7/A8|A0/A10

K5

A6/A11|A1/A9

K10

A5/BA1|A3/BA3

K11

A4/BA2|A2/BA0

H10

A3/BA3|A5/BA1

H11

A2/BA0|A4/BA2

H5

A1/A9|A6/A11

H4

A0/A10|A7/A8

D4

WCK01|WCK23

D5

WCK01#|WCK23#

P4

WCK23|WCK01

P5

WCK23#|WCK01#

R2

EDC3|EDC0

R13

EDC2|EDC1

C13

EDC1|EDC2

C2

EDC0|EDC3

P2

DBI3#|DBI0#

P13

DBI2#|DBI1#

D13

DBI1#|DBI2#

D2

DBI0#|DBI3#

G3

RAS#|CAS#

L3

CAS#|RAS#

J3

CKE#

J11

CK#

J12

CK

G12

CS#|WE#

L12

WE#|CS#

J13

ZQ

J10

SEN

J2

RESET#

J1

MF

A5

Vpp,NC

V5

Vpp,NC1

A10

VREFD1

V10

VREFD2

J14

VREFC

J4

ABI#

SAM_K4G10325FE_HC04_FBGA_170P

MF = 1 FOR MIRROR

VDDQ-B1

VDDQ-B3
VDDQ-B12
VDDQ-B14

VDDQ-D1

VDDQ-D3
VDDQ-D12
VDDQ-D14

VDDQ-E5
VDDQ-E10

VDDQ-F1

VDDQ-F3
VDDQ-F12
VDDQ-F14

VDDQ-G2
VDDQ-G13

VDDQ-H3
VDDQ-H12

VDDQ-K3
VDDQ-K12

VDDQ-L2
VDDQ-L13

VDDQ-M1

VDDQ-M3
VDDQ-M12
VDDQ-M14

VDDQ-N5
VDDQ-N10

VDDQ-P1

VDDQ-P3
VDDQ-P12
VDDQ-P14

VDDQ-T1

VDDQ-T3
VDDQ-T12
VDDQ-T14

VDD-C10

VDD-D11

VDD-G11

VDD-G14

VDD-L11

VDD-L14

VDD-P11

VDD-R10

VSSQ-A1

VSSQ-A3
VSSQ-A12
VSSQ-A14

VSSQ-C1

VSSQ-C3

VSSQ-C4
VSSQ-C11
VSSQ-C12
VSSQ-C14

VSSQ-E1

VSSQ-E3
VSSQ-E12
VSSQ-E14

VSSQ-F5
VSSQ-F10

VSSQ-H2
VSSQ-H13

VSSQ-K2
VSSQ-K13

VSSQ-M5
VSSQ-M10

VSSQ-N1

VSSQ-N3
VSSQ-N12
VSSQ-N14

VSSQ-R1

VSSQ-R3

VSSQ-R4
VSSQ-R11
VSSQ-R12
VSSQ-R14

VSSQ-V1

VSSQ-V3
VSSQ-V12
VSSQ-V14

VSS-B10

VSS-D10

VSS-G10

VSS-H14

VSS-K14

VSS-P10

P1V5S_DGPU

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

C5

VDD-C5

C10
D11
G1

VDD-G1

G4

VDD-G4

G11
G14
L1

VDD-L1

L4

VDD-L4

L11
L14
P11
R5

VDD-R5

R10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14

B5

VSS-B5

B10
D10
G5

VSS-G5

G10
H1

VSS-H1

H14
K1

VSS-K1

K14
L5

VSS-L5

L10

VSS-L10

P10
T5

VSS-T5

T10

VSS-T10

U35

M2

DQB0(14)

58

BI

DQB0(9)

58

BI

DQB0(15)

58

BI

DQB0(8)

58

BI

DQB0(11)

58

BI

DQB0(10)

58

BI

DQB0(13)

58

BI

DQB0(12)

58

BI

DQB0(1)

58

BI

DQB0(6)

58

BI

DQB0(0)

58

BI

DQB0(7)

58

BI

DQB0(2)

58

BI

DQB0(5)

58

BI

DQB0(3)

58

BI

DQB0(4)

58

BI

DQB0(16)

58

BI

DQB0(18)

58

BI

DQB0(17)

58

BI

DQB0(23)

58

BI

DQB0(19)

58

BI

DQB0(21)

58

BI

DQB0(20)

58

BI

DQB0(22)

58

BI

DQB0(26)

58

BI

DQB0(27)

58

BI

DQB0(31)

58

P1V5S_DGPU

R339

60.4_1%_2

21
21

R338

60.4_1%_2

21

C453
R341
R342
C454

C748
R614
R612
C750

1UF_6.3V_2_DY

21

2.37K_1%_2

21

5.49K_1%_2

21

1UF_6.3V_2

21

1UF_6.3V_2_DY

21

2.37K_1%_2

21

5.49K_1%_2

21

1UF_6.3V_2

BI

DQB0(24)

58

BI

DQB0(29)

58

BI

DQB0(28)

58

BI

DQB0(30)

58

BI

DQB0(25)

58

BI

MAB0(8)

58

BI

MAB0(0)

58

BI

MAB0(1)

58

BI

MAB0(3)

58

BI

MAB0(2)

58

BI

MAB0(5)

58

BI

MAB0(4)

58

BI

MAB0(6)

58

BI

MAB0(7)

58

BI

WCKB0_1

58

IN

WCKB0_1#

58

IN

WCKB0_0

58

IN

WCKB0_0#

58

IN

EDCB0_1

58

OUT

EDCB0_0

58

OUT

EDCB0_2

58

OUT

EDCB0_3

58

OUT

DBIB0_1

58

BI

DBIB0_0

58

BI

DBIB0_2

58

BI

DBIB0_3

58

BI

CASB0#

58

IN

RASB0#

58

IN

CKEB0

58

IN

CLKB0#

5863

BI

CLKB0

5863

BI

WEB0#

58

IN

CSB0#

58

IN

R5505

IN

586263

IN

21

ADBIB0#

21
21

1K_5%_2

120_1%_2
1K_5%_2

VM_RST#

R611
R5504

58

DQ31|DQ7

M4

DQ30|DQ6

N2

DQ29|DQ5

N4

DQ28|DQ4

T2

DQ27|DQ3

T4

DQ26|DQ2

V2

DQ25|DQ1

V4

DQ24|DQ0

M13

DQ23|DQ15

M11

DQ22|DQ14

N13

DQ21|DQ13

N11

DQ20|DQ12

T13

DQ19|DQ11

T11

DQ18|DQ10

V13

DQ17|DQ9

V11

DQ16|DQ8

F13

DQ15|DQ23

F11

DQ14|DQ22

E13

DQ13|DQ21

E11

DQ12|DQ20

B13

DQ11|DQ19

B11

DQ10|DQ18

A13

DQ9|DQ17

A11

DQ8|DQ16

F2

DQ7|DQ31

F4

DQ6|DQ30

E2

DQ5|DQ29

E4

DQ4|DQ28

B2

DQ3|DQ27

B4

DQ2|DQ26

A2

DQ1|DQ25

A4

DQ0|DQ24

J5

RFU/A12/NC

K4

A7/A8|A0/A10

K5

A6/A11|A1/A9

K10

A5/BA1|A3/BA3

K11

A4/BA2|A2/BA0

H10

A3/BA3|A5/BA1

H11

A2/BA0|A4/BA2

H5

A1/A9|A6/A11

H4

A0/A10|A7/A8

D4

WCK01|WCK23

D5

WCK01#|WCK23#

P4

WCK23|WCK01

P5

WCK23#|WCK01#

R2

EDC3|EDC0

R13

EDC2|EDC1

C13

EDC1|EDC2

C2

EDC0|EDC3

P2

DBI3#|DBI0#

P13

DBI2#|DBI1#

D13

DBI1#|DBI2#

D2

DBI0#|DBI3#

G3

RAS#|CAS#

L3

CAS#|RAS#

J3

CKE#

J11

CK#

J12

CK

G12

CS#|WE#

L12

WE#|CS#

J13

ZQ

J10

SEN

J2

RESET#

J1

MF

A5

Vpp,NC

V5

Vpp,NC1

A10

VREFD1

V10

VREFD2

J14

VREFC

J4

ABI#

SAM_K4G10325FE_HC04_FBGA_170P

VDDQ-B1

VDDQ-B3
VDDQ-B12
VDDQ-B14

VDDQ-D1

VDDQ-D3
VDDQ-D12
VDDQ-D14

VDDQ-E5
VDDQ-E10

VDDQ-F1

VDDQ-F3
VDDQ-F12
VDDQ-F14

VDDQ-G2
VDDQ-G13

VDDQ-H3
VDDQ-H12

VDDQ-K3
VDDQ-K12

VDDQ-L2

VDDQ-L13

VDDQ-M1

VDDQ-M3
VDDQ-M12
VDDQ-M14

VDDQ-N5
VDDQ-N10

VDDQ-P1

VDDQ-P3
VDDQ-P12
VDDQ-P14

VDDQ-T1

VDDQ-T3
VDDQ-T12
VDDQ-T14

VDD-C10

VDD-D11

VDD-G11

VDD-G14

VDD-L11

VDD-L14

VDD-P11

VDD-R10

VSSQ-A1

VSSQ-A3
VSSQ-A12
VSSQ-A14

VSSQ-C1
VSSQ-C3

VSSQ-C4
VSSQ-C11
VSSQ-C12
VSSQ-C14

VSSQ-E1

VSSQ-E3
VSSQ-E12
VSSQ-E14

VSSQ-F5
VSSQ-F10

VSSQ-H2
VSSQ-H13

VSSQ-K2
VSSQ-K13

VSSQ-M5

VSSQ-M10

VSSQ-N1

VSSQ-N3
VSSQ-N12
VSSQ-N14

VSSQ-R1

VSSQ-R3

VSSQ-R4
VSSQ-R11
VSSQ-R12
VSSQ-R14

VSSQ-V1

VSSQ-V3
VSSQ-V12
VSSQ-V14

VSS-B10

VSS-D10

VSS-G10

VSS-H14

VSS-K14

VSS-L10

VSS-P10

VSS-T10

VDD-C5

VDD-G1
VDD-G4

VDD-L1
VDD-L4

VDD-R5

VSS-B5

VSS-G5

VSS-H1

VSS-K1

VSS-L5

VSS-T5

P1V5S_DGPU

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT
OUT

BI
BI
BI
BI

21
21

IN
IN

IN
IN

IN
IN

IN

IN
IN

IN

BI
BI

120_1%_2
1K_5%_2

R5507

DQB1(27)
DQB1(30)
DQB1(25)
DQB1(29)
DQB1(26)
DQB1(31)
DQB1(24)
DQB1(28)
DQB1(22)
DQB1(23)
DQB1(20)
DQB1(21)
DQB1(18)
DQB1(17)
DQB1(19)
DQB1(16)
DQB1(4)
DQB1(0)
DQB1(7)
DQB1(2)
DQB1(6)
DQB1(3)
DQB1(5)
DQB1(1)
DQB1(10)
DQB1(15)
DQB1(9)
DQB1(14)
DQB1(8)
DQB1(12)
DQB1(11)
DQB1(13)

MAB1(8)
MAB1(7)
MAB1(6)
MAB1(5)
MAB1(4)
MAB1(3)
MAB1(2)
MAB1(1)
MAB1(0)

WCKB1_0
WCKB1_0#

WCKB1_1
WCKB1_1#

EDCB1_3
EDCB1_2
EDCB1_0
EDCB1_1

DBIB1_3
DBIB1_2
DBIB1_0
DBIB1_1

RASB1#
CASB1#

CKEB1
CLKB1#
CLKB1

CSB1#
WEB1#

VM_RST#

R501
R5506

1UF_6.3V_2_DY

2.37K_1%_2

5.49K_1%_2

1UF_6.3V_2

1UF_6.3V_2_DY

2.37K_1%_2

5.49K_1%_2

1UF_6.3V_2

58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58

58
58
58
58
58
58
58
58
58

58
58

58
58

58
58
58
58

58
58
58
58

58
58

58
5863
5863

58
58

586263

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

CHANNEL B MEMORY

P1V5S_DGPU

60.4_1%_2

CLKB1

5863

IN

CLKB1#

5863

IN

P1V5S_DGPU

P1V5S_DGPU

21

R374

21

R340

60.4_1%_2

21

C628

21

R499

21

R498

21

C629

21

C660

21

R530

21

R542

21

C664

P1V5S_DGPU

21

C632
R502
R503
C630

1UF_6.3V_2_DY

21

2.37K_1%_2

21

5.49K_1%_2

21

1UF_6.3V_2

ADBIB1#

58

IN

FF

E

D

C

B

P1V5S_DGPU

C410

C142

C745

2 1

2 1

0.1UF_16V_2

A

8

10UF_6.3V_3

7 6 5 4 3

2 1

2 1

0.1UF_16V_2

C234

2 1

0.1UF_16V_2

0.1UF_16V_2

C237

C140

2 1

2 1

2 1

0.1UF_16V_2

2.2UF_6.3V_2

C174

C236

C419

C235

C177

2 1

2 1

2.2UF_6.3V_2

2.2UF_6.3V_2

C238

2 1

1UF_6.3V_2

1UF_6.3V_2

2 1

1UF_6.3V_2

P1V5S_DGPU

C809

2 1

C708

2 1

2 1

2 1

10UF_6.3V_3

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

C675

C673

2 1

2 1

2 1

0.1UF_16V_2

2 1

0.1UF_16V_2

2.2UF_6.3V_2

CHANGE by

C667

C680

C228

C681

C683

C202

2 1

2 1

2.2UF_6.3V_2

2.2UF_6.3V_2

David Cheng 12-12-2011

C684

C665

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

TITLE

SIZE

DATE

2 1

C

INVENTEC

LV1.1_Lauren

VRAM3 & VRAM4

DOC.NUMBER

CODE

1310A24893-0 MTR

CS

SHEET

of

63 67

A

REV

AX1

8 7

6 5

4

3 2 1

CARDREADER BOARD

64

D

★

RTS5229GR = 6019B0900701

RTS5239GR = 6019B0928001

PLT_RST#_CRB

64

IN

CLKREQ#_CRB

64

OUT

0.1uF_16V_2

21

21

0.1uF_16V_2

P3V3S_CR

4.7UF_6.3V_3

2 1

C1804

DGND_CR

DGND_CR

PCIE_RXP_CRB
PCIE_RXN_CRB

DGND_CR

2 1

2 1

0.1UF_16V_2

10uF_6.3V_3

C1809

C1808

1

HSIP

2

HSIN

3

REFCLKP

4

REFCLKN

5

HSOP

6

HSON

R1800

6.2K_1%_2

P3V3S_CR_AB

0.1UF_16V_2

ZDIFF : 100 OHM

IN
IN
IN

IN
OUT
OUT

PCIE_C_TXP_CRB
PCIE_C_TXN_CRB
CLK_PCIE_CRB
CLK_PCIE#_CRB
PCIE_C_RXP_CRB
PCIE_C_RXN_CRB

C1806

C1805

P1V2_A_CR

C1801

C1819

2 1

2 1

0.1UF_16V_2

DGND_CR

64
64
64

64
64
64

B

P3V3S_CR

C1812

2 1

1uF_6.3V_2

DGND_CR

SD_DATA2
SD_DATA3
SD_CMD

SD_CLK
SD_DATA0

+CR_DV33_18

OUT

4.7UF_6.3V_3_DY

C830

DGND_CR

SD_DATA1

64

BI

64

BI

64

BI

64

BI

64

BI

2 1

5PF_50V_2_DY

64

BI

R752

10K_5%_2

2 1

SD_CD#

SD_WP

19

20

21

24

25

23

22

TML

CLKREQ#

AV12

7

21

U1800

PERST#

MS_INS#

GPIO

SP7

SD_CD#

SP6
SP5
SP4

DV33_18

CARD_3V3

SP3

DV12_S

3V3_IN

SP2

RREF

SP1

REALTEK_RTS5239_GR_QFN_24P

8

9

12

10

11

64

IN

64

IN

18

R1805

17

R1804
16
15
14

R1803
13

R1802

R1801

SI 1115

21

0_5%_2

21

0_5%_2

21
21

21

DGND_CR

0_5%_2
0_5%_2

0_5%_2

C1811

2 1

P1V2_CR

C1807

2 1

0.1UF_16V_2

C1821

2 1

4.7UF_6.3V_3

DGND_CR

64

64
64
64

64

64

64
64

64

64

CARD READER CONN

P3V3S_CR_AB

64

DGND_CR

PLT_RST#_CRB

IN

CLKREQ#_CRB

OUT

PWR_LED#_CRB

IN

HDD_LOCK_LED#_CRB

OUT

LED_3S_SATA#_CRB

OUT

CLK_PCIE_CRB

IN

CLK_PCIE#_CRB

IN

PCIE_C_RXP_CRB

OUT

PCIE_C_RXN_CRB

OUT

PCIE_C_TXN_CRB

IN

PCIE_C_TXP_CRB

IN

64

BI

64

BI

800mA

64

BI

C1800

2 1

BI

10uF_6.3V_3

P3V3A_PBP3V3S_CR

SD_DATA3

SD_CMD

SD_CLK

SD_DATA0

DGND_CR

DGND_CR

2
3
4
5
6

CN1800

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

ACES_50501_0184N_001_18P

CN1801

CMD

VSS

VDD

CLK

VSS

PLAS_CS1S_125_14P-002

G11

GNDDAT3

G2

GND

12

CD_WP_COM

11

CD

10

WP

9

DAT2

87

DAT1DAT0

*BOM

CN1801
PN: 6026B0103603

G1

G

G2

G

DGND_CR

DGND_CR

SD_CD#

SD_WP

SD_DATA2

SD_DATA1

D

CC

64

BI

64

BI
BI
BI

B

64

64

POWER LED

64

IN

PWR_LED#_CRB

8

NC

D1800

NC

1

1 2

EVL_12_21_T3D_CP1Q2B12Y_2C_2P

2

10_5%_2

LED_SINGLE_3PIN_B

7 6

R1809

P3V3A_PB

21

SATA LED & HDD-HALTED LED

HDD_LOCK_LED#_CRB

64

IN

LED_3S_SATA#_CRB

64

IN

R1808

47_5%_2

R1807

10_5%_2

D1801

21

3

21

2

12_22_S2ST3D_C30_2C

5 4

R1806

1

10_5%_2

P3V3S_CR

21

S1800

1

SCREW240_450_1P

DGND_CR DGND_CR

FIX1800

FIX_MASKFIX_MASK

1

CHANGE by

David Cheng

FIX1801

1

S1801

1

SCREW240_450_1P

FIX1802

FIX_MASK

1

DATE

12-12-2011

23

INVENTEC

TITLE

LV1.1_Lauren

CARDREADER BOARD

DOC.NUMBER

CODE

SIZE

A3

1310A24893-0 MTR

CS

SHEET

of

6764

1

REV

AX1

AA

8 7

6 5

4

3 2 1

ODD Board

P5V0S_ODD

(1.6A)

D

65
65

65
65

FIX_MASK

FIX_MASK

SATA_TX1P_OD

IN

SATA_TX1N_OD

IN

SATA_RX1N_OD

OUT

SATA_RX1P_OD

OUT

ODD_MD_OD#

65

IN

FIX1750

FIX17531FIX17541FIX1755

FIX1751

FIX_MASK

FIX_MASK

1

1

FIX_MASK

FIX_MASK

1

C1750

2 1

FIX1752

1

S1
S2
S3
S4
S5
S6
S7
P1
P2
P3
P4
P5
P6

0.1UF_16V_2

SCREW220_500_1P

DGND_AL1

CN1751

FOX_LN25136_B004_9H_13P

GND
A+
A­GND
B­B+
GND
DP
+5V
+5V
MD
GND
GND

S1750

G
G

G2
G1

DGND_AL1

65

65
65

65
65

OUT

OUT
OUT

IN
IN

1

DGND_AL1

C1751

ODD_MD_OD#

SATA_RX1P_OD
SATA_RX1N_OD

SATA_TX1N_OD
SATA_TX1P_OD

2 1

P5V0S_ODD

1

2
3
4

0.1UF_16V_2_DY

DGND_AL1

5
6
7
8

9
10
11
12
13
14
15
16

PLAST_FZ26_16WK_60_H_16P

DGND_AL1 DGND_AL1

CN1750

1
2
3
4
5
6
7
8
9

10

11

12

13

14

15

16

G1

G

G2

G

Power Button Board

P3V3A_PBN

B

65

OUT

65

OUT

65

IN

FIX70001FIX70011FIX7002

1

PWR_LED#_PBN
PWR_SW#_PBN
LID_SW#_PBN

D7000

65

OUT

FIX_MASKFIX_MASK

8

3

AZ23C6V2

3

DGND_PBN

PWR_SW#_PBN

DGND_PBN

FIX_MASK

D7001

21

21

SW7000

T3
T4

DIP_TMG_533_Q_T_R_4P

S7001

S7000

1

1

DGND_PBNDGND_PBN

SCREW520_800_NP_1P

7 6

DGND_PBN

DGND_PBN

SCREW520_800_NP_1P

3

3

S7002

1

DGND_PBN

AZ23C6V2

T1
G2G1
T2

SCREW240_500_1P

smdpad_6

PAD7000

1
2
3
4
5
6

SMDPAD6_100_28X118

21

21

65

OUT

DGND_PBN

1

2

3

4

5
6

65

LID SWITCH

100K_5%_2

LID_SW#_PBN

0.1UF_16V_2

POWER LED

PWR_LED#_PBN

IN

P3V3A_PBN

R7001

C7000

MST_MH_248ESO_a_05TR_SOT23_3P

21

1

2

2 1

DGND_PBN

U7000

VDD

GND

Output

P3V3A_PBN

21

R7000

D7002

19_217_W1D_AP1Q2QY_3T

PN: 6011B0028601

3

DGND_PBN

21

5 4

100_5%_2

WIRELESS AUDIO BOARD

P3V3S_WAB

16

65

IN

65

IN

65

BI

65

BI

65

IN

65

IN

65

IN

TP24

TP9001

TP24

TP9000

RF_SEL_WAB1

65

OUT

65

OUT

RF_SEL_WAB2

FIX90031FIX90041FIX9005

1

WWAN_POWER_OFF_WAB
SMSC_RST#_WAB

USB_4N_WAB
USB_4P_WAB
W_AU_LED#_WAB
RF_SEL_WAB1
RF_SEL_WAB2

P3V3S_WAB

1
1

DGND_WAB

FIX_MASKFIX_MASKFIX_MASK

1

11
13
15

17
19
21
23
25

29
31
33
35
37
39
41
43
45
47
49
51

SCREW240_450_1P

DGND_WAB

DGND_WABDGND_WAB

CHANGE by

3
5
7
9

CN9008

WAKE#
RESERVED1
RESERVED2
CLKREQ#
GND
REFCLK­REFCLK+
GND

KEY

RESERVED3
RESERVED4
GND
PER_N0
PER_P0

GND
PET_N0
PET_P0
GND
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12

BELLW_80052_1023_52P

S90071S9006

S9008

1

1

SCREW240_450_1P

SCREW240_450_1P

David Cheng

DGND_WAB

RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17

RESERVED18

PERST#

+3.3V_AUX

SMB_CLK

SMB_DATA

USB_D-

USB_D+

LED_WWAN#

LED_WLAN#

LED_WPAN#

+3.3V

+1.5V

+1.5VGND

+1.5V

+3.3V

2
4

GND

6
8
10
12
14
16

18

GND

20
22
24
26

GND

2827
30
32
34

GND

36
38
40

GND

42
44
46
48
50

GND

52
G2G1

G2G1

15
14
13
12
11
10

P3V3S_WAB

DGND_WAB

DATE

CN9009

PLAST_FZ26_16WK_60_H_16P

9
8
7
6
5
4
3
2

1

R9026

G2

G

16

G1

G

15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

DGND_WAB

WWAN_POWER_OFF_WAB

21

SMSC_RST#_WAB

0_5%_2_DY

USB_4N_WAB
USB_4P_WAB

W_AU_LED#_WAB

0_5%_2

R9047

21

INVENTEC

TITLE

SIZE

12-12-2011

23

A3

LV1.1_Lauren

ODD,PBB WAB

DOC.NUMBER

CODE

1310A24893-0 MTR

CS

SHEET

D

CC

B

65

IN

65

IN

65

BI

65

BI

65

IN

AA

REV

of

AX1

6765

1

8 7

6 5

4

3 2 1

D

P3V3S

PV 1219

U51

LPC_AD(0)

31

40

51

IN

LPC_AD(1)

31

40

51

IN

LPC_AD(2)

31

40

C954

2 1

IN

10pF_50V_2_DY

BUF_PLT_RST#

CLK_TPM

35

IN

21

3540

51

66

51

IN

LPC_AD(3)

31

40

51

IN

LPC_FRAME#

31

40

51

IN

BUF_PLT_RST#

21

3540

51

66

31

40

R902

0_5%_2

IN

SERIRQ

IN

21

BUF_PLT_RST#_R

B

26

LAD0

23

LAD1

20

LAD2

17

LAD3

21

LCLK

22

LFRAME#

16

LRESET#

27

SERIRQ

15

TEST

9

TESTBI_LRESET#

8

TESTI

INFINEON_SLB9656TT1_2_TSSOP_28P

5

VDD

10

VDD

19

VDD

24

VDD

4

GND

11

GND

18

GND

25

GND

728

PPNC

1

NC

3

NC

12

NC

13

NC

14

NC

6

GPIO

2

NC

C950

0.1uF_16V_2

21

0.1uF_16V_2

2 1

C951

R900
R901

0.1uF_16V_2

2 1

P3V3S

0.1uF_16V_2

C952

2 1

RSC_0402_DY

21

RSC_0402_DY

21

C953

LPC_PP

IN

P3V3S

CHECK

D

CC

B

TPM1.2

AA

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6766

8 7

6 5

4

3 2 1

D

P5V0AP3V3A

ININ

C814

C817

2 1

2 1

0.1UF_25V_2

0.1UF_25V_2

C824

C850

2 1

2 1

0.1UF_25V_2

0.1UF_25V_2

C627

2 1

EMI

C669

C657

C633

2 1

2 1

0.1UF_25V_2_DY

0.1UF_25V_2_DY

0.1UF_25V_2_DY

P1V5

2 1

0.1UF_25V_2_DY

P1V0S_VCCP

C526

2 1

0.1UF_25V_2_DY

C141

2 1

0.1UF_25V_2_DY

PVCORE_DGPU

C139

C138

2 1

0.1UF_25V_2_DY

IN

2 1

0.1UF_25V_2_DY

ININ

C527

2 1

0.1UF_25V_2_DY

B

D

CC

B

AA

INVENTEC

TITLE

LV1.1_Lauren

Block Diagram

SIZE

8

7 6

5 4

CHANGE by

David Cheng

DATE

12-12-2011

23

A3

1310A24893-0 MTR

CS

SHEET

of

1

DOC.NUMBER

CODE

REV

AX1

6767