Inventec Potomac 10 6050A2169901 Schematic

POTOMAC 10
MP BUILD
2008.0430
DATE CHANGE NO.
REV
DRAWER DESIGN CHECK RESPONSIBLE
SIZE = FILE NAME : XXXX-XXXXXX-XX
P/N
EE
3
DATE
POWER
VER :
DATE
TITLE
SIZE DOC. NUMBER
A3
INVENTEC
Potomac 10
CODE
1310A21699 A01
CS
SHEET OF
601
REV
TABLE OF CONTENTS
PAGE
1.COVER PAGE
2.INDEX
3.BLOCK DIAGRAM
4.POWER SEQUENCE BLOCK 5-12.SYSTEM POWER
13.CLOCK GENERATOR
14. PENRYN-1
15. PENRYN-2
16. PENRYN-3
17. PENRYN-4
18. FAN & THERMAL
19. CANTIGA-1
20. CANTIGA-2
21. CANTIGA-3
22. CANTIGA-4
23. CANTIGA-5
24. CANTIGA-6
25. CANTIGA-7
26.DDR2 DIMM0
27.DDR2 DIMM1
29.CRT & TV-OUT CONN
30.LCM CONN
PAGE
31. ICH9-1
32. ICH9-2
33. ICH9-3
34. ICH9-4
35. ICH9-5
36.SATA HDD CONN
37.ODD CONN
PAGE
54.MDC
55.LED(M/B) & HOTKEY/B
56.KILL & LID SWITCH
57.DRILL HOLE
58.For EMI
59.Small board 1
60.Small board 2
38.USB CONN
39.FELICA & CAMERA FINGERPRINT
40.BLUE TOOTH CONN
41.KBC
42.K/B & TP/B CONN
43.AZALIA CODEC & HP & SPDIF
44.AUDIO AMP & MIC & SPEAKER
45.LAN CONTROLLER
46.RJ45 & TRANSFORMER
47.HDMI LEVEL SHIFTER
48.CIR & HDMI CONN &CEC
49.CARDREADER & 1394 CONTROLLER-1
50.CARDREADER & 1394 CONTROLLER-2
51.EXPRESS CARD 28.DDR DAMPING
52.ROBSON & WLAN
53.HD-DVD
CHANGE by
Loren
18-Feb-2008
INVENTEC
TITLE
Potomac 10
SIZE
CODE
CS
DOC. NUMBER
260
A3
REV
A011310A21699
OFSHEET
Penryn
(uFCPGA)
Socket P
XDP
Clock generator
ICS9LPRS365
HDMI CONN
+ eSATA
CONN
USB1
USB0
CONN
CEC
CONN
USB2
PER_PI3VDP411LST
HDMI LEVEL SHIFTER
HDD HDD
ODD
CONN
USB4
USB3
NEW Card
LCM CRT
WLAN
USB5
MDC / Modem
Module 56K
USB6
Bluetooth
SATA_0
SATA_1
SATA_5
USB7
CAMERA
USB9
USB8
FINGER PRINT
3.3V, AZALIA
Realtek
ALC 268
FELICA
FSB 677/800/1067
Cantiga
DMI
ICH9-M
MINI CARD
Boardcom
DDR2 Interface DDR2 Interface
Realtek
RTL8111C RTL8102E
CO-LAYOUT
RJ45
DDR II _SODIMM0
667/800 MHz
3.3V, PCI_Interface,33MHz
MINI CARD
NEWCARD
Wireless LAN
ANT
DDR II _SODIMM1
667/800 MHz
MINI CARD
TURBO MEMORY
ANT
RICOH_R5C833
CO-LAYOUT
R5C837
BATTERY
System Charger &
DC/DC System power
(IMVP-6
VR)
RJ11
MIC
JACK
HP
JACK
SPEAKER
SPDIF
+ HP JACK
3.3V, LPC_Interface,33MHz
WINBOND
WPCE775
BIOS
SPI EEROM
CIR
CHANGE by
Loren
25-Feb-2008
Card reader
CONN
5 in 1
INVENTEC
TITLE
Potomac 10
CODE
SIZE
A3
DOC. NUMBER
1310A21699 A01
CS
SHEET
1394
CONN
OF
REV
603
Adapter
(90W)
AM4825P
0.01
AM4825P
ADP_PRES
KBC_PW_ON
5/3.3V
(TPS51125)
+V3LA
+V5A
+V3S
PC6014
+V5S
PC6014
BATT_CLK
BATT_DATA
CHARGER
SCL
SDA
ACOK
0.01
ACIN#
+VPACK
SLP_S4#_3R
SLP_S3#_5R
DFGT_VID [ 0 : 4 ]
VCCDRE_EN
H_VID [ 0 : 6 ]
IMVP_CKEN#
PM_DPRSLPVR
DFGT_VR_EN
EN_PSV
TPS51117
EN_PSV
TPS51117
VO
VO
VID [ 0: 4 ] EN_PSV
VR_ON
VID [ 0 : 6 ]
CLK_EN#
DPRSLPVR
+V1.8A
VO
PM6650
TPS51620RHAR
VOUT
G2997
APL5913
+VCCP
CHANGE by
+VGFX
+VCC_CORE
Loren 4-Feb-2008
+V0.9S
+V1.5S
INVENTEC
TITLE
Potomac 10
DOC. NUMBER
CODE
SIZE
A3
1310A21699 A01
CS
SHEET
REV
OF
604
CN600
1
1
2
2
3
3
4
4
ACES_91202_0047L_TSB_4P
FUSE601
12
8A_125V
C606
1
10pF_50v
2
+VADPTR
5-
1 2
C605
0.1uF_50v
+VADPTR
5-
NFM60R30T222
ROHM_RLZ24D12
L600
12
34
1
1
R3
1K_5%
2
1
MMBT3904
R2
10K_5%
2
D608
1 2
PDS1040S
1
B
Q1
3
R5
432K_1%
3
C
E
2
1
2
1
R621
33K_1%
2
1
2
ACPRES
CHG_EN
TP2051
0.01uF_50v
C600
47uF_35v
C619
1 2
TP2052
C607
1 2
R4
12
10_5%
R600
12
4.7K_5%
R601
12
4.7K_5%
BAT54S_30V_0.2A
OPEN
41-
41-
D2
1
2
1
2
Q603
AM4825P_AP
1
S
2 3 4
G
2
3
1
R616
47K_5%
C616
1uF_10v
R614
100K_5%
8
D
7 6 5
1
2
+V5LA
5-,6-,7-,12-,18-,48-
C621
0.1uF_25v
+V5LA
1
100K_5%
1 2
5-,6-,7-,12-,18-,48-
1
R613
8.06K_1%
2 1
R619
39.2K_1%
2
41-
1
R617
22.6K_1%
2
R622
2
R606
1
0.01_1%_1W
C620
12
0.1uF_25v
NEAR IC
BATT_IN
R623
200K_5%
+VBAT
6-,7-,8-,9-,10-,11-,58-
Q600
1
2
0.01uF_50v12
L602
12
1
R624
OPEN
2 1
C628
OPEN
2
C601
C609
1
10uF_25v_K_X5R
2
ACDRV#
BATDRV#
PVCC
HIDRV
BTST
REGN
LODRV
PGND SYNP SYNN
ISYNSET
SYS
PH
SRP SRN BAT
EAO
EAI
FBO
TML
C625
1 2
0.1uF_25v
2
23
24
32
30
29
R1200
12
31
4.7_5%
28
EMI
27 26 22 21 20 19 18
7
8 9
16 33
C627
1 2
10uF_25v_K_X5R
C6
1
4.7uF_25v
2
NEAR IC
R1199
12
OPEN
EMI
D611
12
3
1
1
R643
100K_5%
2
2
C623
BAT54AW
R618
200K_5%
12
1
R615
18K_5%
2
C615
1 2
100pF_50v
0.1uF_25v
C624
1
1uF_10v
2
8765
G
23
41
765
8
G
4
123
C618
1
56pF_50v
2
D
S
D
S
Q605
FDS8884
Q604
FDS8884
1
2
1 2
1
PLC0755P_10uH_3.9A
D612
40V_3A_1W2
R620
10K_5%
C617
1500pF_50v
C626
1 2
C622
1
0.1uF_25v
2
10uF_25v_K_X5R
U600
12
VCC
3
ACN
4
ACP
6
BYPASS#
5
ACDET
11
VREF5
10
AGND
15
TS
6-
THRM1
1
CHGEN#
14
SCL
13
SDA
25
ALARM#
TP2043
17
IOUT
TI_BQ24721C_QFN_32P
C1058
1 2
OPEN
1
S
2 3
AM4825P_AP
12
0.01_1%_1W
C641
0.1uF_25v
NEAR IC
C640
1 2
0.1uF_25v
G
R607
12
D
8 7 6 54
C639
1 2
0.22uF_25v
+VPACK
6-
C608
1
10uF_25v_K_X5R
2
2
EC_CLK
EC_DATA
18-,41-
18-,41-
Loren 4-Feb-2008
INVENTEC
TITLE
Potomac 10
SIZE
CODE DOC. NUMBER
A3
1310A21699 A01
CS
REV
OFSHEETCHANGE by
605
+VBAT
5-,7-,8-,9-,10-,11-,58-
1 R642
1M_5%
2
1 R641
56.2K_1%
2
1 R644
180K_1%
2
BATT_DATA
BATT_CLK
C638
1
OPEN
2
BAT_ID
THRM1
+V3LA
7-,12-,18-,31-,38-,41-,48-,55-,56-
1
R608
47K_5%
2
41-
5­41­41-
13
12
R603 1K_5%
U2
3
LTH
RESET#
2
GND HTH
VCC
1
GMT_G680LT1_SOT23_5P
D600
CHENMKO_BAT54_3P_OPEN
12
R935
2
1
R936 33_5%
EZJZ0V500AA
4
7-,41-
5
+V5AUXON
33_5%
D666
+V5LA
1 2
1
1
2
2
5-,7-,12-,18-,48-
C637
0.1uF_10v
+VPACK
5-
LITTLEFUSE_R451015_15A_65V
FUSE600
12
C602
1
1000pF_50v
D665
2
EZJZ0V500AA
CN601
1
BATT+
2
BATT+
3
ID
4
B-I
5
TS
6 7 8 9
ALLTOP_C144P3_109A_L_9P
G1
SMD
G
G2
SMC
G
G3
G
GND
G4
G
GND
CHANGE by
Loren
4-Feb-2008
INVENTEC
TITLE
SELECT & BATTERY CONN
CODE
SIZE
A3
CS
SHEET
DOC. NUMBER
660
REV
A011310A21699
OF
THRM_SHUTDWN#
EC_PW_ON
18-,41-
CHENMKO_BAT54_3P
R280
41-
12
10K_5%
D24 13
SSM3K7002FU
Q25
1
G
SSM3K7002FU
+V5LA
5-,6-,7-,12-,18-,48-
1
R279
10K_5%
2
CHENMKO_BAT54_3P
Q26
3
D
G
1
S
2
3
D
S
2
6-,7-,12-,18-,31-,38-,41-,48-,55-,56-
+V3LA
D23
13
R278
12
100K_5%
1 2
C304
0.1uF_10v
4
3
S
TPC6104
Q31
D
G
+V3A
8-,31-,32-,33-,34-,40-,41-,45-,51-,52-,55-,56-
1 2 5 6
1
R348
200_5%
2
+V3LA
6-,7-,12-,18-,31-,38-,41-,48-,55-,56-
PAD7
2
1
POWERPAD_2_0610
C342
OPEN
1 2
R391
6.8K_1%
1
2
1
R390
10K_1%
2
C341
1uF_10v
MPLC0730_3R3_5.7A
1
C316
1 2
2
330uF_6.3v
Q34
1
SSM3K7002FU
D31 13
CHENMKO_BAT54_3P
R394
12
OPEN
R393
12
OPEN
C339
12
0.1uF_25v
TI_TPS51125_QFN_24P
12
4.7uF_25v
4
C302
6-,41-
10uF_25v_K_X5R
C303
1
1
2
2
+V5AUXON
8D765
Q24
FDS8884
L16
12
G
S
3
12
8765
D
Q23
FDS6690AS
G
S
1
23
4
+V3LDO
C340
1
1
2
2
1uF_10v
D
G
S
R388
OPEN
C338
4.7uF_6.3v
3
2
1
R392
150K_1%
2
7 8
10 11
U27
R389
820K_5%
1
R419
150K_1%
2
25
TML
VO2 VREG3 VBST2
DRVL2
6
VFB2
ENTRIP2
EN0
SKIPSEL
13
1
2
5
TONSEL
GND
14
1 2
4
15
3
1
2
VFB1
VREF
ENTRIP1
VO1
PGOOD
VBST1
DRVH1DRVH2
DRVL1
VREG5
VCLK
VIN
17
18
16
C336
2.2uF_25v
+VBAT
5-,6-,8-,9-,10-,11-,58-
PAD6
POWERPAD_2_0610
C373
12
1uF_6.3v
0.1uF_25v
24
C370
23
12
229 21 20
LL1LL2
1912
+V5LA
5-,6-,7-,12-,18-,48-
C337
1
10uF_6.3v
2
G
41S23
5
G
4
8765
D
8
76
D
S
123
10uF_25v_K_X5R
1 2
Q30
FDS8884
Q32
FDS6690AS
C315
L22
12
C369
330uF_6.3v
10uF_25v_K_X5R
C314
1 2
MPLC0730_3R3_5.7A
1
2
1 2
C372
1uF_10v
1
R422
15.4K_1%
2
1
R420
10K_1%
2
C371
1 2
OPEN
SKIPSEL
TONSEL
+V5A
PAD8
POWERPAD_2_0610
>>VRE3 OR VRE5=OOA
>>VREF=ASKIP
>>GND=PWM
>>VRE5=365/460
>>VRE3=300/375 >>VREF=245/305
>>GND=200/250
8-,9-,10-,11-,12-,34-,38-,39-,43-,44-,55-
INVENTEC
TITLE
SYSTEM POWER(3V/5V/12V)
CODE
Loren 4-Feb-2008
SIZE
A3
DOC. NUMBER
1310A21699 A01
CS
SHEETCHANGE by
REV
OF
607
7-,8-,9-,10-,11-,12-,34-,38-,39-,43-,44-,55-
+V5A
+VBAT
5-,6-,7-,9-,10-,11-,58-
PAD2
POWERPAD_2_0610
SLP_S5#_3R
12-,18-,29-,30-,32-,34-,36-,37-,39-,41-,42-,43-,50-,55-,58-
SLP_S3#_3R
8-,12-,32-,41-
10K_5%_OPEN
8-,11-,12-,32-,41-
R131
1
+V5S
C92
OPEN
1 2
C59
2.2uF_6.3v
R35
10_5%
2
1 2
+V1.8
8-,19-,23-,24-,26-,27-,58-
C93
OPEN
1 2
R59
2
1
274K_1%
U4
1 2 3 4 5 6 7
EN_PSV TON VOUT V5FILT VFB PGOOD GND
VBST DRVH
V5DRV
DRVL PGND
LL
TRIP
TML
TI_TPS51117_QFN_14P
2.2_5%
15K_1%
C91
0.1uF_25v
12
C693
1
2.2uF_6.3v
2
R56
12
12
R34
14 13 12 11 10 9 8 15
SLP_S5#_3R SLP_S3#_3R
C760
C151
1
2.2uF_6.3v
2
U8
6
VCNTL
7
POK
8
EN
VIN 9
1
C152
1
2
2
OPEN
5
VIN
3
VOUT
4
VOUT
2
FB
GND
1
ANPEC_APL5912_KAC_TRL_SOP_8P
1 2
22uF_6.3v
1 2
C150
39pF_50v
SLP_S3_5R
1
R130
9.1K_1%
2
1
R129
10K_1%
2
12-
C149
1 2
22uF_6.3v
PAD5
POWERPAD_2_0610
C148
1
2.2uF_6.3v
2
SSM3K7002FU
+V1.5S
16-,24-,34-,43-,51-,52-,53-,58-
1
R128
200_5%
2
Q15
3
D
G
1
S
2
M_VREF
8765
D
G
Q4
FDS8884
S
41
23
8
765
D
G
S
123
4
Q5
FDS6690AS
8-,12-,32-,41-
8-,11-,12-,32-,41-
19-,26-,27-
+V3A
7-,31-,32-,33-,34-,40-,41-,45-,51-,52-,55-,56-
1 2
1 2
1 2
C722
0.1uF_10v
C268
1uF_10v
C14
C13
1 2
4.7uF_25v
10uF_25v_K_X5R
L3
12
MPLC0730_2R2_7.3A
+V5A
7-,8-,9-,10-,11-,12-,34-,38-,39-,43-,44-,55-
C697
1 2
1uF_10v
U19
IN1OUT
3
SHDN#
GND 2
CHANGE by
1
2
1
220uF_2v_15mR_Panasonic
2
U606
TML1VDDQSNS VIN VLDOIN S5
VTT GND4PGND S3
VTTSNS
VTTREF
1 2
R58
14.3K_1%
R36
10K_1%
11 10
9 8 7 6
GMT_G2997F6U_MSOP10_10P
+V1.5A
12-,34-
5
4
SET
GMT_G916T1Uf_SOT23_5_5P
Loren
OPEN
C94
2 3
5
C23
1
R242
2.1K_1%
2
1
R241
10K_1%
2
+V1.8
1 2
1
1
10uF_6.3v
2
2
8-,19-,23-,24-,26-,27-,58-
C696
1
22uF_6.3v
2
C269
1 2
4.7uF_6.3v
4-Feb-2008
8-,19-,23-,24-,26-,27-,58-
+V1.8
PAD3
POWERPAD_2_0610
C22
+V0.9S
28-,58-
PAD605
POWERPAD_2_0610
C695
22uF_6.3v
INVENTEC
TITLE
Potomac 10
SYSTEM POWER(+V1.8/+V1.25S)
A3
DOC. NUMBERSIZE
1310A21699 A01
CS
SHEET
REVCODE
OF
608
7-,8-,10-,11-,12-,34-,38-,39-,43-,44-,55-
+V5A
+VBAT
5-,6-,7-,8-,10-,11-,58-
PAD601
POWERPAD_2_0610
SLP_S3#_5R
12-
R662
12
100K_5%
VCCP_PG
+V3S
9-,10-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,40-,41-,42-,43-,44-,45-,47-,48-,49-,50-,51-,52-,53-,55-,58-
1
R143
10K_5%
2
11-
C657
0.1uF_10v
1 2
C656
2.2uF_6.3v
C908
1 2
10uF_6.3v
1
R659
10_5%
2
1 2
R942
12
10K_5%
R664
2
274K_1%
U604
1
EN_PSV
2
TON
3
VOUT
4
V5FILT
5
VFB
6
PGOOD
7
1
TI_TPS51117_QFN_14P
2
U37
IN
SHDN#
GND
2
GND
5
OUT
4
SET
C655
OPEN
1
3
GMT_G916T1Uf_SOT23_5_5P
1
DRVH
V5DRV
PGND
VBST
DRVL
8765
D
G
Q611
FDS8878
41S23
8
765
D
G
S
123
4
Q610
FDS8672S
2.2_5%
2
11.5K_1%
C659
0.1uF_25v
12
C658
1
2.2uF_6.3v
2
R665
1
12
R663
14 13 12
LL
11
TRIP
10 9 8 15
TML
+V1.8S+V3S +VCCP
PAD9032
1
R941
4.7K_1%
2
1
R943
10K_1%
2
1 2
C909
10uF_6.3v
POWERPAD_2_0610
C667
1 2
10uF_25v_K_X5R
L607
12
MPLC0730_1R0_10.6A
4.12K_1%
10K_1%
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,58-
R660
R661
1
2
1
2
1
OPEN
C654
2
C680
1
2
330uF_2v_15mR_Panasonic
+VGFX_CORE
PAD100
POWERPAD_2_0610
1
10uF_6.3v
2
10-,23-38-9-,10-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,40-,41-,42-,43-,44-,45-,47-,48-,49-,50-,51-,52-,53-,55-,58-
C678
PAD603
POWERPAD_2_0610
+VCCP
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,58-
CHANGE by
Loren
4-Feb-2008
INVENTEC
TITLE
Potomac 10
GRAPHIC POWER (+VCCP/+V1.8S)
SIZE REVDOC. NUMBER
CODE
A3
1310A21699 A01
CS
SHEET
OF
609
VSS_AXG_SENSE
VCC_AXG_SENSE
23-
C649
OPEN
23-
R653
12
OPEN
1 2
R655
12
OPEN
1
R654
OPEN
2
DFGT_VR_EN
DFGT_VID_0
DFGT_VID_1
DFGT_VID_2
DFGT_VID_3
DFGT_VID_4
+V3S
R101
2
12
12
12
12
12
1
1 2
OPEN
R648
OPEN
R649
OPEN
R650
OPEN
R651
OPEN
R652
OPEN
C631
OPEN
1
31
32
27
28
30
33
U603
1
NC
TML-PAD
2
GSNS
3
VSNS
4
CSNS
5
VOUT
6
COMP
7
VDAC
8
NC
9
R632
OPEN
25
NC
NC
VID026VID1
VID229VID3
VID4
SHDN
OSC14PG
PMF10PMO
SKIP
NC
ILIM
NC
ST_PM6650_VFQPFN_32P_OPEN
13
11
15
16
12
1
1
R631
OPEN
2
2
19­19-
19-
19-
19-
19-
C632
OPEN
2
1
1
R9075
OPEN
2
BOOT HGATE PHASE
LGATE
R630
OPEN
NC
VCC
GND
NC
2
R647
12
OPEN
24 23 22 21 20 19 18 17
+VBAT
5-,6-,7-,8-,9-,10-,11-,58-
R646
12
OPEN
9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,40-,41-,42-,43-,44-,45-,47-,48-,49-,50-,51-,52-,53-,55-,58-
2
3 D620
1
C647
1 2
OPEN
+V5A
R645
12
OPEN
765
G
4
765
G
23
4
8
D
Q609
FDS8884_OPEN
S
123
8
D
S
1
Q608
FDS6690AS_OPEN
C664
1 2
4.7uF_25v_OPEN
2
10uF_25v_K_X5R_OPEN
MPLC0730_2R2_7.3A_OPEN
1
R666
OPEN
7-,8-,9-,11-,12-,34-,38-,39-,43-,44-,55-
BAT54AW_OPEN
C646
12
OPEN
PAD600
POWERPAD_2_0610
C663
1 2
L606
12
R667
12
OPEN
C650
12
OPEN
+VBAT
5-,6-,7-,8-,9-,10-,11-,58-
1
C665
2
560uF_2.5v_OPEN
POWERPAD_2_0610
C666
1 2
10uF_6.3v_OPEN
+VGFX_CORE
9-,23-
PAD602
INVENTEC
TITLE
Potomac 10
SYSTEM POWER(+VGFX_CORE)
CODE
SIZE
CHANGE by OF
Loren
4-Feb-2008
A3
CS
SHEET
DOC. NUMBER
10 60
REV
A011310A21699
SLP_S3#_3R
8-,12-,32-,41-
VR_PWRGD
VR_PWRGD
IMVP_CKEN#
C1006
1
2
1000pF_50v
VCOREGND
R144
2
VCOREGND
C1000
4700pF_25v
C1003
18pF_50v
C1005
680pF_50v
R1005
12
100K_5%
TP2053
TP2054
11-
5
3
1000pF_50v
12
180K_1%
1 2
12
C159
0.1uF_10v
U10
4
PHP_74LVC1G17_SOT753_5P
R929
12
OPEN
R133
12
499_1%
1
EN
2
PWRGD
12
3
PGDELAY
4
CLKEN
5
FBRTN
6
FB
7
COMP
8
SS
9
ST
10
VARFREQ
11
VRTT
12
TTSEN
115K_1%
1
C1007
2
VCOREGND
9-
VCCP_PG
1
3
D19
BAT54C
2
R142
12
11-,18-,32-
R1000
10K_5%
C1001
330pF_50v
+V3S
11-,18-,32-
12
R1002
1.65K_1%
+V5A
12
180K_1%
9-,10-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,40-,41-,42-,43-,44-,45-,47-,48-,49-,50-,51-,52-,53-,55-,58-
H_DPRSTP#
PM_DPRSLPVR
1
1
R1001
10K_5%
2
2
VCORE_EN
H_VID6 H_VID5 H_VID4 H_VID3 H_VID2 H_VID1 H_VID0
PSI#
11-,41-
1 2
C158
1uF_10v
16­16­16­16­16-
16­16­15-
15-,19-,31-
19-,32-
12
R1003
12
12
61.9K_1%
VCCSENSE
VSSSENSE
1 2
1 2
CSREF
C1002
220pF_25v
1
R1004
1
432K_1%
R117
0_5%
R119
0_5%
R1006
OPEN
C1004
2
2
0.012uF_16v
VCOREGND
7-,8-,9-,10-,11-,12-,34-,38-,39-,43-,44-,55-
12
16-
12
16-
+V3S
9-,10-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,40-,41-,42-,43-,44-,45-,47-,48-,49-,50-,51-,52-,53-,55-,58-
5
U11
4
2
PHP_74LVC1G17_SOT753_5P
3
C160
1uF_10v
19-,32-
41
40
39
45
44
43
TML
48
U6
13
47
DPRSLP
DPRSTP
PMONFS
PMON
14
42
46
PSI
VID3
VID4
VID5
VID0
VID1
VID2
VRPM
LLINE
RAMP22RPM23RT SP
CLIM
CSCOMP
CSFEF18CSSUM
21
16
20
15
17
19
49
ADI_ADP3208_LFCSP_48P
2
1
2
R1010
274K_1%
1
1
R1007
VCOREGND
1 2
2
VCOREGND
1
C1010
1000pF_50v
2
PM_PWROK
VCOREGND
37
38
VCC
VID6
BST1
DRVH1
SW1 PVCC1 DRVL1 PGND1 PGND2 DRVL2 PVCC2
SW2 DRVH2
BST2
GND
24
R1008
237K_1%
12
R1009
80.6K_1%
12
C1008
1000pF_50v
R1011
12
10K_5%
C1009
1000pF_50v
36 35 34 33 32 31 30 29 28 27 26 25
VCOREGND
R1012
12
105K_1%
R1013
12
105K_1%
1
C1011
1000pF_50v
2
R1050
12
0_5%
R1018
12
2.2_5%
R1019
12
2.2_5%
+VBAT_CPU
12
115K_1%
1
R6001
10K_5%
2
12
C1012
1
2.2uF_6.3v
2
11-
R1014
FINE_TUNE
11-,41-
VCORE_EN
+V5A
7-,8-,9-,10-,11-,12-,34-,38-,39-,43-,44-,55-
R1017
10_5%
D664
3
1
BAT54A_30V_0.2A
C1013
12
0.1uF_25v
C1014
12
0.1uF_25v
2
R1015
76.8K_1%
1
+VBAT
5-,6-,7-,8-,9-,10-,58-
1
4
L2
NFM60R30T222
3
2
1 2
10uF_25v_K_X5R
2
1
C1015
2
2.2uF_6.3v
C25
1 2
10uF_25v_K_X5R
1
R1016
220K_5%
2
C61
C62
1 2
0.01uF_50v
10uF_25v_K_X5R
R898
12
OPEN
C24
1 2
0.01uF_50v
10uF_25v_K_X5R
R899
12
OPEN
+VBAT_CPU
11-
C60
1 2
C20
1 2
CHANGE by
9
5678
G
Q11
SI7686DP_T1_E3
4321
8
765
9
D
1S23
Q12
FDMS8660S
R62
OPEN
C97
OPEN
G
4
56789
G
Q10
SI7686DP_T1_E3
321
4
9
8765
1
D
R721
G
OPEN
C704
OPEN
Q6
FDMS8660S
2
1 2
41S23
Loren 4-Feb-2008
1
1
D4
2
2
SSM34_3A40V_OPEN
1 2
D621
1 2
SSM34_3A40V_OPEN
L622
1
CSREF
2
11-
L617
1
2
ETQP4LR36WFC_PANASONIC
ETQP4LR36WFC_PANASONIC
INVENTEC
TITLE
Potomac 10
CPU POWER(VCC_CORE)
SIZE
A3
CS
SHEET
+VCC_CORE
16-
2
R1020
10_1%
1
2
R1021
10_1%
1
1310A21699 A01
REVDOC. NUMBERCODE
OF
6011
8
U28-A
74ACT14MTC
14
7
5-,6-,7-,12-,18-,48-
12
U28-E
74ACT14MTC
+V5LA
+V3S
14
1110
+V3
7
Q36
1
S
D
2 5 6
C376
22uF_6.3v
CHENMKO_BAT54_3P
SLP_S5#_5R
1
2
200_5%
12-
R424
TPC6104
1
2
1
3
D33
5-,6-,7-,12-,18-,48-
74ACT14MTC
G
1 2
3
1
CHENMKO_BAT54_3P
+V5LA
U28-B
4
3
C344
680pF_50v
D34
14
34
7
+V3LA
6-,7-,18-,31-,38-,41-,48-,55-,56-
1
R396
220K_5%
2
8-,11-,32-,41-
SLP_S3#_3R
4
S
TPC6104
5-,6-,7-,12-,18-,48-
Q35
1
D
2 5 63
G
C375
1 2
680pF_50v
+V5LA
14
U28-D
98
7
74ACT14MTC
9-,10-,11-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,40-,41-,42-,43-,44-,45-,47-,48-,49-,50-,51-,52-,53-,55-,58-
8-,34-
2
R423
1
2
R421
200_5%
200_5%
1
3
D
S
2
SSM3K7002FU
D40
2
3
1
BAT54A_30V_0.2A
SLP_S5#_5R
1
G
Q33
SLP_S5_3R
12-
12-
R453
220K_5%
R452
220K_5%
1
C374
2
47uF_6.3v
2
1
2
1
Q7
8
D
7 6
5
G
AO4406
12
220K_5%
R33
+V1.5+V1.5A
12
Q612 1
54-
1
R678
200_5%
2
3
D
G
S
2
1
S
2 3 4
C694
680pF_50v
SSM3K7002FU
12-
SLP_S5_3R
C343
0.1uF_10v
+V5LA
1 2
U28-C
74ACT14MTC
+V5A
7-,8-,9-,10-,11-,34-,38-,39-,43-,44-,55-
Q38
1
4
S
D
TPC6104
4
S
TPC6104
C409
12
680pF_50v
2 5 63
G
Q39
1
D
2 5 63
G
14
56
8-,32-,41-
SLP_S5#_3R
7
5-,6-,7-,12-,18-,48-
+V5S
-,12-,18-,29-,30-,32-,34-,36-,37-,39-,41-,42-,43-,50-,55-,58-
1
R395
SLP_S3#_5R
200_5%
CHENMKO_BAT54_3P
9-
D32
2
1
3
5-,6-,7-,12-,18-,48-
U28-F
74ACT14MTC
+V5LA
14
1312
7
CHANGE by
8-
SLP_S3_5R
+V5S
8-,12-,18-,29-,30-,32-,34-,36-,37-,39-,41-,42-,43-,50-,55-,58-
4-Feb-2008Loren
INVENTEC
TITLE
Potomac 10
POWER(SLEEP)
SIZE DOC. NUMBER
A3
CS
SHEET OF
12 60
REVCODE
A011310A21699
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,58-
FSB
15-,19­15-,19-
32-
FSC
1
0 0
1 0
0
CPU_BSEL1 CPU_BSEL2
CLK_R_SB14
FSA
1 0 0
+VCCP_CLK_VDD
+VCCP
L11
BLM11A121S
1
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,58-
1K_5%
R152
Layout note: All decoupling 0.1uF disperse closed to pin
2
C198
1
10uF_10v
2
1
R150
OPEN
2
12
10K_5%
R153
12
2
1
CLK_PWRGD
FSB CLOCK FREQUENCY
HOST CLOCK FREQUENCY
667 800
1066
166 200
266
R151
1 2
33_5%
C199
C167
1
10uF_10v
0.1uF_10v
2
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,58-
CPU_BSEL0
+VCCP
2
1K_5%
R154
1
CLKREQ_R_SATA#
CLKREQ_R_MCH# CLK_R_KBPCI CLK_R_CBPCI
32-
1
0.1uF_10v
2
C267
1 2
0.1uF_10v
1
0.1uF_10v
2
C164
C165
+VCCP
1
R238
1K_5%
2
R237
12
15-,19-
2.2K_5%
833:R=open 837:R=12.1_1%
12
1
32­19-
2
OPEN
ICH_3S_SMDATA
14.31818MHZ
12
1
30PPM
2
50-
32-
R228 R230
ICH_3S_SMCLK
X1
1 2
1
33_5%
R180 R179
C195
33pF_50v
R235
CLK_R_CARD48
CLK_R_SB48
41­49-
R178
C196
33pF_50v
Please place close to CLKGEN within 500mils
C265
1
0.1uF_10v
2
OPENR236
2
833:R=33_5% 837:R=12.1_1%
475_1%
12
475_1%
2
1
12
33_5%
12
33_5%
26-,27-,32­26-,27-,32-
+V3S
+V3S_CLK_VDD
9-,10-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,40-,41-,42-,43-,44-,45-,47-,48-,49-,50-,51-,52-,53-,55-,58-
C266
1
0.1uF_10v
2
9-,10-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,40-,41-,42-,43-,44-,45-,47-,48-,49-,50-,51-,52-,53-,55-,58-
+V3S
R177
R227
R176
2
12
1
2
1
10K_5%
10K_5%
10K_5%
CLK_SB48
CLK_SB14
CLKREQ_SATA# CLKREQ_MCH#
CLK_KBPCI CLK_CBPCI
1
R225
OPEN
2
L12
BLM11A121S
1
U12
26
VDDSRC_IO
45
VDDSRC_IO
36
VDDSRC_IO
12
VDD_IO
39
VDD_SRC
61
VDDREF
20
VDDPLL3_IO
49
VDDCPU_IO
9
VDD48
2
VDDPCI
55
VDDCPU
16
VDD_PLL3
10
USB_48MHZ_FSLA
57
FSLB_TEST_MODE
62
REF0_FSLC_TEST_SEL
1
PCI0_CR#_A
3
PCI1_CR#_B
4
PCI2_TME
5
SRC5_EN_PCI3
56
CK_PWRGD_PD#
64
SCLK
63
SDTAT
60
X1
59
X2
8
GNDPCI
11
GND48
15
GND_IO
19
GND_PLL3
23
GNDSRC
29
GNDSRC
42
GNDSRC
58
GNDREF
52
GNDCPU
REA_RTM875T_606_TSSOP_64P
Layout note: All decoupling 0.1uF disperse closed to pin
2
PCI_STOP#_SRCT5
CPU_STOP#_SRCC5
CPUT2_ITP_SRCT8 CPUC2_ITP_SRCC8
SRCT11_CR#_H SRCC11_CR#_G
PCI4_27M_Select
27MHz_NonSS_SRCT1_SE1
27MHz_SS_SRCC1_SE2
SRCT0_DOTT_96
SRCC0_DOTC_96
C197
1 2
10uF_10v
RESET#
CPUT1_F CPUC1_F
CPUT0
CPUC0
SRCT10 SRCC10
SRCT9
SRCC9
SRCT7_CR#_F
SRCC7_CR#_E
SRCT6
SRCC6
PCI_F5_ITP_EN
SRCT4
SRCC4
SRCT3_CR#_C
SRCC3_CR#_D
SRCT2_SATAT SRCC2_SATAC
C162
1 2
0.1uF_10v
48
38 37
51 50
CLK_CPUBCLK
54
CLK_CPUBCLK#
53
CLK_PCIE_NCARD
47
CLK_PCIE_NCARD#
46
33 32
CLK_PCIE_ROBSON
34
CLK_PCIE_ROBSON#
35
CLK_PCIE_WLAN
30
CLK_PCIE_WLAN#
31
44 43
41 40
6 7
CLK_PEG_MCH
27
CLK_PEG_MCH#
28
CLK_PCIE_LAN
24
CLK_PCIE_LAN#
25
21
CLK_SATA1#
22
CLKSS1_DREF
17
CLKSS1_DREF#
18
CLK_DREF
13
CLK_DREF#
14
CLK_NBCLK CLK_NBCLK#
CLKREQ_ROBSON# CLKREQ_WLAN#
CLK_PCIE_SB CLK_PCIE_SB#
CLK_3S_MINICARD2 CLK_3S_ICHPCI
CLK_SATA1
9-,10-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,40-,41-,42-,43-,44-,45-,47-,48-,49-,50-,51-,52-,53-,55-,58-
C166
1 2
C163
0.1uF_10v
1 2
0.1uF_10v
1 2
C264
0.1uF_10v
10K_5%_OPEN
9-,10-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,40-,41-,42-,43-,44-,45-,47-,48-,49-,50-,51-,52-,53-,55-,58-
+V3S
1
1
R155
R156
10K_5%_OPEN
2
2
475_1%
12
475_1%
33_5% 33_5%
9-,10-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,40-,41-,42-,43-,44-,45-,47-,48-,49-,50-,51-,52-,53-,55-,58-
R158
12
R239
12
R231 R23212
+V3S
R157
10K_5%
+V3S
1
1
2
2
R240
10K_5%
32­32-
21­21-
14­14-
51-
51-
52­52-
52­52-
52­52-
53­53-
32­32-
52-
CLK_R_MINICARD2
33-
CLK_R_ICHPCI
19­19-
45­45-
31­31-
19­19-
19-
19-
PCISTOP#_3 CPUSTOP#_3
CLK_NBCLK CLK_NBCLK#
CLK_CPUBCLK CLK_CPUBCLK#
CLK_PCIE_NCARD CLK_PCIE_NCARD#
CLKREQ_R_ROBSON# CLKREQ_R_WLAN#
CLK_PCIE_ROBSON CLK_PCIE_ROBSON#
CLK_PCIE_WLAN CLK_PCIE_WLAN#
CLK_PCIE_HDDVD CLK_PCIE_HDDVD#
CLK_PCIE_SB CLK_PCIE_SB#
CLK_PEG_MCH CLK_PEG_MCH#
CLK_PCIE_LAN CLK_PCIE_LAN#
CLK_SATA1 CLK_SATA1#
CLKSS1_DREF CLKSS1_DREF#
CLK_DREF
CLK_DREF#
*CLKREQ# pin controls SRC Table.
Byte5: bit6 =0(PWD)
SRC0
CR#_A
Byte5: bit7=0, disable CR#_A; 1,enable CR#_A
Byte5: bit2 =0(PWD)
SRC0
CR#_C
Byte5: bit3=0, disable CR#_C; 1,enable CR#_C
Byte5: bit6 =1
SRC2
Byte5: bit2 =1
SRC2
CR#_B
CR#_D
Byte5: bit4 =0(PWD)
SRC1
Byte5: bit4 =1
SRC4
Byte5: bit5=0, disable CR#_B; 1,enable CR#_B
Byte5: bit0 =0(PWD)
SRC1
Byte5: bit0 =1
SRC4
Byte5: bit1=0, disable CR#_D; 1,enable CR#_D
Byte6: bit7=0, disable CR#_E; 1,enable CR#_E
CR#_E
SRC6
Byte6: bit6=0, disable CR#_F; 1,enable CR#_F
CR#_F
SRC8
Byte6: bit5=0, disable CR#_G; 1,enable CR#_G
CR#_G
SRC9
Byte6: bit4=0, disable CR#_H; 1,enable CR#_H
CR#_H
SRC10
10K_5%
CHANGE by
R234
R940
1
2
12
OPEN
1
2
R233
10K_5%
27_Select=0
LCD_SST 100MHz
27_Select=1
27MHz NON-SPREAD CLOCK
INVENTEC
TITLE
Potomac 10
CLOCK_GENERATOR
Loren
4-Feb-2008
SIZE
A3
CODE
CS
SHEET
DOC. NUMBER
13 60
REV
A011310A21699
OF
H_A#(35:3)
H_ADSTB#1
H_STPCLK#
H_A20M# H_FERR#
H_IGNNE#
H_INTR
H_NMI
H_SMI#
21-
H_A#(3) H_A#(4) H_A#(5) H_A#(6) H_A#(7) H_A#(8) H_A#(9) H_A#(10) H_A#(11) H_A#(12) H_A#(13) H_A#(14) H_A#(15) H_A#(16)
H_REQ#(4:0) H_RS#(2:0)
H_A#(17) H_A#(18) H_A#(19) H_A#(20) H_A#(21) H_A#(22) H_A#(23) H_A#(24) H_A#(25) H_A#(26) H_A#(27) H_A#(28) H_A#(29) H_A#(30) H_A#(31) H_A#(32) H_A#(33) H_A#(34) H_A#(35)
21-
31­31­31-
31­31­31­31-
21- 21-
H_REQ#(0) H_REQ#(1) H_REQ#(2) H_REQ#(3) H_REQ#(4)
H_ADSTB#0
21-
CN606-1
J4
A3#
L5
A4#
L4
A5#
K5
A6#
M3
A7#
N2
A8#
J1
A9#
N3
A10#
P5
A11#
P2
A12#
L2
A13#
P4
A14#
P1
A15#
R1
A16#
M1
ADSTB0#
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L1
REQ4#
Y2
A17#
U5
A18#
R3
A19#
W6
A20#
U4
A21#
Y5
A22#
U1
A23#
R4
A24#
T5
A25#
T3
A26#
W2
A27#
W5
A28#
Y4
A29#
U2
A30#
V4
A31#
W3
A32#
AA4
A33#
AB2
A34#
AA3
A35#
V1
ADSTB1#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD01
N5
RSVD02
T2
RSVD03
V3
RSVD04
B2
RSVD05
C3
RSVD06
D2
RSVD07
D22
RSVD08
D3
RSVD09
F6
RSVD010
FOX_PZ4782K_274M_41_478P
GMCH
CPU
ADS# BNR# BPRI#
DEFER#
DRDY# DBSY#
BR0#
IERR#
ADDR GROUP 0
INIT#
CONTROL
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
HIT#
HITM#
BPM0# BPM1# BPM2# BPM3# PRDY# PREQ#
TCK
ADDR GROUP 1
TDO TMS
XDP/ITP SIGNALS
TRST#
DBR#
THERMAL
PROCHOT#
THERMDA THERMDC
THERMTRIP#
ICH
H CLK
BCLK0 BCLK1
RESERVED
H1 E2 G5
H5 F21 E1
F1
D20 B3
H4
C1 F3 F4 G3 G2
G6 E4
AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6
TDI
AB3 AB5 AB6 C20
D21 A24 B25
C7
A22 A21
ICH8
R718
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,58-
56_5%12
+VCCP
+VCCP
10mils/10mils
21-
H_ADS#
21-
H_BNR#
21-
H_BPRI#
21-
H_DEFER#
21-
H_DRDY#
21-
H_DBSY#
21-
H_BREQ#0
31-
H_INIT#
21-
H_LOCK#
21-
H_CPURST#
21-
H_TRDY#
21-
H_HIT#
21-
H_HITM#
14-
H_BPM5_PREQ#
14-
H_TCK
14-
TDI_FLEX
14-
H_TMS
32-
XDP_DBRESET#
18-
H_THERMDA
18-
THERM_MINUS
18-,19-,31-
PM_THRMTRIP#
13-
CLK_CPUBCLK
13-
CLK_CPUBCLK#
+VCCP
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,58-
+VCCP
R765
12
OPEN
H_RS#(0) H_RS#(1) H_RS#(2)
R121
12
54.9_1%
R124
12
54.9_1%
R123
1
2
54.9_1%
R120
12
54.9_1%
+VCCP
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,58-
1
R717
56_5%
2
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,58-
1
R122
54.9_1%
2
14-
H_BPM5_PREQ#
14-
TDI_FLEX
14-
H_TMS
14-
H_TCK
CLOSED TO CPU
51 ohm +/-1% pull-up to +VCCP (VCCP) if ITP is implemented
PM_THRMTRIP# should be T at CPU
CHANGE by
Loren
4-Feb-2008
INVENTEC
TITLE
Potomac 10
PENRYN-1
CODE
SIZE
A3
DOC. NUMBER
1310A21699 A01
CS
SHEET
REV
OF
6014
H_D#(63:0)
H_DSTBN#0 H_DSTBP#0
H_DINV#0
+VCCP
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,58-
1
R704
1K_1%
2
1
2
R703
2K_1%
GTLREF
Layout note: Zo=55 ohm,
0.5" max for GTLREF.
15-,21-
21­21­21-
15-,21-
H_DSTBN#1
H_DSTBP#1
H_DINV#1
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
CN606-2
H_D#(0) H_D#(1) H_D#(2) H_D#(3) H_D#(4) H_D#(5) H_D#(6) H_D#(7) H_D#(8) H_D#(9) H_D#(10) H_D#(11) H_D#(12) H_D#(13) H_D#(14) H_D#(15)
H_D#(16) H_D#(17) H_D#(18) H_D#(19) H_D#(20) H_D#(21) H_D#(22) H_D#(23) H_D#(24) H_D#(25) H_D#(26) H_D#(27) H_D#(28) H_D#(29) H_D#(30) H_D#(31)
21­21­21-
13-,19­13-,19­13-,19-
1
2
R719
OPEN
1
2
R720
OPEN
C135
1 2
OPEN
Place C642(0.1uF_16V) close to the TEST4 pin. Make sure TEST4 routing is reference
to GND and away from other noisy signals.
E22
D0#
F24
D1#
E26
D2#
G22
D3#
F23
D4#
G25
D5#
E25
D6#
E23
D7#
K24
D8#
G24
DATA GRP 0
D9#
J24
D10#
J23
D11#
H22
D12#
F26
D13#
K22
D14#
H23
D15#
J26
DSTBN0#
H26
DSTBP0#
H25
DINV0#
N22
D16#
K25
D17#
P26
D18#
R23
D19#
L23
D20#
M24
D21#
L22
D22#
M23
D23#
P25
D24#
P23
D25#
P22
DATA GRP 1
D26#
T24
D27#
R24
D28#
L25
D29#
T25
D30#
N25
D31#
L26
DSTBN1#
M26
DSTBP1#
N24
DINV1#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
MISC
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL0
B23
BSEL1
C21
BSEL2
FOX_PZ4782K_274M_41_478P
D32# D33# D34# D35# D36# D37# D38# D39# D40#
DATA GRP 2DATA GRP 3
D41# D42# D43# D44# D45# D46#
D47# DSTBN2# DSTBP2#
DINV2#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63# DSTBN3# DSTBP3#
DINV3#
COMP0 COMP1 COMP2 COMP3
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
R26 U26 AA1 Y1
E5 B5 D24 D6 D7 AE6
1
R764
OPEN
2
11-,19-,31-
H_D#(32) H_D#(33) H_D#(34) H_D#(35) H_D#(36) H_D#(37) H_D#(38) H_D#(39) H_D#(40) H_D#(41) H_D#(42) H_D#(43) H_D#(44) H_D#(45) H_D#(46) H_D#(47)
H_D#(48) H_D#(49) H_D#(50) H_D#(51) H_D#(52) H_D#(53) H_D#(54) H_D#(55) H_D#(56) H_D#(57) H_D#(58) H_D#(59) H_D#(60) H_D#(61) H_D#(62) H_D#(63)
12
27.4_1%R701
12
54.9_1%R702
12
R125 27.4_1%
12
54.9_1%R126
H_DPRSTP#
CLOSED TO CPU
31­21­31­21­11-
+VCCP
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,58-
21­21­21-
H_DPSLP# H_DPWR# H_PWRGD H_CPUSLP# PSI#
H_DSTBN#3 H_DSTBP#3 H_DINV#3
15-,21-
15-,21-
21­21­21-
H_D#(63:0)
H_DSTBN#2 H_DSTBP#2 H_DINV#2
H_D#(63:0)H_D#(63:0)
INVENTEC
TITLE
Potomac 10
PENRYN-2
SIZE
CODE
DOC. NUMBER REV
CHANGE by OF
Loren 4-Feb-2008
A3
1310A21699 A01
CS
SHEET
6015
C98
900uF_2.5v
+VCC_CORE
11-,16-
12
3
CN606-3
A7
VCC001
A9
VCC002
A10
VCC003
A12
VCC004
A13
VCC005
A15
VCC006
A17
VCC007
A18
VCC008
A20
VCC009
B7
VCC010
B9
VCC011
B10
VCC012
B12
VCC013
B14
VCC014
B15
VCC015
B17
VCC016
B18
VCC017
B20
VCC018
C9
VCC019
C10
VCC020
C12
VCC021
C13
VCC022
C15
VCC023
C17
VCC024
C18
VCC025
D9
VCC026
D10
VCC027
D12
VCC028
D14
VCC029
D15
VCC030
D17
VCC031
D18
VCC032
E7
VCC033
E9
VCC034
E10
VCC035
E12
VCC036
E13
VCC037
E15
VCC038
E17
VCC039
E18
VCC040
E20
VCC041
F7
VCC042
F9
VCC043
F10
VCC044
F12
VCC045
F14
VCC046
F15
VCC047
F17
VCC048
F18
VCC049
F20
VCC050
AA7
VCC051
AA9
VCC052
AA10
VCC053
AA12
VCC054
AA13
VCC055
AA15
VCC056
AA17
VCC057
AA18
VCC058
AA20
VCC059
AB9
VCC060
AC10
VCC061
AB10
VCC062
AB12
VCC063
AB14
VCC064
AB15
VCC065
AB17
VCC066
AB18
VCC067
FOX_PZ4782K_274M_41_478P
VCC068 VCC069 VCC070 VCC071 VCC072 VCC073 VCC074 VCC075 VCC076 VCC077 VCC078 VCC079 VCC080 VCC081 VCC082 VCC083 VCC084 VCC085 VCC086 VCC087 VCC088 VCC089 VCC090 VCC091 VCC092 VCC093 VCC094 VCC095 VCC096 VCC097 VCC098 VCC099
VCC0100
VCCP01 VCCP02 VCCP03 VCCP04 VCCP05 VCCP06 VCCP07 VCCP08 VCCP09 VCCP10 VCCP11 VCCP12 VCCP13 VCCP14 VCCP15 VCCP16
VCCA01 VCCA02
VCCSENSE
VSSSENSE
+VCC_CORE
11-,16-
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
B26 C26
AD6
VID0
AF5
VID1
AE5
VID2
AF4
VID3
AE3
VID4
AF3
VID5
AE2
VID6
AF7
AE7
+VCCP
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,58-
1
C749
2
220uF_2v_15mR_Panasonic
11-
H_VID0
11-
H_VID1
11-
H_VID2
11-
H_VID3
11-
H_VID4
11-
H_VID5
11-
H_VID6
+VCC_CORE
11-,16-
1
R116
100_1%
2
1
R118
100_1%
2
11-
11-
+VCCP
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,58-
C752
1 2
0.1uF_10v
VCCSENSE
VSSSENSE
C751
1 2
0.1uF_10v
LAYOUT NOTE: PLACE C2461 NEAR PIN B26
PLACE THESE INSIDE SOCKET CAVITY ON L8 (NORTH SIDE SECONDARY)
C750
1 2
0.1uF_10v
0.1uF_10v
8-,24-,34-,43-,51-,52-,53-,58-
C726
1 2
0.01uF_16v
C703
1 2
+V1.5S
C725
0.1uF_10v
1 2
C727
1 2
0.1uF_10v
1
C702
10uF_6.3v
2
LAYOUT NOTE: ROUTE VCCSENSE AND VSSSENSE TRACE AT
24.7 OHM WITH 50 MIL SPACEING PLACE PU AND PD WITHIN I INCH OF CPU
CHANGE by
Loren
4-Feb-2008
INVENTEC
TITLE
Potomac 10
PENRYN-3
DOC. NUMBER
CODE
SIZE
A3
1310A21699 A01
CS
SHEET
REV
OF
6016
CN606-4
A4
VSS001
A8
VSS002
A11
VSS003
A14
VSS004
A16
VSS005
A19
VSS006
A23
VSS007
AF2
VSS008
B6
VSS009
B8
VSS010
B11
VSS011
B13
VSS012
B16
VSS013
B19
VSS014
B21
VSS015
B24
VSS016
C5
VSS017
C8
VSS018
C11
VSS019
C14
VSS020
C16
VSS021
C19
VSS022
C2
VSS023
C22
VSS024
C25
VSS025
D1
VSS026
D4
VSS027
D8
VSS028
D11
VSS029
D13
VSS030
D16
VSS031
D19
VSS032
D23
VSS033
D26
VSS034
E3
VSS035
E6
VSS036
E8
VSS037
E11
VSS038
E14
VSS039
E16
VSS040
E19
VSS041
E21
VSS042
E24
VSS043
F5
VSS044
F8
VSS045
F11
VSS046
F13
VSS047
F16
VSS048
F19
VSS049
F2
VSS050
F22
VSS051
F25
VSS052
G4
VSS053
G1
VSS054
G23
VSS055
G26
VSS056
H3
VSS057
H6
VSS058
H21
VSS059
H24
VSS060
J2
VSS061
J5
VSS062
J22
VSS063
J25
VSS064
K1
VSS065
K4
VSS066
K23
VSS067
K26
VSS068
L3
VSS069
L6
VSS070
L21
VSS071
L24
VSS072
M2
VSS073
M5
VSS074
M22
VSS075
M25
VSS076
N1
VSS077
N4
VSS078
N23
VSS079
N26
VSS080
P3
VSS081
FOX_PZ4782K_274M_41_478P
VSS082 VSS083 VSS084 VSS085 VSS086 VSS087 VSS088 VSS089 VSS090 VSS091 VSS092 VSS093 VSS094 VSS095 VSS096 VSS097 VSS098 VSS099 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
CHANGE by
INVENTEC
TITLE
Potomac 10
PENRYN-4
CODE
CS
SHEET
DOC. NUMBERSIZE
17 60
4-Feb-2008Loren
A3
REV
A011310A21699
OF
+V5S
8-,12-,29-,30-,32-,34-,36-,37-,39-,41-,42-,43-,50-,55-,58-
FAN1_DAC0_3
U1
1
C3
2.2uF_6.3v
41-
2
2
3
4
FON
VIN
VO
VSET
81
GND
7
GND
6
GND
5
GND
GMT_G995P1U_SOP8_8P
9-,10-,11-,12-,13-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,40-,41-,42-,43-,44-,45-,47-,48-,49-,50-,51-,52-,53-,55-,58-
C2
1 2
2.2uF_6.3v
1 2 3
CN602
1 2 3
G
G1 G2
G
ACES_85205_0300N_3P
FAN CN
+V5LA
5-,6-,7-,12-,48-
U609
R763
12
150_5%
1 2
C781
0.1uF_10v
5
43
HYST
GMT_G708T1U_SOT23_5P
SETVCC
GND
OT
R781
12
1
23.2K_1%
2
7-,18-,41-
Thermal shutdown at 88.5C +/-3C from 60C to 100C RSET=0.0012*T - 0.9308*T+96.147
2
Hysteresis is 30C
H_THERMDA
THERM_MINUS
THRM_SHUTDWN#
6-,7-,12-,18-,31-,38-,41-,48-,55-,56-
+V3LA
2
+V3S
1
R1
10K_5%
2
C1
1 2
0.01uF_50v
THRM_SHUTDWN#
14-
14-
7-,18-,41-
1
R145
OPEN
41-
FAN_TACH1
PM_THRMTRIP#
R149
12
330_5%
2SC2411K
11-,32-
Q17
2
1
R148
2M_5%
2
3
C
B
E
1
1 2
VR_PWRGD
14-,19-,31-
+V3LA
6-,7-,12-,18-,31-,38-,41-,48-,55-,56-
1
C136
2
C137
100pF_50v
12
0.1uF_10v
U7
1
VDD
2
DP
3
DN
4
THERM
SMSC_EMC1402_1_ACZL_MSOP_8P
SMCLK
SMDATA
ALERT
8
7
6
5
GND
Thermal Sensor For CPU
LAYOUT NOTES: PUT THE THERMAL SENSOR CLOSE TO CPU
CHANGE by
SSM3K7002FU
C161
OPEN
Loren
7-,18-,41-
THRM_SHUTDWN#
Q16
3
D
G
1
S
2
5-,41-
EC_CLK
5-,41-
EC_DATA
INVENTEC
TITLE
Potomac 10
THERMAL&FAN CONTROLLER
4-Feb-2008
SIZE
A3
CODE
CS
SHEET
DOC. NUMBER
18
REV
A011310A21699
OF
60
MCH_CFG(5)
MCH_CFG(13:12)
XOR/ALLZ
NOTE: CFG[2:0] STRP : 010b : 800 MT/S
MCH_CFG(5) MCH_CFG(6) MCH_CFG(7) MCH_CFG(9)
MCH_CFG(20)
MCH_CFG(10) MCH_CFG(12) MCH_CFG(13) MCH_CFG(16)
LOW=DMIx2
HIGH=DMIx4
00=PARTIAL CLOCK GATING DISABLE 01=XOR MODE ENABLE 10=ALL-Z MODE ENABLE 11=NORMAL OPERATION
011b : 667 MT/S
19­19­19­19­19-
1
R877
OPEN
2
19­19­19­19-
1
2
R736
OPEN
1
R68
2.2K_1%
2
MCH_CFG(7)
(CPU Strap)
1
2
1
R41
OPEN
2
R80
OPEN
LOW=RSVD HIGH=Mobile CPU
MCH_CFG(16) (FSB Dynamic ODT)
1
R81
OPEN
2
1
R40
OPEN
2
+V3S
9-,10-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,40-,41-,42-,43-,44-,45-,47-,48-,49-,50-,51-,52-,53-,55-,58-
R727 10K_5%
+V1.8
8-,19-,23-,24-,26-,27-,58-
1
R90
1K_1%
2
1
R88
3K_1%
2
1
R89
1K_1%
2
MCH_CFG(20) DIGITAL DISPLAY PORT(SDVO/DP/iHDMI) CONCURRENT WITH PCIE
12
12
VR_PWRGD_CK505
C739
1 2
0.01uF_16v
C741
1 2
0.01uF_16v
LOW=ONLY DIGITAL DISPLAY PORT
(SDVO/DP/iHDMI)OR PCIEIS OPERATIONAL
HIGH= DIGITAL DISPLAY PORT (SDVO/DP/iHDMI)AND PCIE ARE OPERATING
VIA THE PEG PORT
10K_5%R728
PM_PWROK
1 2
1 2
19-,26-
19-,27-
C737
2.2uF_6.3v
C738
2.2uF_6.3v
PM_EXTTS#0 PM_EXTTS#1
32-
11-,19-,32-
19-
SM_RCOMP_VOH
19-
SM_RCOMP_VOL
R105
0_5%_OPEN
1
2
12
1
R730
OPEN
2
R738
OPEN
MCH_CFG(9) PCIE Graphics Lane
LOW=Dynamic ODT
HIGH=Dynamic ODT
9-,10-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,40-,41-,42-,43-,44-,45-,47-,48-,49-,50-,51-,52-,53-,55-,58-
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
MCH_CFG(17:3)
MCH_CFG(19) MCH_CFG(20)
PM_SYNC#
H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1
PM_THRMTRIP#
PM_DPRSLPVR
MCH_CFG(19) (DMI LANE
REVERSAL)
Disable
Enable
MCH_CFG(9) MCH_CFG(19) MCH_CFG(20)
13-,15-
13-,15-
13-,15-
19-
PLT_RST#
LOW=NORMAL HIGH=LANES REVERSED
LOW=Reverse Lane HIGH=Normal operation
MCH_CFG(6)
iPTM
1
1
R741
R731
OPEN
OPEN
2
2
19-
19-
19-
R739 1K_5%
12
R733
1
R740
12
19­19-
32­11-,15-,31­19-,26­19-,27-
33-,41­14-,18-,31­11-,32-
R44
+V3S
1K_5%
2
1K_5%
MCH_CFG(3) MCH_CFG(4) MCH_CFG(5) MCH_CFG(6) MCH_CFG(7) MCH_CFG(8) MCH_CFG(9) MCH_CFG(10) MCH_CFG(11) MCH_CFG(12) MCH_CFG(13) MCH_CFG(14) MCH_CFG(15) MCH_CFG(16)
LOW=Enable
HIGH=Disable
1
R742
OPEN
2
12
NOTE :
USE 4K-OHM RESISTOR WHEN INSTALLING PULL-UP/PULL-DOWN RESISTOR ON ANY MCH-CFG CONNECTION/PINS.
U608-2
M36
RSVD1
N36
RSVD2
R33
RSVD3
T33
RSVD4
AH9
RSVD5
AH10
RSVD6
AH12
RSVD7
AH13
RSVD8
K12
RSVD9
AL34
RSVD10
AK34
RSVD11
AN35
RSVD12
AM35
RSVD13
T24
RSVD14
B31
RSVD15
AJ6
RSVD16
M1
RSVD17
AY21
RSVD20
A47
RSVD21
BG23
RSVD22
BF23
RSVD23
BH18
RSVD24
BF18
RSVD25
T25
CFG_0
R25
CFG_1
P25
CFG_2
P20
CFG_3
P24
CFG_4
C25
CFG_5
N24
CFG_6
M24
CFG_7
E21
CFG_8
C23
CFG_9
C24
CFG_10
N21
CFG_11
P21
CFG_12
T21
CFG_13
R20
CFG_14
M20
CFG_15
L21
100_5%
TP2002 TP2001
PM_SYNC#
H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1
PLT_RST#_R
PM_THRMTRIP#
AT40
AT11
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
H21
P29
R28
T28
R29
B7
N33
P32
T20
R32
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
ITL_CANTIGA_GM_FCBGA_1329P
AP24
SA_CK_0
AT21
SA_CK_1
AV24
SB_CK_0
AU20
SB_CK_1
AR24
SA_CK#_0
AR21
SA_CK#_1
AU24
SB_CK#_0
AV20
SB_CK#_1
BC28
SA_CKE_0
AY28
SA_CKE_1
AY36
SB_CKE_0
BB36
SB_CKE_1
BA17
SA_CS#_0
AY16
SA_CS#_1
AV16
SB_CS#_0
AR13
SB_CS#_1
BD17
SA_ODT_0
AY17
SA_ODT_1
BF15
SB_ODT_0
AY13
SB_ODT_1
BG22
SM_RCOMP
BH21
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
BF28
BH28
AV42
SM_VREF
AR36
SM_PWROK
BF17
SM_REXT
BC36
SM_DRAMRST#
B38
A38
E41
F41
F43
PEG_CLK
E43
PEG_CLK#
AE41
DMI_RXN_0
AE37
DMI_RXN_1
AE47
DMI_RXN_2
AH39
DMI_RXN_3
AE40
DMI_RXP_0
AE38
DMI_RXP_1
AE48
DMI_RXP_2
AH40
DMI_RXP_3
AE35
DMI_TXN_0
AE43
DMI_TXN_1
AE46
DMI_TXN_2
AH42
DMI_TXN_3
AD35
DMI_TXP_0
AE44
DMI_TXP_1
AF46
DMI_TXP_2
AH43
DMI_TXP_3
B33
GFX_VID_0
B32
GFX_VID_1
G33
GFX_VID_2
F33
GFX_VID_3
E33
GFX_VID_4
C34
GFX_VR_EN
AH37
CL_CLK
AH36
CL_DATA
AN36
CL_PWROK
AJ35
CL_RST#
AH34
CL_VREF
N28
M28
G36
E36
13-
K36
CLKREQ#
32-
H36
ICH_SYNC#
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,58-
TSATN
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
B12
B28
B30
B29
C29
A28
R715
12
33_5%
R714 499_1%12
TP2000
CLKREQ_R_MCH# MCH_ICH_SYNC#
+VCCP
56_5%
1
2
31­31-
R726
2
31­31­31-
CHANGE by
DMI_TXN(0) DMI_TXN(1) DMI_TXN(2) DMI_TXN(3)
DMI_TXP(0) DMI_TXP(1) DMI_TXP(2) DMI_TXP(3)
DMI_RXN(0) DMI_RXN(1) DMI_RXN(2) DMI_RXN(3)
DMI_RXP(0) DMI_RXP(1) DMI_RXP(2) DMI_RXP(3)
11-,19-,32-
R916 R917 R918 R919
1
HDA_BCLK HDA_RST#
HDA_SDIN3
HDA_SDOUT HDA_SYNC
13­13­13­13-
13­13­32-
32-
32-
32-
10-
DFGT_VID_0
10-
DFGT_VID_1
10-
DFGT_VID_2
10-
DFGT_VID_3
10-
DFGT_VID_4
10-
DFGT_VR_EN
32­32-
PM_PWROK
32-
CL_RST#0
12 12 12 12
R907
2
OPEN
Loren
26-
MA_CLK_DDR1
26-
MA_CLK_DDR2
27-
MB_CLK_DDR1
27-
MB_CLK_DDR2
26-
MA_CLK_DDR1#
26-
MA_CLK_DDR2#
27-
MB_CLK_DDR1#
27-
MB_CLK_DDR2#
26-,28-
MA_CKE0
26-,28-
MA_CKE1
27-,28-
MB_CKE0
27-,28-
MB_CKE1
26-,28-
MA_CS0#
26-,28-
MA_CS1#
27-,28-
MB_CS0#
27-,28-
MB_CS1#
26-,28-
MA_ODT0
26-,28-
MA_ODT1
27-,28-
MB_ODT0
27-,28-
MB_ODT1
19-
SM_RCOMP
19-
SM_RCOMP#
19-
SM_RCOMP_VOH
19-
SM_RCOMP_VOL
CLK_DREF CLK_DREF# CLKSS1_DREF CLKSS1_DREF#
CLK_PEG_MCH CLK_PEG_MCH# DMI_TXN(3:0)
DMI_TXP(3:0)
DMI_RXN(3:0)
DMI_RXP(3:0)
CL_CLK0 CL_DATA0
OPEN OPEN 0_5% 0_5%
9-,10-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,40-,41-,42-,43-,44-,45-,47-,48-,49-,50-,51-,52-,53-,55-,58-
iHDMI enable : no stuff iHDMI disnable : stuff
47­47-
22-Apr-2008
+V1.8
8-,19-,23-,24-,26-,27-,58-
12
R724
80.6_1%
12
R725
80.6_1%
C123
1 2
0.1uF_10v
1 2
C768
0.1uF_10v
iHDMI enable : stuff iHDMI disnable : no stuff
TMDS_SCLK TMDS_SDATA
R755
R753
INVENTEC
TITLE
Potomac 10
CANTIGA-1
CODE REV
SIZE
A3
CS
SHEET
19-
SM_RCOMP
19-
SM_RCOMP#
8-,26-,27-
M_VREF
+VCCP
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,58-
1
R760
1K_1%
2
12
R761
499_1%
+V3S
2.2K_5%
2
1
2
2.2K_5%
1
DOC. NUMBER
1310A21699 A01
OF
6019
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