INVENTEC PIAGET 2.0 Schematic

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INVENTEC
THIS DRAWING AND SPECIFICATIONS, HEREIN, ARE THE PROPERTY OF INVENTEC CORPORATION AND SHALL NOT BE REPODUCED, COPIED, OR USED IN WHOLE OR IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT WRITTEN PERMISSION, INVENTEC CORPORATION 2009 ALL RIGHT RESERVED
DATEDATEEE POWER DRAWER DESIGN
3
DATEEE
3
SHEET
REV
INVENTEC
DATE
DOC. NUMBER
CORPORATION AND SHALL NOT BE REPODUCED, COPIED, OR USED IN WHOLE OR IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT
XXXXXXXXXXXX
DATEDATE
REV
DRAWER
SIZE =
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DOC. NUMBER
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WRITTEN PERMISSION, INVENTEC CORPORATION 2009 ALL RIGHT RESERVED
POWER
VER :SIZE =
OF
TITLE
THIS DRAWING AND SPECIFICATIONS, HEREIN, ARE THE PROPERTY OF INVENTEC CORPORATION AND SHALL NOT BE REPODUCED, COPIED, OR USED IN WHOLE OR
SIZE CODE
DATEDATE
DATE
SHEET OF
INVENTEC
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT WRITTEN PERMISSION, INVENTEC CORPORATION 2009 ALL RIGHT RESERVED
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2009/08/12
DOC. NUMBER REVVER :
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THIS DRAWING AND SPECIFICATIONS, HEREIN, ARE THE PROPERTY OF INVENTEC
TITLE
FILE NAME : XXXX-XXXXXX-XX
XXXXXXXXXXXX
DATE REV
DRAWER DESIGN
INVENTEC
P09C2.0D
EE
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RESPONSIBLE
FILE NAME : XXXX-XXXXXX-XX
DATE
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TITLE
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DESIGN
THIS DRAWING AND SPECIFICATIONS, HEREIN, ARE THE PROPERTY OF INVENTEC
CHANGE NO. REV
XXXXXXXXXXXX
FILE NAME :
3
DATEEE
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT WRITTEN PERMISSION, INVENTEC CORPORATION 2009 ALL RIGHT RESERVED
XXXX-XXXXXX-XX
P/N
EE
CS
Piaget 2.0 Discrete
RoHS
CORPORATION AND SHALL NOT BE REPODUCED, COPIED, OR USED IN WHOLE OR
INVENTEC
P/N
XXXX-XXXXXX-XX
MV Build
SHEET
PIAGET-Discrete
CHANGE NO.
POWER
A02
1310A22683-0-MTR
1 60
A3
CS
Piaget 2.0 Discrete
RoHS
A02
1 60
A3
CS 1310A22683-0-MTR
Piaget 2.0 Discrete
RoHS
A02
1310A22683-0-MTR
1 60
A3
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16- CPU-1
CHANGE by
REV
43- HDD & ODD CONN
CODE
57- Power Plan CAP
35- LCD CONN & WEBCAM CONN
19- CPU-4
TABLE OF CONTENTS
18- CPU-3
7- +V5A,+V3A & +V2.5S
59- 15’’ ODD Extend Board
12- DDR2 POWER
11- POWER
58- HDMI
48- Earphone & MIC JACK
29- GPU-AMD-M92S2-2
32- Video RAM(GDDR2)-1
OF
39- SB700-4
38- SB700-3
PAGE
42- SPI & ACCELEROMETER
29- GPU-AMD-M92S2-3
22- DDR2-DAMPING
45- TCM CONN
SIZE
20- DDR2-DIMM010- +VCC_CORE
6- SELECT & BATTERY CONN
SHEET
DOC. NUMBER
23- THERMAL&FAN CONTROLLER
8- OCP
TITLE
41- KB & TP CONN
60- Switch Board & LID Switch & QL
INVENTEC
24- RS780-1
55- W/B & SW/B & LED/B CONN
14- POWER(SEQUENCE)
25- RS780-2 27- RS780-4
15- CLOCK_GENERATOR
28- GPU-AMD-M92S2-1
34- CRT
51- Giga-LAN- CONTROLLER
46- FLASH MEDIA CARD
33- Video RAM(GDDR2)-2
13- POWER(SLEEP)
40- KBC
47- AZALIA CODEC
17- CPU-2
37- SB700-2
21- DDR2-DIMM1
52- NIC-10/100/1000-RJ45 CONN 53- MINICARD & BT CONN
PAGE
Table OF Content
Piaget 2.0 Discrete
CS
A3
602
1310A22683-0-MTRA02
Jason Chiu 20-Jul-2009
54- NEW CARD & SIM CONN
5- DC& BATTERY CHARGER
PAGE
50- MDC CNTR
44- USB CONN
56- SCREW
36- SB700-1
26- RS780-3
9- +VCC_NB & +V1.2A
30- GPU-AMD-M92S2-4
49- AUDIO AMP & HP JACK
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LPC interface
USB7
KBC
USB5
PCIE0
IDT_92HD75
LVDS
TCM
RJ11
USB11
SM Bus
OF
LCM
CONN
USB4
PCIE3
Bluetooth
SYSTEM
SMSC KBC1098
DOC. NUMBER
MAIN BATT
USB2
USB2.0
Hyper Transport
Conn
Giga-Lan
USB1
Azalia interface
TITLE
CAMERA
A-LINK
SATA1
Slot
HDMI
USB6
Keyboard
WWAN
MINI CARD
Conn
CONN
System Charger &
4 in 1
ICS9LPR476KLFT
Headphone
DDR II _SODIMM0
GDDR2
(FCBGA)
Accelerometer
AMD
TouchPad
VRAM
SATA0
USB0
Marvell 8072
CONNECTOR
(WLAN)
CODE
M92S2
CRT
AMD Caspian
FIXED ODD
PCIE-GFX
SIG2 Socket/638pin
PCIE2
CHANGE by
BIOS
Speaker
DDR II _SODIMM1
Mic IN
(FCBGA)
DDR2
NEW CARD
DDR2
Flash media
Conn
ALCOR AU6371
HDD
SB710
Turion/Sempron
INVENTEC
DC/DC System power
AMD
Block Diagram
Piaget 2.0 Discrete
CS
A3
603
1310A22683-0-MTRA02
Jason Chiu 20-Jul-2009
RJ45
SIZE
SHEET
RS881
SPI
USB3
AUDIO CODEC
Clock Generator
RGB
mdc v1.5v/3
REV
Conn
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V1.5S_PG
Charger
SYS_PWRGD
DOC. NUMBER
DDR2 POWER
+V3S
5/3.3V
(TPS51125)
CHANGE by
+V1.8S
V18_GOOD
+VBAT
VDD_CORE
(SC471A)
+VCC_NB&+V1.2
INVENTEC
OCP_OC#
+V1.2S
CHGCTRL_3
+V5S
ANPEC
SHEET
+V2.5S
OF
+VCC_CORE_VDD1
CODE
(MAX17009)
VGA_ALTV0
SYS_PWRGD
+VDD_CORE
VGA_ALTV1
(TPS51124)
VCC_CORE
RICH
(RT9194PE)
+V1.1S
PWR_GOOD_3
GMT
(G966)
+V1.5S
+V0.9S
PWR_GOOD3
NB_SKIP#
MAXIM
(MAX8792ETD)
REV
POWER_GOOD_3
SYS_PWRGD
ADP_PRES
ADP_PRES
(MAX17000ETG)
SYS_PWRGD
TITLE
+V3A
+VCC_CORE_NB
AC_AND_CHG
+V5A
+VCC_CORE
+V1.8
KBC_PW_ON
SLP_S5#_5R
+V5AL
NBV_BUF
+V3AL
SIZE
Adapter
Piaget 2.0 Discrete
CS
A3
604
1310A22683-0-MTRA02
Jason Chiu 20-Jul-2009
+VCC_NB
POWER_GOOD_3
(BQ24740)
PWR_GOOD_3
+VBATR
NB_SKIP
(APL5315)
OCP
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SHEET
TITLE
CELLSEL#=0,Vcharger=12.6V
SIZE
CELLSEL#=1,Vcharger=16.8V
DOC. NUMBER
high power trace
Icharger=3A
DC JACK
3.3A_150mil
Kevin sense
OF
5A
INVENTEC
Note:
CODE
DC & BATTERY CHARGER
Piaget 2.0 Discrete
CS
A3
605
1310A22683-0-MTRA02
Jason Chiu 20-Jul-2009
CHANGE by
REV
1 2
255K_1%
R1045
1 2
1 2
C1002
1uF_6.3V
1 2
0.1uF_16V
C1034
1
2
0.1uF_25V
C1035
4.7uF_25V
1 2
7-,9-,10-,11-,12-,13-,14-,35-,57-
22K_5%
R1027
C1003
0.1uF_25V
1 2
C1023
4.7K_5%
R1030
1
2
2
220K_5%
R1057
1 2
RLZ18C2
1
R5012
200K_1%
1
R1048
100K_1%
1 2
D1004
2
7-,13-,14-,38-,40-,49-,51-,54-
5-
8-
G
G2
G
R1024
453K_1%
1
1
1
2
2
3
3
4
4
G1
2N7002W
Q1007
3
D
1
G
S
2
40-
6-,40-
JACK1001
ACES_91302_0047L_1_4P
SRN
18
19
SRP
16
SRSET
VADJ
12
11
VDAC
10
VREF
IADAPT
8
IADSLP
14
ISYNSET
LODRV
23
4
LPMD
7
LPREF
22
PGND
25
PH
PVCC
28
PowerPad
29
24
REGN
ACP
3
ACSET
6
AGND
9
BAT
17
BTST
27
20
CELLS
CHGEN
1
DPMDET
21
13
EXTPWR
HIDRV
26
15
7-,8-
U1003
TI_BQ24740_QFN_28P
5
ACDET
ACN
2
D
765
4
G
S
123
5-,7-,8-,55-
0_5%
1
2
FDMC8884
Q1002
8
0.033uF_16V
C1005 1
2
R1005
+
3
-
2
4
8
OUT
1
R1029
1 2
TI_LMV393IDGKR_SOP_8P
U1002-A
D1003
BAT54_30V_0.2A
1 3
5-
5-,7-,8-,55-
47K_5%
1 2
4.7uF_25V
C1022
1 2
0_5%
R1028
R1047
23.7K_1%
1
2
2
C1016
0.1uF_16V
1 2
1 2
R1040
10K_1%
1
3K_5%
R1008
1 2
1uF_25V
C1017
C1009
4.7uF_25V
1 2
R1004
1
2
40-
1 2
0_5%
41.2K_1%
R1039
1
2
4.7uF_25V
C1007
Q1053
2N7002DW
6
D1
D2
3
2
G1
G2
5
S1
1
4
S2
4.7uF_25V
1 2
210K_1%
R1002
1 2
5-,7-
C1008
PCMB0603T_8R2MS
L1001
1 2
24K_1%
R1051
1 2
6-
C1006
1uF_25V
1 2
5-,6-,7-
R1049
1M_5%
1 2
OUT
4
C1039
0.1uF_25V
1 2
TI_LMV331IDBVR_SOT23_5P
U1004
1
+
3
­2
5
5-,6-,7-
R5011
150K_5%
1 2
R5013
22K_5%
1
2
6-,7-,8-,36-,38-,40-,41-,42-,53-,55-
C1021
4.7uF_25V
1 2
L1002
1 2
3
4
5-,7-
7-,8-,14-
R1007
0.01_1%
1 2
8-
NFM60R30T222
C1013
1
2
R1043
0402_OPEN
12
5-
1uF_6.3V
76.8K_1%
R5063
12
2
604K_1%
R1042
1 2
8
7
OUT
C1019
1uF_25V
1
U1002-B
TI_LMV393IDGKR_SOP_8P
+
5
-
6
4
1M_1%
R1022
1
2
40-
C1040
0.1uF_25V
1 2
5-,7-
1 2
40-
6-40-
1 2
5-
8-
C70
0.022uF_16V
G
S
1 2 3
100K_1%
R1052
FAIR_FDMC6675BZ_8P
Q1009
8
D
7 6 5
4
12
R1050
100K_5%
1 2
C1018
0.1uF_16V
8
D 7 6 5 4
G
S
1 2 3
5-,6-,7-
C1015
1uF_25V
1 2
FAIR_FDMC6675BZ_8P
Q1003
C1020 1uF_10V
1
2
7-,9-,13-,14-,35-,37-,38-,39-,51-,53-,55-,57-
C1001
100pF_50V
1 2
1uF_25V
C1004
1 2
D
8 7 6 5
G
4
1
S
2 3
147K_1%
R1003
1
2
Q1004
AM4825P_AP
1 2
4.7uF_25V
C1010
1 2
C1038 10pF_50V
1 2
5-,7-,8-,55-
B140_SMA
D1009
2 1
0.01_1%
R1053
R1023 20K_5%
12
Q1052
8D765
4
G
S
123
C1037
1 2
FDMC8884
0.1uF_25V
C1036
1 2
10pF_50V
R1021
422K_1%
1 2
2
300K_5%
R185
1 2
1
2
47K_5%
R184
1
1
2
100K_5%
R1006
1uF_6.3V
1 2
R1001
24.9K_1%
R1044
1
2
40-,51-
C1014
ADP_PRES
+V3AL
ACDET
+VADP
15K_5%
+VADPTR
+VADPTR
+VBAT +VBATR
KBC_VCC1_PWRGD
ADP_EN
2VREF
+VADPBL
+V5AL
AC_ADP_PRES
+V3A
BQREF
+VBDCR
I_SET
CHGCTRL_3
+V5AL
+V5AL
CHGEN#
ADPDRV#
CELLS
ICS
SLP_S3#_3R
ADPDRV#
VCTRL_3
+VBDC
+VBDC+VBAT+VADPBL
+VADPBL
+VBDC
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CHANGE by SHEET
SIZE
OF
TITLE
REV
INVENTEC
CODE DOC. NUMBER
2
20-Jul-2009Jason Chiu
A021310A22683-0-MTR
6 60
A3
CS
Piaget 2.0 Discrete
SELECT & BATTERY CONN
2 1
1K_5%
R57
1
R1010
100K_5%
1
2
D10
1SS355W
1 2
5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-
5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-
2
3
1
5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-
0402_OPEN
C5016
2
3
1
D1007
DIODE_BAV99
2
3
1
D1006
DIODE_BAV99
100_5%
R1012
1 2
D1005
DIODE_BAV99
2
0.047uF_16V
C52
1 2
40-
5-,7-
R61 220K_5%
1
Q10
2N7002W
D
3
G
1
2
S
2
40-
R1014 10K_5%
1
2
G1
G
G2
100K_5%
R142
1
1
1
2
2
3
3
4
4 5
5
6
6
G
R1015
100_5%
1 2
SYN_081006_TK001_6P
CN1001
C5018
100pF_50V
1 2
5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-
10K_5%
R1013
1
2
40-
Q1059
MMBT3906
B
1
3
C
E
2
5-
0.1uF_25V
C1012
1 2
R58
1
2
100pF_50V
C5017
1 2
470K_5%
5-
POWERPAD_2_0610
PAD1001
R1009
1K_5%
1 2
5-,40-
470pF_50V
C1011
1 2
+V3AL
SDA_MAIN
THM_MAIN#
+V3AL
SCL_MAIN
+VBDC +VBATA
CHGEN#
CHGCTRL_3
ACDET
+V3AL
+V3AL
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A3
CS
Piaget 2.0 Discrete
+V5A,+V3A&+V2.5S
5A
CHANGE by
200mA
OF
DOC. NUMBERSIZE
INVENTEC
DEBUG_KBCRST SCHEMATIC , MV OPEN
TITLE
SHEET
REVCODE
1 2
12-Aug-2009Jason Chiu
A021310A22683-0-MTR
7 60
12
C5014
2.2uF_6.3V
R5045
64.9K_1%
1
2
51125GND
0.1uF_16V
C5021
R5044
16.5K_1%
1
2
U5003
ANPEC_APL5325_BI_TRG_SOT23_5P
2
GND
5
SETSHDN
1
VIN
3 4
VOUT
5-,7-,8-,14-
21
R427
10K_1%
1 2
D5006
1SS355W
330uF_6.3V
C601
1
2
2 3
38-,40-
R5039
255K_1%
1
2
D
8 7 6 5
G
41
S
D
8765
G
4 1S23
Q1048
FDMC8296
C1455
0402_OPEN
1 2
Q1047
FDMC8296
41S2 3
51125GND
Q1039
FDMC8884
D
8 7 6 5
G
2
2200pF_50V
C1384
1 2
1 2
10K_1%
R426
1
VREG3
17
VREG5
5-,7-,9-,10-,11-,12-,13-,14-,35-,57-
40-
5-,13-,14-,38-,40-,49-,51-,54-
0402_OPEN
R5014
TONSEL
4
VBST1
22
VBST2
9
18
VCLK
VFB1
2
5
VFB2
16
VIN
VO1
24
VO2
7
3
VREF
8
19
DRVL1
12
DRVL2
EN0
13
ENTRIP1
1
6
ENTRIP2
15 GND
LL1
20
LL2
11
23
PGOOD
14 SKIPSEL
25
TML
1
U31
TI_TPS51125_QFN_24P
DRVH1
2110
DRVH2
1 2
D5009
ROHM_RLZ242
20K_1%
1
2
5-,7-,8-,55-
5-
10K_5%
R1210
R430
4.7_5%
1 2
R5046
2
GND
SET
51
SHDN
3
VIN4VOUT
R5043
470K_5%
1
2
ANPEC_APL5315_12BI_TRL_SOT23_5P
U1013
R5042
220K_5%
1
2
C721
1 2
R5041
680K_5%
1 2
0.1uF_16V
1 2
R5040
11.5K_1%
1
2
1 2
5-,7-,9-,10-,11-,12-,13-,14-,35-,57-
9-,10-,11-,12-,13-,14-,35-,44-,57-
10uF_6.3V
C667
1
2
5-,7-,8-,55-
C1456
0603_OPEN
1
2
R472
6.8K_1%
POWERPAD1x1m_OPEN
PAD5003
5-,7-,8-,14-
0402_OPEN
R1274
100_5%
R5016
1 2
R423
0_5%
12
51125GND
5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-
1 2
10uF_6.3V
C5015
1 2
51125GND
0402_OPEN
C723
10K_1%
R1209
1
2
5-,9-,13-,14-,35-,37-,38-,39-,51-,53-,55-,57-
0402_OPEN
R5015
1
2
4.7uF_25V
C1457
1 2
R473
75K_1%
1
2
5-,8-
2 1
CYNTEC_PCMC063_3R3
L38
1 2
1 2
D5007
1SS355W_OPEN
C1386
4.7uF_25V
1 2
0402_OPEN
C1387
1
2
R1246
10_5%
1
2
68.1K_1%
R425
C724
0.1uF_16V
12
D
8765
G
4 1S23
C664
0.1uF_16V
1 2
5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-
Q1033
FDMC8884
1 2
51125GND
1 2
0603_OPEN
C1385
C1341
10uF_6.3V
1 2
C1454
0402_OPEN
1uF_6.3V
C811 1
2
2
D50121SS355W
2 1
7-,40-
2N7002W
Q66
3
D
1
G
S
C810
220uF_6.3V
1
40-
2
D5013
1SS355W
2 1
5-,7-,8-,55-
1 2
R1257
15.4K_1%
1
+VS
5
3
-IN
2
-VS OUT
4
4.7uF_25V
C1388
10-,13-,14-,15-,20-,21-,23-,26-,27-,29-,30-,35-,36-,37-,38-,39-,40-,41-,42-,45-,46-,47-,49-,50-,51-,53-,54-,55-,57-,58-
U5002
FAIR_LMV321AS5X_SOT23_5P
+IN
1
2
C1413
0402_OPEN
1 2
1
2
CYNTEC_PCMC063_3R3
L56
1
1 2
18-
R1208 22K_1%
12
0.22uF_6.3V
C661
1 2
R429
33_5%
330K_5%
R470
D5008
DAN202K
1 2
3
POWERPAD_2_0610
PAD8
C666
10uF_6.3V
1 2
R424 100K_5%
1
2
2
R474
4.7_5%
1 2
S1
S2
4
C1340
10uF_6.3V
1
2N7002DW
Q57
D1
6
3
D2
G1
2
5
G2
1
5-,7-,8-,55-
PAD5002
POWERPAD1x1m
1 2
POWERPAD_2_0610
PAD3
1 2
1uF_6.3V
C662
2
7-,40-
5-,6-
C665
4.7uF_25V
+V3ALP
5-,7-,9-,10-,11-,12-,13-,14-,35-,57-
1uF_16V
C5013
1
+VBATR
RSMRST#
+VBATR
+VADPBL
+V5AL
+V5AL
+V3AL
+V3AL
DEBUG_KBCRST
+V5AL
2VREF
+V2.5S
2VREF
DEBUG_KBCRST
+VBATR
SLP_S3#_3R
+VADP+VBDC
+VADP_DEBUG
+V3A
+V5A
+V3S
+V5AL
KBC_PWR_ON
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CODE
OCP
Piaget 2.0 Discrete
CS
A3
608
1310A22683-0-MTRA02
Jason Chiu 20-Jul-2009
SHEETCHANGE by OF
TITLE
SIZE DOC. NUMBER REV
INVENTEC
1
2
C1045
0.1uF_10V
1 2
5-,7-
33.2K_1%
R1075
U1007-B
5
+
6
­4
8
7
OUT
R1061 0_5%
1 2
AS393MTR_E1
C5019
0.01uF_16V
1 2
5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-
R1078 130K_1%
1
2
AS393MTR_E1
U1007-A
3
+
2
­4
8
OUT
1
1
2
5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-
2N7002W
Q1013
3
D
1
G
S
2
100K_1%
R5051
R1070
3.9K_1%
1
2
1 2
13-,14-,23-,29-,34-,35-,37-,38-,41-,43-,48-,49-,53-,57-,58-
8-
40-
5-,8-
1
2
R1062
100_5%
2
5-,7-,14-
18-,23-
40-
R1074
8.06K_1%
R1054
45.3K_1%
1
2
11K_5%
R5037
1 2
1 2
5-
10K_1%
R1083
1
GND
2
4
OUT
5
Vcc+
C1046
3900pF_16V
55-
TI_LMV321IDBVR_SOT23_5P
U1006
1
1IN+
1IN-
3
R5029
0_5%
1 2
5-
2
27.4K_1%
R5048
1
2
40-
1 2
C1049
1uF_25V
1
1 2
R1058
10K_5%
B
1
C
3
2
E
1M_5%
R1079
1 2
Q1015
D_MMST3904
200K_1%
R5054
1 2
169K_1%
R1060
R1059 100K_1%
1
2
5-,7-,8-,55-
5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-
1 2
2
E
R5019
39.2K_1%
1
2
1uF_10V
C5006
2
40-
MMBT3906
Q1054
1
B
C
3
2 1
R1085
4.7K_1%
1
2 1
1SS355W
D1014
D
3
G
1
2
S
1SS355W
D1015
1
2
Q1014
BSS84_3P
R5017
100_5%
1
2
5-,8-
2K_1%
R1087
2
R1077 10K_1%
1
2
1
2
R1080 47K_5%
1
1
2
10K_5%
R5053
100K_1%
R5049
1 2
0_5%
R5052
1 2
5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-
D1013
1SS355W 2
1
8-
100K_1%
R5050
1
5-,7-,8-,55-
R1068
100K_5%
1 2
GND
OUT
4
Vcc+
5
RLZ4.7B
D5010
2
2
U5001
TI_LMV321IDBVR_SOT23_5P
1IN+
1
3
1IN-
2
1 2
R5018
49.9K_1%
1
R1076 68K_1%
1
2
0.22uF_10V
C1044
0402_OPEN
R5047
1 2
R1072
8.66K_1%
12
40-
ADP_DET#
2VREF
+VADP
VBIAS
+V3AL
OCP_OC
+V3AL
+V3AL
+V5AL
ADP_ID_ADC
BQREF
PROCHOT#
VBIAS
I_SET
+V5S
ICS
LIMITsignal
OCP_IN_ADC ICS
PMC
+V5AL
+V3AL
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CHANGE by
SIZE REVDOC. NUMBERCODE
INVENTEC
A021310A22683-0-MTR
9 60
A3
CS
Piaget 2.0 Discrete
+VCC_NB & +V1.2A
SHEET
TITLE
OF
0.1uF_16V
1 2
14-Aug-2009Jason Chiu
0_5%_OPEN
R316
1 2
C502
2
4.7uF_25V
C1337
1 2
1
2
L22
PCMC063T_1R5MN
1
12
R315
10K_1%
1 2
0_5%
R307
10uF_6.3V
1 2
C1334
0402_OPEN
1 2
C874
PAD2
C1370
0402_OPEN
0_5%
1 2
5-,7-,13-,14-,35-,37-,38-,39-,51-,53-,55-,57-
POWERPAD_2_0610
1S2 3
9
51124GND
R274
Q1019
FDMS8670S
D
8 7 6 5
G
4
D
8 7 6 5
G
41S2 3
1 2
Q1020
FDMC8884
C5010
330uF_2.5V
1
2
37-
0402_OPEN
C499
5.1K_1%
1
2
R304 10K_5%
1
2
R317
1 2
10K_1%
R303
1
2
G
4 1S23
0402_OPEN
C1366
Q1058
FDMC8296
D
8765
PCMC063T_1R5MN
L33
1 2
C1336
4.7uF_25V
1 2
23
0_5%
R306
12
Q1023
FDMC8884
D
8765
G
4 1
S
R314
10_5%
1 2
4.7uF_25V
C1368
1 2
1 2
PAD7
POWERPAD_2_0610
1 2
C1496
10uF_6.3V
C1552
0.1uF_10V
1 2
0.1uF_25V
C1367
16
VBST1
22
VBST2
9
VFB12VFB2
5
1
VO1
VO2
6
LL1
20 11
LL2
PGND1
18
13
PGND2
24
PGOOD1
7
PGOOD2
TONSEL
4
17
TRIP1
TRIP2
14
15
V5FILT
V5IN
U20
GND
25
GND
3
21
DRVH1
10
DRVH2
DRVL1
19
DRVL2
12
EN1
23
EN2
8
4.64K_1%
1
2
TI_TPS51124RGER_QFN_24P
0_5%
1 2
51124GND
7-,9-,10-,11-,12-,13-,14-,35-,44-,57-
R272
R273
10K_5%
12
R313
R628
4.75K_1%
1
2
7-,9-,10-,11-,12-,13-,14-,35-,44-,57-
VCNTL
VIN
9
51124GND
51124GND
ANPEC_APL5930KAI_TRL_SOP_8P
U51
VOUT
3
VOUT
4
5
VIN
EN
8 2
FB
GND
1
7
POK
6
0402_OPEN
C500
1 2
R548
10K_1%
1
2
C1335
0.1uF_25V
1 2
C1272
2200pF_50V
1 2
4.7uF_6.3V
C1331
1 2
C1332
0.1uF_10V
1 2
C416
1 2
9-,10-,11-,14-
5-,7-,9-,10-,11-,12-,13-,14-,35-,57-
9-,10-,11-,14-
0_5%
1 2
0.1uF_16V
6.04K_1%
1
2
R309
330uF_2.5V
C5011
1
2
11-,15-,18-,19-,27-,36-,37-,57-
R305
2
1uF_6.3V
C506
1 2
27-
10K_5%
R629
1
1 2
1000pF_50V
C415
1 2
1
2
C1369
4.7uF_25V
1
2
0402_OPEN
R1239
+VBATR
+V1.2A
+VBATR
+V1.2S
5-,7-,9-,10-,11-,12-,13-,14-,35-,57-
10_5%
R1185
PWR_GOOD_3
V1.2S_PG
+VCC_NB
+V5A
PWR_GOOD_3
+V3A+V5A
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CHANGE by
have 10mil clearance to other traces.)
SIZE CODE
OF
(Should routed in 5/5/5 pair and need to
(Should routed in 5/5/5 pair and need to
REV
TITLE
+VCC_CORE
Piaget 2.0 Discrete
CS
A3
6010
1310A22683-0-MTRA02
Jason Chiu 20-Jul-2009
SHEET
INVENTEC
have 10mil clearance to other traces.)
DOC. NUMBER
1uF_6.3V
C55
1 2
MAX17009
4.02K_1%
R104
1 2
R73
10_5%
1 2
MAX17009
C1056
330uF_2V_6mR
1
2
10-,18-,19-,57-
2
10K_1%
R34
1 2
1 2
C36
0.0047uF_50V
1
23
VDD2
14
VDDIO
32
VRHOT#
4.7uF_25V
C1032
36
33
PRO#
REF
4
3
SHDN#
8
SVC
9
SVD THRM
10
TIME
7
41
TMLPAD
VCC
18
28
VDD1
4011
GNDS215GNDS_NB
5
ILIM
LX1
30
LX2
21
NBSKP#
19
2
NV_BUF
OPTION
37
OSC
6
PERGD
1
PGD_IN
DH1
3120
DH2
DL1
27
DL2
24
38
FBAC1FBAC2
13
39
FBDC1FBDC2
12
26
GND1 GND2
25
GNDS1
U2
MAX_MAX17009GTL+_TQFN_40P
29
BST1
22
BST2
35
CSN1CSN2
16
CSP1
3417
CSP2
1K_5%
R105
1
2
4.7uF_25V
C1042
1 2
MAX17009
C1055
330uF_2V_6mR
1
2
18-
C1026
4.7uF_25V
1 2
C69
47uF_25V
1
2
1 2
0402_OPEN
C1024
1 2
1 2
10K_1%_THER_NTC
R103
C1054
4700pF_25V
1 2
7-,9-,10-,11-,12-,13-,14-,35-,44-,57-
C84
220pF_50V
SBR3U40P1
D1012
2
1
C8
1 2
154K_1%
1 2
18-
0.0047uF_50V
R43
100_1%
1
2
R37
1 2
22_5%
R79
1
2
1
2
C34
1000pF_50V
1 2
100_1%
R44
C9
1 2
18-
C37
0.0047uF_50V
C1043
4700pF_25V
1 2
0.22uF_6.3V
1 2
1
2
11-
C1025
0603_OPEN
C56
0.1uF_16V
1 2
4.7K_5%
R41
D
8765
G
4S123
R39
1 2
Q1011
FDMS7660
SBR3U40P1
D1011
2
1
36.5K_1%
C63
0.22uF_10V
1 2
0.0047uF_50V
C29
1 2
10-,18-,19-,57-
R32 10K_5%
1
2
1000pF_50V
C87
1 2
5-,7-,9-,10-,11-,12-,13-,14-,35-,57-
R109
4.02K_1%
1 2
11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-
3
R31
100_1%
1
2
8D765
4
G
S
12
R77
0_5%
1 2
Q1010
FDMS8692
1000pF_50V
C31
1 2
2
R75
4.7_5%
1
2
MAX17009
1 2
C1028
0402_OPEN
1
10-,18-,19-,57-
38-,40-
L3
ETQP4LR45XFC
100K_1%
R3
1 2
1000pF_50V
C35
1 2
0_5%
R1020
12
11-,40-
MAX17009
4.7uF_25V
C1041
1 2
ETQP4LR45XFC
L4
1 2
2.4K_1%
R107
1
2
2
0.22uF_10V
C33
1 2
11-
1
2
121K_1%
R36
1
G
S
123
330uF_2V_6mR
C108
FDMS8692
8D765
4
2
1.5K_1%
R78
1
2
Q1005
MAX17009
R40 100_1%
1
C32
1000pF_50V
1 2
1
2
R42
1.2K_1%
1
2
4
G
S
123
0.1uF_16V
C57
Q1012
FDMS7660
8D765
R1019 51_5%
1
2
7-,13-,14-,15-,20-,21-,23-,26-,27-,29-,30-,35-,36-,37-,38-,39-,40-,41-,42-,45-,46-,47-,49-,50-,51-,53-,54-,55-,57-,58-
7-,9-,10-,11-,12-,13-,14-,35-,44-,57-
1 2
MAX17009
0603_OPEN
C1029
1 2
18-
10_1%
R28
R74
4.7_5%
1
2
2
330uF_2V_6mR
C106
1
2
18-
C89
220pF_50V
1
2
R106
2.4K_1%
1
2
1 2
R110 1K_5%
1
5-,7-,9-,10-,11-,12-,13-,14-,35-,57-
MAX17009
18-
MAX17009
0_5%
R45
2
R29
1.5K_1%
1
2
1
2
4.7uF_6.3V
C1027
1
R76
1
2
1.2K_1%R30
4.7uF_25V
1 2
22_5%
1
2
C1031
1000pF_50V
1 2
9-,11-,14-
0402_OPEN
R1018
1 2
C66
1 2
MAX17009
R108
10K_1%_THER_NTC
+VCC_CORE
+VBATR
+VBATR
VDD1_FB
4.7uF_25V
C1030
CPU_SVD_R
CPU_SVC_R
SYS_PWRGD
NBV_BUF
+VCC_CORE
NB_SKIP#
SB_PWRGD
+V5A
+V1.8
PWR_GOOD_3
VDD1_FB#
NB_GNDS
+V5A
COREFB#
+V3S
COREFB
+VCC_CORE
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OF
SIZE CODE
INVENTEC
REV
20-Jul-2009Jason Chiu
A021310A22683-0-MTR
11 60
A3
CS
Piaget 2.0 Discrete
POWER
SHEET
TITLE
DOC. NUMBER
CHANGE by
7-,9-,10-,11-,12-,13-,14-,35-,44-,57-
4.7uF_25V
C1382
1 2
C526
0.22uF_16V
12
U1008
RICH_RT9194PE_05P_SOT23_6P
DRI
5
EN
1
FB
3
2
GND
4
PGOOD
6
VCC
9-,10-,11-,14-
10
12
SKIP
15
TML-PAD
7
TON
13
VCCVDD
2
BST
6
5
DH
DL
3
1
EN
FB
8
9
ILIM
4
LX
PGOOD
14
REF
11
REFIN
12
MAX_MAX8792ETD+T_DFN_14P
U24
R1086
0_5%
1 2
10-,11-,40-
R331
5.76K_1%
4.7uF_10V
C1062
1 2
9-,15-,18-,19-,27-,36-,37-,57-
10-
7
6
5 4
G
S
1 2 3
R411
9.1K_1%
1
2
FDMC8296
Q1018
8
D
5
NC
POK
1
VCNTL
4
3
VIN6VOUT
ANPEC_APL5910KAI_TRL_SOP_8P
U33
8
GND
GND
9
2
EN FB
7
0603_OPEN
C1345
1 2
R1088
4.12K_1%
1
2
5-,7-,9-,10-,12-,13-,14-,35-,57-
10-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-
100pF_50V
1 2
0_5%
1 2
C1344
0_5%
R339
12
R324
0.1uF_10V
C1053
1 2
8792GND
2
0402_OPEN
C1346
1 2
1
2
C1574
0.1uF_10V
1
1 2
220uF_2.5V
C599
0402_OPEN
C1342
1 2
C1383
4.7uF_25V
0_5%
R338
1 2
0402_OPEN
1
2
R333
80.6K_1%
1
2
R1214
2
R1215
0402_OPEN
1
2
19-
L37
CYNTEC_PCMC063_3R3
1
9-,10-,11-,14-
10uF_10V
C633
1
2
C635
10uF_10V
1 2
24-,25-,26-,27-,28-,29-,30-,57-
0402_OPEN
R332
1
2
10-,11-,40-
C525
0.22uF_16V
12
1 2
C1061
220uF_2.5V
1
2
12
0_5%
R1213
1uF_6.3V
C531
1 2
R328
0_5%
12
4
S2
S1_D2
5 6 7
G1 8
9-,10-,11-,14-
R330
1.5K_1%
FDS6900AS
Q1024
D1 1
2
3G2
C1343
1uF_6.3V
1 2
R1089
10K_1%
1
2
10-
8792GND
7-,9-,10-,11-,12-,13-,14-,35-,44-,57-
7-,9-,10-,11-,12-,13-,14-,35-,44-,57-
8792GND
R449 10K_1%
1
2
8792GND
R1212
100K_1%
12
0402_OPEN
R1211
1
2
1000pF_50V
C524 12
PAD5
POWERPAD_2_0610
54-
PWR_GOOD_3
+V5A
+V1.1S
+V1.2S
SYS_PWRGD
+V1.8
+V5A
8792GND
PWR_GOOD_3
+VBATR
+VCC_CORE_NB
NBV_BUF
+V5A
NB_SKIP#
SYS_PWRGD
PWR_GOOD_3
+V1.5S
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SHEET
SIZE
OF
TITLE
CODE DOC. NUMBER
NOTE: DDR2 REGULATOR
CHANGE by
1 2
20-Jul-2009Jason Chiu
A021310A22683-0-MTR
12 60
A3
CS
Piaget 2.0 Discrete
DDR2 POWER
REV
INVENTEC
5-,7-,9-,10-,11-,13-,14-,35-,57-
C542
10uF_6.3V
POWERPAD_2_0610
PAD1002
13-
7-,9-,10-,11-,13-,14-,35-,44-,57-
10-,11-,13-,18-,19-,20-,21-,22-,23-,38-,57-
0.1uF_16V
C611
1
2
C612
0.22uF_16V
1 2
20-,21-
1
2
806_1%
R1217
1 2
330uF_2V_9mR_Panasonic
C1414
1
2
200K_5%
R394
12
C606
0402_OPEN
1 2
R396
0_5%
C610
0603_OPEN
1 2
C1415
0603_OPEN
1 2
1 2
0402_OPEN
R1258
1
2
17000GND
PCMC063T_2R2MN
L1024
1 2
R398 0_5%
1 2
C613
3300pF_50V12
0_5%
R395
1 2
17000GND
23
VDD
19
8
VTT
9
VTTI
VTTR
6
5
VTTS
C614
1uF_6.3V
OVP
1
20
PGND1
PGND2
7
2
PGOOD1
3
PGOOD2
REFIN
10
24
SHDN SKIP
22
4
STDBY
14
TON
VCC
U27
MAX_MAX17000ETG+_TQFN_24P
21
AGND
17
BST
13
CSH
12
CSL
DH
15
DL
18
FB
11
GND
25
16
LX
5
4
G
S
123
1 2
FDMC8884
Q47
8D76
1uF_6.3V
1
2
0.033uF_16V
C615
4 1S23
9
C539
Q48
FDMS8670S
D
8765
G
C607
4.7uF_25V
1 2
13-
R346 10K_5%
1
2
19-,22-
R347
8.45K_1%
1
2
R397
10_5%
1 2
1 2
10uF_6.3V
C541 1 2
17000GND
4.7uF_25V
C609
+VBATR
10K_1%
R1218
1
2
+V1.8
V18_GOOD
M_VREF
+V0.9S
+V5A
SLP_S5#_5R
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CHANGE by SHEET
TITLE
SIZE
OF
REV
INVENTEC
CODE DOC. NUMBER
2
5-,7-,13-,14-,38-,40-,49-,51-,54-
20-Jul-2009Jason Chiu
A021310A22683-0-MTR
13 60
A3
CS
Piaget 2.0 Discrete
POWER(Sleep)
1
2
R400 20K_5%
1
13- 13-
13-,14-,58-
5-,7-,9-,10-,11-,12-,13-,14-,35-,57-
C1348
1000pF_50v
D1
6 3
D2
G1
2
5
G2
1
S1
S2
4
100K_5%
R436
1
2
2N7002DW
Q60
2
100K_5%
R568
1
2
14-,18-,24-,26-,27-,30-,38-,57-10-,11-,12-,18-,19-,20-,21-,22-,23-,38-,57-
470K_5%
R438
1
5-,7-,9-,14-,35-,37-,38-,39-,51-,53-,55-,57-
47_5%
R401
1
2
100uF_6.3V
C1411
1
2
13-,14-,58-
47_5%
R1256
1
2
5-,7-,13-,14-,38-,40-,49-,51-,54-
10uF_6.3V
C1347
1 2
R399
470_5%
1 2
1 2
7-,9-,10-,11-,12-,13-,14-,35-,44-,57-
13-
R1216 47_5%
1
2
C616 10uF_6.3V
R402
100K_5%
1 2
12-
13-
51-
3K_5%
R566
1
2
2
Q79
SSM3K7002F
D
3
G
1
2
S
D
1
G
S
2
10K_5%
R567
1
D
3
G
1
2
S
SSM3K7002F
Q74
3
SSM3K7002F
Q1025
3
D
1
G
S
2
Q1026
SSM3K7002F
D
3
G
1
2
S
R437
4.7K_5%
1 2
7-,9-,10-,11-,12-,13-,14-,35-,44-,57-
7-,9-,10-,11-,12-,13-,14-,35-,44-,57-
Q37
SSM3K7002F
1
2
38-,44-
12-
1 2
C617
2200pF_50V
8
D
7
6 5 4
G
S
1 2 3
1000pF_50V_OPEN
C1517
2 1 3
G
S
4
SI7230DN
Q1022
3
G
S
4
FDC655BN
Q1041
6
D
5
FDC655BN
Q38
6
D
5 2
1
D-MMST3906
Q59
B
B
C
C
E
E
5-,7-,9-,10-,11-,12-,13-,14-,35-,57-
8-,14-,23-,29-,34-,35-,37-,38-,41-,43-,48-,49-,53-,57-,58- 7-,10-,14-,15-,20-,21-,23-,26-,27-,29-,30-,35-,36-,37-,38-,39-,40-,41-,42-,45-,46-,47-,49-,50-,51-,53-,54-,55-,57-,58-
13-
+V1.8S
GATE_3SGATE_5S
V18_GOOD
SLP_S5#_5R
SLP_S5_FPR
+V5A
+V5A
SLP_S3#_3R
SLP_S3#_3R
+V3S
+V3A
+V1.8
+V5A
SLP_S3_5R
+V5S
GATE_5S
SLP_S3_5R
+VBATR +VBATR
GATE_3S
GATE_5S SLP_S5#_3R
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OF
CODE
SHEET
REVDOC. NUMBERSIZE
INVENTEC
TITLE
POWER(Sequence)
Piaget 2.0 Discrete
CS
A3
6014
1310A22683-0-MTRA02
Jason Chiu 14-Aug-2009
CHANGE by
5
4
OUT
0.1uF_16V
C1330
1 2
TI_LMV331IDBVR_SOT23_5P
U1012
1
+
3
­2
1 2
R1205
1M_5%
1 2
2
14-
0.1uF_16V
C1363
30-,57-
9-,10-,11-
13-,18-,24-,26-,27-,30-,38-,57-
1uF_6.3V
C1362
1
2
14-
C1333
470pF_50V
1 2
1 2
0_5%
R1230
1
1 2
L42
PCMC104T_1R0MN
1 2
5-,7-,9-,13-,35-,37-,38-,39-,51-,53-,55-,57-
C1364
4.7uF_25V
1
2
8-,13-,23-,29-,34-,35-,37-,38-,41-,43-,48-,49-,53-,57-,58-
100K_1%
R1207
PGOOD
11
RTN
6
VCC
310
VOUT
C1371
1000pF_50V
7
16
DH
4
DL
12
EN
FB
9
14G015
G1
5
GND
ILIM
13
LX
1
PAD
17
1
2
U1014
SEMTECH_SC471A_MLPQ_16P
2
BST
D08D1
D
3
G
1
2
S
1.2K_1%
R1206
4.7uF_25V
C1081
1 2
Q1021
SSM3K7002F
S
23
9
28-
Q1029
FDMS8670S
D
8765
G
4 1
FDMC8884
D
8765
G
4 1S23
1
2
28-
13-,58-
Q1030
1
2
R1243
54.9K_1%
1 2
37.4K_1%
R1237
R1232
75K_1%
1
2
37.4K_1%
R1203
C1339
0.1uF_16V
1 2
R1241
1 2
330uF_2v_9mR_Panasonic
C631
1
2
5-,7-,8-
7-,9-,10-,11-,12-,13-,14-,35-,44-,57-
280K_1%
0.022uF_16V_OPEN
C1365
1 2
D1017
DAP202K
3
12
7-,10-,13-,15-,20-,21-,23-,26-,27-,29-,30-,35-,36-,37-,38-,39-,40-,41-,42-,45-,46-,47-,49-,50-,51-,53-,54-,55-,57-,58-
R1204
75K_1%
1
2
7-,9-,10-,11-,12-,13-,14-,35-,44-,57-
7-,9-,10-,11-,12-,13-,14-,35-,44-,57-
2
R1231
5.11K_1%
1 2
1 2
R1201
0_5%
1
R1202
75K_1%
1 2
220pF_50V
C1329
1 2
R1244
100K_1%
1 2
4700pF_25V
C1372
10uF_6.3V_OPEN
C629
1 2
R1235
95.3K_1%
1
2
VGAP_AGND
VGAP_AGND
4.7uF_25V
C1398
1 2
1 2
R1238
14.7K_1%
1
2
5-,7-,9-,10-,11-,12-,13-,35-,57-
R1236 10K_1%
1
2
C1063
2200pF_50V
PAD6
POWERPAD_2_0610
R1234 100K_5%
1
2
R1233
0_5%
1 2
5-,7-,13-,38-,40-,49-,51-,54-
2
R1242
100K_1%
1 2
+VBATR
R1240
20K_5%
1
+VDD_CORE
+VDD_FB
+V5A
+VDD_FB
+V3A
PWR_GOOD_3
POW_SW0
+V5A
SLP_S3#_3R
POW_SW1
+V5A
+V1.8S
+V5S
2VREF
SLP_S3_5R
+V3S
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Place close to CLKGEN within 500mils
30PPM
TITLE
12-Aug-2009Jason Chiu
A021310A22683-0-MTR
15 60
A3
CS
Piaget 2.0 Discrete
CLOCK_GENERATOR
SIZE
CHANGE by SHEET OF
REVCODE
INVENTEC
DOC. NUMBER
C637
10uF_6.3V
1 2
C590
12pF_50V_OPEN
1 2
C589
12pF_50V_OPEN
1 2
36-
C1380
47pF_50V_OPEN
1 2
9-,11-,18-,19-,27-,36-,37-,57-
27pF_50V
C516
1 2
2
26-
TP25
1
2
14.31818MHZ
X1
1
1
2
53-
40-
R388
8.2K_5%_OPEN
38-
15-
261_1%_OPEN
R1245
0.047uF_10V
1 2
18-
29-
26-
1uF_10V
C1379
1 2
C1403
BLM11A121S
L1022
1 2
15-
47pF_50V_OPEN
C1374
1 2
0.047uF_10V
1 2
26-
51-
12
36-
C1378
158_1%
R387
1 2
L43
BLM11A121S
2
TP24
7-,10-,13-,14-,15-,20-,21-,23-,26-,27-,29-,30-,35-,36-,37-,38-,39-,40-,41-,42-,45-,46-,47-,49-,50-,51-,53-,54-,55-,57-,58-
20-,21-,23-,29-,38-,42-
C515
27pF_50V
1
L35 1 2
38-,54-
R389
33_5%
1 2
BLM11A121S
1 2
TP26
10uF_6.3V
C595
1 2
C1376
2.2uF_6.3V
1 2
26-
18-
1 2
33_5%
R383
1 2
C636
0.1uF_16V
0.1uF_16V
1 2
C1402
0.047uF_10V
0.1uF_16V
1 2
C1401
0.1uF_16V
C1399
1 2
C1377
2
33_5%
R382
1 2
15-
7-,10-,13-,14-,15-,20-,21-,23-,26-,27-,29-,30-,35-,36-,37-,38-,39-,40-,41-,42-,45-,46-,47-,49-,50-,51-,53-,54-,55-,57-,58-
0.1uF_16V
C1373
1
26­26-
7-,10-,13-,14-,15-,20-,21-,23-,26-,27-,29-,30-,35-,36-,37-,38-,39-,40-,41-,42-,45-,46-,47-,49-,50-,51-,53-,54-,55-,57-,58-
0.1uF_16V
1 2
51-
53-
46-
36-
20-,21-,23-,29-,38-,42-
C596
2
15-
TP27
1
G
S
2
4.7pF_50V_OPEN
C582
1
1 2
SSM3K7002F
Q1031
3
D
29-
15-
54-
L1023
600OHM_25%
1K_5%
R390
1
2
1 2
R386
90.9_1%
1
2
R414
1 2
0.1uF_16V
C1375
1
2
53-
26-
10K_5%
1 2
10K_5%
R392
1 2
15-
15-
4.7pF_50V
C584
37
17
VDDSRC
67
X1 X2
68
0.047uF_10V
C641
69
VDDA
49
29
VDDATIG
VDDATIG_IO
28
VDDCPU
54
53
VDDCPU_IO
3
VDDDOT
61
VDDHTT
VDDREF
62
VDDSATA
44
VDDSB_SRC
38
VDDSB_SRC_IO
14
SRC3T_LPRS
SRC4C_LPRS
9
10
SRC4T_LPRS
7
SRC5C_LPRS SRC5T_LPRS
8
SRC6C_SATAC_LPRS
45 46
SRC6T_SATAT_LPRS
SRC7C_LPRS_27MHZ_NS
4 5
SRC7T_LPRS_27MHZ_SS
THERMAL-PAD
73
VDD48
SB_SRC1T_LPRS
SB_SRC_SLOW#
41
1
SMBCLK SMBDAT
2
SRC0C_LPRS
22 23
SRC0T_LPRS
20
SRC1C_LPRS SRC1T_LPRS
21
15
SRC2C_LPRS SRC2T_LPRS
16
SRC3C_LPRS
13
47 36
GNDSB_SRC
59
HTT0C_LPRS_66M
60
HTT0T_LPRS_66M
57
PD#
REF0_SEL_HTT66
65
REF1_SEL_SATA
64 63
REF2_SEL_27
39
SB_SRC0C_LPRS
40
SB_SRC0T_LPRS
34
SB_SRC1C_LPRS
35
42
CLKREQ4#
55
CPUKG0C_LPRS
CPUKG0T_LPRS
56
GND48
72
GNDA
48
GNDATIG
27
52
GNDCPU
GNDDOT
6
58
GNDHTT
GNDREF
66
GNDSATA
48MHZ_1
32
ATIG0C_LPRS ATIG0T_LPRS
33
ATIG1C_LPRS
30
ATIG1T_LPRS
31
ATIG2C_LPRS
25 26
ATIG2T_LPRS
CLKREQ0#
24
51
CLKREQ1#
50
CLKREQ2#
CLKREQ3#
43
GNDSRC
11
12
VDDSRC_IO
VDDSRC_IO
18
19
GNDSRC
48MHZ_0
71 70
0.1uF_16V
1 2
U30
ICS_ICS9LPRS476KLFT_MLF_72P
8.2K_5%
R385
1
2
C1400
22uF_6.3V
C1381
1 2
CLK_R_PCIE_LAN#
SB_3S_SMDATA
SB_3S_SMCLK
WL_OFF
+V1.2S
+V3S
+V3S
+V3S
CLKGEN_X2
SB700_R_J21
SB700_R_J21
54-
CLK_R3S_NB14
CLK_R_PCIE_NEWCARD# CLK_R_PCIE_NEWCARD
NBHT_CLK#
NBHT_CLK#
NBHT_CLK
NBHT_CLK
CLK_R_CPUBCLK
CLK_R_CPUBCLK
CLK_48M
+V3S_CLK
+V3S_CLK
CLK_R3S_KBC14
+V3S_CLK_VDDREF
CLK_R_PCIE_MINICARD1
CLK_R_PCIE_MINICARD1#
CLK_R_PCIE_LAN
VGA_PCIE_CLK#
CLK_48M_1
CLK_R3S_FM48
CLK_KBC&SB14
+V1.2S_CLK_IO
+V1.2S_CLK_IO
CLK_R_PCIE_ALINK#
CLK_R_PCIE_ALINK#
CLK_R_PCIE_ALINK
CLK_R_PCIE_ALINK
CLK_R_PCIE_SB#
CLK_R_PCIE_SB#
CLK_R_PCIE_SB
CLK_R_PCIE_SB
+V3S_CLK_VDDA
CLK_R_CPUBCLK#
CLK_R_CPUBCLK#
CLK_R3S_SB48
+V3S_CLK
+V3S_CLK
CLKGEN_X1
NBGFX_CLK
+V3S_CLK
CLK_R3S_NB14
CLK_R3S_NB14
CPPE_NC#
CLK_DVI# CLK_DVI
VGA_PCIE_CLK
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HYPERTRANSPORT
AF1
SIZE
Top View
INVENTEC
TITLE
CODE
CHANGE by OF
A26
REV
Layout: Add stitching caps if crossing plane split.
A1
DOC. NUMBER
20-Jul-2009Jason Chiu
A021310A22683-0-MTR
16 60
A3
CS
Piaget 2.0 Discrete
CPU-1
SHEET
S1
24-
24-
24­24- 24-
24-
24­24-
24-
24-
24-
24-
24-
24-
24-
24-
24-
24-
24-
24­24-
24-
24-
24- 24-
24-
24-
24-
24-
24-
24-
24-
R5
L0_CTLOUT_L1
24-
24-
24-
24-
24-
24-
24-
24-
Y1
Y4
L0_CLKOUT_H1
W1
L0_CLKOUT_L0
L0_CLKOUT_L1
Y3
L0_CTLIN_H0
N1
P3
L0_CTLIN_H1
P1
L0_CTLIN_L0
L0_CTLIN_L1
P4
R2
L0_CTLOUT_H0
L0_CTLOUT_H1
T5
L0_CTLOUT_L0
R3
L0_CADOUT_L3
W3
L0_CADOUT_L4
L0_CADOUT_L5
U1
L0_CADOUT_L6
U3
R1
L0_CADOUT_L7
L0_CADOUT_L8
AD3
AC5
L0_CADOUT_L9
J3
L0_CLKIN_H0
L0_CLKIN_H1
J5
L0_CLKIN_L0
J2
K5
L0_CLKIN_L1
L0_CLKOUT_H0
L0_CADOUT_H9
AD5
AC1
L0_CADOUT_L0
L0_CADOUT_L1
AC3
AB3
L0_CADOUT_L10
L0_CADOUT_L11
AA5
L0_CADOUT_L12
W5
V3
L0_CADOUT_L13
U5
L0_CADOUT_L14
L0_CADOUT_L15
T3
L0_CADOUT_L2
AA1
AA3
L0_CADOUT_H12
L0_CADOUT_H13
V4
L0_CADOUT_H14
V5
T4
L0_CADOUT_H15
AB1
L0_CADOUT_H2
L0_CADOUT_H3
AA2
L0_CADOUT_H4
W2
V1
L0_CADOUT_H5
U2
L0_CADOUT_H6
L0_CADOUT_H7
T1
AD4
L0_CADOUT_H8
H1
L0_CADIN_L4
K1
L2
L0_CADIN_L5
M1
L0_CADIN_L6
L0_CADIN_L7
N2
F5
L0_CADIN_L8
L0_CADIN_L9
F4
L0_CADOUT_H0
AD1
AC2
L0_CADOUT_H1
L0_CADOUT_H10
AB4
AB5
L0_CADOUT_H11
Y5
F3
L0_CADIN_H9
L0_CADIN_L0
E2
F1
L0_CADIN_L1
L0_CADIN_L10
H5
H4
L0_CADIN_L11
K4
L0_CADIN_L12
L0_CADIN_L13
M5
L0_CADIN_L14
M4
P5
L0_CADIN_L15
G2
L0_CADIN_L2
L0_CADIN_L3
K3
L5
L0_CADIN_H13
M3
L0_CADIN_H14
L0_CADIN_H15
N5
L0_CADIN_H2
G3
G1
L0_CADIN_H3
J1
L0_CADIN_H4
L0_CADIN_H5
L3
L0_CADIN_H6
L1
N3
L0_CADIN_H7
L0_CADIN_H8
E5
CN12-1
FOX_PZ63823_284S_41F_TEMP_638P
E3
L0_CADIN_H0
L0_CADIN_H1
E1
G5
L0_CADIN_H10
L0_CADIN_H11
H3
L0_CADIN_H12
24-
24-
24- 24-
24-
24-
24-
24-
24-
24-
24-
24­24-
24-
24-
24-
24-
24-
24-
24-
24-
24-
24-
24-
24­24-
24-
24-
24­24-
24-
24-
24-
24-
24-
24-
24-
24-
24-
24-
L0_CADIN1 L0_CADIN0
L0_CADIN3# L0_CADIN2# L0_CADIN1# L0_CADIN0#
L0_CLKIN1 L0_CLKIN1#
L0_CTLIN0 L0_CTLIN0#
L0_CLKIN0 L0_CLKIN0#
L0_CTLIN1
L0_CTLIN1#
L0_CTLOUT1 L0_CTLOUT1#
L0_CADIN9 L0_CADIN8
L0_CADIN11# L0_CADIN10#
L0_CADIN9# L0_CADIN8# L0_CADIN7 L0_CADIN6 L0_CADIN5 L0_CADIN4
L0_CADIN7# L0_CADIN6# L0_CADIN5# L0_CADIN4#
L0_CADIN3 L0_CADIN2
L0_CLKOUT1 L0_CLKOUT1#
L0_CTLOUT0 L0_CTLOUT0#
L0_CLKOUT0 L0_CLKOUT0#
L0_CADIN15 L0_CADIN14 L0_CADIN13 L0_CADIN12
L0_CADIN15# L0_CADIN14# L0_CADIN13# L0_CADIN12#
L0_CADIN11 L0_CADIN10
L0_CADOUT15 L0_CADOUT14 L0_CADOUT13 L0_CADOUT12
L0_CADOUT15# L0_CADOUT14# L0_CADOUT13# L0_CADOUT12#
L0_CADOUT11 L0_CADOUT10 L0_CADOUT9 L0_CADOUT8
L0_CADOUT11# L0_CADOUT10# L0_CADOUT9# L0_CADOUT8# L0_CADOUT7 L0_CADOUT6 L0_CADOUT5 L0_CADOUT4
L0_CADOUT7# L0_CADOUT6# L0_CADOUT5# L0_CADOUT4#
L0_CADOUT3 L0_CADOUT2 L0_CADOUT1 L0_CADOUT0
L0_CADOUT3# L0_CADOUT2# L0_CADOUT1# L0_CADOUT0#
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MEMORY INTERFACE
MEMORY INTERFACE
CHANGE by SHEET OF
TITLE
SIZE CODE DOC. NUMBER REV
INVENTEC
CPU-2
Piaget 2.0 Discrete
CS
A3
6017
1310A22683-0-MTRA02
Jason Chiu 20-Jul-2009
21-,22-
21-,22-
20­20-
21-
21-
20-,22­20-,22-
21-
21-
21-
20­20-
21-,22­21-,22-
20-,22­20-,22-
20-
20-
20-
20-
20-,22-
20-
20-
21-
21-
20-,22-
20-
21-,22­21-,22-
20-
20-
20-,22­20-,22-
20-
20-
20-
21-
21-
20-,22- 21-,22-
21-
21-
20- 21-
20-
21-,22­21-,22-
20-,22-
20-,22-
21-
21-
21-
20-
20-
21­21-
21-,22­21-,22-
21-
21-
21-
20-,22-
20-,22-
21­21-
20-
20-
21-,22­21-,22-
U25
U23
MB_WE_L
F26
MB_DQS_H3
AC25
MB_DQS_H4
MB_DQS_H5
AF21
MB_DQS_H6
AE16
AF12
MB_DQS_H7
MB_DQS_L3
E26
MB_DQS_L4
AC26
AF22
MB_DQS_L5
AD16
MB_DQS_L6
MB_DQS_L7
AE12
MB_RAS_L
MB_DM0
MB_DM1
B16
MB_DM2
A22
E25
MB_DM3
MB_DM4
AB26
AE22
MB_DM5
AC16
MB_DM6
MB_DM7
AD12
C12
MB_DQS_H0
MB_DQS_H1
D16
MB_DQS_H2
A24
AC12
MB_DATA58
AB11
Y11
MB_DATA59
MB_DATA6
D12
MB_DATA60
AE14
AF14
MB_DATA61
AF11
MB_DATA62
MB_DATA63
AD11
A13
MB_DATA7
MB_DATA8
A15
A16
MB_DATA9
A12
AD18
MB_DATA48
MB_DATA49
AE18
MB_DATA5
E11
MB_DATA50
AC14
AD14
MB_DATA51
MB_DATA52
AF19
AC18
MB_DATA53
AF16
MB_DATA54
MB_DATA55
AF15
AF13
MB_DATA56
MB_DATA57
AD26
AE25
MB_DATA39
G11
MB_DATA4
MB_DATA40
AC22
AD22
MB_DATA41
AE20
MB_DATA42
MB_DATA43
AF20
AF24
MB_DATA44
MB_DATA45
AF23
MB_DATA46
AC20
AD20
MB_DATA47
C26
D26
MB_DATA29
MB_DATA3
B14
G23
MB_DATA30
MB_DATA31
G24
MB_DATA32
AA24
AA23
MB_DATA33
AD24
MB_DATA34
MB_DATA35
AE24
AA26
MB_DATA36
MB_DATA37
AA25
MB_DATA38
C25
MB_DATA19
A14
MB_DATA2
MB_DATA20
B20
C20
MB_DATA21
B24
MB_DATA22
MB_DATA23
C24
E23
MB_DATA24
MB_DATA25
E24
MB_DATA26
G25
G26
MB_DATA27
MB_DATA28
C11
A11
MB_DATA1
A19
MB_DATA10
MB_DATA11
A20
C14
MB_DATA12
MB_DATA13
D14
MB_DATA14
C18
D18
MB_DATA15
D20
MB_DATA16
MB_DATA17
A21
MB_DATA18
D24
U24
MB_CKE0
J25
H26
MB_CKE1
MB_CLK_H0
P22
A17
MB_CLK_H1
MB_CLK_H2
AF18
R26
MB_CLK_H3
MB_CLK_L0
R22
MB_CLK_L1
A18
AF17
MB_CLK_L2
R25
MB_CLK_L3
MB_DATA0
N23
MB_ADD3
MB_ADD4
N26
L23
MB_ADD5
N25
MB_ADD6
MB_ADD7
L24
M26
MB_ADD8
MB_ADD9
K26
R24
MB_BANK0
MB_BANK1
U26
J26
MB_BANK2
MB_CAS_L
U22
Y26
MB1_ODT0
P24
MB_ADD0
MB_ADD1
N24
MB_ADD10
T26
L26
MB_ADD11
MB_ADD12
L25
W24
MB_ADD13
J23
MB_ADD14
MB_ADD15
J24
MB_ADD2
P26
CN12-3
FOX_PZ63823_284S_41F_TEMP_638P
MA_DQS_L0
B12
C16
MA_DQS_L1
A23
MA_DQS_L2
V26
MB0_CS_L0
MB0_CS_L1
W25
MB0_ODT0
W26
W23
MB0_ODT1
MB1_CS_L0
MA_DQS_L2
MA_DQS_L3
G21
MA_DQS_L4
AC23
AB20
MA_DQS_L5
W15
MA_DQS_L6
MA_DQS_L7
W13
MA_RAS_L
R19
T24
MA_WE_L
Y13
G13
MA_DQS_H0
MA_DQS_H1
G16
MA_DQS_H2
C22
G22
MA_DQS_H3
AD23
MA_DQS_H4
MA_DQS_H5
AB19
MA_DQS_H6
Y15
W12
MA_DQS_H7
MA_DQS_L0
H13
G15
MA_DQS_L1
C21
E13
MA_DATA7
MA_DATA8
H15
E15
MA_DATA9
E12
MA_DM0
MA_DM1
C15
MA_DM2
E19
F24
MA_DM3
MA_DM4
AC24
Y19
MA_DM5
AB16
MA_DM6
MA_DM7
MA_DATA54
MA_DATA55
AD15
AB13
MA_DATA56
MA_DATA57
AD13
MA_DATA58
Y12
W11
MA_DATA59
MA_DATA6
C13
MA_DATA60
AB14
AA14
MA_DATA61
AB12
MA_DATA62
MA_DATA63
AA12
MA_DATA44
MA_DATA45
AD21
MA_DATA46
AD19
Y18
MA_DATA47
AD17
MA_DATA48
MA_DATA49
W16
MA_DATA5
H12
MA_DATA50
W14
Y14
MA_DATA51
MA_DATA52
Y17
AB17
MA_DATA53
AB15
MA_DATA35
AA21
W22
MA_DATA36
MA_DATA37
W21
MA_DATA38
Y22
AA22
MA_DATA39
H11
MA_DATA4
MA_DATA40
Y20
AA20
MA_DATA41
AA18
MA_DATA42
MA_DATA43
AB18
AB21
F22
MA_DATA26
H24
J19
MA_DATA27
MA_DATA28
E21
E22
MA_DATA29
MA_DATA3
G14
H20
MA_DATA30
MA_DATA31
H22
MA_DATA32
Y24
AB24
MA_DATA33
AB22
MA_DATA34
MA_DATA15
G18
MA_DATA16
MA_DATA17
C19
MA_DATA18
D22
E20
MA_DATA19
H14
MA_DATA2
MA_DATA20
E18
F18
MA_DATA21
B22
MA_DATA22
MA_DATA23
C23
F20
MA_DATA24
MA_DATA25
MA_CLK_L1
F16
AA16
MA_CLK_L2
P20
MA_CLK_L3
MA_DATA0
G12
F12
MA_DATA1
E17
MA_DATA10
MA_DATA11
H17
E14
MA_DATA12
MA_DATA13
F14
MA_DATA14
C17
G17
MA_BANK0
MA_BANK1
R23
J21
MA_BANK2
MA_CAS_L
T22
MA_CKE0
J22
J20
MA_CKE1
MA_CLK_H0
N19
E16
MA_CLK_H1
MA_CLK_H2
Y16
P19
MA_CLK_H3
MA_CLK_L0
N20
MA_ADD13
K24
MA_ADD14
MA_ADD15
K19
MA_ADD2
N22
M19
MA_ADD3
MA_ADD4
M22
L20
MA_ADD5
M24
MA_ADD6
MA_ADD7
L21
L19
MA_ADD8
MA_ADD9
K22
R20
V22
MA0_ODT1
MA1_CS_L0
U20
V20
MA1_CS_L1
U21
MA1_ODT0
MA1_ODT1
V19
N21
MA_ADD0
MA_ADD1
M20
MA_ADD10
R21
L22
MA_ADD11
MA_ADD12
K20
V24
CN12-2
FOX_PZ63823_284S_41F_TEMP_638P
T20
MA0_CS_L0
MA0_CS_L1
U19
MA0_ODT0
T19
MB_DQS#(4)
MB_DQS#(3)
MB_DQS#(3)
MB_DQS#(2)
MB_DQS#(2)
MB_DQS#(1)
MB_DQS#(1)
MB_DQS#(0)
MB_DQS#(0)
MB_DATA(63:0)
MB_DQS(5)
MB_DQS(5)
MB_DQS(4)
MB_DQS(4)
MB_DQS(3)
MB_DQS(3)
MB_DQS(2)
MB_DQS(2)
MB_DQS(1)
MB_DQS(1)
MB_DQS(0)
MB_DQS(0)
MB_DQS#(5)
MB_DQS#(5)
MB_DQS#(4)
MB_WE#
MB_RAS#
MB_CAS#
MB_BA2 MB_BA1 MB_BA0
MB_DQS(7)
MB_DQS(7)
MB_DQS#(7)
MB_DQS#(7)
MB_DQS(6)
MB_DQS(6)
MB_DQS#(6)
MB_DQS#(6)
MB_DM(7) MB_DM(6)
MB_CLK_DDR1
MB_CLK_DDR2
MB_CLK_DDR1#
MB_CLK_DDR2#
MB_CKE0
MB_CKE1
MB_CS1# MB_CS0#
MB_ODT1 MB_ODT0
MA_BA1 MA_BA0
MA_CKE1 MA_CKE0
MB_DM(7:0)
MB_DM(5) MB_DM(4) MB_DM(3) MB_DM(2) MB_DM(1) MB_DM(0)
MA_DQS#(1)
MA_DQS#(1)
MA_DQS#(0)
MA_DQS#(0)
MA_CS1# MA_CS0#
MA_ODT1 MA_ODT0
MA_WE#
MA_RAS#
MA_CAS#
MA_BA2
MA_DQS(1)
MA_DQS(0)
MA_DQS(0)
MA_DQS#(7)
MA_DQS#(7)
MA_DQS#(6)
MA_DQS#(6)
MA_DQS#(5)
MA_DQS#(5)
MA_DQS#(4)
MA_DQS#(4)
MA_DQS#(3)
MA_DQS#(3)
MA_DQS#(2)
MA_DQS#(2)
MA_DM(7) MA_DM(6)
MA_DQS(6)
MA_DQS(6)
MA_DQS(5)
MA_DQS(5)
MA_DQS(4)
MA_DQS(4)
MA_DQS(7)
MA_DQS(7)
MA_DQS(3)
MA_DQS(3)
MA_DQS(2)
MA_DQS(2)
MA_DQS(1)
MB_A(15) MB_A(14)
MA_CLK_DDR2
MA_CLK_DDR2#
MA_CLK_DDR1
MA_CLK_DDR1#
MA_DM(7:0)
MA_DM(5) MA_DM(4) MA_DM(3) MA_DM(2) MA_DM(1) MA_DM(0)
MB_A(10)
MB_A(9) MB_A(8) MB_A(7) MB_A(6) MB_A(5) MB_A(4) MB_A(3) MB_A(2) MB_A(1) MB_A(0)
MA_A(4) MA_A(3) MA_A(2) MA_A(1) MA_A(0)
MA_A(15) MA_A(14)
MB_A(15:0)
MB_A(13) MB_A(12) MB_A(11)
MB_DATA(0)
MA_A(15:0)
MA_A(13) MA_A(12) MA_A(11) MA_A(10) MA_A(9) MA_A(8) MA_A(7) MA_A(6) MA_A(5)
MB_DATA(11) MB_DATA(10)
MB_DATA(9) MB_DATA(8) MB_DATA(7) MB_DATA(6) MB_DATA(5) MB_DATA(4) MB_DATA(3) MB_DATA(2) MB_DATA(1)
MB_DATA(22) MB_DATA(21) MB_DATA(20) MB_DATA(19) MB_DATA(18) MB_DATA(17) MB_DATA(16) MB_DATA(15) MB_DATA(14) MB_DATA(13) MB_DATA(12)
MB_DATA(32) MB_DATA(31) MB_DATA(30) MB_DATA(29) MB_DATA(28) MB_DATA(27) MB_DATA(26) MB_DATA(25) MB_DATA(24) MB_DATA(23)
MB_DATA(43) MB_DATA(42) MB_DATA(41) MB_DATA(40) MB_DATA(39) MB_DATA(38) MB_DATA(37) MB_DATA(36) MB_DATA(35) MB_DATA(34) MB_DATA(33)
MB_DATA(54) MB_DATA(53)
MB_DATA(52) MB_DATA(51) MB_DATA(50) MB_DATA(49) MB_DATA(48) MB_DATA(47) MB_DATA(46) MB_DATA(45) MB_DATA(44)
MB_DATA(63) MB_DATA(62) MB_DATA(61) MB_DATA(60) MB_DATA(59) MB_DATA(58) MB_DATA(57) MB_DATA(56) MB_DATA(55)
MA_DATA(10)
MA_DATA(9) MA_DATA(8) MA_DATA(7) MA_DATA(6) MA_DATA(5) MA_DATA(4) MA_DATA(3) MA_DATA(2) MA_DATA(1) MA_DATA(0)
MA_DATA(21) MA_DATA(20) MA_DATA(19) MA_DATA(18) MA_DATA(17) MA_DATA(16) MA_DATA(15) MA_DATA(14) MA_DATA(13) MA_DATA(12) MA_DATA(11)
MA_DATA(32) MA_DATA(31) MA_DATA(30) MA_DATA(29) MA_DATA(28) MA_DATA(27) MA_DATA(26) MA_DATA(25) MA_DATA(24) MA_DATA(23) MA_DATA(22)
MA_DATA(42) MA_DATA(41) MA_DATA(40) MA_DATA(39) MA_DATA(38) MA_DATA(37) MA_DATA(36) MA_DATA(35) MA_DATA(34) MA_DATA(33)
MA_DATA(53) MA_DATA(52) MA_DATA(51) MA_DATA(50) MA_DATA(49) MA_DATA(48) MA_DATA(47) MA_DATA(46) MA_DATA(45) MA_DATA(44) MA_DATA(43)
MA_DATA(63)
MA_DATA(63:0)
MA_DATA(62) MA_DATA(61) MA_DATA(60) MA_DATA(59) MA_DATA(58) MA_DATA(57) MA_DATA(56) MA_DATA(55) MA_DATA(54)
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MISC
Keep trace to resistors less
and trace to AC caps less than 1250mils.
SHEET
SIZE
DOC. NUMBER REV
INVENTEC
TITLE
Keep trace to resistor less than 600mils from CPU pin
Routing differential pair type
To put pull high resistors near switching power source
CPU-3
Piaget 2.0 Discrete
CS
A3
6018
1310A22683-0-MTRA02
Jason Chiu 20-Jul-2009
HDT Header
CODE
Keep trace to resistors less
OF
Routing differential pair type
than 1" from CPU pin.
than 1" from CPU pin.
Routing differential pair type
CHANGE by
300_5%R280
1 2
3
4
4 5
5
6
6 7
7
8
8 9
9
8-,23-
2
20
20
21
21
22
22 23
23
24
24 25
25 26
26
3
13
13
14
14 15
15
16
16 17
17
18
18 19
19
2
CN1003
SAMTEC_ASP_68200_26P_OPEN
1
1
10
10
11
11
12
12
1
2
300_5%
R1112
1 2
1 2
1K_1%
R1175
1
2
C120
3900pF_16V
51_5%
R46
1
2
R322 300_5%
VDDIO_FB_H VDDIO_FB_L
Y9
VDDNB_FB_H
H6 G6
VDDNB_FB_L
F6
VDD_FB_H VDD_FB_L
E6
Y10
VTT_SENSE
18-,26-,36-
TEST6
TEST7
C3
TEST8
C4
C2
TEST9
W8
THERMDA
THERMDC
W7
AF6
THERMTRIP_L
AA9
TMS
AD9
TRST_L
VDD1_FB_H
Y6
AB6
VDD1_FB_L
W9
TEST22
AE8
AD7
TEST23
TEST24
AE7
E9
TEST25_H TEST25_L
E8
AF8
TEST27
J7
TEST28_H TEST28_L
H8
TEST29_H
C9 C8
TEST29_L
AA6
TDO
K8
TEST10
AC8
TEST12
TEST14
C7
F7
TEST15
TEST16
E7
D7
TEST17
TEST18
H10
G9
TEST19
TEST20
AF7
AB8
TEST21
M_ZN M_ZP
AF10
PROCHOT_L
AC7
PWROK
A7
RESET_L
B7
SIC
AF4 AF5
SID
A6
SVC SVD
A4
TCK
AC9
TDI
AF9 AE9
G10
DBREQ_L
E10
VDDA
F8 F9
VDDA
R6
HTREF0
HTREF1
P6
LDTREQ_L
C6F10
LDTSTOP_L
AA8
MEMHOT_L
M_VREF
W17
AE10
CN12-4
FOX_PZ63823_284S_41F_TEMP_638P
ALERT_L
AE6
A9
CLKIN_H CLKIN_L
A8
DBRDY
TP1011
18-
9-,11-,15-,19-,27-,36-,37-,57-
TP1009
18-
10-
13-,14-,18-,24-,26-,27-,30-,38-,57-
1 2
3300pF_50V
C1087
1 2
2
18-
470_5%
R1114
1 2
C1208
0.22uF_6.3V
1
1 2
R1111
300_5%
R150
300_5%
R148 1K_1%
1
2
15-
10-
TP1019
300_5%R282
1 2
39.2_1%
R286
1 2
10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-
TP1012
100pF_50V
C435
1 2
13-,14-,18-,24-,26-,27-,30-,38-,57-
R151 1K_5%
1
2
10-
18-,36-
10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-
10-,19-,57-
TP1010
169_1%
R149
1
2
38-
2
1K_1%
R147
1
2
10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-
10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-
18-
R152 30K_5%
1
1 2
C436
100pF_50V
1 2
1000pF_50V
C1207
1
2
10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-
1 2
15-
L1008
BLM11A221S
39.2_1%
R285
1 2
604_1%
R284
TP22
10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-
C1088
0.22uF_6.3V
1
2
0_5%_OPEN
1
2
TP1004
R340
300_5%
1
2
TP1003
Q31
MMBT3904
B
1
C32E
R323
R47 51_5%
1
2
3900pF_16V
C119
1 2
18-
23-,29-,38-
18-
TP1008
1 2
18-,26-,36-
18-
TP1016
18-,26-,36-
4.7uF_6.3V
C1086
1 2
TP1015
R1113
300_5%
TP1002
10-
TP1017
R341
300_5%
1
2
18-
TP1007
R283
604_1%
1 2
13-,14-,18-,24-,26-,27-,30-,38-,57-
18-,36-
300_5%
R1531 2
18-
10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-
44.2_1% R1186
1
2
TP23
1K_5%
R327
1
2
18-,26-,36-
300_5%R277
1 2
18-,36-
R1176 1K_1%
1
2
7-
B
1
C32E
18-,36-
18-
TP1014
18-
Q35
MMBT3904
TP1001
12
18-,36-
TP1013
38-
R118744.2_1%
10-
10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-
10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-
TP1005
R281
1 2
10-
18-
18-
18-
+V1.8
18-
18-
23-,29-,38-
300_5%
+V1.8
+V1.8
+V1.8S
+V1.8
+V1.8S
+V1.8S
PROCHOT#CPU_SID
CPU_MVREF
+V1.8
CPU_SVC_R CPU_SVD_R
VDD1_FB
VDD1_FB#
CPU_THERM_SCI#
Therm_SCI#
LDT_REQ#
CPU_MVREF
+V1.8
LDT_REQ#
CPU_DBRDY
CPU_DBREQ#
+V1.2S
THERMTRIP#
H_THERMTRIP#CPU_SIC
LDT_PG
LDTSTOP#
LDT_RST#
LDT_PG
LDT_RST#
LDTSTOP#
+V1.8
CPU_TDO
LDT_RST#
+V1.8
+V2.5S
CPU_VDDA
CLK_R_CPUBCLK#
CLK_R_CPUBCLK
CPUBCLKIN_H CPUBCLKIN_L
CPU_TDI
CPU_TRST#
CPU_TCK
CPU_TMS
CPU_TDO
CPU_DBRDYCPU_DBREQ#
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TCK
+VCC_CORE
COREFB
COREFB#
+V1.8
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