Inventec Luxor-10FG Schematics

THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC
CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT
WRITTEN PERMISSION,INVENTEC CORPORATION,2009 ALL RIGHT RESERVED.

8

7654321

HSF Property:ROHS or Halogen-Free(5L3?)

E

D

FF

E

D

LUXOR10FG

2011.08.02

C

B

A

21-OCT-2002

DATE CHANGE NO.

8

REV

76543

DRAWER

DESIGN

CHECK

RESPONSIBLE

FILE NAME:
P/N

C

B

POWER

DATEDATEEE

SIZE=

XXX

VER:

2

TITLE

MODEL,PROJECT,FUNCTION

Everest Main Board

SIZE

CODE

C

INVENTEC

DOC.NUMBER REV

1310xxxxx-0-0

CS

SHEET

1

A

X01

of

661

87

65

TABLE OF CONTENTS

4

32 1

D

PAGE

1. COVER PAGE

2. INDEX

3. BLOCK DIAGRAM

4. POWER MAP

5. POWER CHARGER

6. POWER +V3LA/+V3A/+5A

7. POWER +V1.5/+V0.75

8. POWER +V1.8S

9. POWER VCCIO

10. POWER VCCSA

11. POWER VCORE

12. POWER VGFX

13. POWER VCORE_DGPU

14. ENABLE PIN

15. LOAD SWITCH

16. PCB SCREW

B

17. HALL SENSOR

18. LED

19. K/B & TP/B CONN

20. EC

21. LAN

22. RJ45 & TRANSFORMER

23. AUDIO CODEC

24. SPEAKER/HP JACK/MIC JACK

PAGE

25. CARDREADER

26. MINI1 WLAN/DEBUG CARD

27. MINI2 3G

28. SATA HDD/ODD CONN

29. USB 2.0 CONN

30. USB 3.0 CONTROLLER

31. USB 3.0 CONN W/ S&C

32. USB 3.0 CONN

33. LCM CONN

34. CRT CONN

35. HDMI CONN

36. DDR3 DIMM0

37. DDR3 DIMM1

38. FAN & THERMAL SENSOR

39. CPU 1

40. CPU 2

41. CPU 3 DRAM

42. CPU 4 POWER

43. CPU 5 POWER

44. CPU 6 GND

45. PCH 1

46. PCH 2

47. PCH 3

48. PCH 4 AXG

PAGE

49. PCH 5 USB

50. PCH 6 MISC

51. PCH 7 POWER

52. PCH 8 POWER

53. PCH 9 GND

54. VGA 1

55. VGA 2

56. VGA 3

57. VGA 4

58. VGA 5

59. VRAM 1

60. VRAM 2

61. VRAM 3

62. VRAM 4

63. POWER BUTTON BOARD

64. EMI

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

662

87

65

4

32 1

DDR3@1.5/0.75V

(1333/1600 MHZ)

204-PIN SODIMM0

DDR3@1.5/0.75V

(1333/1600 MHZ)

204-PIN SODIMM1

INTERNAL MIC IN

EXT MIC IN
HEADPHONE

D

CC

NVIDIA

W/ OPTIMUS

N13P-GL

PEG

IVY BRIDGE

DC 35W

SOCKET-RPGA989

37.5 X 37.5 X 5 mm

DDR3 INTERFACE

DDR3 INTERFACE

29X 29 MM

D

FDI

DMI 2.0

AUDIO CODEC

HDMI

HDA

REA_ALC269Q_VB6

PCH

CRT

LCM

LVDS

PANTHER POINT

25 X 25 X 2.3 mm

USB2.0

SLEEP & CHARGE

USB_0: USB CONN
USB_2: USB CONN

USB_5: MINICARD WLAN

USB_8: CARD READER
USB_10:WEBCAM

B

RJ45

PCIE_1:LAN

ATHEROS_AR8161/8162

PCIE_2:WLAN

PCIE_3:USB3.0

PCIE

PCIE

PCIE

USB2.0

SATA

SPI

USB3.0

USB_1: USB3.0 CONN

USB_8:CARD READER

REA_RTS5129

SATA0:ESATA
SATA1: HDD

B

SATA6: ODD

ENE-P2809A

THERMAL SENSOR

EC WINDBOND

NPCE885LA0DX

SPI

SPI FLASH 8MB

MXIC_MX25L3206EM2I

AA

BATTERY CHARGER &

DC/DC & IMVP 7

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

REV

of

1

X011310xxxxx-0-0

663

LI-ION BATTERY

6-Cell

8

76

KEYBOARD

TOUCH PAD

54

CHANGE by

DATE

21-OCT-2002XXX

23

87

65

4

32 1

ADAPTOR

FUSE

65W-75W 8A 6036A0003401
90W 10A 6036A0002901

D

120W 12A 6036A0006001

BQ24725RGRR

CHARGER

EC_SMB2
CHG_EN
BATT_IN
ACPRES

BATTERY PACK

+VCORE_+-0.5%

+VCORE1_+-0.5%

TI_TPS61640

POWER BUDGET 53A
F 280K
OCP 53A
PEAK 53A AVG 28.822A
1880UF_1.1M£[ // 2276UF_0.203M£[

VDD_CORE

TPS51217

POWER BUDGET 20.070A
F 340K
OCP 29.1A R=75K
PEAK 20.070A AVG 11.531A
560UF_25M£[ // 80UF_0.93M£[

B

+VBAT

TPS51123

POWER BUDGET 12.139 A
F 300K
OCP 10.4A R=120K
PEAK 7.283A AVG 2.363A
220UF_25M£[ // 53.92UF_1.529M£[

TPS51123

POWER BUDGET 9.429 A
F 375K

OCP 10.7A R=130K
PEAK 5.695A AVG1.048 A
220UF_25M£[ //10.6UF_5.924M£[

TPS51216

POWER BUDGET 13.7 A
F 340K
OCP 10.1A R=115K
PEAK 17.107A AVG4.835 A
560UF_25M£[ // 1274.8UF_0.214M£[

+V5A_+-5%

+V3LA_+-5%

V1.5_+-5%

AO6402L

POWER BUDGET 4.711A
PEAK2.592A

100.82UF_0.842M£[

TSP51461

POWER BUDGET 6A
F 340K
OCP 6A
PEAK 6A AVG 1.262A

AO6402L

POWER BUDGET 4.711A
PEAK2.592A

100.82UF_0.842M£[

AO6402L

POWER BUDGET 4.711A
PEAK2.592A

100.82UF_0.842M£[

TPS51216

AON7410

INRUSH 0.9A

+V3A

INRUSH 0.9A

+V3S

INRUSH 0.9A

+V5S

+V0.85S_+-0.5%

AM2321P

POWER BUDGET 4.711A
PEAK2.592A

GMT_AT1530F11U

POWER BUDGET 4.711A
PEAK2.592A

+V0.75S

+V1.5S

INRUSH 0.9A

100.82UF_0.842M£[

INRUSH 0.9A

100.82UF_0.842M£[

D

+V3_LAN

+V1.8S

CC

B

TPS51216

POWER BUDGET 13.7 A
CHANGING POINTS~~
TPS51218 SAME AS 2009 PROJECT OCP 10.1A R=115K
TPS51217 SAME AS 2010 PROJECT

+V1.8S IS NEW IC GMT_AT1530F11U
CHARGE IS NEW IC BQ24725
VCC CORE IS NEW IC TPS51640
VTT IS NEW IC TPS51219
V0.85 IS NEW IC TPS 51641
V3_V5 IS NEW IC TPS51123
POWER BUDGET ~~IC SPEC (MAX CURRENT )
PEAK CURRENT ~~RATIO OF INTERNAL PREDICTION
AVG CURRENT ~~TEST RESULT(MAX CURRENT)
INRUSH ~~L/S TURN NO

8

76

54

F 340K

PEAK 17.107A AVG4.835 A

560UF_25M£[ // 1274.8UF_0.214M£[

+VTT_+-5%

AON7410

CHANGE by

+V1.5_CPU

DATE

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

664

FUSE6000
65W-75W 8A(6036A0003401)
90W 10A(6036A0002901)

120W 12A(6036A0006001)

D

PVADPTR

C6014

R6018

B

87

CN6000

ACES_91202_0047N_TSB_4P

4.7K_5%_3

RSC_0603_DY

8

D

7
6

AM4410NC

OUT

100PF_50V_2

OUT

BI

BI

2200PF_50V_2

P3V3AL

HW_I_ADC

C6037

NEAR EC

EC_SMB2_DATA

EC_SMB2_CLK

CSC0805_DY

R6019

21

2121

RSC_1206_DY

R6003

3.32K_1%_3

RSC_1206_DY

21E6

21 21

R6002

20.5K_1%_2

ACPRES

21E8 21E6

C6029

CSC0603_DY

21

21D3 21D2

60D2

21D3 21D2

60E2

8

65

C7602

10PF_50V_2

D

8
7
6

L7600

NFE31PT222Z1E9L

R6015

R6014

NMOS_4D3S

C7601

1000PF_50V_2

21

1
2
3
45

C6031C6030

FUSE6000

8A_125V

1
2
3
45

2121

21

Q6011Q6010

S

G

NMOS_4D3S

AM4410NC

1

1

2

2

3

3

4

4

21

21

S

G

0.1UF_25V_3

R6006

21

C6036

100PF_50V_2

NEAR IC

21

C6035

21

R6016

21

R6017

21

21

CSC0402_DY

C6034

21

TI_BQ24725RGRR_QFN_20P

21

R6005R6004

4.3K_5%_24.3K_5%_2

21

R6013

10K_5%_3

21

RSC_0603_DY

21

CSC0402_DY

SHORT_0402

SHORT_0402

30K_5%_2

76

4

3

3

D6002

DIODES_BAV99

P3V3AL

R6008

2121

21E8 21E6

0.1UF_25V_3

R6007

110K_5%_2

2121

PVADPTR

OUT

0.1UF_16V_2_DY

0.1UF_16V_2

21

U6000

6

ACDET

7

IOUT

8

SDA

9

SCL

10

ILIM

C6032

0.1UF_16V_2

21

4

PVBAT

R6800

RSC_0603_DY

R6802

RSC_0603_DY

R6801

21

21E8 21E6

2121

EC_SMB1_DATA

21D2

21D3

EC_SMB1_CLK

HW_V_ADC

0.01_1%_6

R6000

C6020

C6800

NEAR EC

21
43

21

33K_5%_2_DY

21

PVADPTR

11

ACOK

BATDRV

D6000

C6022C6021

21

0.1UF_25V_3

3

251

4

ACP

ACN

ACDRV

CMSRC

PHASE
HIDRV

BTST
REGN

LODRV

SRP

SRN

GND

13

12

15

14

1UF_10V_2

TML

VCC

C6028

1UF_25V_3

21

20
19
18
17
16

21

C6026

21

D6001

BAT54C_30V_0.2A

C

3

21

A2A1

BAT54C_30V_0.2A

R6012

10_5%_5

VRCHARGER_HG

VRCHARGER_PH

C6027

3

0.047UF_16V_2

C

A2A1

21

AON7410 AON7410

21

21

VRCHARGER_LG

R6011

21

SHORT_0402

R6010

21

6.98_1%_2

R6009

21

4.3K_5%_2

54

OUT

BATT_IN

21D2

21D3

BI
BI

EZJZ0V500AA_DY

PVBAT

12

PAD6000

POWERPAD_2_0610

21

678

Q6000

D

NMOS_4D3S

G

S

321

45

678

D

NMOS_4D3S

G

S

321

45

C6001 C6002 C6003

470PF_50V_2

21

Q6001

D6700

21

CHANGE by

32 1

R6054 R6053

2121

1M_5%_2

33_5%_2

R6050

21
21

21

33_5%_2

R6051

EZJZ0V500AA_DY

R6052

220K_1%_2

P3V3AL

1K_5%_2

21

PVPACK

21

21

EZJZ0V500AA_DY

C6050

1000PF_50V_2

D6703D6702D6701

FUSE6050

21

LITTLEFUSE_R451015_15A_65V

1
2
3
4
5
6

21

7
8
9

SYN_200045GR009G15JZR_9P

CN6050

BATT+
BATT+
ID
B-I
TS
SMD
SMC
GND
GND

G1

G

G2

G

G3

G

G4

G

PVPACK

1
2
3

0.1UF_25V_3

45

C6013

21

4.7UF_25V_5

C6033

CSC0805_DY

21

21

R7600

RSC_0603_DY

SBR3U40P1_DY

21

4.7UF_25V_5

21

L6000

PCMC063T_4R7MN

C7600

CSC0402_DY

21

21

C6024

21

0.1UF_25V_3

0.01_1%_6

0.1UF_16V_2

R6001

C6023

21

21
43

21

C6025

C6004

CSC0805_DY4.7UF_25V_5

C6010

21

21

0.1UF_25V_3

Q6012

8

D

7
6

NMOS_4D3S

TPCA8065_H

C6011

21

4.7UF_25V_5

S

G

C6012

21

4.7UF_25V_5

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

665

D

CC

B

AA

87

65

4

32 1

IN

IN

R6114

2.2_5%_3

P3V3_LDO

C6121

EN_5V

EN_3V

2121

VRP3V3A_HG
VRP3V3A_PH
VRP3V3A_LG

14C7

14C7

21

R6160

2121

120K_1%_2

R6110

130K_1%_2

3

1

4

5

25

TML

724

VO2 VO1

8

VREG3

922

VBST2

10 21

DRVH2

11 20

LL2

12 19

DRVL2

SKIP_3V_5V

IN

VRP5V0A_VIN

IN

R6113

RSC_0402_DY

2

TONSEL

TRIP2

TRIP1

VREF

VFB1

VFB2

U6100

SKIPSEL

VREG5

ENC

VIN

EN0

GND

14

16

15618

13

17

C6122

1UF_25V_3

21

21

21

23

PGOOD
VBST1

VRP5V0A_HG

DRVH1

VRP5V0A_PH

LL1

VRP5V0A_LG

DRVL1

TI_TPS51123RGER_QFN_24P

VRP5V0A_LDO

OUT

5V_PG

OUT

C6123

0.22UF_6.3V_2

2.2_5%_3

0.1UF_16V_2

EN_3V_5V

C6120

10UF_6.3V_3

21

D

VRP5V0A_PH2VREF

6C614C8

IN

678

AON7410

NMOS_4D3S

C6155R6155

IN

OUT

G

2121

321

45

678

AON7702L

G

321

45

VBATP

D

S

D

S

14D6

OUT

Q6150

Q6151

6D3

4.7UF_25V_5

2121

R7615

RSC_0603_DY

C7615

CSC0402_DY

21

C6161C6160

4.7UF_25V_5

21

ETQP3W3R3WFN

330UF_6.3V

C6150

2121

+

21

R6150

15.4K_1%_2

R6151

10K_1%_2

VRP5V0A

OUT

CC

14D6
14C8
14D4

B

VO=(( R6150/R6151)+1)*2

VRP5V0A_LG

OUT

6B3 14D5

14D7

D

PVBAT

14C7

PAD6110

12

POWERPAD_2_0610

VBATP

21

C6110

4.7UF_25V_5

OUT

VRP3V3A

R6100

6.8K_1%_2

21

R6101

10K_1%_2

21

C6100

+

330UF_6.3V

21

14D6

B

L6100 L6150

ETQP3W3R3WFN

C6111

4.7UF_25V_5

21

21 21

R7610

RSC_0603_DY

C7610

CSC0402_DY

6C3 14C8

OUT

D

21

S

Q6101

D

21

S

21

678

Q6100

NMOS_4D3S

AON7410

G

321

C6115

45

0.1UF_16V_2

678

AON7702L

G

321

45

1UF_6.3V_2

VOUT=((R6100/R6101)+1)*2

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

666

87

65

4

32 1

PVBAT

P5V0A

D

P0V75S

21

PAD6210

12

D

POWERPAD_2_0610

C6216

21

2.2UF_6.3V_3

U6200

14D1

IN
IN

21

C6218

21

0.1UF_16V_2

EN_1V5

R6203

21

100K_5%_2

R6202

21

75K_1%_2

14D1

C6217

21

52.3K_1%_2

R6200

10K_1%_2

0.01UF_50V_2

DDR3L_SEL

IN

21

R6201

B

17

S3

16

S5

6

VREF

8

REFIN

7

GND

19

MODE

18

TRIP

TI_TPS51216RUKR_QFN_20P

VDDQSNS

VLDOIN

VTTSNS

VTTGND

VTTREF

PGOOD

1512

VBSTV5IN

14

VRP1V5_HG

DRVH

VRP1V5_PHEN_0V75

13

SW

VRP1V5_LG

11

DRVL

10

PGND

20

9

2

3

VTT

1

4

5

21

TML

2.2_5%_3

P0V75M_VREF

C6220

21

10UF_6.3V_5

C6221

21

0.1UF_16V_2

0.22UF_6.3V_2

C6215R6215

2121

678

FDMC8884

D

NMOS_4D3S

G

S

321

45

678

FDMS0310AS

Q6201Q6200

D

G

S

321

45

1V5_PG

OUT

14C2

C6211

C6210

21

4.7UF_25V_5

R7620

C7620

C6212

21

21

4.7UF_25V_5

2121

RSC_0603_DY

CSC0402_DY

4.7UF_25V_5

ETQP3W1R0WFN

L6200

+

C6200

POWERPAD1X1M

21

VRP1V5

560UF_2.5V

OUT

14C2

CC

21

21

12

PAD6220

B

VOUT=REFIN=1.8*(R6201/(R6200+R6201))

MODE=100KOHM:TRACKING DISCHARGE

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

667

87

65

4

32 1

D

P5V0A

P3V3S

D

CC

VIN

VCC

EN

GMT_AT1530F11U_SOP8_8P

PGNDLXGND

673

9

TML

VRP1V8S_PH

L6970

VOUT=((13K+10K)+1)*0.8

21

OCP=4.5AMP

VRP1V8S

OUT

14A2

PAN_ELL5PR2R2N

4

FB

2

REF

C6973

21

0.1UF_16V_2

R6973R6972

C6974

13K_1%_2

2121

10K_1%_2

C6970

21

21

CSC0402_DY

22UF_6.3V_5

B

U6970

EN_1V8

C6971

21

10UF_6.3V_3

8

1

5

R6970C6972

10_5%_2

2121

14B1

IN

B

0.1UF_16V_2

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

668

87

65

4

32 1

D

C6311

21

4.7UF_25V_5

21

R7630

RSC_0603_DY

C7630

CSC0402_DY

21

PVBAT

2121

12

PAD6310

POWERPAD_2_0610

C6312

4.7UF_25V_5

L6300

21

21

43

43

CYN_PCMB063T_R68MS_4P

C6300

21

22UF_6.3V_5

+

C6301

21

560UF_2.5V

VRP1V05S

OUT

14A8

14B7

OUT

VCCP_PG

14A814B6

P3V3A

R6306

21

10K_5%_2

R6307

IN
IN
IN

VCCIO_SEL

VSS_SENSE_VCCIO

VCC_SENSE_VCCIO

C6318

21

2.2UF_6.3V_3

45A2

44A2

44A2

B

21

0_5%_2_DY

TI_TPS51219RTER_QFN_16P

0.01UF_50V_2

VOUT=1.05V@REFIN=3.3V; VOUT=1.0V@REFIN=GND

EN_VCCP

IN

U6300

1

VREF

2

REFIN

3

GSNS

4

VSNS

C6319

21

R6303

21

100K_5%_2

17

16815

PWPD

MODE

PGOOD

TRIP

GND

COMP

6

7

5

21

R6302

86.6K_1%_2

21

0.1UF_16V_2

P5V0A

C6316

21

2.2UF_6.3V_3

C6315

21

R6315

14

13

2.2_5%_3

EN

BST

12

VRP1VO_VCCP_PH

SW

11

VRP1VO_VCCP_HG

DH

10

VRP1V0_VCCP_LG

DL

9

V5

PGND

678

FDMC8884

D

NMOS_4D3S

G

S

321

45

678

FDMS0310AS

Q6301Q6300

D

G

S

321

45

C6310

21

4.7UF_25V_5

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

669

87

65

4

32 1

D

C6522

21

R6524

R6525

0.01UF_50V_2

21

VCCSA_SENSE

0.1UF_16V_2

EN_SA

21

VCCSA_VID0

21

VCCSA_VID1

14A6 21B6

C6515

45A2

IN

L6500

21

21

43

21

14B5

IN

45A2

IN

45A2

IN

CYN_PCMB063T_R33MS_4P

R7650

RSC_0603_DY

21

C7650

CSC0402_DY

21

43

22UF_6.3V_5

21

21

21

VRPVCCSA

C6503C6502C6501C6500

22UF_6.3V_5_DY22UF_6.3V_522UF_6.3V_5

21

OUT

14A6

5.11K_1%_2

C6521

0.22UF_6.3V_2

R6520

21

R6521

COMP

PGOOD

16

5

4

6

VOUT

SLEW

MODE

EN

VID1

VID0

151417

RSC_0402_DY

TI_TPS51461RGER_QFN_24P

7

VRPVSA_PH

SWVIN

8

SW

9

SW

10

SW

11

SW

12

BST

2

1133

GND

25
24
23
22
21
20
19

VREF

TML

VIN

U6500

VIN
PGND
PGND
PGND

V5FILT

V5DRV

18

P5V0A

22UF_6.3V_5

21

3300PF_50V_2

C6511C6510

0.1UF_16V_2

21

C6520

21

21

SHORT_0402

B

C6523

21

1UF_6.3V_2

C6524

21

1UF_6.3V_2

SA_PG

SHORT_0402

OUT

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6610

D

B

21D3

R6638

87

2+1 2+0

R6626

3.3K
R6627
R6711

200K

R6712

30K

R6714

DNP 0

R6716

DNP

R6719

DNP

R6723 DNP 0

VREF_CPU

R6711

200K_1%_2

2121

R6712

30K_1%_2

IN

R6628

0_5%_2_DY

2121

R6629

20K_1%_2

EN_PVCORE

8

DNP
DNP56K
DNP
DNP

0
0

P3V3A

11C8 11D4
11B7
11A4

IN

11A7

C6633

21

2.2UF_6.3V_3

45C3

IN

45C3

R6630

20K_5%_2

2121

VR_ON

R6631

8.66K_1%_2

11D6 11D7

OUT

2.2UF_6.3V_3

GFX_VSS_SENSE

GFX_VCC_SENSE

0_5%_2_DY

OUT

11A411A711B711C811D411D7

IN

11A411A711B7
11C811D411D6

VREF_CPU

IN

C6632

100PF_50V_2

R6625

21

21

8.45K_1%_2

R6626

3.3K_1%_2

21

R6627

56K_1%_2

21

13

21

21

100PF_50V_2

4.12K_1%_2

IN

R6718

C6726

14

15

16

17

18

19

20

21

22

23

24

21

21

VREF_CPU

VREF_CPU

C6634

11C7

11A7

11A440B449B7

21

11A344B1

44B1

11A344B1

21C341D6

11A4

21

VR_ON

IN

PVCORE_PG

OUT

VR_SVID_CLK

IN

VR_SVID_ALERT#

OUT

VR_SVID_DATA

BI

CPU_PROCHOT#

OUT

PVAXG_PG

OUT

R6713

R6715

11D7
11D6
11C8

VREF_CPU

11A4

IN

11A7
11D4

R6716R6714

0_5%_2_DY

21

0_5%_2

0_5%_2

11A411B711C811D411D611D7

76

65

VREF_CPU

43K_1%_2

R6621

90.9K_1%_2

2

3

COCP-R

CF-IMAX

GPWM1

GPWM2

34

35

GPWM1

GPWM2

OUT

OUT

12B8

R6731

RSC_0402_DY

R6618

100K_5%_NTC

21

1

2.2UF_10V_3

CTHERM

GND

V5

CDH1

CBST1

CSW1

CDL1

V5DRV

PGND

CDL2

CSW2

CBST2

CDH2

VBAT

CPWM3

36

CPWM3

OUT

21

VREF_CPU

44A3

VSSSENSE

12

CGFB

GOCP-R

VREF

V3R3

VR_ON

CPGOOD

VCLK

ALERT#

VDIO

VR_HOT#

SLEW

GPGOOD

GF_IMAX

GGFB

25

P3V3A

R6719

R6723

R6728

15.4K_1%_2

100K_5%_NTC

44A3

INININ

VCCSENSE

10

11

CCOMP

CVFB

U6600

TI_TPS51650RSLR_QFN_48P

GCOMP

GVFB

26

21

0_5%_2_DY

21

0_5%_2_DY

21

R6729

21

P3V3A

11C3

IN

CPU_CSN2

CPU_CSP2

7

6

8

9

CCSP2

CCSP3

CCSN3

GCSP2

GCSN1

GCSP1

313233

30

282729

P3V3A

0_5%_2

0_5%_2

21

21

R6724

R6720

GPU_CSP1

GPU_CSN1

IN

IN

12C5

12C5

11C3

11D3

IN

IN

CPU_CSN1

5

CCSN2

CCSN1

GTHERM

GCSN2

C6727

0.1UF_16V_2_DY

21

11D3

IN

CPU_CSP1

4

CCSP1

GSKIP#

R6730

100K_5%_2

21

54

R6622R6620

39K_1%_2

R6623

24K_1%_2

GSKIP#

2121

2121

C6631

0.1UF_16V_2_DY

21

R6619

15.4K_1%_2

P5V0A

R6617

21

10_5%_3

21

P5V0A

49

48

47

R6601

46

45

44

43

42

41

40

39

38

37

2.2_5%_3

V5DRV_CPU

2.2_5%_3

R6616

21

IN

0.1UF_16V_2

21

10K_5%_3

PVBAT

11A7 11B7 11C8 11D4 11D6 11D7

IN

12C8

OUT

11C740B449B7

11B7

4

PVBAT

68UF_25V

VREF_CPU

21

V5DRV_CPU

C6630C6629

4.7UF_10V_3

21

C6622

21

0.1UF_16V_2

11D4

C6624R6606

2121

PVCORE_PG

OUT

PVAXG_PG

PAD6610

POWERPAD_2_0610

21

12

C6000

+

C6610

21

21

4.7UF_25V_5

11A4 11A7 11B7 11C8 11D6 11D7

IN

OUT

678

FDMS7692 FDMS7692

NMOS_4D3S

G

321

45

678

FDMS0306AS

G

321

45

678

NMOS_4D3S

G

321

45

678

FDMS0306AS

G

321

45

P3V3A

R6732

R6634

21

2K_5%_2

21

CHANGE by

32 1

C6611

21

4.7UF_25V_5

PVBAT_CPU

11C4

D

S

D

PVBAT_CPU

D

S

Q6621Q6611 Q6620Q6610

DS

S

C6613

C6612

21

4.7UF_25V_5

11D5

IN

R7661

RSC_0603_DY

2121

C7661

CSC0402_DY

11D5

11D5

IN

R7662

RSC_0603_DY

2121

C7662

CSC0402_DY

C6614

21

21

4.7UF_25V_5

4.7UF_25V_5

CPU_CSN1

OUT

CPU_CSP1

OUT

11B3 11D1

CPU_CSN2

OUT

CPU_CSP2

OUT

11D1 11D3

17.8K_1%

C6616

C6615

21

4.7UF_25V_5

100K_5%_NTC17.8K_1%

100K_5%_NTC

PVBAT_CPU

C6617

21

21

4.7UF_25V_5

4.7UF_25V_5

C6623

0.033UF_16V_2

R6605

162K_1%_2

R6603R6602

2121

PAN_ETQP4LR36ZFC_4P

L6610

0.033UF_16V_2

R6610

162K_1%_2

R6608R6607

2121

PAN_ETQP4LR36ZFC_4P

L6620

21

28.7K_1%_2

43
21

C6625

21

28.7K_1%_2

43
21

21

R6604

21

R6609

OUT

21

21

11B3 11D3

1

++

2

1

2

470UF_2V

3

C6602

470UF_2V

3

PVCORE

1

+

2

PVCORE

1

2

C6601C6600

470UF_2V

3

C6603

470UF_2V

+

3

P1V05S

C6635

R6633

2K_5%_2

11C7
44B1

11C744B1

VR_SVID_CLK

IN

VR_SVID_DATA

BIOUT

R6632

21

54.9_1%_2

DATE

130_1%_2

21

21

21-OCT-2002XXX

23

INVENTEC

0.1UF_16V_2

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CODE

SIZE

CS

A3

SHEET

DOC.NUMBER

REV

of

X011310xxxxx-0-0

6611

1

D

CC

B

AA

87

65

4

32 1

D

11A6

11A6

PVBAT_AXG

678

FDMS7692

C6720R6701

2.2_5%_3

U6710

11A4
11B5

GSKIP#

IN

GPWM1

IN

3

PWM

45

GND DRVL

TI_TPS51601DRBR_SON_8P

B

0.1UF_16V_2

PAD

DRVHBST

SWSKIP#

VDD

2121

9
81

72
6

P5V0A

C6721

21

1UF_6.3V_2

D

NMOS_4D3S

G

S

321

45

678

FDMS0306AS

Q6711Q6710

D

G

S

321

45

IN

R7671

RSC_0603_DY

2121

C7671

CSC0402_DY

GPU_CSN1

OUT

C6722

L6710

R6705

21

21

28.7K_1%_2

43
21

R6704R6703

2121

C6700

470UF_2V

PVAXG

1

2

+

3

3

1

+

C6701 C6702

470UF_2V_DY

2

1

+

470UF_2V

3

2

PVBAT

12

PAD6710

POWERPAD_2_0610

2121

C6711

C6710

4.7UF_25V_5

C6712

21

21

4.7UF_25V_5

4.7UF_25V_5

PVBAT_AXG

C6713

21

4.7UF_25V_5

OUT

12C5

GPU_CSP1

OUT

12B1

R6702

0.033UF_16V_2

162K_1%_2

21

100K_5%_NTC17.8K_1%

PAN_ETQP4LR36ZFC_4P

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6612

87

65

4

32 1

PVBAT

21

12

PAD6753

POWERPAD_2_0610

D

FDMS7692

NMOS_4D3S

G

45

FDMS0306AS

G

DGPU_PG

EN_DGPU

IN

14B2

C6790

21

2.2UF_6.3V_3

C6791

21

0.22UF_16V

13C4

B

13C4

OUT

13A4

13A4

56C2

IN

IN

56C2

G_CSP2

OUT

C6796

21

47PF_50V_2
47PF_50V_2

C6797

21

G_CSN2

G_CSN1

OUT

C6794

21

47PF_50V_2
47PF_50V_2

C6795

21

G_CSP1

OUT

PVCORE_DGPU_VSS

PVCORE_DGPU_SENSE

330_5%_2

C6799

R6757

330_5%_2

330_5%_2

C6798

47PF_50V_2

330_5%_2

R6756

21

21

47PF_50V_2

21

R6759

21

21

R6760

21

R6782

0_5%_2

R6783

0_5%_2

21

21

C6758C6757C6759

212121

CSC0402_DY

CSC0402_DY

P3V3S

GPU_SENSE

3900PF_16V_2

C6776

0.022UF_16V_2

R6779

124K_1%_2

C6792

330PF_50V_2

R6758

20K_5%_2

R6755

RSC_0402_DY

21

R6781

11.3K_1%_2

P3V3S

IN

13B1

21

21

10

21

0_5%_2

0_5%_2

21

1
2
3
4
5
6
7
8
9

R6799

R6798

21

6.8K_1%_2

U6750

PU
GND
CSP2
CSN2
CSN1
CSP1
GFB
VFB
THRM
THAL#

R6797

0_5%_2

33

341332

35

37

EN

PGD

PG#

SLEW

TONSEL

VID6

VID5

VID4

VID3

VID2

14151617181920

2

R6773

OSRSEL

VID1

1

DRVH2

TRIPSEL

VBST2

DRVL2

DRVL1

VBST1
DRVH1

VID0

LL2

V5IN
PGND

LL1

TML

0_5%_2_DY

DGPU_VID0

DGPU_VID1

R6777C6770

2121

40

383136

39

VREF

DROOP

V5FILT

SLP

PCNT

IMON

12

11

21

DGPU_VID2

DGPU_VID3

21

DGPU_VID4

DGPU_VID5

DGPU_VID6

14A4

OUT

52D6

R6772

21

0_5%_2

21

P3V3S

30

R6762

29

21

28

2.2_5%_2

0.47UF_25V_3

27

21

26
25

C6771

24

2.2UF_6.3V_3

23

R6761

22
21

2.2_5%_2

41

TI_TPS51728RHAR_QFN_40P

IN
IN
IN
IN
IN
IN
IN

C6766

21

C6767

21

21

0.47UF_25V_3

P5V0A

60C4

60C2

60C4

60C2

60C2 60C4 13B8

60C2

60D4

60D4

60C2

60C2

60C4

14A4

45

FDMS7692

FDMS0306AS

CSC0402_DY

8

76

54

PVBAT_GPU

678

D

321

678

321

Q6760 Q6761

S

D

S

R7676C7676

2121

34.8K_1%_2

RSC_0603_DY

C6760

21

CSC0402_DY

IN
IN

Q6750

D

S

D

Q6751

S

G_CSP2
G_CSN2

OUT

C6763

21

R7675

21

RSC_0603_DY

C7675

21

13B8

13B8

PVBAT_GPU

678

NMOS_4D3S

G

321

45

678

G

321

45

CSC0402_DY

G_CSP1

13A8

IN

G_CSN1

IN

OUT

4.7UF_25V_5

R6769

13D3

4.7UF_25V_5

34.8K_1%_2

CHANGE by

13C3

C6761

21

4.7UF_25V_5

L6751

ETQP4LR36AFM

R6754

21

62K_1%

422K_1%_2

21

0.01UF_50V_2

C6765

C6764

21

4.7UF_25V_5

L6750

ETQP4LR36AFM

62K_1%

C6762

21

4.7UF_25V_5

21
43

R6763

21

220K_5%_NTC

R6768

21

C6786

21

4.7UF_25V_5

21
43

R6753R6770

2121

R6771

422K_1%_2

C6787

21

0.01UF_50V_2

21

R6752

220K_5%_NTC

21

MAX=40A
OCP=56A

D

PVCORE_DGPU

470UF_2V

1

+

2

470UF_2V

C6752C6751C6750

+

+

470UF_2V

3

213

213

CC

R6774

GPU_SENSE

0_5%_2_DY

21

OUT

13A6

B

21

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6613

87

65

4

32 1

3V & 5V

3

Q7000

DS

SSM3K7002FU

1

G

C7000

21

2

0.047UF_16V_2

EC_PW_ON#

21C3 15D4

IN

EN_5V

D

21F6
14C8

IN

15D6

P5VAUXON

3

P3V3_LDO

6C114D4

14D6

6C6

6C3

21F6
14D8
15D6

VRP5V0A SKIP_3V_5V

IN

VBATP

IN

P5VAUXON

IN

D7000

C

BAT54C_30V_0.2A_DY

A2A1

21

R7000

21

RSC_0402_DY

R7001

21

10K_5%_2

R7002

21

0_5%_3

R7003

0_5%_2

VRP5V0A_VIN

21

EN_3V_5V

EN_3V

OUT

OUT

OUT

OUT

OUT

6D6

6C114C814D4

IN

6C8

IN

6B4

IN

6D6

6B5

6B5

6B4

VCCIO VCCSA

45D3
14D2

SLP_S3#_3R

14A6

IN

14B4
21D6
49B3

B

9C614A8

14B6

9B1

IN

VCCP_PG VCCP_PG

IN

VRP1V05S

8

R7021

47K_5%_2

P3V3S

21

R7022

PAD6300

12

POWERPAD_2_0610

PAD6301

12

POWERPAD_2_0610

21

C7020

21

10K_5%_2

EN_VCCP

0.1UF_16V_2

OUT

9D6

OUT

P1V05S

21

21

76

VRP5V0A_LDO

9C614A8

10A514A621B6

14B414B814D2
21D645D349B3

VRP5V0A

VRP3V3A

10C1

PAD6150

12

POWERPAD_2_0610

PAD6100

12

POWERPAD_2_0610

12

PAD6120

POWERPAD1X1M

VCCP_PG

SA_PG SA_PG

IN

SLP_S3#_3R

IN

DIODE-BAT54-TAP-PHP

VRPVCCSA

IN

P5V0A

21

P3V3AL

21

P5V0AL

21

R7040

21

0_5%_2

D7040

PAD6500

POWERPAD_2_0610

6C114C814D6

IN

0.1UF_16V_2

6B3

VRP5V0A_LG

IN

0.1UF_16V_2

DGPU

14A614B814D2
21D645D349B3

EN_SA

C7040

CSC0402_DY

21

P3V3S

R7041

10K_5%_2

21

2

NC

13

21

12

54

PVSA

10B4

OUTIN

16A716B316B7
16D7

OUT

13C552D6

13A4

VRP5V0A

21

213

C7001

C7002

21

D7002

DIODES_BAV99

IN OUT

IN

D7001

DIODES_BAV99

21

3

C7004

1UF_25V_3

21

SLP_S3#_3R

DGPU_PWR_EN_5R

C7003

0.1UF_16V_2

21

P15V0A

R7016

0_5%_2_DY

R7018

10K_5%_2

21

EN_DGPU

21

21

P3V3S

R7017

10K_5%_2

DGPU_PG

IN OUT

DGPU_VID6

IN

R7019

2.2K_5%_2

21 21

CHANGE by

DDR_P1V5

45D3
14B8

14B4
21D6
49B3

21D3
49B3

13C7

C7010

0.1UF_16V_2

R7010

IN

SLP_S5#_3R

IN

47K_5%_2

R7012

0_5%_2

21

21

P3V3S

21

R7013

VRP1V5

RSC_0402_DY

POWERPAD_2_0610

POWERPAD_2_0610

PAD6200

PAD6201

1V5_PG

7B314C2

IN

7C1

IN

C7005

0.1UF_16V_2

21

C7006

CSC0402_DY

21

12

12

21

21

EN_0V75SLP_S3#_3R

EN_1V5

1V5_PG

P1V5

OUT

OUT

OUT

7C714A6

7C7

D

CC

P1V8S

P3V3S

R7050

21

10K_5%_2

EN_1V8

C7050

0.01UF_50V_2

21

OUT

8B6

B

P1V8S

PAD6900

VRP1V8S

8C2

IN

POWERPAD_2_0610

12

21

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6614

87

65

4

32 1

R7105

100K_5%_2

C7100

2200PF_50V_2

P3V3AL

P3V3A

Q7102

1

D

NMOS_4D1S

AO6402AL

S

G

2
5

4

POWERPAD_2_0610

36

PAD7100

12

21

R7106

200_5%_2

21

D

3

Q7103

DS

1

G

SSM3K7002FU

2

CC

B

P3V3AL

SSM3K7002FU

SSM3K7002FU

R7104

100K_5%_2_DY

2121

R7100

10K_5%_2

R7109

212
3212

Q7106

DS

1

G

R7111

3

Q7108

DS

1

G

Q7101

1

200_5%_2

G

3

DS

SSM3K7002FU

2

PVBAT P3V3_LDO

R7491

510K_1%_2

D

THRM_SHUTDWN#

40A8 40B1

OUT

DIODE-BAT54-TAP-PHP

D7490

2

NC

120K_1%_2

21

13

R7492

21

P15V0A

R7107

212

470K_5%_2

3

Q7104

49B1
15A4
15B4

SLP_S3_3R

IN

DS

1

G

SSM3K7002FU

B

4

U7490

VDD

53

SENSE RESET#

GND

1

C7101

21

2200PF_50V_2

GND

TI_TPS3801_01_SC70_5P

2

P5VAUXON

OUT

21C3

14D8

21F6
14C8
14D8

0_5%_2

0_5%_2

P3V3AL

R7108

P5V0A

R7110

PAD7101

Q7105

1

D

2
5

NMOS_4D1S

AO6402AL

21

Q7107

1

D

2
5

NMOS_4D1S

AO6402AL

21

4

S

36

G

C7102

21

POWERPAD_2_0610

4

S

36

G

C7104

21

POWERPAD_2_0610

21

680PF_50V_2

PAD7102

21

CSC0402_DY

12

12

C7105

P3V3S

C7103

21

22UF_6.3V_5

15B8
15A4
15B4
49B1

P5V0S

21

22UF_6.3V_5

15B8
15A4
15B4
49B1

EC_PW_ON#

IN

SLP_S3_3R

IN

SLP_S3_3R

IN

P15V0A

21

21

12

P1V5S

21

C7107

21

22UF_6.3V_5

R7113

3

P0V75S

200_5%_2 200_5%_2

212

Q7110

15B4

SLP_S3_3R

49B1

IN

15B8

SSM3K7002FU

1

DS

G

SSM3K7002FU

Q7111

1

CHANGE by

R7114

3

21

DS

G

2

200_5%_2

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

DATE

21-OCT-2002XXX

23

of

6615

1

AA

REV

X011310xxxxx-0-0

R7112

P1V5

Q7109

8

D

AON7410

Q7112

D

AON7410

NMOS_4D3S

NMOS_4D3S

S

G

S

G

7
6

8
7
6

21

POWERPAD_2_0610

1
2
3
45

1
2
3
45

PAD7103

0_5%_2

C7106

21

CSC0402_DY

8

76

54

87

65

4

32 1

1
2
3
45

1
2
3
45

21

1

G

1

S

2
3
45

G

21

1

4

S

36

G

21

1

P1V5S_DGPU

R7115

200_5%_2

21

3

Q7115

DS

SSM3K7002FU

2

P1V05S_DGPU

R7118R7117

200_5%_2

32 1

Q7117

DS

G

SSM3K7002FU

2

P3V3S_DGPU

200_5%_2

212

3

Q7119

DS

G

SSM3K7002FU

NVIDIA OPTIMUS

DURING RESET AFTER RESET

100K_5%_2

1

R7121

G

HIGH

LOW

P15V0A

212
3

Q7120

DS

SSM3K7002FU

DGPU_PWR_EN#

DGPU_PG

DGPU_HOLD_RST#

16C7 52C7 52D6

16A7

16B7

54

IN

DGPU_PWR_EN#

DGPU_PWR_EN_5R

CHANGE by

HIGH

LOW

OUT

0 : DGPU POWER SWITCH TURNED ON
1 : POWER SWITCH TURNED OFF

0 : DGPU POWER IS NOT STABLE
1 : DGPU POWER IS STABLE

0 : KEEP DGPU IN RESET
1 : RESET IS RELEASED

16D716B716A714B4

DATE

21-OCT-2002XXX

23

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

D

CC

B

AA

REV

of

X011310xxxxx-0-0

6616

1

P1V5

Q7113

8

D

NMOS_4D3S

AON7410

Q7114

D

NMOS_4D3S

AON7410

R7116

680PF_50V_2

S

G

S

G

21

C7108

7
6

D

IN

DGPU_PWR_EN_5R

14B4

16A716B316B7

8
7
6

220K_5%_2

52C7 52D6

16A716B516B7

IN

DGPU_PWR_EN#

P1V05S

Q7116

8

D

7
6

NMOS_4D3S

AON7410

IN

DGPU_PWR_EN_5R

14B416A716B316D7

21

220K_5%_2

C7109

B

52C7 52D6

16A716B516C7

IN

680PF_50V_2

DGPU_PWR_EN#

P3V3S

Q7118

1

D

2
5

NMOS_4D1S

AO6402AL

IN

DGPU_PWR_EN_5R

14B416B316B716D7

R7120 R7119

21

220K_5%_2

C7110

680PF_50V_2

52C7 52D6

16B516B716C7

8

76

IN

DGPU_PWR_EN#

87

REFERENCE 0~49(PCB SCREW)

65

4

32 1

D

1

1

FIX_MASK

1

FIX_MASK

FIX_MASK

FIX1

FIX2

FIX3

1

FIX_MASKFIX_MASK

1

FIX_MASK

1

FIX_MASK

11

FIX_MASK

FIX5

FIX6

FIX7

FIX8FIX4

D

CC

S1

1

SCREW300_900_1P

S2

1

SCREW300_900_1P

S3

1

SCREW300_900_1P

S5

1

B

SCREW300_900_1P

S6

1

SCREW300_900_1P

S7

1

SCREW300_900_1P

S8

1

SCREW300_900_1P

S9

1

SCREW300_900_1P

S18

1

SCREW300_700_600_1P

S20

1

SCREW300_600_700_1P

S22

1

SCREW500_700_800_NP_1P

CPUPCB

S10

1

S11

1

S12

1

S13

1

SCREW330_600_1P

SCREW330_600_1P

SCREW330_600_1P

SCREW330_600_1P

1

1

GPU

S14

S15

SCREW330_600_1P

SCREW330_600_1P

WLAN

S16

1

3G

S17

1

MSATA

S19

1

FAN

S21

1

SCREW120_0_600_1P

SCREW120_0_600_1P

B

SCREW120_0_600_1P

SCREW120_0_600_1P

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6617

87

REFERENCE 50-99(HALL SENSOR)

65

4

32 1

D

P3V3AL

R50

1

2

100K_5%_2

21

C50

1000PF_50V_2

21

LID_SW#_3

VARISTOR_DY

21

21E6

OUT

D50

U50

VDD

3

GND

MAG_MH248BESO_SOT23_3P

OUT

B

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6618

87

REFERENCE 100~199(LED)

65

4

32 1

D

SUSPEND LED

21B6

PWR_OLED#

IN

TP100

1

TP30

D154

HT_191UY

2121

R160

150_5%_2

P3V3A

BATTERY LED

D

CHARGE:BRIGHT

POWER ON LED

21D6

PWR_WLED#

IN

TP101

1

TP30

D159

19_217_T1D_CP1Q2QY_3T

2121

R150

220_5%_2

P5V0S

WIFI/WIMAX/3G/LTE LED

1

21B6

WL_OLED#

IN

TP30

TP104

D156

HT_191UY

2121

CC

P3V3S

R155

150_5%_2

DC IN / BATTERY CHARGE LED

B

D152 BRIGHT:BOTH AC-ADAPTER IS PLUGGED IN AND BATTERY IS FULL CHARGED
D155 BRIGHT:WHILE CHARGING BATTERY FROM AC-ADAPTER

BLINK:LOW BATTERY

P5V0A

21B660C3

DCIN_WLED#

IN

TP102

1

TP30

D152

19_217_T1D_CP1Q2QY_3T

2121

R152

220_5%_2

P3V3AL

B

21D6

BAT_OLED#

IN

TP103

1

TP30

D155

HT_191UY

2121

R154

150_5%_2

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6619

87

65

4

32 1

REFERENCE 200~249(POWER CONN)
REFERENCE 250~299(KB/TP CONN)

D

R253

21

0_5%_2_DY

P3V3S

OUT

SCAN_IN<7..0>

21

200_5%_2

21

200_5%_2

21

200_5%_2

SCAN_OUT<17..0>

7
2

3
4
0
5

6
1

16

17

4
2

13
15
1
0

11
9
5
6

10
14
8
12

7
3

SCAN_OUT<16>

SCAN_OUT<17>

SCAN_OUT<4>
SCAN_OUT<2>

SCAN_OUT<13>
SCAN_OUT<15>
SCAN_OUT<1>
SCAN_OUT<0>

SCAN_OUT<11>
SCAN_OUT<9>
SCAN_OUT<5>
SCAN_OUT<6>

SCAN_OUT<10>
SCAN_OUT<14>
SCAN_OUT<8>
SCAN_OUT<12>

SCAN_OUT<7>
SCAN_OUT<3>
SCAN_IN<7>
SCAN_IN<2>

SCAN_IN<3>
SCAN_IN<4>
SCAN_IN<0>
SCAN_IN<5>

SCAN_IN<6>
SCAN_IN<1>

21B3

20D321B3

IN

IN
IN

IN

CAPS_LED#_3

SCROLL_LED#_3
NUM_LED#_3

21B6

21D6
21D6

R250

R251
R252

CN250

34

34

33

33

32

32

31

31

30

30

29

29

28

28

27

27

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

G2

G2

G1

G1

IN

SCAN_IN<7..0>

SCAN_IN<0>

0

SCAN_IN<1>

1

SCAN_IN<2>

2

SCAN_IN<3>

3

SCAN_IN<4>

4

SCAN_IN<5>

5

SCAN_IN<6>

6

SCAN_IN<7>

7

VARISTOR_DY

D250
D251
D252
D253
D254
D255
D256
D257

21

VARISTOR_DY

21

VARISTOR_DY

21

VARISTOR_DY

21

VARISTOR_DY

21

VARISTOR_DY

21

VARISTOR_DY

21

VARISTOR_DY

21

20C621B3

D

CC

PTWO_AFF340_A2G1V_P _34P

21

VARISTOR_DY

21

VARISTOR_DY

21

D260D259D258

VARISTOR_DY

KEYBOARD CONN

B

21D3

21D2
21D3

21D2

IM_CLK_5

BI

IM_DAT_5

BI

PHP_PESD5V2S2UT_SOT23_3P_DY

P5V0S

CN280

1

1

2

2

3
4

2

1

D280

3

G1

G

3

G2

G

4

ACES_50503_0044N_001_4P

21D3

VARISTOR_DY

PWR_SWIN#_3

OUT

21

D200

TOUCHPAD CONN

P3V3AL

CN200

1

1

2

2

G1

3
4G2

G1
G2

3
4

ACES_50224_0040N_001_4P

POWER CONN

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6620

8

REFERENCE 300~389(KBC)

7654321

C304

21

0.1UF_16V_2

IN
IN

0.1UF_16V_2

P3V3AL

21D6
21C6

P3V3S

C312

21

10UF_6.3V_5_DY

47A6
47A6

CLOSE PIN4

C306

21

0.1UF_16V_2

C309

21

0.1UF_16V_2

P3V3AL

R346

21

100K_5%_2

21C847A6
21C747A6

21C747A6
21C847A6

P3V3AL

R320

2

D300

100K_5%_2

NC

21

13

VCC_POR#P5VAUXON

21B614C814D815D6

OUTIN

FF

DIODE-BAT54-TAP-PHP

P3V3AL_EC

P3V3AL_ECP3V3S

R332 R323

4.7K_5%_2

10K_5%_2

21

21

P3V3AL_EC_VREF

TP308

USB30_PWR_EN
EC_ILIM_SEL
AOAC_ON#
PWR_WLED#

BAT_OLED#

EC_SPI_CLK_R

EC_SPI_SI_R
EC_SPI_SO_R

TP307

TP30

TP24

104

97
98

99
100
108

96

95

94

101
105
106
107

79
114

6

109

1

80

26
123

73

74

1

75

117
112
110

93

91

90

92

86

87

44

C310

1UF_6.3V_2

21

5B7
5D5
5D3
49A5
34B5

50D7

5B8

18C4

32A8
32A8

14A6

30A3

49C7
20B7
27B7
20B7

49A5

49B8
49A8
47B7
32A6
24A2
22D7

31D3 31A5

HW_I_ADC

IN

HW_V_ADC

IN

BATT_IN

IN

SUS_PWR_ACK

OUT

EC_BKLTEN

OUT

LCM_BKLTEN

IN

ACPRES

IN

LID_SW#_3

IN

EC_CTL1

OUT

EC_CTL2

OUT

SLP_S3#_3R

IN

USB_OC#_3

OUT

SUSACK#

OUT

SCROLL_LED#_3

OUT

BTIFON#

OUT

NUM_LED#_3

OUT

ACPRESENT

IN

EC_PWRSW#

IN

LOW_BAT#_3

OUT

FLASH_OVERRIDE

OUT

USB_OC#_1

OUT

EC_MUTE#

OUT

WOL_AUX_ON#

OUT

OUT

32A8

OUT

27C2

OUT

19C7

OUT

19A7

OUT

33_5%_2

21

R342

33_5%_2

21

R341

21

R340

33_5%_2

21E8
21E8
21E8

49B7

14B414B814D245D349B3

27C7

49A6

47B8

EC_SPI_CS0#

OUT

EC_SPI_CLK

OUT

EC_SPI_SI

OUT

EC_SPI_SO

IN

P3V3AL_R

P3V3S

4

11588764619

U301

VREF

GPIO90/AD0
GPIO91/AD1
GPIO92/AD2
GPIO93/AD3
GPIO05/AD4
GPIO04/AD5
GPIO03/AD6
GPIO07/AD7

GPIO94/DA0
GPIO95/DA1
GPIO96/DA2
GPIO97/DA3

GPIO02
GPIO16
GPIO24 GPIO27/PSDAT2
GPIO30/F_WP#
GPIO34/CIRRXL
GPIO36
GPIO41/F_WP#
GPIO51/N2TCK

GPIO70
GPIO71
GPIO72

GPIO20/TA2/IOX_DIN_DIO
GP(I)O84/IOX_SCLK/XORTR#
GPO82/IOX_LDSH/TEST#
GPIO06/IOX_DOUT

GPIO81/F_WP#
F_CS0#
F_SCK

F_SDI_F_SDIO1
F_SDIO_F_SDIO0

VCORF

GND1

18

VCC5

VCC4

VCC3

VCC2

VCC1

GND6

GND5

GND4

GND3

GND2

5

897845

116

21

POWERPAD1X1M

102

AVCC

GPIO46/SDA4B/CIRRXM/TRST#

PAD319

12

VDD

LRESET#/GPIOF7

LCLK/GPIOF5

LFRAME#/GPIOF6

SERIRQ/GPIOF0

GPIO11/CLKRUN#

ECSCI#/GPIO54
GPIO10/LPCPD#

KBRST#/GPIO86

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1

GPIO17/SCL1/N2TCKGPIO67/N2TMS
GPIO22/SDA1/N2TMS

GPIO23/SCL3A
GPIO31/SDA3A
GPIO47/SCL4A

GPIO53/SDA4A
GPIO42/SCL3B/TCK
GPIO43/SDA3B/TMS
GPIO44/SCL4B/TDI

GPIO75/SPI_SCK

GPIO77/SPI_DI
GPIO76/SPI_DO

AGND

WINB_NPCE885LA0DX_LQFP_128P

103

LAD3/GPIOF4
LAD2/GPIOF3
LAD1/GPIOF2
LAD0/GPIOF1

GPIO65/SMI#

GPIO85/GA20

GPIO73/SCL2
GPIO74/SDA2

7
2
3
1
128
127
126
125
8
9
29
124
121
122

27
25
11
10
7114
7215

70
69
67
68
119
120
24
28

R349
17
20
21
23

82
84
83

BUF_PLT_RST#

CLK_KBPCI

LPC_3S_FRAME#

LPC_3S_AD<3>
LPC_3S_AD<2>
LPC_3S_AD<1>
LPC_3S_AD<0>
PCI_3S_SERIRQ

PCI_3S_CLKRUN#

EC_SMI
RUNSCI0#_3
SB_USB_3
EC_3S_A20GATE
KBRST#

21

10K_5%_2

TP30

EN_PVCORE
SLP_SUS#
IM_DAT_5
IM_CLK_5

EC_SMB1_CLK
EC_SMB1_DATA
EC_SMB2_CLK
EC_SMB2_DATA
EC_SMB3_CLK
EC_SMB3_DATA
3G_ON#

TP30

TP302

TP30

TP303

TP30

TP304

TP30

TP305

EC_PW_ON#
SB_USB_1
WLON#

R300

TP306

21

10K_5%_2_DY

IN

BI
BI
BI
BI
BI
BI
BI

OUT
OUT

OUT

P3V3AL

PWR_SWIN#_3

RSMRST#

1

BI
BI

BI
BI
BI
BI
BI
BI

OUT

EC_CTL3

1

SLP_S5#_3R

1

H_PROCHOT_EC

1

SB_USB_2

1

OUT
OUT
OUT

R336

10K_5%_2_DY

21

28C3

27C3 27C7 51A8

51A7
27C3 47C3
27C3 47C3
27C3 47C3
27C3 47C3
27C3 47C3
27B7 47C2

49B349A5

52D6

51C7
30B6

20A4

OUT

21D1

OUT

11A8

OUT

49A3

IN

20A8 21D2

20A8

21D2

5D3

21D2
21D2

5D3

48C2
37C6
21D2
21D2

37C3 48C2

28C2

32A8

OUT

IN
OUT
OUT

14D8

15D4
32A8
27B2

P3V3A

R343

21

14D2
21B1
32C3

56F5

49B3

10K_5%_2

49C249B7

P3V3S

R326

R312

21

21

10K_5%_2

10K_5%_2

E

47B6

OUT

52C2

OUT

52C2

OUT

21D3

BI

21D3

20A8

BI

21D3

5D3

BI

5D321D3

BI

21D3

5A7

60E2
60D2

21D3

21D3 37C6 48C2
37C3 21D3

5A7

48C2

R315

21

BI
BI

BI
BI

10K_5%_2_DY

IM_CLK_5

EC_SMB1_CLK
EC_SMB1_DATA
EC_SMB2_CLK
EC_SMB2_DATA

EC_SMB3_CLK
EC_SMB3_DATA

INV_PWM_3
RSMRST#

R333

10K_5%_2

21

R308
R311

IM_DAT_5

20A8

21
21

P5V0S

47K_5%_2
47K_5%_2

21

R322

21

R321

21

R317

21

R316

21

R334

21

R335

OUT
OUT

P3V3AL

3.3K_5%_2

3.3K_5%_2

1.8K_5%_2

1.8K_5%_2

P3V3S

1.8K_5%_2

1.8K_5%_2

21B6

50D734B5

21D3

49C249B7

D

C

P3V3AL_RP3V3AL

R318

21

2.2_5%_3

FOR ESD PROTECT

C313

21

4.7UF_6.3V_3

C300

21

0.1UF_16V_2

P3V3AL

L300

21

FBM_11_160808_121T

E

C314

21

10UF_6.3V_5_DY

C302

C301

21

0.1UF_16V_2

P3V3AL_EC

C305

21

0.1UF_16V_2

C303

21

21

0.1UF_16V_2

AGND_KBC

HW_I_ADC

5B721E6

IN

HW_V_ADC

5D521E6

IN

BATT_IN

5D321E6

OUT

C317

C316

C315

21

21

21

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

D

1.BATTERY

P3V3AL

21D647A6

IN

21C647A6

OUT

R313

EC_SPI_CS0#
EC_SPI_SO

21

10K_5%_2

EC_SMB2EC_SMB1

1.CHARGE

2.GPU THERMAL

1
2
3
4

C

U300

CS#
SO_SIO1

HOLD#

WP#_ACC

SCLK

SI_SIO0

GND

MXIC_MX25L3206EM2I_12G_SOP_8P

VCC

EC_SMB3

1.CEC

8

R314

3.3K_5%_2

7

21

6

EC_SPI_CLK

5

EC_SPI_SI

AGND_KBC

CPU_PROCHOT#

11B741D6

U301

TP24

1

31

TP309

FAN_TACH1

C311

680PF_50V_2

21

21B6

40C8

IN

36A3 37B1
60C3

B

FAN_TACH1

21B640C8

IN

SA_PG

10A514A6

IN

INV_PWM_3

21D134B550D7

OUT

PCH_PWROK

49A649B7

OUT

HDMI_HPD_EC

IN

DCIN_WLED#

19A7

OUT

WL_OLED#

19B4

OUT

FAN1_PWM

40C6

OUT

CAPS_LED#_3

20C7

OUT

PWR_OLED#

19D7

OUT

TP300

USB_OC#_2

32C1

OUT

EC_32KHZ

49B3

IN

LAN_RST#

22B5

OUT

VCC_POR#

21F4

IN

41D552C2

BI

H_PECI

43_5%_2

R339

0_5%_2_DY

TP24

P1V05S

R338

EC_PECI

21

63
64

21

32

118

62
65
22
81
66
16

1

111
113

77
30

85

13
12

GPIO56/TA1
GPIO14/TB1
GPIO01/TB2

GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
GPIO32/D_PWM
GPIO45/E_PWM
GPIO66/G_PWM
GPIO33/H_PWM
GPIO40/F_PWM

GP(I)O83/SOUT_CR/TRIST#
GPIO87/CIRRXM/SIN_CR

GPIO00/EXTCLK

GPIO55/CLKOUT/IOX_DIN_DIO

VCC_POR#

PECI
VTT

WINB_NPCE885LA0DX_LQFP_128P

KBSOUT0/GPOB0/JENK#

KBSOUT1/GPIOB1/TCK
KBSOUT2/GPIOB2/TMS
KBSOUT3/GPIOB3/TDI

KBSOUT4/GPOB4/JEN0#

KBSOUT5/GPIOB5/TDO

KBSOUT6/GPIOB6/RDY#

KBSOUT9/GPOC1/SDP_VIS#
KBSOUT10_P80_CLK/GPIOC2
KBSOUT11_P80_DAT/GPIOC3

KBSOUT15/GPIO61/XOR_OUT

KBSIN0/GPIOA0/N2TCK
KBSIN1/GPIOA1/N2TMS

KBSOUT7/GPIOB7
KBSOUT8/GPIOC0

KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62

GPIO60/KBSOUT16
GPIO57/KBSOUT17

KBSIN2/GPIOA2
KBSIN3/GPIOA3
KBSIN4/GPIOA4
KBSIN5/GPIOA5
KBSIN6/GPIOA6
KBSIN7/GPIOA7

53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33

54
55
56
57
58
59
60
61

SCAN_OUT<0>
SCAN_OUT<1>
SCAN_OUT<2>
SCAN_OUT<3>
SCAN_OUT<4>
SCAN_OUT<5>
SCAN_OUT<6>
SCAN_OUT<7>
SCAN_OUT<8>
SCAN_OUT<9>
SCAN_OUT<10>
SCAN_OUT<11>
SCAN_OUT<12>
SCAN_OUT<13>
SCAN_OUT<14>
SCAN_OUT<15>
SCAN_OUT<16>
SCAN_OUT<17>

SCAN_IN<0>
SCAN_IN<1>
SCAN_IN<2>
SCAN_IN<3>
SCAN_IN<4>
SCAN_IN<5>
SCAN_IN<6>
SCAN_IN<7>

SCAN_OUT<17..0>

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17

SCAN_IN<7..0>

0

1

2

3

4

5

6

7

20D6

OUT

20C6 20D3

IN

A

CHANGE by

OUT

8

76543

XXX 21-OCT-2002

3

Q300

DS

H_PROCHOT_EC

1

G

SSM3K7002FU

2

DATE

21

R324

100K_5%_2

21

21D3

IN

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CODE

SIZE

CCS

1310xxxxx-0-0

SHEET

DOC.NUMBER

21 66

B

A

REV

X01

of

87

REFERENCE 400~499(LAN)

65

4

32 1

D

21D6

IN

PVLX_LAN

LQM21PN2R2MC0D_DY

B

FOR SW MODE

WOL_AUX_ON#

PDVDDL_LAN

C406

P3V3A

Q400

2

SD

C400

21

CSC0402_DY

R400

100K_5%_2

C407

21

21

10UF_6.3V_5_DY

3

G

C401

1

AM2321P

21

C408

21

0.1UF_16V_2_DY

X400

21

0.047UF_16V_2

R406L400

RSC_0603_DY

1000PF_50V_2_DY

21

POWERPAD_2_0610

2121

PAD400

12

PAVDDL_LAN

P3V3A_LAN

21

C402

21

21B6

C412

C413

21

1UF_6.3V_2

C403

C404

21

1UF_6.3V_2

4.7UF_6.3V_3

48D8
48D7
48C7

OUT

P3V3S

21

R401

30K_5%_2

22A5

PAVDDH_LAN

21

0.1UF_16V_2

LAN_X1

LAN_X2

C405

21

21

0.1UF_16V_2
10UF_6.3V_5_DY

CLKREQ_LAN#

49B3
49A5
27C7
31C6

22A5

C414

C415

21

21

1UF_6.3V_2

23B7
23C7

23B7
23C7

22B5

OUT

22B5

OUT

PDVDDL_LAN

IN

OUT

IN
IN

23B7
23C7

0.1UF_16V_2

23B7
23C7

23B7
23B7
23B7
23A7

C427

C426

21

21

1UF_6.3V_2

P3V3A_LAN

LAN_RST#
PCIE_WAKE#

LAN_X1
LAN_X2

R405

2.37K_1%_2

BI
BI
BI
BI
BI
BI
BI
BI

PVLX_LAN

FOR LDO MODE

0.1UF_16V_2

R403

21

10K_5%_2

R404

21

10K_5%_2

402339

38541

LX

GND

LED_1

TRXP0

TRXN0

12

C416

37

RX_N

LED_0

DVDDL_REG

TRXP1

TRXN1

AVDDL

141115

13916

21

U400

1

VDD33

2

PERSTN

3

WAKEN

4

CLKREQN
ISOLATN

6

AVDDL_REG

7

XTLO

8

XTLI
AVDDH_REG

10

21

RBIAS

LAN_TRD0_DP
LAN_TRD0_DN
LAN_TRD1_DP
LAN_TRD1_DN
LAN_TRD2_DP
LAN_TRD2_DN
LAN_TRD3_DP
LAN_TRD3_DN

PAVDDL_LAN

0.1UF_16V_2 0.1UF_16V_2

C424

34

31

353633

32

RX_P

AVDDL

AVDDLTRXP3

TX_P

REFCLK_P

REFCLK_N

TX_N

NC

TESTMODE

SMDATA

SMCLK

PPS
LED_2
AVDDH
TRXN3

AVDD33

AVDDL

TRXN2

TRXP2

ATHEROS_AR8161_AL3A_R_QFN_40P

201918

17

C417

21

PAVDDVCO_LAN

C425

2121

21

1UF_10V_2_DY

PAVDDL_LAN

0.1UF_16V_2

PCIE_LAN_TX_DN
PCIE_LAN_TX_DP
CLK_PCIE_LAN_DP
CLK_PCIE_LAN_DN

30

PCIE_LAN_RX_C_DP

29

PCIE_LAN_RX_C_DN

28
27
26
25
24

22
21

C418

0.1UF_16V_2

C423

PAVDDH_LAN

21

21

R402

0_5%_3

21

48D8

IN

48D8

IN

48C7

IN

48C7

IN

C421
C422

C420

0.1UF_16V_2

21

P3V3A_LAN

C419

0.1UF_16V_21UF_10V_2_DY

21

0.1UF_16V_2

21

0.1UF_16V_2

PCIE_LAN_RX_DP
PCIE_LAN_RX_DN

OUT
OUT

D

CC

48D8
48D8

B

25MHZ

C409

21

33PF_50V_2

C410

21

33PF_50V_2

C417:8161 STUFF 8162 OPEN

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6622

87

REFERENCE 400~499(LAN)

65

4

32 1

23C3 23B2
23C3 23B2
23C3 23B2
23C2 23B2
23C2 23B2

D

23C3 23B2
23C2 23B2
23C2 23A2

LAN_TD_DP

IN

LAN_TD_DN

IN

LAN_RD_DP

IN

LAN_C_DP

IN

LAN_C_DN

IN

LAN_RD_DN

IN

LAN_D_DP

IN

LAN_D_DN

IN

JACK470

1

TX+

2

TX-

3

RX+

4

P4

5

P5

6

RX-

7

P7

8

P8

G1

G

G2

G

D

SANTA_130451_6_8P

U471

215

TCT TCT

TX-

TD-

TX+

TD+
RCT

RCT
RX-

RD-

RX+

RD+
NC
NC

1

2

3

4

5

6

7

8

9

10

11

12

14
16
10
9
11
12

NC

13

NC

U470

TD+

TD1-

TDCT

TDCT

TD2+

TD2-

TD3+

TD3-

TDCT

TDCT

TD4+

TD4-

BOTH_NA0069RLF_SMD_24P

LAN_TD_DN
LAN_TD_DP

LAN_RD_DN
LAN_RD_DP

R475

R474

75_5%_3

75_5%_3

21

21

24

TX+

23

TX1-

22

TXTC

21

TXTC

20

TX2+

19

TX2-

18

TX3+

17

TX3-

16

TXTC

15

TXTC

14

TX4+

13

TX4-

OUT
OUT

OUT
OUT

23D523B222B523B7
23D523B2

23D523B2
23D523B2

21

RSC_0603_DY

21

RSC_0603_DY

CC

R476

21

RSC_0402_DY

R477

21

RSC_0402_DY

LAN_TD_DP

LAN_TD_DN

LAN_RD_DP

LAN_RD_DN

LAN_C_DP

LAN_C_DN

LAN_D_DP

LAN_D_DN

LAN_C_DN

R478

LAN_C_DP

LAN_D_DN

R479

LAN_D_DP

23C3 23D5

OUT

23C3 23D5

OUT

23C3 23D5

OUT

23C3

OUT
OUT
OUT

OUT
OUT

23D5

23C2 23D5

23C2 23D5

23D523C2

23C2 23D5

OUT
OUT

OUT
OUT

23B2 23D5

23D523B2

23A2 23D5

23B2 23D5

B

LAN_TRD0_DN

IN

23B7 22B5

23B7

22B5
22B5

23B7

22B5

23C7

22B5

23C7

23C7

B

22B5

22B523C7

22B5

22B5

22B5

22B5

LAN_TRD0_DP

IN

LAN_TRD0_DN

IN

LAN_TRD1_DP

IN

LAN_TRD1_DN

IN

LAN_TRD2_DP

IN

LAN_TRD2_DN

IN

LAN_TRD3_DP

IN

LAN_TRD3_DN

IN

LAN_TRD0_DP

IN

LAN_TRD1_DN

IN

LAN_TRD1_DP

IN

C479

C478

21

21

0.1UF_16V_2

0.1UF_16V_2

3
1
7
8
6
4
5

BOTH_TS21C_HF_SOP_16P

R470

75_5%_3

21

C470

21

CSC0402_DY

0.1UF_16V_2

C481

21

C480

21

8

76

C471

21

CSC0402_DY

C482

21

0.1UF_16V_2

C472

21

CSC0402_DY

0.1UF_16V_2

C483

C473

21

21

CSC0402_DY

C474

21

0.1UF_16V_2

1UF_6.3V_2

54

21

75_5%_3

75_5%_3

21

21

21

C476

21

100PF_50V_2

75_5%_3

C475

1000PF_2000V_6

C477

21

CSC0402_DY

CHANGE by

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6623

R473

R472

R471

87

65

4

32 1

REFERENCE 500~549(AUDIO CODEC)

D

B

P5V0S

BLM18PG121SN1(6014B0041601_0603)

C532

C506

21

10UF_6.3V_3_DY

21

1000PF_50V_2

21

1000PF_50V_2

21

1000PF_50V_2

21

1000PF_50V_2

R516

0_5%_3

21

0.1UF_16V_2_DY

C514

C515

C516

C517

AGND_AUDIO

21

P5V0S_PVDD

C505

21

4.7UF_6.3V_3

OUT

25B8

OUT

25B8

OUT

25B8

OUT

C529

C531

21

21

0.1UF_16V_2

4.7UF_6.3V_3

TIED UNDER OR NEAR CODEC

PAD500

12

POWERPAD1X1M

C503

AGND_AUDIO

2.2UF_6.3V_3

21

P5V0S_AUDIO_AVDD

C502

2.2UF_6.3V_3

21

CBP

DVDD1

CBN

GPIO0/DMIC-DATA

2

343635

CPVEE

GPIO1/DMIC-CLK

3

C500

C536

C507

21

0.1UF_16V_2

AGND_AUDIO

SPK_OUT_L_P

SPK_OUT_L_N

RESERVE FOR EMI (THERMAL PAD 4X4 VIAS)

SPK_OUT_R_N

SPK_OUT_R_P

R512
R511

R510

R509

21

21

4.7UF_6.3V_3

21

21

21

21

0.1UF_16V_2

0_5%_3

0_5%_3

0_5%_3

0_5%_3

U500

37

AVSS2

AVDD2

39

PVDD1

40

SPK-L+

41

SPK-L-

42

PVSS1

43

PVSS2

44

SPK-R-

45

SPK-R+

46

PVDD2

47

EAPD

48

SPDIFO

P3V3S

C508

C509

21

21

1UF_6.3V_2

0.1UF_16V_2

34B3

21

34B3

MIC_IN_DATA

BI

MIC_IN_CLK

BI

100_5%_2

R505

MIC_IN_CLK_R

21

33

HP-OUT-R

PD#

4

10UF_6.3V_5

31

32

HP-OUT-L

MIC1-VREFO-L

DIGITAL

BIT-CLK

SDATA-OUT

5

6

C512

29

30

MIC2-VREFO

MIC1-VREFO-R

SDATA-IN

DVSS2

8

719

21

2710

28

VREF

LDO-CAP

ANALOG

SYNC

DVDD-IO

HDA_R_SDIN0

HDA_R_BITCLK

CLOSE TO PIN27

2.2UF_6.3V_3

21

AGND_AUDIO

263825

AVSS1

AVDD1

LINE1-R

LINE1-L

MIC1-R

MIC1-L

MONO-OUT

JDREF

Sense-B

MIC2-R

MIC2-L

LINE2-R

LINE2-L

Sense A

GND

PCBEEP

RESET#

REA_ALC269Q_VB6_CGT_QFN_48P

11

12

P3V3A

C513C519

0.1UF_16V_2

21

HP_R

HP_L
MIC_REF_L
MIC_REF_R

24

23

22

21

20

19

18

17

16

15

14

13

49

C520

0.1UF_16V_2

R502

22_5%_2

R503

0_5%_2

21

21

OUT
OUT
OUT
OUT

MIC_R

MIC_L

R514

20K_1%_2

HDA_3S_RST#
HDA_3S_SYNC

HDA_3S_SDIN0

HDA_3S_BITCLK
HDA_3S_SDOUT
EC_MUTE#

25B3

25A3

25D3

25D3

21

AGND_AUDIO

CLOSE TO PIN13

R500

20K_1%_2

R501

39.2K_1%_2

R507

2121

47K_1%_2

BI
BI

21

21

IN
IN

IN

IN
IN
IN

P5V0S P5V0S_AUDIO_AVDD

BLM18PG121SN1(6014B0041601_0603)

P5V0S_AUDIO_AVDD

25C2

25C225B8

MICS

IN

HPS

IN

PCSPKR_PCH_3

C521

21

100PF_50V_2

R506

4.7K_1%_2

47C7

47C7

47B7

47C7

47B7

21D6

R515

21

0_5%_3

D

C504

C501

21

21

0.1UF_16V_2

4.7UF_6.3V_3

AGND_AUDIO

CC

25C5

25B2

47C8

IN

21

B

AA

AGND_AUDIO

C518

21

22PF_50V_2_DY

C510

C522

21

0.1UF_16V_2

21

1UF_6.3V_2

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6624

87

REFERCE 600~649(JACK/MIC/SPEAKER)

65

AUDIO JACKS

4

32 1

D

MICPHONE

JACK600

SINGA_2SJ2311_000111_6P

6

6

5

5

2

2

1

1

3

3

7

7

AGND_AUDIO

MICS

OUT

RESERVE FOR EMI

0_5%_3

0_5%_3

R606

24B2

R607

R602

21

21

21

1K_5%_2

21

1K_5%_2

R603

CSC0402_DY

21

2.2K_5%_2

21

MIC_REF_L

MIC_REF_R

21

R604R605

2.2K_5%_2

C601C600

CSC0402_DY

21

24D3

IN

24D3

IN

2.2UF_6.3V_3

C606

21

MIC_R

MIC_L

21

C607

2.2UF_6.3V_3

24C2

BI

24C2

BI

D

CC

RESERVE FOR EMI

AGND_AUDIO

D600

2

B

AGND_AUDIO

2121

21

PHP_PESD5V2S2UT_SOT23_3P_DY

0_5%_3

R608

0_5%_3

NOTE:SPK TRACE SHOULD 30~40 MILS WIDTH

IN
IN
IN
IN

SPK_OUT_L_P
SPK_OUT_L_N
SPK_OUT_R_N
SPK_OUT_R_P

24C7
24C7
24C7
24C7

C602

21

470PF_50V_2_DY

C603

21

470PF_50V_2_DY

C605

C604

21

470PF_50V_2_DY

21

470PF_50V_2_DY

INTERNAL SPEAKERS

CN600

1

1

2

2

3

G1

3

4

4G2

ACES_50224_0040N_001_4P

C608

C609

21

470PF_50V_2_DY

21

470PF_50V_2_DY

G1
G2

24D3

24D3

HP_R

IN

HP_L

IN

75_5%_2

R600

R601 R609

75_5%_2

RESERVE FOR EMI

RESERVE FOR EMI

3

1

HEADPHONE

JACK601

6

OUT

C611

HPS

C610

21

21

470PF_50V_2_DY

AGND_AUDIO

470PF_50V_2_DY

24B2

21

AGND_AUDIO

6

5

5

2

2

1

1

3

3

7

7

SINGA_2SJ2311_000111_6P

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6625

87

REFERNCE 900~999(CARDREADER)

65

4

32 1

D

SD_CMD

R901

21

SD_CLKSD_R_CLK

0_5%_2

RESERVE FOR EMI

SD_CD#

161514

SP9

SP8

SP7

DPDMCARD_3V3

3V3_IN

4

13

SP6

SP5

SP4

SP3

SP2SP14

SP1

XD_CD#V18

SDREG

REA_RTS5129_QFN_24P

6

C904

1UF_6.3V_2

21

P3V3S_CR

C902

0.1UF_16V_2

21

18

U900

SP10

SP11

SP12

SP13

XD_D7

TML

117325

C903

0.1UF_16V_2

21

GPIO0

RREF

19

SD_D3

26B3

26B3

BI

C901

1UF_6.3V_2

B

51B2

51B2

USB_CR_DN

BI

USB_CR_DP

BI

P3V3S

PAD900

POWERPAD_2_0610

SD_D2

21

R900

6.2K_1%_2

21

12

4.7UF_6.3V_3

20

21

23

25

21

CARD_REF

P3V3S_CARD

C900

21

26B3

BI

12

SD_D0

11

SD_D1

10

922

8

SD_WP

724

26B3

BI

26B3

BI

P3V3S_CR

C905 C906

26B3

BIBI

26B3

BI

26B3

BI

2.2UF_6.3V_3

0.1UF_16V_2

21

21

26C7
26D5

26C5

26C5
26C5
26C7
26C5
26B5

SD_D3

BI

SD_CMD

BI

SD_CLK

BI

SD_D0

BI

SD_D1

BI

SD_D2

BI

SD_CD#

BI

SD_WP

BI

CN900

P1

CD-DAT3

P2

CMD

P3

P3

P4

VDD

P5

CLK

P6

VSS

P7

DAT0

P8

DAT1

P10
P11

TAI_PSDAT0_11GLBS1N14H0_11P

G1DAT2
G2

CD

G3

WP

G4

G1P9
G2
G3
G4

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6626

87

REFERENCE 1300~1349(WLAN)

65

4

32 1

D

SUPPORT AOAC:STUFFSUPPORT AOAC:OPEN

C1305

R1304

0_5%_5

P3V3S

21

C1301

10UF_6.3V_3

21

LPC_3S_FRAME#

LPC_3S_AD<3>
LPC_3S_AD<2>
LPC_3S_AD<1>
LPC_3S_AD<0>

BUF_PLT_RST#

PCH_3A_ALERT_CLK
PCH_3A_ALERT_DAT

USB_WLAN_DN
USB_WLAN_DP

Q1300

1

D

2
5

PMOS_4D1S

AM3423P_DY

C1306

CSC0402_DY

21

21E3 47C3

IN

21E3 47C3

IN

21E3 47C3

IN

21E3 47C3

IN

21E3 47C3

IN

21E3 27C7

IN

28C3 51A8
56F5

48D2

BI

48D3

BI

51C2

BI

51B2

BI

P3V3A

4

S

36

G

C1307

CSC0402_DY

21

AOAC_ON#

3

Q1

DS

1

G

48D2
48D3

SSM3K7002FU

2

WLON#

21D6

IN

21C3

IN

P3V3S

P1V5S

C1302

10UF_6.3V_3

21

C1304

0.1UF_16V_2

21

0.1UF_16V_2

21

R1300

0_5%_2

22B531C649A549B3

21D627B7
48B748D748D8

48B7
48B7

21E327C328C351A856F5
51A7

48D8
48D8

48D8
48D8

B

21D627C7

PCIE_WAKE#

BI

BTIFON#

BI

CLKREQ_WLAN#

IN

CLK_PCIE_WLAN_DN

IN

CLK_PCIE_WLAN_DP

IN

BUF_PLT_RST#

IN

CLK_PCI_DEBUG

IN

PCIE_WLAN_RX_DN

OUT

PCIE_WLAN_RX_DP

OUT

PCIE_WLAN_TX_DN

IN

PCIE_WLAN_TX_DP

IN

BTIFON#

BI

21E347C2

PCI_3S_SERIRQ

IN

211

R1301

0_5%_2

21

R1302

0_5%_2

21

R1303

21

0_5%_2_DY

CN1300

3
5
7

9
11
13
15
17
19
21
23
25

29
31
33
35
37
39
41
43
45
47
49

SANTA_280290_1_52P

WAKE#
CH_DATA
CH_CLK
CLKREQ#
GND
REFCLK­REFCLK+
GND
LPC_DEBUG_RST#
LPC_PCI_CLK
GND
PERn0
PERp0

GND
PETn0
PETp0
GND
Reserved
+V3AL
CAPS_LED#
Reserved
Reserved
PWR_LED#
NUM_LED#

LPC_FRAME#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

W_DISABLE#

+3.3VAUX

SMB_CLK

SMB_DATA

LED_WWAN#
LED_WLAN#
LED_WPAN#

PERST#

USB_D­USB_D+

2

3.3V

4

GND

6

1.5V

8
10
12
14
16
18

GND

20
22
24
26

GND

2827

1.5VGND

30
32
34

GND

36
38
40

GND

42
44
46
48

1.5V

50

GND

5251

3.3VReserved

G2G1

GG

D

CC

B

MINI CARD 1(WLAN)

8

76

54

CHANGE by

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6627

87

65

4

32 1

REFERENCE 1400~1499(3G)

D

P1V5S

C1410

21

0.1UF_16V_2

21

21

0.1UF_16V_2

22UF_6.3V_5

C1412

C1411

P3V3S

D

CN1400

1

WAKE#

3

CH_DATA

5

CH_CLK

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

LPC_DEBUG_RST#

CLOSE TO CONN SIDE

47C3
47C3

47C3
47C3

SATA_MINICARD_RX_DN

BI

SATA_MINICARD_RX_DP

BI

SATA_MINICARD_TX_DN

BI

SATA_MINICARD_TX_DP

BI

C1405

C1407

0.01UF_50V_2

21

C1406

0.01UF_50V_2

21

C1408

21

0.01UF_50V_2

0.01UF_50V_2

21

52D6

OUT

SATA_MINICARD_C_RX_DN
SATA_MINICARD_C_RX_DP

SATA_MINICARD_C_TX_DN
SATA_MINICARD_C_TX_DP

MSATA_DET

TP1402

19

LPC_PCI_CLK

21

GND

23

PERn0

25

PERp0

29

GND

31

PETn0

33

PETp0

35

GND

37

Reserved

39

+V3AL

41

CAPS_LED#

43

Reserved

45

Reserved

47
49

PWR_LED#
NUM_LED#

SANTA_280290_1_52P

TP24

1

LPC_FRAME#

W_DISABLE#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

+3.3VAUX

SMB_CLK

SMB_DATA

LED_WWAN#
LED_WLAN#
LED_WPAN#

PERST#

USB_D­USB_D+

2

3.3V

4

GND

6

1.5V

8
10
12
14
16
18

GND

20
22
24
26

GND

2827

1.5VGND

30
32
34

GND

36
38
40

GND

42
44
46
48

1.5V

50

GND

5251

3.3VReserved

G2G1

GG

UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST

BUF_PLT_RST#

1

TP24

1

TP24

USB_3G_DN
USB_3G_DP

TP1400
TP1401

OUT

OUT

BI
BI

BI
BI

28A4 28B6
28A6
28A4
28A4

IN

51B2
51B2

0.1UF_16V_2

21

3G_OFF#

21E3 27C3
27C7 51A8
56F5

3

Q1400

DS

SSM3K7002FU

2

0.1UF_16V_2

21

3G_ON#

1

G

22UF_6.3V_5

21

21D3

IN

C1400C1401C1402

CC

B

28A428D3

UIM_PWR

IN

U1400

1

VIO

3

VIO VIO

6

VIO

52

VBUSGND

4

P3V3S

B

NXP_IP4223CZ6_SOT457_6P_DY

CN1401

P5

28D3

UIM_DATA

BI BI

P6
P7

G2 G1

P1

VCC

GND

P2

VPP

RST

P3

I_O

CLK

G

G

TAI_PMPAT5_06GLBS7NI4H1_6P

C1403

UIM_PWR
UIM_RST
UIM_CLK

C1404

21

21

0.1UF_16V_2

4.7UF_6.3V_3

IN
IN

28B6 28D3
28C3

28C3

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6628

87

REFERENCE 1700~1749(HDD)
REFERENCE 1750~1799(ODD)

D

B

52D2

IN

10K_5%_2

SATA_ODD_PWREN

P3V3S

21

SSM3K7002FU

Q1750

1

P5V0S

1M_5%_2

21

3

DS

G

2

R1752

R1751

100K_5%_2

65

IN
IN

OUT
OUT

SATA_HDD_TX_DP

SATA_HDD_TX_DN

SATA_HDD_RX_DN

SATA_HDD_RX_DP

47C3

47C3

47C3

47C3

PLACE CLOSE TO CONNECTOR(<100MILS)

CSC0402_DY

21

C1754

0.047UF_16V_2

21

Q1751

AM3423P

C1758

21

36

G

PMOS_4D1S

521

4

S

D

C1757

R1754R1750

0_5%_6_DY

21

C1756

21

22UF_6.3V_5

C1704

C1705

C1700

C1701

C1755

21

21

22UF_6.3V_5

0.1UF_16V_2

0.01UF_50V_2

21

0.01UF_50V_2

21

0.01UF_50V_2

21

0.01UF_50V_2

21

4

32 1

SATA HDD

CN1700

1

P5V0S

40MIL

C1706

21

22UF_6.3V_5

SATA_HDD_TX_C_DP

SATA_HDD_TX_C_DN

SATA_HDD_RX_C_DN

SATA_HDD_RX_C_DP

C1702

C1703

21

22UF_6.3V_5

21

0.1UF_16V_2

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V3.3

9

V3.3

10

V3.3

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

RESERVED

19

GND

20

V12

21

V12

22

V12

SUYIN_127076HR022G205ZR_22P

G1

G1

G2

G2

D

CC

B

CN1750

P6

GND

P5

51C7 51B6

52D7 52B6

0.01UF_50V_2

21

0.01UF_50V_2

0.01UF_50V_2

21

0.01UF_50V_2

OUT
OUT

IN
IN

SATA_ODD_RX_DP
SATA_ODD_RX_DN

SATA_ODD_TX_DN
SATA_ODD_TX_DP

C1750

C1753

47B3
47B3

47B3
47B3

C1751

C1752

21

21

SATA_ODD_DA#

OUT

SATA_ODD_PRSNT#

OUT

SATA_ODD_RX_C_DP
SATA_ODD_RX_C_DN

SATA_ODD_TX_C_DN
SATA_ODD_TX_C_DP

PLACE CLOSE TO CONNECTOR(<100MILS)

GND

P4

MD

P3

+5V

P2

+5V

P1

DP

S7

GND

S6

B+

S5

B-

S4

GND

S3

A-

S2

A+

S1

GND

ALLTOP_C18556_11305_L_13P

SATA ODD

G1

G

G2

G

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6629

87

REFERENCE 2000~2099(USB)

65

4

32 1

D

D

PLACEMENT @LEFT SIDE

P5V0A_USB3

CN2001

L2001

21

51C2

BI

51C2

USB_P2_DP

BI

WCM_2012_900T

34

USB_L_P2_DNUSB_P2_DN
USB_L_P2_DP

1
2
3
4

P5V0A

PAD2000

POWERPAD_2_0610

12

22UF_6.3V_5_DY

P5V0A_USB_PW1

21

C2000 C2001

1UF_6.3V_2

21

21

B

U2000

1

GND

VOUT

2

VIN

VOUT

3

VOUT

21E3

SB_USB_3

IN

C2004

CSC0402_DY

21

VIN

FLG#

EN_EN#

RICH_RT9711APF_MSOP_8P

G1

G

VCC

G2

G

D-

G3

G

D+

G4

G

G

SUYIN_020173GR004M29CZL_4P

8
7
6
54

10K_5%_2

22UF_6.3V_5

R2001

C2002

P3V3AL

USB_OC#_3

21

C2003

0.1UF_16V_2

21

OUT

P5V0A_USB3

R2000

RSC_0402_DY

21

21

21D6

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6630

87

65

REFERENCE 2400~2499(USB3.0)

P1V05_USB3

C2425

C2424

C2417

C2418

21

D

0.01UF_50V_2

C2419

21

21

0.01UF_50V_2

0.01UF_50V_2

P3V3_USB3

R4754

21

10K_5%_2

1

10K_5%_2

R4955

CLKREQ_USB3#

2

USB3_SMI#

31B8 48B7

IN

IN

P3V3_USB3

DIODE-BAT54-TAP-PHP

C2420

21

0.01UF_50V_2

48B7

IN
IN

48B7

48D8

OUT

48D8

OUT

48D8

IN

48D8

IN

51B631C6

10K_5%_2

D2400

C2421

21

0.01UF_50V_2

CLK_PCIE_USB3_DP
CLK_PCIE_USB3_DN

PCIE_USB3_RX_DP
PCIE_USB3_RX_DN

PCIE_USB3_TX_DP
PCIE_USB3_TX_DN

R2406

21

2

NC

13

B

R2405

OUT

CLKREQ_USB3#

0_5%_2

31C7
48B7

CLKREQ_IC_USB3#

21

P3V3_USB3

R2480 R2481

10K_5%_2

31B6

USB3_CS#

IN

USB3_SO

31B6

OUT

8

47K_5%_2

21

21

1

2

3

4

U2480

CS#

SO

WP#

GND

MAC_MX25L5121EMC_20G_SOP_8P

SCLK

76

VCC

NC

SI

C2423

C2422

21

0.01UF_50V_2

C2411

1UF_6.3V_2

21

IN

P3V3_USB3

C2480

0.1UF_16V_2

21

8

7

USB3_SCLK

6

USB3_SI

5

21

21

0.1UF_16V_2

C2409

21

C2410

0.1UF_16V_2

41C751A7

36A3

22B527C749A549B3

31B6

31C7
51B6

12PF_50V_2

21

31C6

31B6

IN

31B6

IN

0.1UF_16V_2

0.1UF_16V_2

21

IN
OUT
IN

OUT

31A6
31A8
31A6
31A8

X2400

24MHZ

21

0.1UF_16V_2

PCIE_USB3_RX_C_DP
PCIE_USB3_RX_C_DN

PLT_RST#
PCIE_WAKE#
CLKREQ_IC_USB3#

USB3_SMI#

USB3_SCLK

OUT

USB3_CS#

OUT

USB3_SI

OUT

USB3_SO

IN

USB3_XT1
USB3_XT2

21

21

C2412C2413

12PF_50V_2

P3V3_USB3

12

22

U2400

VDD33

1

PECLKP

2

PECLKN

4

PETXP

5

PETXN

7

PERXP

8

PERXN

47

PERSTB

48

PEWAKEB

10

PECREQB

46

SMIB

11

PONRSTB

15

SPISCK

14

SPICSB

16

SPISI

13

SPISO

24

XT1

23

XT2

27

IC(L)

31D3 21D6

P1V05_USB3

34

43

69213033

VDD33

VDD33

IN

VDD33

USB30_PWR_EN

VDD10

54

4

P3V3_USB30_AVDD

39

VDD10

VDD10

VDD10

VDD10

VDD10

GND

RENESAS_UPD720202K8_BAA_A_QFN_48P

49

P1V5

C2438

22UF_6.3V_5

31A5 21D6

3

25

42

VDD10

AVDD33

AVDD33

U3TXDP2

U3TXDN2

U2DM2

U2DP2

U3RXDP2

U3RXDN2

OCI2B
OCI1B

PPON2
PPON1

U3TXDP1

U3TXDN1

U2DM1

U2DP1

U3RXDP1

U3RXDN1

RREF

P5V0A

9

VIN

8

EN

7

POK

6

VCNTL

5

VIN

ANPEC_APL5930KAI_TRG_SOP_8P

C2435

1UF_6.3V_2

21

21

USB30_PWR_EN

IN

37

USB3_IC_TX2_DP

38

USB3_IC_TX2_DN

45

USB2_IC_TX2_DN

44

USB2_IC_TX2_DP

40

USB3_IC_RX2_DP

41

USB3_IC_RX2_DN

17
19

18
20

USB3_IC_TX1_DP

28

USB3_IC_TX1_DN

29
36

USB2_IC_TX1_DN

35

USB2_IC_TX1_DP
USB3_IC_RX1_DP

31

USB3_IC_RX1_DN

32

1.6K_1%_2

26

U2403

VOUT

VOUT

31.6K_1%_2

CHANGE by

32 1

R2415
R2416

GND

R2400

FB

R2423

10K_5%_2

21

1

2

3

4

21

P3V3A

R2424

32 1

DS

Q2402

G

SSM3K7002FU

1

2

21

10K_5%_2

21

10K_5%_2

BI
BI

BI
BI

BI
BI

TRACE WIDTH>20MILS

R2422

10K_1%_2

21

C2433

150PF_50V_2

2

AM2321P

R2427

220K_5%_2

21

Q2403

SD

G

1

21

BI
BI

BI
BI

BI
BI

P3V3_USB3

32D7

32D7

32B8

32A8
32D7

32D7

C2434

21

22UF_6.3V_5

DATE

P3V3_USB3

3

C2400

21

0.1UF_16V_2

P3V3_USB3

BLM21PG600SN1D_3A

33B5

33B5
33C5

33C5
33B5

33B5

P1V05_USB3

PAD2400

12

POWERPAD1X1M

21-OCT-2002XXX

23

C2401

C2402

21

21

0.1UF_16V_2

L2400

21

C2405

C2404

C2403

21

21

0.01UF_50V_2

0.01UF_50V_2

0.01UF_50V_2

P3V3_USB30_AVDD

21

C2406

C2408

21

21

10UF_6.3V_3

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

C2470

21

21

0.01UF_50V_2

C2414

C2415

21

21

0.1UF_16V_2

0.1UF_16V_2

of

6631

1

C2471

21

0.01UF_50V_2

C2416

21

0.01UF_50V_2

10UF_6.3V_5

0.01UF_50V_2

REV

X011310xxxxx-0-0

D

CC

B

AA

87

65

4

32 1

USB3.0 FROM CONTROLLLER

USB3.0 FROM PCH

USB3.0 FROM CONTROLLLER

D

USB3.0 FROM PCH

32A8
32A8

32B8

51C2
32B8

51C2

REFERENCE 2400~2499(USB3.0)

R2432
R2433

C2448

C2441

P5V0A_USB1

21

FOX_UEA111AC_RABHA_8H_9P

21

0_5%_2

21

0_5%_2

21

0_5%_2

21

0_5%_2

21

0.1UF_16V_2

21

R2449R2448

21

1
2
3
4
5
6
7
8
9

31B2
31B2

51C6
51C6

31B2
31B2

51C6
51C6

USB3_IC_RX1_DN

BI

USB3_IC_RX1_DP

BI

USB3_PCH_RX1_DN

BI

USB3_PCH_RX1_DP

BI

USB3_IC_TX1_DN USB3_SSTX1_DN

BI

USB3_IC_TX1_DP

BI

USB3_PCH_TX1_DN

BI

USB3_PCH_TX1_DP

BI

R2430
R2431

C2447

C2440

P5V0A_USB2

0_5%_6 0_5%_6

R2455

R2454

R2446

21

0_5%_2

21

0_5%_2

R2447

L2404

0_5%_2

USB_P0_R_DN

21

USB_P0_R_DP USB_P0_L_DP

21

0_5%_2

WCM_2012_900T

32D5
32D5

32D5
32D5

21
34

BI
BI

BI
BI

USB_P0_L_DN

USB3_SSRX1_DN
USB3_SSRX1_DP

USB3_SSTX1_DN
USB3_SSTX1_DP

USB_IC_DP

BI

USB_IC_DN

BI

USB_P0_DN

BI

USB_P0_DP

BI

USB3_SSRX1_DN
USB3_SSRX1_DP

21

0.1UF_16V_2

0.1UF_16V_2

21

0.1UF_16V_2

USB3_SSTX1_DP

USB3.0

SUPPORT SLEEP&CHARGE: R2449 STUFF

NO SUPPORT SLEEP&CHARGE: R2448 STUFF

C2426

CN2401

VBUS
D­D+
PGND
SSRX­SSRX+
GND
SSTX­SSTX+

22UF_6.3V_5

G
G
G
G
G
G

21

G1
G2
G3
G4

USB 3.0 CONNECTOR

G5
G6

32C7

BI

32C7

BI

BI
BI

C2427

21

32B7
32B7

C2432

1000PF_50V_20.1UF_16V_2

21

D

P5V0A_USB2

P5V0A

CURRENT LIMIT 2.5A

U2402
1
2

SB_USB_2

21D3

IN

C2428

47UF_6.3V_5

3
4

GMT_G547E1P81U_MSOP_8P

21

8

OUT

GND

7

OUT

IN

6

OUT

IN

5

EN

OC#

C2429

+

100UF_6.3V

21

USB_OC#_2

P3V3AL

R2408

10K_5%_2

21

OUT

CC

21B6

B

USB_IC_DP
USB_IC_DN

R2456

21

0_5%_2

21

0_5%_2

R2457

U2401

1

4

310

211

TI_TPS2541_QFN_16P

DP_OUT DP_IN

DM_OUT DM_IN

IN

ILIM_SEL

5

DSC

6

CTL1

7

CTL2

8

CTL3

PWPD
ILIM0
ILIM1

GND
FAULT#
OUT

NC

P5V0A_USB1

9

12

17
16
15
14

USB_OC#_1

13

P5V0A

0.1UF_16V_2

21

P5V0A

R2434

10K_5%_2

OUT

C2442

21

21D6

24K_5%_2

21

R2436R2435

210K_1%_2

21

51C2 32C8

51C2 32C8

USB_P0_DN

BI

USB_P0_DP

BI

21C3
21E6
21E6
21D3

BI
BI
IN

IN
IN
IN
IN

32C8

32C8

USB2_IC_TX1_DN
USB2_IC_TX1_DP

EC_ILIM_SEL

SB_USB_1
EC_CTL1
EC_CTL2
EC_CTL3

BI
BI

31B2

31B2

21D6

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6632

87

REFERENCE 2400~2499(USB3.0)

65

4

32 1

D

D

USB 3.0 CONNECTOR

P5V0A_USB2

C2452

C2451

22UF_6.3V_5_DY

CN2402

VBUS
D­D+
PGND
SSRX­SSRX+
GND
SSTX­SSTX+

21

G1

G

G2

G

G3

G

G4

G

G5

G

G6

G

R2437
R2438

R2439
R2440

C2443

C2445

21
21

21
21

0_5%_2
0_5%_2

C2444

C2446

0_5%_2
0_5%_2

USB_P1_R_DN
USB_P1_R_DP USB_P1_L_DP

WCM_2012_900T

21

0_5%_2

21

0_5%_2

21

0_5%_2

21

0_5%_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

L2405

USB3_SSRX2_DN
USB3_SSRX2_DP

USB3_SSTX2_DN
USB3_SSTX2_DP

34

33B3
33B3

33B2
33B2

BI
BI

BI
BI

USB3_SSRX2_DN
USB3_SSRX2_DP

USB3_SSTX2_DN
USB3_SSTX2_DP

BI
BI

BI
BI

1
221
3
4
5
6
7
8
9

33C3
33C3

33C3
33C3

FOX_UEA111AC_RABHA_8H_9P

USB2.0 FROM PCONTROLLER

USB2.0 FROM PCH

31C2

51C2

USB3.0 FROM CONTROLLLER

USB3.0 FROM PCH

B

USB3.0 FROM CONTROLLLER

USB3.0 FROM PCH

USB2_IC_TX2_DN

BI

USB2_IC_TX2_DP

BI

USB_P1_DN USB_P1_L_DN

BI

USB_P1_DP

BI

USB3_IC_RX2_DN

BI

USB3_IC_RX2_DP

BI

51C6
51C6

51C6
51C6

USB3_PCH_RX2_DN

BI

USB3_PCH_RX2_DP

BI

BI
BI

BI
BI

USB3_IC_TX2_DN
USB3_IC_TX2_DP

USB3_PCH_TX2_DN
USB3_PCH_TX2_DP

R2453
R2452

R2450
R2451

21

C2453

1000PF_50V_20.1UF_16V_2

21

CC

B

USB3.0

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6633

87

REFFERENCE 3000~3049(LCM)

65

4

32 1

P3V3S

Q3000

2

R3001

C3000

21

21B621D150D7
21E6

21

0.01UF_50V_2

PCH_LCM_VDDEN#

INV_PWM_3

IN

EC_BKLTEN

IN

Q3001

1

R3000

21

3

DS

G

2

47K_5%_2

470K_5%_2

D

IN

PCH_LCM_VDDEN

50D7

SSM3K7002FU

B

SD

G

AM2321P

1

P3V3S_MOS_LCM

3

R3009

100_5%_2

R3003

100_5%_2

1000PF_50V_2

21
21

POWERPAD_2_0610

C3003

21

680PF_50V_2

SSM3K7002FU

C3006

21

PAD3003

12

100_5%_2

R3004

Q3002

1

50D7
50C7

100K_5%_2

21

G

R3006

P3V3S_LCM

C3002

212

3

DS

PCH_LVDS_DDCCLK

BI

PCH_LVDS_DDCDATA

BI

50C6
50C6

50C6
50C6

50C6
50C6

50C6
50C6

INV_PWM_3_R

EC_BKLTEN_R

C3007

CSC0402_DY

21

21

C3001

21

10UF_6.3V_5

PCH_LVDS_TXDL0_DN

IN

PCH_LVDS_TXDL0_DP

IN

PCH_LVDS_TXDL1_DN

IN

PCH_LVDS_TXDL1_DP

IN

PCH_LVDS_TXDL2_DN

IN

PCH_LVDS_TXDL2_DP

IN

PCH_LVDS_TXCL_DN

IN

PCH_LVDS_TXCL_DP

IN

51B2
51B2

24A6

BI

24A6

BI

21

0.1UF_16V_2

P3V3S

2.2K_5%_2

21

USB_CAM_DN

BI

USB_CAM_DP

BI

MIC_IN_CLK
MIC_IN_DATA

R3002

2.2K_5%_2

R3010

100_5%_2

R3005

21

MIC_IN_DATA_R

21

P3V3S

C3004

21

0.1UF_16V_2

CN3000

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

ACES_50203_03001_001_30P

D

CC

G1

G

G2

G

B

PVBAT PVBAT_LCD

PAD3001

21

12

POWERPAD_2_0610

C3009

21

C3010

4.7UF_25V_5

21

0.1UF_25V_3

P3V3S

C3011

21

0.1UF_16V_2

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6634

87

REFERENCE 3050~3099(CRT)

65

4

32 1

P5V0S

50B7

50B7

50B7

D

CRTR

IN

CRTG

IN

CRTB

IN

L3052

L3051

L3050

21

21

120NH,5%

21

120NH,5%

120NH,5%

CRTR_L

CRTG_L

CRTB_L

OUT

OUT

OUT

35A7 35C3

35A7 35C3

35A7 35C3

D3050

SBR3U40P1

P5V0S_CRT1

2121

FUSE3050

D

SMD1812P110TF

R3055

R3054

21

21

150_1%_2

150_1%_2

R3056

21

150_1%_2

C3050

21

15PF_50V_2

C3051

21

15PF_50V_2

C3052

21

15PF_50V_2

P5V0S_CRT2

P5V0S_CRTVDD

R3050 R3051

2.2K_5%_2

BI

BI

CRT_DDCDATA_OUT

CRT_DDCCLK_OUT

35A3

35A3

2.2K_5%_2

21

21

100_5%_2

100_5%_2

R3053

R3052

21

35A3
35A3

21

IN
IN

35A735D5
35A735D5
35A735D5

CRT_DDCDATA_R_OUT
CRT_HSYNC_R_OUT
CRT_VSYNC_R_OUT
CRT_DDCCLK_R_OUT

0.1UF_16V_2_DY

CRTR_L

IN

CRTG_L

IN

CRTB_L

IN

TP3050

TP3051

C3054C3053

0.1UF_16V_2_DY

21

21

CN3051

1

1

2

2

3

1

1

3

4

TP24

4

5

5

6

6

7

7

8

8

9

9

10

10

TP24

11

11

12

12

13

13

14

14

15

15

SUYIN_070546HR015M251ZR_15P

G1

G

G2

G

CC

RESERVE CAP FOR EMI

B

B

8

0.22UF_6.3V_2

C3055

P3V3S

21

P5V0S

C3056

P5V0S_CRTVDD

C3057

0.22UF_6.3V_2

21

0.22UF_6.3V_2

35C335D5

IN

35C335D5

IN

35C3

IN

35D5

CRTR_L
CRTG_L
CRTB_L

21

76

2.2K_5%_2 2.2K_5%_2

U3050

116

VCC-SYNC SYNC_OUT2

2

VCC-VIDEO

3

VIDEO_1

4

VIDEO_2

5

VIDEO_3

6

GND

7

VCC-DCC

TI_TPD7S019_15DBQR_SSOP_16P

SYNC_IN2

SYNC_OUT1

SYNC_IN1
DCC_OUT2

DDC_IN2
DDC_IN1

DDC_OUT1BYP

CRT_VSYNC_OUT
CRT_VSYNC

15

CRT_HSYNC_OUT

14

CRT_HSYNC

13
12

CRT_DDCDATA

11

CRT_DDCCLK

10
98

54

P3V3S

R3061R3060

21

21

IN
IN
IN

IN

R3062

21

R3063

21

30_5%_2

30_5%_2

50A6

50A6

50A6
50A6

CRT_VSYNC_R_OUT

CRT_HSYNC_R_OUT

CRT_DDCDATA_OUT

CRT_DDCCLK_OUT

OUT
OUT
OUT

OUT

35C3

35C3

35C5

35C5

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CHANGE by

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6635

87

65

4

32 1

REFERENCE 3150~3199(HDMI)

D

50B2

50B2

B

P3V3S

G

Q3151

SSM3K17FU

HDMI_DDCDATA

BI BI

HDMI_DDCCLK

BI BI

G

HDMI_CN_DDCDATA

S

D

DS

G

Q3150

G

SSM3K17FU

DS

HDMI_CN_DDCCLK

D

S

P3V3S

1

Q3152

R3164

IN

IN

IN

IN

IN

IN

IN

IN

HDMI_TXC_C_DP

HDMI_TXC_C_DN

HDMI_TX0_C_DN

HDMI_TX0_C_DP

HDMI_TX1_C_DN

HDMI_TX1_C_DP

HDMI_TX2_C_DN

HDMI_TX2_C_DP

36C550B1

36C550B1

36D550B1

36D550B1

36D550B1

36D550B1

36D550B1

36D550B1

680_5%_2

R3163

680_5%_2

R3162

680_5%_2

R3161

680_5%_2

R3160

680_5%_2

R3159

680_5%_2

R3158

680_5%_2

R3157

680_5%_2

SSM3K7002FU

21

21

21

21

21

21

21

21

G

3

DS

36C3 37C3

36C3 37D3

R3165

100K_5%_2

21

2

PLACE CLOSE TO CONNECTOR

R3166

IN

IN

IN

IN

IN

IN

IN

IN

40MIL

HDMI_TX2_C_DP

HDMI_TX2_C_DN

HDMI_TX1_C_DP

HDMI_TX1_C_DN

HDMI_TX0_C_DP

HDMI_TX0_C_DN

HDMI_TXC_C_DP

HDMI_TXC_C_DN

P5V0AL

D3155

21 21

36A750B1

36A750B1

36A750B1

36A750B1

36A750B1

36B750B1

36B750B1

36B750B1

SBR3U40P1

C3150

100PF_50V_2

21

CLOSE TO CONNECTOR

U3150

OUT

HPDET

50B2

4

TC7SZ08FU

0_5%_2

R3167

0_5%_2

R3168

0_5%_2

R3169

0_5%_2

R3170

0_5%_2

R3171

0_5%_2

R3172

0_5%_2

R3173

0_5%_2

P3V3S

5

+-

3

HDMI_TX2_R_DP

21

HDMI_TX2_R_DN

21

HDMI_TX1_R_DP

21

HDMI_TX1_R_DN

21

HDMI_TX0_R_DP

21

HDMI_TX0_R_DN

21

HDMI_TXC_R_DP

21

HDMI_TXC_R_DN

21

1

HDMI_HPD_EC

2

PLT_RST#

SMD1812P110TF

37C1

FUSE3150

OUT

37D6

36C637D3
36C637C3

HPDET_IC

BI
BI

BI

P5V0AL_HDMI_VDD2P5V0AL_HDMI_VDD1

R3150

470K_5%_2

21

IN

31C6 41C7 51A7

IN

2

R3152

2.2K_5%_2

HDMI_CEC

HDMI_CN_DDCCLK
HDMI_CN_DDCDATA

C3151

22PF_50V_2_DY

21

37B121B6

P5V0AL

13

NC

DIODE-BAT54-TAP-PHP

2.2K_5%_2

21

TP3151

R3154

1K_5%_2

D3150

R3153

21

TP24

21

1
2
3
4
5
6
7
8

9
10
11
12
13
14

1

15
16
17
18
19

CN3150

1
2
3
4
5
6
7
8
9
10
11
12
13
14

P1

P1

15

P2

P2

16

P3

P3

17

P4

P4

18
19

SUYIN_100042GB019M173ZR_19P

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6636

87

65

4

32 1

P3V3AL

P3V3AL

1321

D3200

2

NC

DIODE-BAT54-TAP-PHP

D

37B3 36C3 36C6

HDMI_DDCCLK_CEC HDMI_CN_DDCCLK

BI

4.02K_1%_2

R3201

P3V3AL

R3204

27K_5%_2

5

1

U3203

NC

4

21

SSM3K7002FU

+

-

3

HDMI_CEC

2

3

Q3203

DS

R3206

G

BI

2121

CEC_OUT

36C337B6

OUT

37B6

37B3

BI

HDMI_DDCDATA_CEC

4.02K_1%_2

R3200

22K_5%_2

R3205

100K_5%_2

21

R3213

4.7K_5%_2

21

P3V3AL

R3210

4.7K_5%_2

21

21D2

BI

21D3

37A8

OUT

37A6

37D8
37C6

OUT

IN

IN

EC_SMB3_CLK

CEC_XOUT

CEC_XIN

CEC_IN
CEC_OUT

U3202

1 20

P3_5-SSCK-SCL-CMP1_2 P3_4-SCS#-SDA-CMP1_1

2

P3_7-CNTR0#-SSO-TXD1

3

RESET#

4

XOUT-P4_7

5

VSS-AVSS

6

XIN-P4_6

7

VCC-AVCC

8

MODE

9

P4_5-INT0#-RXD1

10 11

P1_7-CNTR00-INT10# P1_6-CLK0-SSI01

RENESAS_R5F211B4D61SP_LSSOP_20P

P3_3-TCIN-INT3#-SSI00-CMP1_0

P1_0-KI0#-AN8-CMP0_0
P1_1-KI1#-AN9-CMP0_1

P1_2-KI2#-AN10-CMP0_2

P1_3-KI3#-AN11-TZOUT

P1_5-RXD0-CNTR01-INT11#

IN

68_5%_2

74LVC1G14GV

R3214

CEC_IN

B

Q3201

G

SSM3K17FU

G

21

S

P3V3AL

G

Q3200

SSM3K17FU

G

21

S

DS

P4_2-VREF

P1_4-TXD0

D

DS

D

HDMI_CN_DDCDATA

EC_SMB3_DATA

19
18

HDMI_DDCDATA_CEC

17

HDMI_DDCCLK_CEC

16
15
14
13
12

BI

BI

BI

BI
BI

36C3 36C6

R3209

21

21D2
48C248C2

21D3

C3202

21

P3V3AL

R3208

4.7K_5%_2

0.1UF_16V_2

21

4.7K_5%_2

37C5
37D5

P3V3AL

C3205

21

1UF_6.3V_2

R3227

21

33_5%_2

PHP_74LVC1G17_SOT753_5P

U3200

4

R3202

P3V3AL

C3200

21

1

5

NC

+

2

HPDET_IC

-

3

HDMI_HPD_EC

21

RSC_0402_DY

0.1UF_16V_2

IN

OUT

D

CC

36C4

36A3

21B6

B

P3V3AL

R3211

47K_5%_2

21

R3212

47K_5%_2

21

CEC_XINCEC_XOUT

37B637B6

INOUT

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6637

87

65

4

32 1

REFERENCE 4100~4299(DDR)

43A4

BI

D

43A8
43A8
43A8
43C5
43C5
43D4
43D4
43D4
43D4
43D4
43D4
43A8
43A8
43A8
38A6
38A6
39C848A8
39C848A8

43C5
43C5

43B5
43B5
43B5
43B5
43B5
43B5

B

43B5
43B5
43B5
43B5
43B5
43B5
43B5
43B5
43B5
43B5

M_A_A<15..0>

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
OUT
OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

M_A_A<0>

0

M_A_A<1>

1

M_A_A<2>

2

M_A_A<3>

3

M_A_A<4>

4

M_A_A<5>

5

M_A_A<6>

6

M_A_A<7>

7

M_A_A<8>

8

M_A_A<9>

9

M_A_A<10>

10

M_A_A<11>

11

M_A_A<12>

12

M_A_A<13>

13

M_A_A<14>

14

M_A_A<15>

15

M_A_BS0
M_A_BS1
M_A_BS2
M_CS#0
M_CS#1
M_CLK_DDR0_DP
M_CLK_DDR0_DN
M_CLK_DDR1_DP
M_CLK_DDR1_DN
M_CKE0
M_CKE1
M_A_CAS#
M_A_RAS#
M_A_WE#

SA0_DIM0

SA1_DIM0
PCH_3S_SMCLK
PCH_3S_SMDATA

M_ODT0

M_ODT1

M_A_DQS0_DP
M_A_DQS1_DP
M_A_DQS2_DP
M_A_DQS3_DP
M_A_DQS4_DP
M_A_DQS5_DP
M_A_DQS6_DP
M_A_DQS7_DP
M_A_DQS0_DN
M_A_DQS1_DN
M_A_DQS2_DN
M_A_DQS3_DN
M_A_DQS4_DN
M_A_DQS5_DN
M_A_DQS6_DN
M_A_DQS7_DN

98
97
96
95
92
91
90
86
89
85

107

84
83

119

80
78

109
108

79
114
121
101
103
102
104

73

74
115
110
113
197
201
202
200

116
120

11

28

46

63
136
153
170
187

12

29

47

64
137
154
171
188

10

27

45

62
135
152
169
186

CN4100

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

JAE_MM80_204B1_D9R_R400_DT_204P

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

M_A_DQ<0>

5

M_A_DQ<1>

7

M_A_DQ<2>

15

M_A_DQ<3>

17

M_A_DQ<4>

4

M_A_DQ<5>

6

M_A_DQ<6>

16

M_A_DQ<7>

18

M_A_DQ<8>

21

M_A_DQ<9>

23

M_A_DQ<10>

33

M_A_DQ<11>

35

M_A_DQ<12>

22

M_A_DQ<13>

24

M_A_DQ<14>

34

M_A_DQ<15>

36

M_A_DQ<16>

39

M_A_DQ<17>

41

M_A_DQ<18>

51

M_A_DQ<19>

53

M_A_DQ<20>

40

M_A_DQ<21>

42

M_A_DQ<22>

50

M_A_DQ<23>

52

M_A_DQ<24>

57

M_A_DQ<25>

59

M_A_DQ<26>

67

M_A_DQ<27>

69

M_A_DQ<28>

56

M_A_DQ<29>

58

M_A_DQ<30>

68

M_A_DQ<31>

70

M_A_DQ<32>

129

M_A_DQ<33>

131

M_A_DQ<34>

141

M_A_DQ<35>

143

M_A_DQ<36>

130

M_A_DQ<37>

132

M_A_DQ<38>

140

M_A_DQ<39>

142

M_A_DQ<40>

147

M_A_DQ<41>

149

M_A_DQ<42>

157

M_A_DQ<43>

159

M_A_DQ<44>

146

M_A_DQ<45>

148

M_A_DQ<46>

158

M_A_DQ<47>

160

M_A_DQ<48>

163

M_A_DQ<49>

165

M_A_DQ<50>

175

M_A_DQ<51>

177

M_A_DQ<52>

164

M_A_DQ<53>

166

M_A_DQ<54>

174

M_A_DQ<55>

176

M_A_DQ<56>

181

M_A_DQ<57>

183

M_A_DQ<58>

191

M_A_DQ<59>

193

M_A_DQ<60>

180

M_A_DQ<61>

182

M_A_DQ<62>

192

M_A_DQ<63>

194

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

M_A_DQ<63..0>

CHA

43D8

BI

P1V5

C4100

+

330UF_2.5V_DY 1UF_6.3V_2

21

NOTE:PLACE C4100 ON COMMON PATH FOR BOTH DIMM'S

2.2UF_6.3V_3

38C339C3

LAYOUT NOTE: PLACE CAPS NEAR SO-DIMM0 POWER PIN

21

21

P3V3S

C4114 C4115

0.1UF_16V_2

21

21

2.2UF_6.3V_3

PM_EXTTS#1_R

IN

C4102C4101 C4103 C4104

1UF_6.3V_21UF_6.3V_21UF_6.3V_2

21

21

P0V75M_VREF

ALL VREF TRACES SHOULD HAVE 10 MIL TRACE WIDTH

C4150 C4116

0.1UF_16V_2

21

21

P3V3S

R4104

10K_5%_2

21

C4105 C4107C4106

21

C4110 C4108C4109

10UF_6.3V_3

21

2.2UF_6.3V_3

10UF_6.3V_310UF_6.3V_310UF_6.3V_3

21

21

10UF_6.3V_310UF_6.3V_3

21

21

38B539C3

OUT

39C341A5

OUT

P0V75M_VREF

C4117 C4118

0.1UF_16V_2

21

21

PM_EXTTS#1_R
DDR3_DRAMRST#

CN4100

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8
VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

JAE_MM80_204B1_D9R_R400_DT_204P

PLACE THESE CAPS CLOSE TO VTT1 AND VTT2

44

VSS16

48

VSS17

49

VSS18

54

VSS19

55

VSS20

60

VSS21

61

VSS22

65

VSS23

66

VSS24

71

VSS25

72

VSS26

127

VSS27

128

VSS28

133

VSS29

134

VSS30

138

VSS31

139

VSS32

144

VSS33

145

VSS34

150

VSS35

151

VSS36

155

VSS37

156

VSS38

161

VSS39

162

VSS40

167

VSS41

168

VSS42

172

VSS43

173

VSS44

178

VSS45

179

VSS46

184

VSS47

185

VSS48

189

VSS49

190

VSS50

195

VSS51

196

VSS52

1.5A

20325

VTT1

204

VTT2

G1

G1

G2

G2

P0V75S

D

CC

B

NOTE:
IF SA0_DIM0=1 , SA1_DIM0=0

SO-DIMMA SPD ADDRESS IS 0XA2
SO-DIMMA TS ADDRESS IS 0X32

IF SA0_DIM0=0 , SA1_DIM0=0
SO-DIMMA SPD ADDRESS IS 0XA0
SO-DIMMA TS ADDRESS IS 0X30

8

P3V3S

10K_5%_2_DY

10K_5%_2

R4100

R4102

R4101

10K_5%_2_DY

SA0_DIM0

SA1_DIM0

R4103

10K_5%_2

2121

2121

38C8

IN

38C8

IN

76

54

CHANGE by

C4119 C4120 C4121 C4122

1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2

21

21

21

21

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6638

87

REFERENCE 4100~4299(DDR)

65

4

32 1

BI

43A4
43A4
43A4
43C1
43C1
43D1
43D1
43D1
43D1
43D1
43D1
43A4
43A4

38C848A8
38C848A8

43C1
43C1

43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1

M_B_A<15..0>

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

M_B_A<0>

0

M_B_A<1>

1

M_B_A<2>

2

M_B_A<3>

3

M_B_A<4>

4

M_B_A<5>

5

M_B_A<6>

6

M_B_A<7>

7

M_B_A<8>

8

M_B_A<9>

9

M_B_A<10>

10

M_B_A<11>

11

M_B_A<12>

12

M_B_A<13>

13

M_B_A<14>

14

M_B_A<15>

M_B_BS0
M_B_BS1
M_B_BS2
M_CS#2
M_CS#3
M_CLK_DDR2_DP
M_CLK_DDR2_DN
M_CLK_DDR3_DP
M_CLK_DDR3_DN
M_CKE2
M_CKE3
M_B_CAS#
M_B_RAS#
M_B_WE#

PCH_3S_SMCLK
PCH_3S_SMDATA

M_ODT2
M_ODT3

M_B_DQS0_DP
M_B_DQS1_DP
M_B_DQS2_DP
M_B_DQS3_DP
M_B_DQS4_DP
M_B_DQS5_DP
M_B_DQS6_DP
M_B_DQS7_DP
M_B_DQS0_DN
M_B_DQS1_DN
M_B_DQS2_DN
M_B_DQS3_DN
M_B_DQS4_DN
M_B_DQS5_DN
M_B_DQS6_DN
M_B_DQS7_DN

CN4101

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10_AP

84

A11

83

A12

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS#0

27

DQS#1

45

DQS#2

62

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

JAE_MM80_204B1_H2R_R250_DT_204P

5

DQ0

M_B_DQ<1>

7

DQ1

M_B_DQ<2>

15

DQ2

M_B_DQ<3>

17

DQ3

M_B_DQ<4>

4

DQ4

M_B_DQ<5>

6

DQ5

M_B_DQ<6>

16

DQ6

M_B_DQ<7>

18

DQ7

M_B_DQ<8>

21

DQ8

M_B_DQ<9>

23

DQ9

M_B_DQ<10>

33

DQ10

M_B_DQ<11>

35

DQ11

M_B_DQ<12>

22

DQ12

M_B_DQ<13>

24

DQ13

M_B_DQ<14>

34

DQ14

M_B_DQ<15>

36

DQ15

M_B_DQ<16>

39

DQ16

M_B_DQ<17>

41

DQ17

M_B_DQ<18>

51

DQ18

M_B_DQ<19>

53

DQ19

M_B_DQ<20>

40

DQ20

M_B_DQ<21>

42

DQ21

M_B_DQ<22>

50

DQ22

M_B_DQ<23>

52

DQ23

M_B_DQ<24>

57

DQ24

M_B_DQ<25>

59

DQ25

M_B_DQ<26>

67

DQ26

M_B_DQ<27>

69

DQ27

M_B_DQ<28>

56

DQ28

M_B_DQ<29>

58

DQ29

M_B_DQ<30>

68

DQ30

M_B_DQ<31>

70

DQ31

M_B_DQ<32>

129

DQ32

M_B_DQ<33>

131

DQ33

M_B_DQ<34>

141

DQ34

M_B_DQ<35>

143

DQ35

M_B_DQ<36>

130

DQ36

M_B_DQ<37>

132

DQ37

M_B_DQ<38>

140

DQ38

M_B_DQ<39>

142

DQ39

M_B_DQ<40>

147

DQ40

M_B_DQ<41>

149

DQ41

M_B_DQ<42>

157

DQ42

M_B_DQ<43>

159

DQ43

M_B_DQ<44>

146

DQ44

M_B_DQ<45>

148

DQ45

M_B_DQ<46>

158

DQ46

M_B_DQ<47>

160

DQ47

M_B_DQ<48>

163

DQ48

M_B_DQ<49>

165

DQ49

M_B_DQ<50>

175

DQ50

M_B_DQ<51>

177

DQ51

M_B_DQ<52>

164

DQ52

M_B_DQ<53>

166

DQ53

M_B_DQ<54>

174

DQ54

M_B_DQ<55>

176

DQ55

M_B_DQ<56>

181

DQ56

M_B_DQ<57>

183

DQ57

M_B_DQ<58>

191

DQ58

M_B_DQ<59>

193

DQ59

M_B_DQ<60>

180

DQ60

M_B_DQ<61>

182

DQ61

M_B_DQ<62>

192

DQ62

M_B_DQ<63>

194

DQ63

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
1515
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

M_B_DQ<0>

M_B_DQ<63..0>

BI

43A1

D

43A4

OUT
OUT

SA0_DIM1
SA1_DIM1

39A7
39A6

B

43D4

2.2UF_6.3V_3

CHB

P1V5

LAYOUT NOTE: PLACE CAPS NEAR SO-DIMM0 POWER PIN

C4124

1UF_6.3V_2

C4138

1UF_6.3V_2

21

P3V3S

0.1UF_16V_2

21

21

2.2UF_6.3V_3

21

C4137

P0V75M_VREF

1UF_6.3V_2

21

C4128

C4127C4126C4125

1UF_6.3V_2

21

10UF_6.3V_3

21

2121

C4133

10UF_6.3V_3

ALL VREF TRACES SHOULD HAVE 10 MIL TRACE WIDTH

C4139C4151

0.1UF_16V_2

21

2.2UF_6.3V_3

C4129

10UF_6.3V_3

2121

C4132

10UF_6.3V_3

38B538C3

OUT

38C341A5

OUT

P0V75M_VREF

21

C4130

10UF_6.3V_3

2121

C4131

10UF_6.3V_3

PM_EXTTS#1_R
DDR3_DRAMRST#

C4141C4140

0.1UF_16V_2

21

CN4101

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

JAE_MM80_204B1_H2R_R250_DT_204P

44

VSS16

48

VSS17

49

VSS18

54

VSS19

55

VSS20

60

VSS21

61

VSS22

65

VSS23

66

VSS24

71

VSS25

72

VSS26

127

VSS27

128

VSS28

133

VSS29

134

VSS30

138

VSS31

139

VSS32

144

VSS33

145

VSS34

150

VSS35

151

VSS36

155

VSS37

156

VSS38

161

VSS39

162

VSS40

167

VSS41

168

VSS42

172

VSS43

173

VSS44

178

VSS45

179

VSS46

184

VSS47

185

VSS48

189

VSS49

190

VSS50

195

VSS51

196

VSS52

203

VTT1

204

VTT2

G1

G1

G2

G2

PLACE THESE CAPS CLOSE TO VTT1 AND VTT2

1.5A

D

CC

P0V75S

B

NOTE:
SO-DIMMB SPD ADDRESS IS 0XA4
SO-DIMMB TS ADDRESS IS 0X34

8

P3V3S

R4106R4105

10K_5%_2_DY

10K_5%_2

2121

SA0_DIM1 SA1_DIM1

39C8 39C8

IN

R4107

10K_5%_2

R4108

10K_5%_2_DY

IN

2121

76

54

CHANGE by

C4145C4144.C4143C4142

1UF_6.3V_21UF_6.3V_2

21

21

1UF_6.3V_21UF_6.3V_2

21

21

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6639

87

REFERENCE 4300~4349(FAN)
REFERENCE 4411~4449(THERMAL )

D

65

4

32 1

P5V0S

PAD4300

12

POWERPAD_2_0610

L4300

KC_FBM_11_160808_101_T_2P_DY

P3V3S

R4300

10K_5%_2

21

IN

FAN_TACH1

21B6

TP4300

1 G2

TP30

C4300

21

220pF_50V_2

C4305

21B6

IN

P5V0S_FAN

21

21

21

CSC0402_DY

FAN1_PWM

C4307

21

22UF_6.3V_5_DY

TP4301

1

TP30

C4301

21

4.7UF_6.3V_3

P3V3S

R4306

10K_5%_2

21

C4302

21

0.1UF_16V_2

C4306

21

CSC0402_DY

CN4300

1

1

2
3
4

ACES_50271_0040N_001_4P

G1

G

2

G

3
4

FAN CN

D

CC

B

IN

330_5%_2

PVCORE_PG

R4413

THRM_SHUTDWN#

R4414

2M_5%_2

21EC

Q4412

CE

B

21

B

MMBT4401

SSM3K7002FU

C4412

CSC0402_DY

21

3

Q4411

DS

1

G

2

OUT

15D8 40A8

40B1 15D8

OUT

100K_5%_2

THRM_SHUTDWN#

R4445

P5V0AL

C4441

21

21

0.1UF_16V_2

1

2

3

4

U4441

VCC

TMSNS1

GND

RHYST1

OT1

TMSNS2

RHYST2

OT2

ENE_P2809A2_SOT23_8P

8

R4443

7

13.3K_1%_2

6

5

P5V0AL

21

R4442

21

R4444

21

100K_1%_NTC 26.7K_1%_2

11A411C749B7

PM_THRMTRIP#

41D552C1

IN

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6640

87

65

4

32 1

REFERENCE 4500~4699(CPU)

P1V8S

21

41D5

D

OUT

PLACE CLOSE TO CPT AND NVRAM CONNECTOR

H_SNB_IVB#

2.2K_5%_2

21

1K_5%_2

R4501.

21

R4502R4500

2.2K_5%_2_DY

PROCESS STRAP SETTING

SANDY BRIDGE ONLY

SANDY BRIDGE/IVY BRIDGE

STUFF R4502

STUFF R4500/R4501

DMI&FDI TERMINATIONVOLTAGE

NV_CLE

SET TOVSS WHEN LOW

(DEFAULT)

SET TOVCC WHEN HIGH

49B7

51A7

31C636A3

B

S3 CIRCUIT: DRAM_RST# TO MEMORY SHOULD BE HIGH DURING S3

NV_CLE

IN

IN

P3V3A

52B2

OUT

PM_DRAM_PWRGD

PLT_RST#

CN4500

A28

CLK_DMI_PCH_DP

A27

CLK_DMI_PCH_DN

A16
A15

R8

CPU_DRAMRST#

AK1

SM_RCOMP0

A5

SM_RCOMP1

A4

SM_RCOMP2

AP29
AP27

AR26
AR27
AP30

AR28
AP26

AL35

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

IN
IN

21

R4512
R4513
R4514

TP4502
TP4503

TP4504
TP4505
TP4506

TP4507
TP4508

TP4509

IN
IN
IN

IN
IN

1K_5%_2

21

1K_5%_2

OUT

H_PRDY#
H_PREQ#

H_TCK
H_TMS
H_TRST#

H_TDI
H_TDO

SYS_RESET#

H_TMS
H_TDI
H_PREQ#

H_TCK
H_TRST#

41A5

21
21
21

R4510
R4511

1

TP30

1

TP30

1

TP30

1

TP30

1

TP30

1

TP30

1

TP30

1

TP30

CAD NOTE: ALL DDR_COMP SIGNALS SHOULD BE ROUTED SUCH TAHT

- MAX LENGTH = 500 MILS

- TRACE WIDTH = 15MILS AND

- MB TRACE IMPEDANCE < 68 MOHMS
(WORST CASE RESISTANCE)

41C1

41C1

41C1

41C1

41C1

140_1%_2

25.5_1%_2
200_1%_2

R4516
R4517
R1418

R4519
R4520

48B3
48B3

P1V05S

D

OUT

41B2

IN

41B2

IN

41B2

IN

41B2

IN

41B2

IN

OUT

OUT

49B8

CC

P1V05S

21

51_5%_2

21

51_5%_2

21

21
21

51_5%_2_DY

51_5%_2
51_5%_2

B

TP24

TP24

C26

PROC_SELECT#

AN34

1

1

AL33

AN33

AL32

AN32

AM34

AP33

AR33

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

V8

SM_DRAMPWROK

RESET#

CLOCKS

MISCDDR3

JTAG & BPM

PWR MANAGEMENT THERMAL MISC

41D8

P1V05S

CPU_PROCHOT#

21A652C2

40A4
52C1

R4503

62_5%_2

11B721C3

OUT

C4500

CSC0402_DY

2121

P1V5S

R4506

49A3

52C2

21

R4505

200_5%_2

21

H_SNB_IVB#

OUT

H_PECI

OUT

R4504

21

CPU_PROCHOT#_R

56_5%_2

PM_THRMTRIP#

OUT

LOW IN C6/C7

H_PM_SYNC

BI

H_CPUPWRGD

IN

PM_DRAM_PWRGD_R

TP4500

TP4501

130_1%_2

R4507

21

1.5K_5%_2

750_1%_2

R4508

21

10K_5%_2

R4509

21

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

BCLK

BCLK#

PRDY#
PREQ#

TCK
TMS

TRST#

TDI
TDO

DBR#

P1V5

Q4600

1

1K_5%_2

3

DS

G

2

21 21

R4602

R4604

4.99K_1%_2

R4603

1K_5%_2

DDR3_DRAMRST#

21

CPU_DRAMRST#

OUT

38C3 39C3

41D2

IN

AA

R4601

1K_5%_2

OUT

IN

DRAMRST_CNTRL

DRAMRST_CNTRL_PCH

R4600

0_5%_2

0.047UF_16V_2

21

SSM3K7002FU

C4620

21 21

45D6
45D8

48D3

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6641

87

65

4

32 1

REFERENCE 4500~4699(CPU)

D

P1V05S

R4521

B

CAD NOTE: DP_COMPIO AND ICOMPO SIGNALS
SHOULD BE SHORTED NEAR BALLS AND ROUTED WITH

- TYPICAL IMPEDANCE < 25 MOHMS

24.9_1%_2

21

49C3

IN

49C3

IN

49C3

IN

49C3

IN

49C3

IN

P1V0S_VCCP_EDP_COMPIO

49D6
49D6
49D6
49C6

49C6
49C6
49C6
49C6

49D6
49D6
49D6
49D6

49D6
49D6
49D6
49D6

49D3
49D3
49D3
49D3
49D3
49D3
49D3
49D3

49D3
49D3
49D3
49D3
49C3
49C3
49C3
49C3

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

DMI_TX0_DN
DMI_TX1_DN
DMI_TX2_DN
DMI_TX3_DN

DMI_TX0_DP
DMI_TX1_DP
DMI_TX2_DP
DMI_TX3_DP

DMI_RX0_DN
DMI_RX1_DN
DMI_RX2_DN
DMI_RX3_DN

DMI_RX0_DP
DMI_RX1_DP
DMI_RX2_DP
DMI_RX3_DP

FDI_TX0_DN
FDI_TX1_DN
FDI_TX2_DN
FDI_TX3_DN
FDI_TX4_DN
FDI_TX5_DN
FDI_TX6_DN
FDI_TX7_DN

FDI_TX0_DP
FDI_TX1_DP
FDI_TX2_DP
FDI_TX3_DP
FDI_TX4_DP
FDI_TX5_DP
FDI_TX6_DP
FDI_TX7_DP

P1V05S

R4522

CN4500

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HDP#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

eDP Intel(R) FDI DMI

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]

PCI EXPRESS* - GRAPHICS

PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

P1V0S_VCCP_PEG_ICOMPI

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_C_RX15_DN
PEG_C_RX14_DN
PEG_C_RX13_DN
PEG_C_RX12_DN
PEG_C_RX11_DN
PEG_C_RX10_DN
PEG_C_RX9_DN
PEG_C_RX8_DN
PEG_C_RX7_DN
PEG_C_RX6_DN
PEG_C_RX5_DN
PEG_C_RX4_DN
PEG_C_RX3_DN
PEG_C_RX2_DN
PEG_C_RX1_DN
PEG_C_RX0_DN

PEG_C_RX15_DP
PEG_C_RX14_DP
PEG_C_RX13_DP
PEG_C_RX12_DP
PEG_C_RX11_DP
PEG_C_RX10_DP
PEG_C_RX9_DP
PEG_C_RX8_DP
PEG_C_RX7_DP
PEG_C_RX6_DP
PEG_C_RX5_DP
PEG_C_RX4_DP
PEG_C_RX3_DP
PEG_C_RX2_DP
PEG_C_RX1_DP
PEG_C_RX0_DP

PEG_TX15_DN
PEG_TX14_DN
PEG_TX13_DN
PEG_TX12_DN
PEG_TX11_DN
PEG_TX10_DN
PEG_TX9_DN
PEG_TX8_DN
PEG_TX7_DN
PEG_TX6_DN
PEG_TX5_DN
PEG_TX4_DN
PEG_TX3_DN
PEG_TX2_DN
PEG_TX1_DN
PEG_TX0_DN

PEG_TX15_DP
PEG_TX14_DP
PEG_TX13_DP
PEG_TX12_DP
PEG_TX11_DP
PEG_TX10_DP
PEG_TX9_DP
PEG_TX8_DP
PEG_TX7_DP
PEG_TX6_DP
PEG_TX5_DP
PEG_TX4_DP
PEG_TX3_DP
PEG_TX2_DP
PEG_TX1_DP
PEG_TX0_DP

24.9_1%_2

21

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

CAD NOTE: PEG_ICOMPI AND RCOMPO SIGNALS
SHOULD BE SHORTED AND ROUTED WITH

- MAX LENGTH = 500 MILS

- TYPICAL IMPEDANCE = 43 MOHMS

PEG_ICOMPO SIGNALS SHOULD BE ROUTED WITH

- MAX LENGTH = 500 MILS

- TYPICAL IMPEDANCE = 14.5 MOHMS

56B5
56B5
56B5
56C5
56C5
56C5
56C5
56C5
56D5
56D5
56D5
56D5
56E5
56E5
56E5
56E5

56B5
56B5
56B5
56C5
56C5
56C5
56C5
56D5
56D5
56D5
56D5
56D5
56E5
56E5
56E5
56E5

42B3
42B3
42C3
42C3
42C3
42C3
42C3
42C3
42C3
42C3
42C3
42C3
42C3
42D3
42D3
42D3

42A3
42A3
42A3
42A3
42A3
42A3
42B3
42B3
42B3
42B3
42B3
42B3
42B3
42B3
42B3
42B3

42B4

42B4

42B4

42B4

42B4

42B4

42B4

42B4

42B4

42B4

42B4

42B4

42B4

42C4

42C4

42C4

42A4

42A4

42A4 56E5

42A4 56E5

42A4 56D5

42A4 56D5

42A4 56D5

42B4 56D5

42B4 56C5

42B4 56C5

42B4

42B4 56C5

42B4 56C5

42B4 56B5

42B4 56B5

42B4

CLOSE TO CPU

PEG_TX0_DN

IN

PEG_TX1_DN

IN

PEG_TX2_DN

IN

PEG_TX3_DN

IN

PEG_TX4_DN

IN

PEG_TX5_DN

IN

PEG_TX6_DN

IN

PEG_TX7_DN

IN

PEG_TX8_DN

IN

PEG_TX9_DN

IN

PEG_TX10_DN

IN

PEG_TX11_DN

IN

PEG_TX12_DN

IN

PEG_TX13_DN

IN

PEG_TX14_DN

IN

PEG_TX15_DN

IN

PEG_TX0_DP

IN

PEG_TX1_DP

IN

PEG_TX2_DP PEG_C_TX2_DP

IN

PEG_TX3_DP PEG_C_TX3_DP

IN

PEG_TX4_DP PEG_C_TX4_DP

IN

PEG_TX5_DP PEG_C_TX5_DP

IN

PEG_TX6_DP PEG_C_TX6_DP

IN

PEG_TX7_DP PEG_C_TX7_DP

IN

PEG_TX8_DP PEG_C_TX8_DP

IN

PEG_TX9_DP PEG_C_TX9_DP

IN

PEG_TX10_DP

IN

PEG_TX11_DP PEG_C_TX11_DP

IN

PEG_TX12_DP PEG_C_TX12_DP

IN

PEG_TX13_DP PEG_C_TX13_DP

IN

PEG_TX14_DP PEG_C_TX14_DP

IN

PEG_TX15_DP

IN

C4580

C4581

C4582

C4583

C4584

C4585

C4586

C4587

C4588

C4589

C4590

C4591

C4592

C4593

C4594

C4595

C4596

C4597

C4598

C4599

C4600

C4601

C4602

C4603

C4604

C4605

C4606

C4607

C4608

C4609

C4610

C4611

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

0.22UF_6.3V_1

PEG_C_TX0_DN

PEG_C_TX1_DN

PEG_C_TX2_DN

PEG_C_TX3_DN

PEG_C_TX4_DN

PEG_C_TX5_DN

PEG_C_TX6_DN

PEG_C_TX7_DN

PEG_C_TX8_DN

PEG_C_TX9_DN

PEG_C_TX10_DN

PEG_C_TX11_DN

PEG_C_TX12_DN

PEG_C_TX13_DN

PEG_C_TX14_DN

PEG_C_TX15_DN

PEG_C_TX0_DP

PEG_C_TX1_DP

PEG_C_TX10_DP

PEG_C_TX15_DP

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

D

56E5

56E5

56E5

56D5

56D5

56D5

56D5

56D5

56C5

CC

56C5

56C5

56C5

56B5

56B5

56B5

56B5

56E5

56E5

B

56C5

56B5

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6642

87

REFERENCE 4500~4699(CPU)

38D5

D

B

BI

M_A_DQ<63..0>

38D8

OUT

38D8

OUT

38D8

OUT

38C8

OUT

38C8

OUT

38C8

OUT

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

M_A_DQ<0>
M_A_DQ<1>
M_A_DQ<2>
M_A_DQ<3>
M_A_DQ<4>
M_A_DQ<5>
M_A_DQ<6>
M_A_DQ<7>
M_A_DQ<8>
M_A_DQ<9>
M_A_DQ<10>
M_A_DQ<11>
M_A_DQ<12>
M_A_DQ<13>
M_A_DQ<14>
M_A_DQ<15>
M_A_DQ<16>
M_A_DQ<17>
M_A_DQ<18>
M_A_DQ<19>
M_A_DQ<20>
M_A_DQ<21>
M_A_DQ<22>
M_A_DQ<23>
M_A_DQ<24>
M_A_DQ<25>
M_A_DQ<26>
M_A_DQ<27>
M_A_DQ<28>
M_A_DQ<29>
M_A_DQ<30>
M_A_DQ<31>
M_A_DQ<32>
M_A_DQ<33>
M_A_DQ<34>
M_A_DQ<35>
M_A_DQ<36>
M_A_DQ<37>
M_A_DQ<38>
M_A_DQ<39>
M_A_DQ<40>
M_A_DQ<41>
M_A_DQ<42>
M_A_DQ<43>
M_A_DQ<44>
M_A_DQ<45>
M_A_DQ<46>
M_A_DQ<47>
M_A_DQ<48>
M_A_DQ<49>
M_A_DQ<50>
M_A_DQ<51>
M_A_DQ<52>
M_A_DQ<53>
M_A_DQ<54>
M_A_DQ<55>
M_A_DQ<56>
M_A_DQ<57>
M_A_DQ<58>
M_A_DQ<59>
M_A_DQ<60>
M_A_DQ<61>
M_A_DQ<62>
M_A_DQ<63>

M_A_BS0
M_A_BS1
M_A_BS2

M_A_CAS#
M_A_RAS#
M_A_WE#

SOCKET,CPU,989P,TIN,3.0MM,STR,SMD,TR

CN4500

C5

SA_DQ[0]

D5

SA_DQ[1]

D3

SA_DQ[2]

D2

SA_DQ[3]

D6

SA_DQ[4]

C6

SA_DQ[5]

C2

SA_DQ[6]

C3

SA_DQ[7]

F10

SA_DQ[8]

F8

SA_DQ[9]

G10

SA_DQ[10]

G9

SA_DQ[11]

F9

SA_DQ[12]

F7

SA_DQ[13]

G8

SA_DQ[14]

G7

SA_DQ[15]

K4

SA_DQ[16]

K5

SA_DQ[17]

K1

SA_DQ[18]

J1

SA_DQ[19]

J5

SA_DQ[20]

J4

SA_DQ[21]

J2

SA_DQ[22]

K2

SA_DQ[23]

M8

SA_DQ[24]

N10

SA_DQ[25]

N8

SA_DQ[26]

N7

SA_DQ[27]

M10

SA_DQ[28]

M9

SA_DQ[29]

N9

SA_DQ[30]

M7

SA_DQ[31]

AG6

SA_DQ[32]

AG5

SA_DQ[33]

AK6

SA_DQ[34]

AK5

SA_DQ[35]

AH5

SA_DQ[36]

AH6

SA_DQ[37]

AJ5

SA_DQ[38]

AJ6

SA_DQ[39]

AJ8

SA_DQ[40]

AK8

SA_DQ[41]

AJ9

SA_DQ[42]

AK9

SA_DQ[43]

AH8

SA_DQ[44]

AH9

SA_DQ[45]

AL9

SA_DQ[46]

AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15

AE10
AF10

SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]

V6

SA_BS[2]

AE8

SA_CAS#

AD9

SA_RAS#

AF9

SA_WE#

65

M_CLK_DDR0_DP

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

SA_CS#[0]

SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

SA_ODT[0]

SA_ODT[1]
RSVD_TP[9]

RSVD_TP[10]

DDR SYSTEM MEMORY A

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4]

SA_DQS[5]

SA_DQS[6]

SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

M_A_DQS0_DN
M_A_DQS1_DN
M_A_DQS2_DN
M_A_DQS3_DN
M_A_DQS4_DN
M_A_DQS5_DN
M_A_DQS6_DN
M_A_DQS7_DN

M_A_DQS0_DP
M_A_DQS1_DP
M_A_DQS2_DP
M_A_DQS3_DP
M_A_DQS4_DP
M_A_DQS5_DP
M_A_DQS6_DP
M_A_DQS7_DP

M_CLK_DDR0_DN

M_CLK_DDR1_DP
M_CLK_DDR1_DN

M_CS#0
M_CS#1

M_ODT0
M_ODT1

M_A_A<0>
M_A_A<1>
M_A_A<2>
M_A_A<3>
M_A_A<4>
M_A_A<5>
M_A_A<6>
M_A_A<7>
M_A_A<8>
M_A_A<9>
M_A_A<10>
M_A_A<11>
M_A_A<12>
M_A_A<13>
M_A_A<14>
M_A_A<15>

M_CKE0

M_CKE1

OUT
OUT

OUT
OUT

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15

38D8
38C8

38C8
38C8

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

M_A_A<15..0>

4

39D5

38C8

OUT

38C8

OUT

38C8

OUT

38C8

OUT

38C8

OUT

38C8

OUT

38B8
38B8
38B8
38B8
38B8
38B8
38B8
38B8

38B8
38B8
38B8
38B8
38B8
38B8
38B8
38B8

OUT

M_B_DQ<63..0>

BI

M_B_DQ<0>
M_B_DQ<1>
M_B_DQ<2>
M_B_DQ<3>
M_B_DQ<4>
M_B_DQ<5>
M_B_DQ<6>
M_B_DQ<7>
M_B_DQ<8>
M_B_DQ<9>
M_B_DQ<10>
M_B_DQ<11>
M_B_DQ<12>
M_B_DQ<13>
M_B_DQ<14>
M_B_DQ<15>
M_B_DQ<16>
M_B_DQ<17>
M_B_DQ<18>
M_B_DQ<19>
M_B_DQ<20>
M_B_DQ<21>
M_B_DQ<22>
M_B_DQ<23>
M_B_DQ<24>
M_B_DQ<25>
M_B_DQ<26>
M_B_DQ<27>
M_B_DQ<28>
M_B_DQ<29>
M_B_DQ<30>
M_B_DQ<31>
M_B_DQ<32>
M_B_DQ<33>
M_B_DQ<34>
M_B_DQ<35>
M_B_DQ<36>
M_B_DQ<37>
M_B_DQ<38>
M_B_DQ<39>
M_B_DQ<40>
M_B_DQ<41>
M_B_DQ<42>
M_B_DQ<43>
M_B_DQ<44>
M_B_DQ<45>
M_B_DQ<46>
M_B_DQ<47>
M_B_DQ<48>
M_B_DQ<49>
M_B_DQ<50>
M_B_DQ<51>
M_B_DQ<52>
M_B_DQ<53>
M_B_DQ<54>
M_B_DQ<55>
M_B_DQ<56>
M_B_DQ<57>
M_B_DQ<58>
M_B_DQ<59>
M_B_DQ<60>
M_B_DQ<61>
M_B_DQ<62>
M_B_DQ<63>

C9
A7

D10

C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8

K10

K9
J9

J10

K8
K7
M5
N4
N2
N1
M4
N5
M2

M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9

AJ11

AT8
AT9

AH11

AR8

AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA9
AA7

R6

AA10

AB8
AB9

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

OUT
OUT
OUT

OUT
OUT
OUT

61
62
63

M_B_BS0
M_B_BS1
M_B_BS2

M_B_CAS#
M_B_RAS#
M_B_WE#

38D8

39D8
39D8
39C8

39C8
39C8
39C8

32 1

CN4500

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

SB_CS#[0]

SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

SB_ODT[0]

SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]

DDR SYSTEM MEMORY B

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AE2
AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

M_CLK_DDR2_DP
M_CLK_DDR2_DN

M_CLK_DDR3_DP
M_CLK_DDR3_DN

M_CS#2
M_CS#3

M_ODT2
M_ODT3

M_B_DQS0_DN
M_B_DQS1_DN
M_B_DQS2_DN
M_B_DQS3_DN
M_B_DQS4_DN
M_B_DQS5_DN
M_B_DQS6_DN
M_B_DQS7_DN

M_B_DQS0_DP
M_B_DQS1_DP
M_B_DQS2_DP
M_B_DQS3_DP
M_B_DQS4_DP
M_B_DQS5_DP
M_B_DQS6_DP
M_B_DQS7_DP

M_B_A<0>
M_B_A<1>
M_B_A<2>
M_B_A<3>
M_B_A<4>
M_B_A<5>
M_B_A<6>
M_B_A<7>
M_B_A<8>
M_B_A<9>
M_B_A<10>
M_B_A<11>
M_B_A<12>
M_B_A<13>
M_B_A<14>
M_B_A<15>

M_CKE2

M_CKE3

OUT
OUT

OUT
OUT

10
11
12
13
14
15

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

0
1
2
3
4
5
6
7
8
9

OUT
OUT
OUT

OUT
OUT
OUT

39C8
39C8

39C8
39C8

39B8
39B8
39B8
39B8
39B8
39B8
39B8
39B8

39B8
39B8
39B8
39B8
39B8
39B8
39B8
39B8

M_B_A<15..0>

39C8
39C8
39C8

39C8
39C8
39C8

OUT

D

CC

B

AA

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

REV

of

X011310xxxxx-0-0

6643

1

87

REFERENCE 4500~4699(CPU)

D

22UF_6.3V_5

22UF_6.3V_5 22UF_6.3V_5

B

8

22UF_6.3V_5

21

C4514 C4515 C4516 C4517

22UF_6.3V_5

21

C4518 C4519 C4520 C4521

22UF_6.3V_5 22UF_6.3V_5

21

C4522 C4523 C4524 C4525

22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_522UF_6.3V_5

21

21

22UF_6.3V_5

21

21

21

22UF_6.3V_522UF_6.3V_522UF_6.3V_5

21

22UF_6.3V_5

21

21

21

76

65

C4513C4512C4511C4510

21

21

21

21

PVCORE

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26

CN4500

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

4

POWER

CORE SUPPLY

PEG AND DDR

VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

SVID SIGNAL TO VR

AJ29

SVIDSENSE LINES

VIDALERT#

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

VIDSCLK
VIDSOUT

54

H_CPU_SVIDALRT# VR_SVID_ALERT#

AJ30

H_CPU_SVIDCLK

AJ28

H_CPU_SVIDDAT

PVCORE

AJ35
AJ34

B10
A10

C4531

21

R4532

100_1%_2

VCCSENSE
VSSSENSE

R4533

100_1%_2

2121

P1V05S

R4534

10_1%_2

R4535

10_1%_2

2121

32 1

P1V05S

C4535

C4536

C4537

21

21

22UF_6.3V_5

22UF_6.3V_5

C4542

21

22UF_6.3V_5

C4541

21

22UF_6.3V_5

C4540

21

22UF_6.3V_5

C4532

21

22UF_6.3V_5

C4533

C4534

21

22UF_6.3V_5

21

21

22UF_6.3V_5

22UF_6.3V_5

P1V05S

PLACE CLOSE TO CPU

R4527R4528

43_5%_2

0_5%_2
0_5%_2

75_5%_2

21

9B7
9B7

DATE

21-OCT-2002XXX

23

VR_SVID_CLK
VR_SVID_DATA

11C7

OUT

11A3 11C7

OUT

11A3 11C7

OUT

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

of

6644

1

CHANGE by

130_1%_2

21

R4529
R4530
R4531

11D6

OUT

11D6

OUT

VCC_SENSE_VCCIO
VSS_SENSE_VCCIO

21
21
21

OUT
OUT

22UF_6.3V_5

REV

X011310xxxxx-0-0

D

CC

B

AA

87

PROCESSOR DRIVEN VREF PATH WAS STUFFED BY DEFAULT:
ROUTE WITH MIN. TRACE WIDTH OF 10 MILS

P0V75M_VREF

65

P0V75M_VREF

4

32 1

P0V75M_VREF_HP0V75M_VREF

G

1

SENSE

DDR3 -1.5V RAILS

MISC VREFSA RAIL

3

DS

Q4502

AM2302N

VSSAXG_SENSE

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

VCCIO_SEL

PVAXG

R4539

10_1%_2

GFX_VCC_SENSE

AK35
AK34

GFX_VSS_SENSE

2121

OUT
OUT

R4540

10_1%_2

P0V75M_VREF_H

SM_VREF

AL1

CPUDDR_WR_VREF1

B4

CPUDDR_WR_VREF2

D1

45D8

IN

45D6

IN

NOTE : DDR_WR_VREF SHOULD HAVE 20/20 MIL WHEREVER POSSIBLE

5A

AF7

VDDQ1

AF4

VDDQ2

AF1

VDDQ3

AC7

VDDQ4

AC4

VDDQ5

AC1

VDDQ6

Y7

VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

VDDQ7

Y4

VDDQ8

Y1

VDDQ9

U7
U4
U1
P7
P4
P1

M27
M26
L26
J26
J25
J24
H26
H25

H23

C22
C24
A19

10UF_6.3V_3

PVSA

R4544

100_5%_2

21

R4555

10K_5%_2_DY

21

10UF_6.3V_3

21

21

10UF_6.3V_3

21

21

CHANGE by

10K_5%_210K_5%_2

21

14B814D221D649B3
14A6

IN

14B4

11B8
11B8

10UF_6.3V_3

21

10UF_6.3V_3

21

VCCSA_SENSE

VCCSA_VID0
VCCSA_VID1
VCCIO_SEL

R4547R4556

SLP_S3#_3R

21

C4576C4575C4574

10UF_6.3V_3

21

OUT

OUT
OUT
OUT

R4547

SNB:0 OHM
IVB:10K OHM

R4538

0_5%_2

21

PVSA

+

C4577

100UF_6.3V

21

10C4

10B4
10B4
9C7

DATE

3

21

21-OCT-2002XXX

23

2

DS

G

Q4500

1

AM2302N

C4578

21

470PF_50V_2

C4572C4571C4570C4569C4568C4567

10UF_6.3V_310UF_6.3V_310UF_6.3V_3

21

R4541

100K_5%_2

21

P1V5S

+

C4573

220UF_2.5V

21

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

D

CC

B

AA

REV

of

X011310xxxxx-0-0

6645

1

CPUDDR_WR_VREF2

22UF_6.3V_5

21

45C3

IN

41A845D8

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17

DRAMRST_CNTRL

IN

CN4500

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

VAXG1 VAXG_SENSE
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

IN

IN

CPUDDR_WR_VREF1

DRAMRST_CNTRL

45C3

D

41A845D6

2

G

1

3

DS

Q4501

AM2302N

PVAXG

C4651 C4545 C4550C4546 C4547 C4548 C4549

21

22UF_6.3V_522UF_6.3V_5

21

21

21

21

22UF_6.3V_522UF_6.3V_522UF_6.3V_522UF_6.3V_5

21

B

2

POWER

LINES

GRAPHICS

P1V8S

8

L4500

MPZ1608S221AT

21

C4562 CC4563 C4564

10UF_6.3V_3

21

1UF_6.3V_2

21

76

1.2A

1UF_6.3V_2

21

P1V8S_VCCPLL

C4565

22UF_6.3V_5

21

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

1.8V RAIL

54

87

65

4

32 1

CN4500 CN4500

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13 AJ2

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

D

B

AR22
AR19
AR16
AR13
AR10

AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10

AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AM29
AM25
AM22
AM19
AM16
AM13
AM10

AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AJ25

VSS14
VSS15
VSS16
VSS17
VSS18
VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42

AN7

VSS43

AN4

VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51

AM7

VSS52

AM4

VSS53

AM3

VSS54

AM2

VSS55

AM1

VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77

AK7

VSS78

AK4

VSS79
VSS80

VSS

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22

VSS81

AJ19

VSS82

AJ16

VSS83

AJ13

VSS84

AJ10

VSS85

AJ7

VSS86

AJ4

VSS87

AJ3

VSS88
VSS89

AJ1

VSS90

AH35

VSS91

AH34

VSS92

AH32

VSS93

AH30

VSS94

AH29

VSS95

AH28

VSS96

AH25

VSS98

AH22

VSS99

AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

PEG STATIC LAN REVERSAL

LOW EDP ENABLE

PCIE PORT BIFURCATION

PEG DEFER TRAINING

46D4

46D4

46D4

VSS

IN

IN

IN

IN

IN

CFG<2>

CFG<4>

CFG<5>

CFG<6>

CFG<7>

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

1K_1%_2

1K_1%_2_DY

R4552

1K_1%_2_DY

1K_1%_2_DY

1K_1%_2_DY

STRAP PIN

8

76

54

R4550

R4551

R4553

R4554

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

46A6

46A6
46A6
46A6
46A6

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

CFG<0>
CFG<1>
CFG<2>
CFG<3>
CFG<4>
CFG<5>
CFG<6>
CFG<7>
CFG<8>
CFG<9>
CFG<10>
CFG<11>
CFG<12>
CFG<13>
CFG<14>
CFG<15>
CFG<16>
CFG<17>

AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29

AJ31
AH31
AJ33
AH33

AJ26

PEG STATIC LANE REVERSAL

1 : (DEFAULT) NORMAL OPERATION

CFG(2)

0 : LANE REVERSED

21

21

21

21

21

LOW EDP ENABLE

1 : (DEFAULT) EDP DISABLED

CFG(4)

0 : EDP ENABLED

PEG DEFER TRAINING

CFG(7)

1 : (DEFAULT) PEG TRAIN IMMEDIATELY FOLLOWING XXRESETB DE ASSERTION
0 : PEG WAIT FOR BIOS FOR TRAINING

PCIE PORT BIFURCATION STRAPS

11 : (DEFAULT) X16 - DEVICE 1 FUNCTION AND 2 DISABLED
10 : X8, X8 - DEVICE 1 FUNCTION 1 ENABLE ; FUNCTION 2 DISABLED
01 : RESERVED - (DEVICE 1 FUNCTION 1 DISABLED ; FUNCTION 2 ENABLED)

CFG[6:5]

00 : X8,X4,X4 - DEVICE 1 FUNCTION 1 AND 2 ENABLED

CN4500

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

CHANGE by

VCC_DIE_SENSE
VSS_DIE_SENSE

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

RESERVED

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9

RSVD_NCTF10

BCLK_ITP

BCLK_ITP#

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

RSVD28
RSVD29
RSVD30
RSVD31
RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD51
RSVD52

L7
AG7
AE7
AK2
W8

AT26
AM33
AJ27

AH27
AH26

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

REMOVE

AN35

CLK_XDP_CLKGEN_DP

AM35

CLK_XDP_CLKGEN_DN

AT2
AT1
AR1

B1

KEY

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6646

87

REFERENCE 4700~4949(PCH)

P3V3AL

21

A2A1

P3V3_RTC

3

C

D4700

24B1

OUT

OUT

BAT54C_30V_0.2A

CN4700

-+

LOTES_AAA_BAT_059_P03_2P

2121

PCSPKR_PCH_3

OUT

FLASH_OVERRIDE

HDA_3S_SYNC_R

8

D

R4700

1K_1%_2

INTVRMEN-INTEGRATE (SUS 1.05V VRM ENABLE
1:ENABLE INTERNAL VRS
0:ENABLE EXTERNAL VRS

PCSPKR_PCH_3(NO REBOOT)
1 : NO REBOOT ENABLED
0 : (DEFAULT) NO REBOOT DISABLED

FLASH OVERRIDE
FLASH DESCRIPTOR SECURITY OVERIDE

1:ENABLE
0:DISABLE : (DEFAULT INTERNAL PULL-DOWN)

B

21D6
47B7

HDA_3S_SYNC_R(PLL ODVR VOLTAGE)
1 : VCC VRM = 1.6V

0 : VCC VRM = 1.8V(DEFAULT)

R4720

10K_5%_2_DY

1K_5%_2

R4714

R4706

0_5%_2_DY

21

21

P3V3_RTC

R4703

20K_1%_2

21

R4704

20K_1%_2

C4700

P3V3_RTC

21

24A2

24B2

24B2

24A2

R4707

330K_5%_3

21

HDA_3S_BITCLK

BI

HDA_3S_SYNC

BI

HDA_3S_RST#

OUT

HDA_3S_SDIN0

IN

R4705

21

21

1UF_6.3V_2

33_5%_2

R4711

1M_5%_2

33_5%_2

21

33_5%_2

STRAP

47B8
21D6

P3V3A

76

24A2

IN

OUT

R4718

RSC_0402_DY

21D6

21D6 21C8

21C7 21C6

21C8 21C6

FLASH_OVERRIDE

HDA_3S_SDOUT

21

OUT

47D3

OUT

47D3

OUT

47D3

OUT

21C7

OUT
OUT
OUT

OUT
OUT

21E2

TP30

TP30

TP30

TP30

EC_SPI_CLK

EC_SPI_CS0#

PCH_SPI_CS1#

EC_SPI_SI

EC_SPI_SO

65

RTCX2

4

32

1

U4700

RTCX1

RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

STRAPPING

HDA_BCLK

HDA_SYNC

STRAPPING

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

STRAPPING

HDA_DOCK_EN#/GPIO33

HDA_DOCK_RST#/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

ITL_PANTHERPOINT_FCBGA_989P

C4701

1UF_6.3V_2

21

C4702

21

1UF_6.3V_2

R4709

21

R4712

21

R4715

1K_5%_2

R4716

33_5%_2

IN

TP4720

1

1

TP4721

1

TP4722

1

TP4723

RSC_0402_DY

21

HDA_3S_BITCLK_R

HDA_3S_SYNC_R

HDA_3S_RST#_R

21

21

EC_SMI

PCH_TCK

PCH_TMS

PCH_TDI

PCH_TDO

21

R4734

R4708

10M_5%_2

21

A20

C20

D20

G22

K22

C17

N34

L34

T10

K34

E34

G34

C34

A34

A36

C36

N32

J3

H7

K5

H1

T3

Y14

T1

V4

U3

RTCX1

54

X4700

32.768KHZ

JTAG

C4703

18PF_50V_2

18PF_50V_2

RTC

IHDA

SPI

C4704

21

21

LPC

SATA

STRAPPING

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ1#/GPIO23

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA 6G

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

LDRQ0#

SERIRQ

4

32 1

P3V3A

R4736

21

0_5%_2_DY

P1V05S

R4737

21

RSC_0402_DY

R4742R4740R4738

RSC_0402_DY

21

R4743R4741R4739

RSC_0402_DY

21

D

CC

B

AA

C38

LPC_3S_AD<0>

A38

LPC_3S_AD<1>

B37

LPC_3S_AD<2>

C37

LPC_3S_AD<3>

D36

LPC_3S_FRAME#

E36
K36

V5

PCI_3S_SERIRQ

AM3

SATA_MINICARD_RX_DN

AM1

SATA_MINICARD_RX_DP

AP7

SATA_MINICARD_TX_DN

AP5

SATA_MINICARD_TX_DP

AM10

SATA_HDD_RX_DN

AM8

SATA_HDD_RX_DP

AP11

SATA_HDD_TX_DN

AP10

SATA_HDD_TX_DP

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3

SATA_ODD_RX_DN

Y1

SATA_ODD_RX_DP

AB3

SATA_ODD_TX_DN

AB1

SATA_ODD_TX_DP

Y11

Y10

P1V05S_SATARCOMPO

AB12

AB13

P1V05S_SATA3RCOMPO

R4749

AH1

750_1%_2

P3

V14

P1

47A6
47B6
47A6

OUT
OUT

OUT
OUT

IN
IN

IN
IN

IN

IN
OUT
OUT

29A7
29A7

37.4_1%_2

R4748

49.9_1%_2

29D6
29D6
29D6
29D6

29A7
29A7

27C321E3

R4747

27C321E3
27C321E3
27C321E3
27C321E3

28C7
28C7

28C7
28C7

21

21

BI
BI
BI
BI

OUT

21

PCH_TDI

OUT

PCH_TMS

OUT

PCH_TDO

OUT

P3V3S

R4744

10K_5%_2

21

P1V05S

P1V05S

BI

21

RSC_0402_DY

21

RSC_0402_DY

21

27B721E3

R4750

10K_5%_210K_5%_2

21

RSC_0402_DY

21

RSC_0402_DY

21

P3V3S

R4752R4751

10K_5%_2

21

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CHANGE by

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6647

REFERENCE 4700~4949(PCH)

D

48D7
22C5
48C7

48D7
27C7
48B7

48B3

48B3

48B3

48B3

48A3

48B3

48B3

B

38C8
39C8

48D3

48D3

38C8
39C8

87

22B1
22B1
22C2
22C2

27B7
27B7
27B7
27B7

31C7
31C7
31C7
31C7

CLKREQ_LAN#

OUT

CLKREQ_WLAN#

OUT

CLOCK TERMINATION FOR FICM
STUFF FOR INTEGRATED CLK

CLKIN_DMI_PCH_DN

IN

CLKIN_DMI_PCH_DP

IN

CLKIN_BUF_DOT96_DN

IN

CLKIN_BUF_DOT96_DP

IN

CLKIN_PCH14

IN

CLKIN_SATA1_DP

IN

CLKIN_SATA1_DN

IN

PCH_3S_SMCLK

BI

PCH_3A_SMCLK

BI

PCH_3A_SMDATA

BI

PCH_3S_SMDATA

BI

8

PCIE_LAN_RX_DN

IN

PCIE_LAN_RX_DP

IN

PCIE_LAN_TX_DN

OUT

PCIE_LAN_TX_DP

OUT
IN

IN
OUT
OUT

IN
IN
OUT
OUT

10K_5%_2_DY

R4784 R4785

2.2K_5%_2

PCIE_WLAN_RX_DN
PCIE_WLAN_RX_DP
PCIE_WLAN_TX_DN
PCIE_WLAN_TX_DP

PCIE_USB3_RX_DN
PCIE_USB3_RX_DP
PCIE_USB3_TX_DN
PCIE_USB3_TX_DP

R4775

10K_5%_2_DY

R4776

21

P3V3S

2.2K_5%_2

R4786

2.2K_5%_2

21

21

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

48D8

21

22C5
48C7

48D8
27C7
48B7

R4777

21

10K_5%_2

R4778

21

10K_5%_2

R4779

21

10K_5%_2

R4780

21

10K_5%_2

R4781

21

10K_5%_2

R4782

21

10K_5%_2

R4783

21

10K_5%_2

P3V3A

R4787

2.2K_5%_2

21

21

SSM3K7002FU

76

C4724

C4726

C4793

OUT

OUT

2

Q4700

DS

SSM3K7002FU

3

3

Q4701

DS

2

21

C4725

0.1UF_16V_2

21

C4727

0.1UF_16V_2

21

C4794

0.1UF_16V_2

CLKREQ_LAN#

CLKREQ_WLAN#

22C2
22C2

48D8
22C5
48D7

27C7
27C7

48D8
27C7
48D7

31C7
31C7

31B8
31C7

P5V0S

1

G

1

G

OUT
OUT

IN

OUT
OUT

IN

OUT
OUT

IN

P3V3A

21

21

21

10K_5%_2_DY

10K_5%_2_DY

10K_5%_2_DY

10K_5%_2_DY

10K_5%_2_DY

10K_5%_2_DY

PCIE_LAN_TX_C_DN
PCIE_LAN_TX_C_DP

PCIE_WLAN_TX_C_DN
PCIE_WLAN_TX_C_DP

PCIE_USB3_TX_C_DN
PCIE_USB3_TX_C_DP

R4773

21

10K_5%_2

R4772

21

10K_5%_2

CLK_PCIE_LAN_DN
CLK_PCIE_LAN_DP

CLKREQ_LAN#

CLK_PCIE_WLAN_DN
CLK_PCIE_WLAN_DP

CLKREQ_WLAN#

CLK_PCIE_USB3_DN
CLK_PCIE_USB3_DP

CLKREQ_USB3#

TP4703
TP4704

R4789

21

R4790

21

R4791

21

R4792

21

R4793

21

R4794

21

65

U4700

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34
BB34

BG37
BH37
AY36
BB36

BJ38
BG38
AU36
AV36

BG40
BJ40
AY40
BB40

BE38
BC38
AW38
AY38

AB49
AB47

AA48
AA47

AB42
AB40

AK14
AK13

Y40
Y39

J2

M1

V10

Y37
Y36

A8

Y43
Y45

L12

V45
V46

L14

E6

V40
V42

T13

V38
V37

K12

PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6
PERP6
PETN6
PETP6

PERN7
PERP7
PETN7
PETP7

PERN8
PERP8
PETN8
PETP8

CLKOUT_PCIE0N
CLKOUT_PCIE0P

PCIECLKRQ0#/GPIO73

CLKOUT_PCIE1N
CLKOUT_PCIE1P

PCIECLKRQ1#/GPIO18

CLKOUT_PCIE2N
CLKOUT_PCIE2P

PCIECLKRQ2#/GPIO20

CLKOUT_PCIE3N
CLKOUT_PCIE3P

PCIECLKRQ3#/GPIO25

CLKOUT_PCIE4N
CLKOUT_PCIE4P

PCIECLKRQ4#/GPIO26

CLKOUT_PCIE5N
CLKOUT_PCIE5P

PCIECLKRQ5#/GPIO44

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

PEG_B_CLKRQ#/GPIO56

CLKOUT_PCIE6N
CLKOUT_PCIE6P

PCIECLKRQ6#/GPIO45

CLKOUT_PCIE7N
CLKOUT_PCIE7P

PCIECLKRQ7#/GPIO46

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

ITL_PANTHERPOINT_FCBGA_989P

PCI-E*

Controller

CLOCKS

P3V3A

P3V3S

TP24
TP24

1
1

54

SMBUS

Link

FLEX CLOCKS

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SML1ALERT#/PCHHOT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

4

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

E12

H14

PCH_3A_SMCLK

C9

PCH_3A_SMDATA

A12

DRAMRST_CNTRL_PCH

C8

PCH_3A_ALERT_CLK

G12

PCH_3A_ALERT_DAT

C13

E14

M16

M7

T11

P10

48C3

OUT

56E4

M10

CLKREQ_GPU#

AB37

CLK_PEG_PCH_DN

AB38

CLK_PEG_PCH_DP

AV22

CLK_DMI_PCH_DN

AU22

CLK_DMI_PCH_DP

AM12
AM13

BF18

CLKIN_DMI_PCH_DN

BE18

CLKIN_DMI_PCH_DP

BJ30
BG30

G24

CLKIN_BUF_DOT96_DN

E24

CLKIN_BUF_DOT96_DP

AK7

CLKIN_SATA1_DN

AK5

CLKIN_SATA1_DP

CLKIN_PCH14

K45

H45

CLKIN_PCI_FB

V47
V49

Y47

K43

F47

H47

K49

32 1

SMB_ALERT#

OUT

48B2

P3V3A

R4795

SML1ALERT#

SML1_CLK

SML1_DATA

CLKREQ_GPU#

XTAL25_IN
XTAL25_OUT

R4802

90.9_1%_2

21

10K_5%_2

R4837

10K_5%_2

21

10K_5%_2

21

OUT
OUT
OUT

R4753

OUT
OUT

BI
BI

IN

OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN
IN

IN
IN

IN
IN

IN

IN

48A8

48A8

41A8

27B3 48D2

27B3 48D2

48D2

48D2

48C2

21

48C3
56E4

56E4
56E4

41D2
41D2

48C8
48C8

48C8
48C8

48B8
48B8

48B8

51A7

48B1
48C1

P3V3A

P1V05S

48D3

48D3
27B3

48D3
27B3

48D3

37C6
21D2
21D3

48D3

21D3
21D2
37C3

18PF_50V_2

IN

IN

IN

BI

BI

BI

BI

C4728

48D3

SML1ALERT#

PCH_3A_ALERT_CLK

PCH_3A_ALERT_DAT

SML1_CLK

EC_SMB3_CLK

SML1_DATA

EC_SMB3_DATA

X4701

25MHZ

21

SMB_ALERT#

IN

21

R4796

10K_5%_2

R4797

2.2K_5%_2

R4798

2.2K_5%_2

R4799

2.2K_5%_2

R4800

2.2K_5%_2

Q4702

G

DS

SSM3K7002FU_DY

3

2

Q4703

G

DS

SSM3K7002FU_DY

32

XTAL25_OUT

R4801

1M_5%_2

2121

XTAL25_IN

C4729

18PF_50V_2

B500

PASSWORD_0805

P3V3A

1

1

OUT

OUT

21

CLOSE TO PCH

TP24

1

TP4700

TP24

1

TP4701

TP24

1

TP4702

CHANGE by

DATE

21-OCT-2002XXX

23

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

of

6648

1

P3V3A

21

21

21

21

21

D

CC

48A3

48A3

B

AA

REV

X011310xxxxx-0-0

87

65

4

32 1

U4700

IN
IN
IN
IN

IN
IN
IN
IN

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

R4814

750_1%_2

R4816

ACPRESENT

PM_RI#

PCH_PWROK

R4823

10K_5%_2

DMI_RX0_DN
DMI_RX1_DN
DMI_RX2_DN
DMI_RX3_DN

DMI_RX0_DP
DMI_RX1_DP
DMI_RX2_DP
DMI_RX3_DP

DMI_TX0_DN
DMI_TX1_DN
DMI_TX2_DN
DMI_TX3_DN

DMI_TX0_DP
DMI_TX1_DP
DMI_TX2_DP
DMI_TX3_DP

21

21

21

42D7

D

P1V05S

R4812

49.9_1%_2

21

42D7
42D7
42D7

42D7
42D7
42C7
42C7

42D7
42D7
42D7

42D7
42D7
42D7
42D7

P3V3S

R4815

10K_5%_2

21D6

NC

10K_5%_2_DY

13

BAT54_30V_0.2A

R4822

21

40B4
11A4
11C7

21B6
49A6

P3V3A

41C7

49C2
21D1
21D3

R4820

21E6
49A5

21

2

D4707

NC

21

SYS_RESET#

41C1

IN

B

2

21D6

EC_PWRSW#

IN

D4706

BAT54_30V_0.2A

LOW_BAT#_3

21D6

IN

P3V3A

8.2K_5%_2

8

76

13

IN

IN

IN

OUT

IN

OUT

SUSACK#

PCH_PWROK

PM_DRAM_PWRGD

RSMRST#

SUS_PWR_ACK

21D6
49A5

49A5

21B6

IN

49B7

0_5%_2_DY

IN

IN

BC24
BE20
BG18
BG20

BE24
BC20
BJ18
BJ20

AW24
AW20
BB18
AV18

AY24
AY20
AY18
AU18

BJ24

BG25

BH21

49A6 21D6

49B7

31C6 22B5
49B3

C12

P12

L22

L10

B13

C21

K16

E20

H20

E10

A10

IN

21E6

IN

49A6

IN
IN

27C7

21E349B3

IN

DPWROK

WAKE#

SLP_A#

10K_5%_2

10K_5%_2

10K_5%_2

10K_5%_2

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9K3

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

P3V3A

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

SUSACK#

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SUSPWRDNACK/GPIO30

PWRBTN#

INT. PU 20K

ACPRESENT/GPIO31

INT. PD 20K

INT. PU 20K

BATLOW#/GPIO72

RI#

ITL_PANTHERPOINT_FCBGA_989P

ACPRESENT

SUS_PWR_ACK

PM_RI#

PCIE_WAKE#

DMI

FDI

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

System Power Management

SLP_LAN#/GPIO29

R4824

R4825

R4826

R4827

21

21

21

21

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

DSWVRMEN

STRAPPING

SLP_S4#

SLP_S3#

SLP_SUS#

PMSYNCH

P3V3S

PCI_3S_CLKRUN#

R4828

21

8.2K_5%_2

54

FDI_TX0_DN
FDI_TX1_DN
FDI_TX2_DN
FDI_TX3_DN
FDI_TX4_DN
FDI_TX5_DN
FDI_TX6_DN
FDI_TX7_DN

FDI_TX0_DP
FDI_TX1_DP
FDI_TX2_DP
FDI_TX3_DP
FDI_TX4_DP
FDI_TX5_DP
FDI_TX6_DP
FDI_TX7_DP

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

PCIE_WAKE#

PCI_3S_CLKRUN#PVCORE_PG

EC_32KHZ

SLP_S5#_3R

SLP_S3#_3R

SLP_SUS#

H_PM_SYNC

R4831

0_5%_2

CHANGE by

IN
IN
IN
IN
IN
IN
IN
IN

IN
IN
IN
IN
IN
IN
IN
IN

OUT
OUT
OUT
OUT
OUT

RSMRST#

21

IN

IN

OUT

OUT

OUT

OUT

BI

DSWVRMEN - DEEP S4/S5 WELL ON-DIE VOLTAGE REGULATOR ENABLE
HIGH-ENABLED(DEFAULT)

LOW-DISABLED

42C7
42C7
42C7
42C7
42C7
42C7
42C7
42C7

42C7
42C742D7
42C7
42C7
42C7
42C7
42C7
42B7

42B7

42B7

42B7

42B7

42B7

21D1 49B7

IN

22B5 27C7 31C6 49A5

21E3 49A5

21B6

14D2 21D3

14A6 14B4 14B8
14D2 21D6 45D3

21D3

41C5

STRAPPING

21D3

1

SSM3K7002FU_DY

Q4713

G

P3V3_LDO

R4883

10K_5%_2_DY

212

SLP_S5_3R

3

DS

P3V3_RTC

R4829

330K_5%_2

21

R4830

330K_5%_2_DY

21

INVENTEC

TITLE

SIZE

DATE

21-OCT-2002XXX

23

A3

P3V3A

R4832

1K_5%_2_DY

21

OUT

Q4714

1

G

SSM3K7002FU

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

CS

SHEET

P3V3_LDO

10K_5%_2

SLP_S3_3R

32 1

DS

2

of

R4834

1

D

CC

B

OUT

AA

REV

X011310xxxxx-0-0

6649

87

REFERENCE 4700~4949(PCH)

65

4

32 1

D

PCH_LVDS_DDCDATA - LVDS DETECT

HIGH-LVDS ENABLED
LOW-LVDS DISABLED (DEFAULT)

B

P3V3S

2.2K_5%_22.2K_5%_2

21

21

R4854 R4855

100K_5%_2

21

R4858

OUT
OUT

OUT
OUT

OUT

LCM_BKLTEN
PCH_LCM_VDDEN

INV_PWM_3

PCH_LVDS_DDCCLK
PCH_LVDS_DDCDATA

R4857R4856

21E6
34D6

21B6

21D1

34B5

34C3
34C3

2.37K_1%_2

34B3

34B3

34C3
34C3
34C3

34C3
34C3
34C3

35D8

OUT

35D8

OUT

35D8

OUT

R4859

21

150_1%_2

R4860

21

150_1%_2

R4861

21

OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

CRTB
CRTG
CRTR

35A4
35A4

35A4
35A4

PCH_LVDS_TXCL_DN
PCH_LVDS_TXCL_DP

PCH_LVDS_TXDL0_DN
PCH_LVDS_TXDL1_DN
PCH_LVDS_TXDL2_DN

PCH_LVDS_TXDL0_DP
PCH_LVDS_TXDL1_DP
PCH_LVDS_TXDL2_DP

OUT
OUT

OUT
OUT

150_1%_2

1K_1%_2

R4862

100K_5%_2

21

21

CRT_DDCCLK
CRT_DDCDATA

CRT_HSYNC
CRT_VSYNC

21

AF37
AF36

AE48
AE47

AK39
AK40

AN48
AM47
AK47
AJ48

AN47
AM49
AK49
AJ47

AF40
AF39

AH45
AH47
AF49
AF45

AH43
AH49
AF47
AF43

J47
M45

P45

T40
K47

T45
P39

N48
P49
T49

T39
M40

M47
M49

T43
T42

U4700

L_BKLTEN
L_VDD_EN

L_BKLTCTL

L_DDC_CLK

L_DDC_DATA

L_CTRL_CLK

L_CTRL_DATA

WHEN ¡¥1¡¦- LVDS IS DETECTED

LVD_IBG
LVD_VBG

LVD_VREFH
LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK

CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

ITL_PANTHERPOINT_FCBGA_989P

LVDS

CRT

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_INTN
SDVO_INTP

SDVO_CTRLCLK
SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_CTRLCLK
DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N

Digital Display Interface

DDPC_2P
DDPC_3N
DDPC_3P

DDPD_CTRLCLK
DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

HDMI_TX2_DN
HDMI_TX2_DP
HDMI_TX1_DN
HDMI_TX1_DP
HDMI_TX0_DN
HDMI_TX0_DP
HDMI_TXC_DN
HDMI_TXC_DP

P3V3S

R4863

21

2.2K_5%_2

C4744

C4746

C4748

C4750

R4864

21

2.2K_5%_2

HPDET

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

HDMI_DDCCLK
HDMI_DDCDATA

IN

C4745

C4747

C4749

C4751

36C8

BI

36C8

BI

36A5

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

HDMI_TX2_C_DN
HDMI_TX2_C_DP
HDMI_TX1_C_DN
HDMI_TX1_C_DP
HDMI_TX0_C_DN
HDMI_TX0_C_DP
HDMI_TXC_C_DN
HDMI_TXC_C_DP

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

36A7
36A7
36A7
36B7
36A7
36B7
36B7 36C5

D

CC

36D536A7
36D5
36D5
36D5

B

36D5
36D5
36C5

AA

CLOSE TO PCH

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6650

REFERENCE 4700~4949(PCH)

D

P3V3S

R4874

R4875

R4876

R4877

R4878

R4880

R4881

R4882

R2

R4956

R4879

B

27C7

87

BBS_BIT1

0
10

GPIO19

BBS_BIT0

1

BOOT BIOS

DESTINATION
RESERVED(NAND)

------

GPIO51

1 1 SPI (DEFAULT)

31C641C7
36A3

BUF_PLT_RST#

R4888

LPC

PCI_3S_INTA#

PCI_3S_INTB#

PCI_3S_INTC#

PCI_3S_INTD#

RUNSCI0#_3

PCI_3S_REQ1#

PCI_3S_REQ2#

PCI_3S_REQ3#

SATA_ODD_DA#

PCI_3S_PIRQG#

PCI_3S_PIRQH#

BI

21

TC7SZ08FU

BI
BI
BI
BI

IN

IN
IN
IN

IN
IN
IN

LOW=A16 SWAP OVERRIDE
STP_A16OVR
TOP-BLOCK SWAP OVERRIDE

HIGH=DEFAULT

PLT_RST#

P3V3A

5

U4705

+-

4

1

2

3

76

00

21

8.2K_5%_2

21

8.2K_5%_2

21

8.2K_5%_2

21

8.2K_5%_2

21

8.2K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21E327C328C3

BI

56F5

100K_5%_2

8

51B6

51B6

51B6

51B6

21E3
52D6

51B6

51B6

51B6

51B6

29A5

51B6

51B6

BBS STRAPING

BBS_BIT1

21

R4885 R4886

1K_5%_2_DY

21E3

OUT

48A3

OUT

27C7

OUT

65

ROUTE WITH 90 OHMS IMPEDANCE
TOTAL LENGTH NO LONGER THAN 11 INCHES

32D7
33B5

32D7
33B5

32D7
33B5

32D7
33B5

STP_A16OVR

21

1K_5%_2_DY

P3V3A

R4887

10K_5%_2_DY

CLK_KBPCI
CLKIN_PCI_FB

CLK_PCI_DEBUG

R4889
R4890

R4891

BI
BI

BI
BI

BI
BI

BI
BI

51D7
51C7
51C7
51C7

51C7
51C7
51C7

31C7
31C6

29A5
51C7

51C7

51B7

21

21
21

21

USB3_PCH_RX1_DN
USB3_PCH_RX2_DN

USB3_PCH_RX1_DP
USB3_PCH_RX2_DP

USB3_PCH_TX1_DN
USB3_PCH_TX2_DN

USB3_PCH_TX1_DP
USB3_PCH_TX2_DP

PCI_3S_INTA#

BI

PCI_3S_INTB#

BI

PCI_3S_INTC#

BI

PCI_3S_INTD#

BI

PCI_3S_REQ1#

OUT

PCI_3S_REQ2#

OUT

PCI_3S_REQ3#

OUT

USB3_SMI#

BI

SATA_ODD_DA#

BI

PCI_3S_PIRQG#

BI

PCI_3S_PIRQH#

BI

P3V3A_PME#

CLK_KBPCI_R

22_5%_2

CLK_PCI_FB_R

22_5%_2

22_5%_2

TP4717

CLK_PCI_DEBUG_R

51A251A4

OUT

51A251A4

OUT

51A251A4

OUT

51A251A4

OUT

51A251A4

OUT

51A251A4

OUT

51A251A4

OUT

51A251A4

OUT

NOTE:10K_5%(60130B1030ZT)

4

U4700

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46
AB45

AY16
BG46

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

TP24

1

MACHINE_ID0
MACHINE_ID1
MACHINE_ID2
MACHINE_ID3
MACHINE_ID4
MACHINE_ID5
MACHINE_ID6
MACHINE_ID1_DB

TP19
TP20

B21

TP21

M20

TP22
TP23
TP24

USB3RN1
USB3RN2
USB3RN3
USB3RN4
USB3RP1
USB3RP2
USB3RP3
USB3RP4
USB3TN1
USB3TN2
USB3TN3
USB3TN4
USB3TP1
USB3TP2
USB3TP3
USB3TP4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1#/GPIO50

C44

REQ2#/GPIO52

E40

REQ3#/GPIO54

D47

GNT1#/GPIO51

E42

GNT2#/GPIO53

F46

GNT3#/GPIO55

G42

PIRQE#/GPIO2

G40

PIRQF#/GPIO3

C42

PIRQG#/GPIO4

D44

PIRQH#/GPIO5

K10

PME#

C6

PLTRST#

H49
H43
J48
K42
H40

R4892
R4893
R4894
R4895
R4896
R4897
R4898
R4899

RSVD

USED AS GPIO ONLY.
INT. PU 20K

INT. PU 20K

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4 OC7#/GPIO14

ITL_PANTHERPOINT_FCBGA_989P

PCI

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

NVRAM

DEBUG PORT

USB

P3V3A

51A5
51A2

51A5
51A2

51A2
51A5

51A5
51A2

51A2
51A5

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43

OC6#/GPIO10

54

RSVD1
RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD23

RSVD24

RSVD25

RSVD26
RSVD27

RSVD28
RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC5#/GPIO9

TO BE USED AS GPIO

MACHINE_ID0

OUT

MACHINE_ID1

OUT

MACHINE_ID2

OUT

MACHINE_ID3

OUT

MACHINE_ID4

OUT

MACHINE_ID5

OUT

MACHINE_ID6

OUT

MACHINE_ID1_DB

OUT

NOTE:10K_5%(60130B1030ZT)

32 1

AY7
AV7
AU3
BG4

AT10
BC8

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AV5

AV10

AT8

AY5
BA2

AT12

NOTE:

BF3

USB2.0/3.0 COMBO-USB2.0 PORT 0,1 MAPPEDUSB3.0 PORT 1,2

USB_P0_DN

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

B33

A14
K20
B17
C16
L16
A16
D14
C14

CHANGE by

USB_P0_DP
USB_P1_DN
USB_P1_DP
USB_P2_DN
USB_P2_DP

USB_WLAN_DN
USB_WLAN_DP

USB_CR_DN
USB_CR_DP

USB_CAM_DN
USB_CAM_DP

USB_3G_DN
USB_3G_DP

22.6_1%_3

CLOSE TO PCH

MACHINE_ID0
MACHINE_ID1
MACHINE_ID2
MACHINE_ID3
MACHINE_ID4
MACHINE_ID5
MACHINE_ID6
MACHINE_ID1_DB

R4900
R4901
R4902
R4903
R4904
R4905
R4906
R4907

R4835

21C33

BI
BI
BI
BI
BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

IN
IN
IN
IN
IN
IN
IN
IN

21
21
21
21
21
21
21
21

32C8
32C8
33C5
33C5
30C6
30C6

27B3
27B3

26A8
26A8

34B3
34B3

28C3
28C3

51A4
51A4
51A4
51A4 51A5
51A4
51A4
51A4
51A4

10K_5%_2_DY
10K_5%_2_DY
10K_5%_2_DY
10K_5%_2_DY
10K_5%_2_DY
10K_5%_2_DY
10K_5%_2_DY
10K_5%_2_DY

DATE

32B8

P0.P1 RESERVER FOR USB3.0

32B8

WLAN

CARD READER

WEBCAM

3G

51A5
51A5
51A5

51A5
51A5
51A5
51A5

21-OCT-2002XXX

23

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

of

6651

1

D

CC

B

AA

REV

X011310xxxxx-0-0

87

P3V3A

65

4

32 1

REFERENCE 4700~4949(PCH)

R4927
R4908
R4909

D

R4910

P3V3S

R4916
R4917
R4918
R4915
R4919
R4722

R4727

R4923

GFX_CRB_DET(GPIO39)

INTERNAL GFX :100K PD

EXTERNAL GFX :10K PU

P3V3S

R4920
R4926

B

FDI_OVRVLTG(GPIO37)

LOW- TX,RXTERMINATED TO SAME VOLTAGE
(DC COUPLING MODE) DEFAULT

P3V3S

R4934

R4935

PLL_ODVR_EN(PLL ON DIE VR ENABLE)(GPIO28)

HIGH-ENABLED (DEFAULT)

LOW-DISABLED

P3V3A

R4950

10K_5%_2

R4936

10K_5%_2_DY

8

21
21
21
21

21

10K_5%_2_DY

21

100K_5%_2

21

1K_5%_2_DY

21

100K_5%_2

21

21

10K_5%_2_DY

21

1K_5%_2_DY

21

21

10K_5%_2_DY

10K_5%_2_DY

10K_5%_2_DY

10K_5%_2_DY

10K_5%_2_DY

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2_DY

100K_5%_2_DY

21

STRAP

10K_5%_2

DGPU_HOLD_RST#

SATA_ODD_PRSNT#
DGPU_PWR_EN#

GPIO39

GPIO37

PLL_ODVR_EN

OUT

OUT

GPIO24
GPIO15

GPIO12

GPIO22
GPIO38
GPIO57
GPIO16

GPIO22

GPIO57

IN

52B6

52C6

52C6

OUT

52C6

OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT
OUT

52C6

52C6

52B6

52B6

52C6

29A5 52B6

16A7

16B7

16C7

52D6

56F552D6

52C7

52C7

16B5

52D752C6

52D752B6

P3V3S

52B6

52D7

P3V3S

16B5
16C7

16B7
52C7

51C7

56F5 52D7

52D7

R4928

52A7

R4929

R4930

R4932

29A5

52D7 52C7

76

R4721

21

33K_5%_2_DY

28C6

16A7

13C514A4

52D7

52D7

52D7

52C7

52D7

52B7

52D7

52B7

OUT

MSATA_DET

IN OUT

DGPU_PWR_EN#

IN

DGPU_PG

IN

RUNSCI0#_3

21E3

IN

DGPU_HOLD_RST#

OUT

GPIO12

OUT

GPIO15

OUT

GPIO16

OUT

TP4908

OUT
OUT

PLL_ODVR_EN

OUT

OUT
OUT
OUT

TP4907

SATA_ODD_PRSNT#

OUT

GPIO22

GPIO24

21

21

21

21

GPIO37

GPIO38

GPIO39

GPIO57

121

10K_5%_2_DY

10K_5%_2_DY

10K_5%_2_DY

10K_5%_2_DY

1

TP24

STRAPPING

STRAPPING

STRAPPING

TP24

U4700

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

C4

G2

U2

D40

T5

E8

E16

P8

K1

K4

V8

M5

N2

M3

V13

V3

D6

A4

A45

A46

A5

A6

B3

B47

BD1

BD49

BE1

BE49

BF1

BF49

INT. PU 20K

GPIO8

LAN_PHY_PWR_CTRL/GPIO12

INT. PD 20K

GPIO15

STRAPPING

SATA4GP/GPIO16

INT. PU 20K

TACH0/GPIO17

SCLOCK/GPIO22

GPIO24

GPIO27

INT.PD 20K

GPIO28

INT. PU 20K

STP_PCI#/GPIO34

GPIO35

SATA2GP/GPIO36

SATA3GP/GPIO37

SLOAD/GPIO38

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

SATA5GP/GPIO49/TEMP_ALERT#

GPIO57

VSS_NCTF_1

VSS_NCTF_2

VSS_NCTF_3

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

VSS_NCTF_8

VSS_NCTF_9

VSS_NCTF_10

VSS_NCTF_11

VSS_NCTF_12

VSS_NCTF_13

VSS_NCTF_14

INT. PD 20K

STRAPPING

ITL_PANTHERPOINT_FCBGA_989P

GPIO

NCTF

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

INT. PU 20K

PROCPWRGD

THRMTRIP#

INIT3_3V#

CPU/MISC

STRAPPING

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

A20GATE

PECI

RCIN#

DF_TVS

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44A44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

CHANGE by

SATA_ODD_PWREN

R4724

R4725

R4726

PCH_PECI

THRMTRIP#_R

FOLLOW EDS1.0

54

R4940

0_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

P3V3S

29B8

EC_3S_A20GATE

H_PECI

KBRST#

H_CPUPWRGD

P1V05S

R4942

56_5%_2

R4941

21

390_5%_2

BOTH THESE SHOULD BE CLOSE TO PCH

NV_CLE

DATE

21-OCT-2002XXX

23

IN

OUT

IN

OUT

R4943

21

0_5%_2_DY

OUT

21E2

41D521A6

21D2

41C5

P1V05S

R4944

56_5%_2

21

PM_THRMTRIP#

21

41D6

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

D

CC

40A4

IN

41D5

B

AA

REV

of

X011310xxxxx-0-0

6652

1

87

REFERENCE 4700~4949(PCH)

65

4

32 1

P1V05S

D

10UF_6.3V_3

1UF_6.3V_2

21

21

1UF_6.3V_21UF_6.3V_2

21

P1V05S

P1V05S

3A

C4776

10UF_6.3V_3

C4777 C4778 C4779

1UF_6.3V_2

21

1UF_6.3V_2

21

1UF_6.3V_2

21

P3V3S

B

0.1UF_16V_2

C4781

P1V05S

P1V05S

P1V05S

C4780

1UF_6.3V_2

21

21

P1V5S_VCCAFDI_VRM

0_5%_2_DY

C4775C4774C4773C4772

21

R4945

0_5%_2_DY

21

15MIL

R4946

21

1.3A

P1V05S

21

20MIL

P1V05S_VCCAPLLEXP

15MIL

P1V05S_VCCAFDIPLL

20MIL

15MIL

U4700

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3] VCCDFTERM[2]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

ITL_PANTHERPOINT_FCBGA_989P

POWER

VCC CORE

VCCIO

FDI

CRT

LVDS

DMI HVCMOS

NAND / SPI

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCDFTERM[1]

VCCDFTERM[3]

VCCDFTERM[4]

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCSPI

U48

U47

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

15MIL

15MIL

15MIL

15MIL

15MIL

P1V5S_VCCAFDI_VRM

15MIL

15MIL

15MIL

0_5%_2_DY

P3V3S_VCCADAC

P3V3S

21

1UF_6.3V_2_DY

P3V3AL

R4947

C4782 C4783

10UF_6.3V_3

21

0.01UF_50V_2

21

15MIL

C4785 C4786 C4787

0.01UF_50V_20.01UF_50V_2

0.1UF_16V_2

P1V05S

C4790

21

P3V3A

21

C4792

1UF_6.3V_2

21

21

C4788

21

R4948

0_5%_2

21

21

1UF_6.3V_2

C4784

0.1UF_16V_2

21

P1V8S_VCCTX_LVDS

22UF_6.3V_5

C4789

21

C4791

0.1UF_16V_2

21

L4700

FBM_11_160808_121T

L4701

FBM_11_160808_121T

P1V05S

P1V8S

P3V3S

21

D

P1V8S

21

P3V3S

CC

B

AA

P1V5S_VCCAFDI_VRM

40MIL

0_5%_3

8

76

54

R4949

21

CHANGE by

P1V5S

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6653

VCCIO[29]

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[12]

VCCIO[13]

VCCAPLLSATA

VCCVRM[1]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

VCCIO[5]

VCCIO[6]

VCCIO[2]

VCCIO[3]

VCCIO[4]

4

3A

N26

P26

P28

T27

T29

10MIL

20MIL

V5REF

V5REF_SUS

10MIL

10MIL

21

1UF_6.3V_2_DY

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

V5REF

N20

N22

P20

P22

AA16

W16

T34

32 1

0.1UF_16V_2

0.1UF_16V_2

C4832

C4836

C4837

C4830

C4831

C4835

1UF_6.3V_2

C4829

1UF_6.3V_2

21

21

21

10MIL

10MIL

21

20MIL

0.1UF_16V_2

21

0.1UF_16V_2

21

P1V05S

P3V3A

P3V3A

P1V05S

P3V3A

10MIL

P3V3A

P3V3S

P3V3S

REFERENCE 4700~4949(PCH)

2

D4708

R4869

C4833

D4709

R4870

1UF_6.3V_2

C4834

2

NC NC

BAT54_30V_0.2A

10_5%_5

21

0.1UF_16V_2

21

BAT54_30V_0.2A

13

10_5%_5

21

P3V3A

13

P5V0A

P3V3S

P5V0S

21

D

CC

P3V3S

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

P1V05S_VCCAPLLSATA

10MIL

P3V3A

C4841

21

C4838

1UF_6.3V_2

0.1UF_16V_2

C4839

C4840

1UF_6.3V_2

20MIL

CHANGE by

20MIL

21

0.1UF_16V_2

21

21

L4708

0603_DY

P1V05S

20MIL

P1V05S

P1V05S

21

P1V5S_VCCAFDI_VRM

B

10MIL

P1V05S

20MIL

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6654

87

P1V05S

20MIL

20MIL

P3V3A

15MIL

C4803

0.1UF_16V_2

P1V05S

0_5%_2_DY

C4805

1UF_6.3V_2_DY

P3V3S

0.1UF_16V_2

C4802C4801

10UF_6.3V_3

21

21

D

P1V05S

1.1A

22UF_6.3V_5

P1V05S

1UF_6.3V_2

1UF_6.3V_2

21

P1V05S

L4706

FBM_11_160808_121T

L4707

B

FBM_11_160808_121T

P1V05S_VCCADPLLA

21

C4812

22UF_6.3V_5_DY 1UF_6.3V_2

22UF_6.3V_5_DY 1UF_6.3V_2

P1V05S_VCCADPLLB

21

C4815

2121

C4816 C4817

C4814C4813

10UF_6.3V_3

21

10UF_6.3V_3

21

21 21

P1V05S

C4818

C4819

C4820

C4821

C4822

P1V05S

4.7UF_6.3V_3

0.1UF_16V_2 0.1UF_16V_2

21

21

8

C4825C4824C4823

21

21

1UF_6.3V_2_DY

P3V3_RTC

0.1UF_16V_2

76

22UF_6.3V_5

21

C4810C4809C4808

1UF_6.3V_2

21

P1V5S_VCCAFDI_VRM

1UF_6.3V_2

21

1UF_6.3V_2

21

1UF_6.3V_2

21

0.1UF_16V_2

21

C4827C4826 C4828

1UF_6.3V_2 0.1UF_16V_2

21

21

65

P1V05S

R4865

0_5%_2_DY

C4804

21

0.1UF_16V_2_DY

R4867

21

21

C4807C4806

21

0.1UF_16V_2

P1V05S_VCCACLK

21

P1V05S_VCCAPLLDMI2

21

C4811

21

15MIL

15MIL
15MIL

15MIL

21

R4866

0_5%_2

20MIL

15MIL

10MIL

AD49

BH23

AL29

AL24

AA19

AA21

AA24

AA26

AA27

AA29

AA31

AC26

AC27

AC29

AC31

AD29

AD31

BD47

BF47

AF17
AF33
AF34
AG34

AG33

2121

T16

V12

T38

W21

W23

W24

W26

W29

W31

W33

N16

Y49

V16

T17
V19

BJ8

A22

U4700

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3[5]

VCCAPLLDMI2

VCCIO[14]

DCPSUS[3]

VCCASW[1]

VCCASW[2]

VCCASW[3]

VCCASW[4]

VCCASW[5]

VCCASW[6]

VCCASW[7]

VCCASW[8]

VCCASW[9]

VCCASW[10]

VCCASW[11]

VCCASW[12]

VCCASW[13]

VCCASW[14]

VCCASW[15]

VCCASW[16]

VCCASW[17]

VCCASW[18]

VCCASW[19]

VCCASW[20]

DCPRTC

VCCVRM[4]

VCCADPLLA

VCCADPLLB

VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

VCCSSC

DCPSST

DCPSUS[1]
DCPSUS[2]

V_PROC_IO

VCCRTC

ITL_PANTHERPOINT_FCBGA_989P

POWER

USB

VCCSUS3_3[10]

Clock and Miscellaneous

PCI/GPIO/LPCMISC

SATA

CPU

HDA

RTC

54

87

65

4

32 1

REFERENCE 4700~4949(PCH)

U4700

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

D

B

AC19

AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39

AD40
AD42
AD43
AD45
AD46

AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38

AF42
AF46

AG19

AG31
AG48
AH11

AH36
AH39
AH40
AH42
AH46

AJ19
AJ21
AJ24
AJ33
AJ34
AK12

VSS[11]

AB7

VSS[12]
VSS[13]

AC2

VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]

AD4

VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]

AF4

VSS[55]
VSS[56]
VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]
VSS[61]

AG2

VSS[62]
VSS[63]
VSS[64]
VSS[65]

AH3

VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]

AH7

VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]

AK3

VSS[79]

ITL_PANTHERPOINT_FCBGA_989P

8

76

VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

54

U4700

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

ITL_PANTHERPOINT_FCBGA_989P

CHANGE by

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6655

8

7654321

P3V3S_DGPU

5

U5012

+-

51A8 28C3 27C7 27C3 21E3

U5000

18/19 NC/VDD33

AC6

NC_1

AJ28

NC_2

AJ4

NC_3

AJ5

NC_4

AL11

NC_5

C15

NC_6

D19

NC_7

D20

NC_8

D23

NC_9

D26

NC_10

H31

NC_11

T8

NC_12

V32

NC_13

E

NVIDIA_N13P_GLP_A1_BGA_908P

J8

VDD33_1

K8

VDD33_2

L8

VDD33_3

M8

VDD33_4

C5146

C5145

21

0.1UF_16V_2

C5144

21

21

0.1UF_16V_2

C5143

0.1UF_16V_2

C5071

21

0.1UF_16V_2

21

1UF_6.3V_2

P3V3S_DGPU

C5014

21

4.7UF_6.3V_3

52D7

BUF_PLT_RST#

IN

DGPU_HOLD_RST#

52D6

IN

D

C

P1V05S_DGPU

B

A

8

L5001

BLM15AG221SN1D_300MA

L5002

BLM15AG221SN1D_300MA

21

21

C5104

21

22UF_6.3V_5

P1V05S_GPU_SP_PLLVDD

C5053

0.1UF_16V_2

P1V05S_GPU_VID_PLLVDD

C5147

21

0.1UF_16V_2

4.7UF_6.3V_3

C5054

21

C5056

21

0.1UF_16V_2

12PF_50V_2

U5000

12/19 XTAL_PLL

AD8

PLLVDD

60MA

AE8

SP_PLLVDD

45MA

AD7

VID_PLLVDD

GF108/GKx GF117

R5006 R5007

H1 J4

21 21

10K_5%_2

XTAL_SSIN

XTAL_IN

NVIDIA_N13P_GLP_A1_BGA_908P

21

45MA

NC

1
432

27MHZ_12PF

X5000

XTAL_OUTBUFF

12PF_50V_2

XTAL_OUT

C5079C5078

10K_5%_2

H2H3

21

22UF_6.3V_5

21

C5055

21

76543

1

2

TC7SZ08FU

3

R5070

100K_5%_2

21

CLOSE TO GPU

42C4

OUT

42C4

OUT

42B1

IN

42D1

IN

42C4

OUT

42C4

OUT

42B1

IN

42D1

IN

42C4

OUT

42D4

OUT

42B1

IN

42D1

IN

42C4

OUT

42D4

OUT

42B1

IN

42C1

IN

42C4

OUT

42D4

OUT

42B1

IN

42C1

IN

42C4

OUT

42D4

OUT

42B1

IN

42C1

IN

42C4

OUT

42D4

OUT

42B1

IN

42C1

IN

42C4

OUT

42D4

OUT

42B1

IN

42C1

IN

42C4

OUT

42D4

OUT

42B1

IN

42C1

IN

42C4

OUT

42D4

OUT

42B1

IN

42C1

IN

42C4

OUT

42D4

OUT

42A1

IN

42C1

IN

42C4

OUT

42D4

OUT

42A1

IN

42C1

IN

42C4

OUT

42D4

OUT

42A1

IN

42C1

IN

42C4

OUT

42D4

OUT

42A1

IN

42C1

IN

42C4

OUT

42D4

OUT

42A1

IN

42B1

IN

42C4

OUT

42D4

OUT

42A1

IN

42B1

IN

4

PEG_C_RX0_DP
PEG_C_RX0_DN

PEG_C_TX0_DP
PEG_C_TX0_DN

PEG_C_RX1_DP
PEG_C_RX1_DN

PEG_C_TX1_DP
PEG_C_TX1_DN

PEG_C_RX2_DP
PEG_C_RX2_DN

PEG_C_TX2_DP
PEG_C_TX2_DN

PEG_C_RX3_DP
PEG_C_RX3_DN

PEG_C_TX3_DP
PEG_C_TX3_DN

PEG_C_RX4_DP
PEG_C_RX4_DN

PEG_C_TX4_DP
PEG_C_TX4_DN

PEG_C_RX5_DP
PEG_C_RX5_DN

PEG_C_TX5_DP
PEG_C_TX5_DN

PEG_C_RX6_DP
PEG_C_RX6_DN

PEG_C_TX6_DP
PEG_C_TX6_DN

PEG_C_RX7_DP
PEG_C_RX7_DN

PEG_C_TX7_DP
PEG_C_TX7_DN

PEG_C_RX8_DP
PEG_C_RX8_DN

PEG_C_TX8_DP
PEG_C_TX8_DN

PEG_C_RX9_DP
PEG_C_RX9_DN

PEG_C_TX9_DP
PEG_C_TX9_DN

PEG_C_RX10_DP
PEG_C_RX10_DN

PEG_C_TX10_DP
PEG_C_TX10_DN

PEG_C_RX11_DP
PEG_C_RX11_DN

PEG_C_TX11_DP
PEG_C_TX11_DN

PEG_C_RX12_DP
PEG_C_RX12_DN

PEG_C_TX12_DP
PEG_C_TX12_DN

PEG_C_RX13_DN

PEG_C_TX13_DP
PEG_C_TX13_DN

PEG_C_RX14_DP
PEG_C_RX14_DN

PEG_C_TX14_DP
PEG_C_TX14_DN

PEG_C_RX15_DP
PEG_C_RX15_DN

PEG_C_TX15_DP
PEG_C_TX15_DN

R5071

100K_5%_2

21

C5021

C5022

C5023

C5024

C5025

C5026

C5027

C5028

C5029

C5030

C5031

C5032

C5033

C5035

C5036

C5037

C5038

C5039

C5041

C5043

C5044

C5045

C5046

C5047

C5048

C5049

C5051

C5052

FF

U5000

1/19 PCI_EXPRESS

AJ11

PEX_WAKE*

PEG_RX0_DP
PEG_RX0_DN

PEG_RX1_DP
PEG_RX1_DN

PEG_RX2_DP
PEG_RX2_DN

PEG_RX3_DP
PEG_RX3_DN

PEG_RX4_DP
PEG_RX4_DN

PEG_RX5_DP
PEG_RX5_DN

PEG_RX6_DP
PEG_RX6_DN

PEG_RX7_DP
PEG_RX7_DN

PEG_RX8_DP

PEG_RX8_DN

PEG_RX9_DP

PEG_RX9_DN

PEG_RX10_DP

PEG_RX10_DN

PEG_RX11_DP
PEG_RX11_DN

PEG_RX12_DP
PEG_RX12_DN

PEG_RX13_DPPEG_C_RX13_DP
PEG_RX13_DN

PEG_RX14_DP
PEG_RX14_DN

PEG_RX15_DP
PEG_RX15_DN

AJ12

PEX_RST*

AK12

PEX_CLKREQ*

AL13

PEX_REFCLK

AK13

PEX_REFCLK*

AK14

PEX_TX0

AJ14

PEX_TX0*

AN12

PEX_RX0

AM12

PEX_RX0*

AH14

PEX_TX1

AG14

PEX_TX1*

AN14

PEX_RX1

AM14

PEX_RX1*

AK15

PEX_TX2

AJ15

PEX_TX2*

AP14

PEX_RX2

AP15

PEX_RX2*

AL16

PEX_TX3

AK16

PEX_TX3*

AN15

PEX_RX3

AM15

PEX_RX3*

AK17

PEX_TX4

AJ17

PEX_TX4*

AN17

PEX_RX4

AM17

PEX_RX4*

AH17

PEX_TX5

AG17

PEX_TX5*

AP17

PEX_RX5

AP18

PEX_RX5*

AK18

PEX_TX6

AJ18

PEX_TX6*

AN18

PEX_RX6

AM18

PEX_RX6*

AL19

PEX_TX7

AK19

PEX_TX7*

AN20

PEX_RX7

AM20

PEX_RX7*

AK20

PEX_TX8

AJ20

PEX_TX8*

AP20

PEX_RX8

AP21

PEX_RX8*

AH20

PEX_TX9

AG20

PEX_TX9*

AN21

PEX_RX9

AM21

PEX_RX9*

AK21

PEX_TX10

AJ21

PEX_TX10*

AN23

PEX_RX10

AM23

PEX_RX10*

AL22

PEX_TX11

AK22

PEX_TX11*

AP23

PEX_RX11

AP24

PEX_RX11*

AK23

PEX_TX12

AJ23

PEX_TX12*

AN24

PEX_RX12

AM24

PEX_RX12*

AH23

PEX_TX13

AG23

PEX_TX13*

AN26

PEX_RX13

AM26

PEX_RX13*

AK24

PEX_TX14

AJ24

PEX_TX14*

AP26

PEX_RX14

AP27

PEX_RX14*

AL25

PEX_TX15

AK25

PEX_TX15*

AN27

PEX_RX15

AM27

PEX_RX15*

NVIDIA_N13P_GLP_A1_BGA_908P

DGPU_RST#

CLKREQ_GPU#

48C3

OUT

CLK_PEG_PCH_DP

IN

CLK_PEG_PCH_DN

IN

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

C5034

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

C5040

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

C5042

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

C5050

0.22UF_6.3V_1

21

0.22UF_6.3V_1

21

0.22UF_6.3V_1

+1.05V POWER RAIL SHOULD HAVE 3500MA CAPABILITY AT LEAST

AG19

PEX_IOVDD_1

AG21

PEX_IOVDD_2

AG22

PEX_IOVDD_3

AG24

PEX_IOVDD_4

AH21

3300MA

PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14

PEX_IOVDD_5
PEX_IOVDD_6

PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9

PEX_PLL_HVDD

PEX_SVDD_3V3

210MA

AH25

AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28

AH12

AG12

C5000

2121 21

C5099

21

1UF_6.3V_2

C5098

22UF_6.3V_5

C5005

C5001

21

21

1UF_6.3V_2

C5097

21

21

22UF_6.3V_5

C5012

0.1UF_16V_2

21

PVCORE_DGPU

R5008

100_1%_2_DY

L4

L5

P8

AJ26
AK26

AG26

AK11

AP29

10K_5%_2

2.49K_1%_2

R5005

200_1%_2

R5004

R5003

PVCORE_DGPU_SENSE

PVCORE_DGPU_VSS

R5001

100_1%_2_DY

21

C5015 C5017

0.1UF_16V_2

21

21

21

P1V05S_GPU_PEX_PLLVDD

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT*

150MA

VDD_SENSE

GND_SENSE

3V3AUX_NC

PEX_PLLVDD

TESTMODE

PEX_TERMP

C5006

21

1UF_6.3V_2

22UF_6.3V_5

P3V3S_DGPU

C5020

4.7UF_6.3V_3

21

OUT

OUT

C5016

1UF_6.3V_2

21

C5010

1UF_6.3V_2

C5008

C5007

21

10UF_6.3V_3

13A8

13A8

4.7UF_6.3V_3

21

P1V05S_DGPU

C5003

21

21

4.7UF_6.3V_3

C5004

21

21

10UF_6.3V_3

L5000

BLM18PG181SN1D

4.7UF_6.3V_3

10UF_6.3V_3

21

E

D

C

P1V05S_DGPU

B

A

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CHANGE by

XXX 21-OCT-2002

CODE

SIZE

1310xxxxx-0-0

CS

DATE

21

C

SHEET

of

56 66

REV

X01

62F1 61F6 61F1 61E6 61E1

E

D

62C8 62C3 61C8 61C3

C

B

A

8

FBA_D<63..0>

BI

62F6

I68

FBA_DQM<7..0>

BI

61C3

BI

61C8

BI

61C8

BI

61C3

BI

62C8

BI

62C3

BI

62C3

BI

62C8

BI

61C3

BI

61C8

BI

61C8

BI

61C3

BI

62C8

BI

62C3

BI

62C3

BI

62C8

BI

R5027

RSC_0402_DY

R5028

RSC_0402_DY

8

7654321

FB_CLAMP
N13P-PES/GL/GLP : NC

U5000

2/19 FBA

FBC_D<63..0>

BI

62F862F461F357B757A7

61F8

FBC_DQM<7..0>

BI

63C8
63C3
63C3
63C8
64C3
64C7
64C7
64C3

63C8
63C3
63C3
63C8
64C3
64C7
64C7
64C3

P1V5S

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

0
1
2
3
4
5
6
7

2121

FBA_DQM<0>
FBA_DQM<1>
FBA_DQM<2>
FBA_DQM<3>
FBA_DQM<4>
FBA_DQM<5>
FBA_DQM<6>
FBA_DQM<7>

FBA_DQS0_DP
FBA_DQS1_DP
FBA_DQS2_DP
FBA_DQS3_DP
FBA_DQS4_DP
FBA_DQS5_DP
FBA_DQS6_DP
FBA_DQS7_DP

FBA_DQS0_DN
FBA_DQS1_DN
FBA_DQS2_DN
FBA_DQS3_DN
FBA_DQS4_DN
FBA_DQS5_DN
FBA_DQS6_DN
FBA_DQS7_DN

FBA_D<0>

L28

FBA_D<1>

M29

FBA_D<2>

L29

FBA_D<3>

M28

FBA_D<4>

N31

FBA_D<5>

P29

FBA_D<6>

R29

FBA_D<7>

P28

FBA_D<8>

J28

FBA_D<9>

H29

FBA_D<10>

J29

FBA_D<11>

H28

FBA_D<12>

G29

FBA_D<13>

E31

FBA_D<14>

E32

FBA_D<15>

F30

FBA_D<16>

C34

FBA_D<17>

D32

FBA_D<18>

B33

FBA_D<19>

C33

FBA_D<20>

F33

FBA_D<21>

F32

FBA_D<22>

H33

FBA_D<23>

H32

FBA_D<24>

P34

FBA_D<25>

P32

FBA_D<26>

P31

FBA_D<27>

P33

FBA_D<28>

L31

FBA_D<29>

L34

FBA_D<30>

L32

FBA_D<31>

L33

FBA_D<32>

AG28

FBA_D<33>

AF29

FBA_D<34>

AG29

FBA_D<35>

AF28

FBA_D<36>

AD30

FBA_D<37>

AD29

FBA_D<38>

AC29

FBA_D<39>

AD28

FBA_D<40>

AJ29

FBA_D<41>

AK29

FBA_D<42>

AJ30

FBA_D<43>

AK28

FBA_D<44>

AM29

FBA_D<45>

AM31

FBA_D<46>

AN29

FBA_D<47>

AM30

FBA_D<48>

AN31

FBA_D<49>

AN32

FBA_D<50>

AP30

FBA_D<51>

AP32

FBA_D<52>

AM33

FBA_D<53>

AL31

FBA_D<54>

AK33

FBA_D<55>

AK32

FBA_D<56>

AD34

FBA_D<57>

AD32

FBA_D<58>

AC30

FBA_D<59>

AD33

FBA_D<60>

AF31

FBA_D<61>

AG34

FBA_D<62>

AG32

FBA_D<63>

AG33

P30
F31
F34

M32
AD31
AL29
AM32
AF34

M31

G31

E33

M33
AE31
AK30
AN33
AF33

M30

H30

E34

M34
AF30
AK31
AM34
AF32

H26

62F8 57E5

62F4 61F8 61F3

62F8 62F4 61F8 61F3 57E5

62F8 62F4 61F8 61F3 57E5

62F8 62F4 61F8 61F3 57E5

62F8 62F4 61F8 61F3 57E5

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FB_VREF

NVIDIA_N13P_GLP_A1_BGA_908P

IN

IN

IN

IN

IN

FBA_CMD<2>

FBA_CMD<3>

FBA_CMD<5>

FBA_CMD<18>

FBA_CMD<19>

66MA

35MA

10K_5%_2

10K_5%_2

10K_5%_2

10K_5%_2

10K_5%_2

FB_DLL_AVDD

FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

FBA_CMD_RFU0
FBA_CMD_RFU1

FBA_DEBUG0
FBA_DEBUG1

FBA_CLK0*

FBA_CLK1*

FBA_WCK01

FBA_WCK01*

FBA_WCK23

FBA_WCK23*

FBA_WCK45

FBA_WCK45*

FBA_WCK67

FBA_WCK67*

FBA_WCKB01

FBA_WCKB01*

FBA_WCKB23

FBA_WCKB23*

FBA_WCKB45

FBA_WCKB45*

FBA_WCKB67

FBA_WCKB67*

FBA_PLL_AVDD

R5010

R5011

R5012

R5013

R5014

FB_CLAMP

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9

FBA_CLK0

FBA_CLK1

21

21

21

21

21

E1

P1V05S_GPU_FBA_PLLAVDD

K27

C5013

0.1UF_16V_2

21

FBA_CMD<0>

U30

FBA_CMD<1>

T31

FBA_CMD<2>

U29

FBA_CMD<3>

R34

FBA_CMD<4>

R33

FBA_CMD<5>

U32

FBA_CMD<6>

U33

FBA_CMD<7>

U28

FBA_CMD<8>

V28

FBA_CMD<9>

V29

FBA_CMD<10>

V30

FBA_CMD<11>

U34

FBA_CMD<12>

U31

FBA_CMD<13>

V34

FBA_CMD<14>

V33

FBA_CMD<15>

Y32

FBA_CMD<16>

AA31

FBA_CMD<17>

AA29

FBA_CMD<18>

AA28

FBA_CMD<19>

AC34

FBA_CMD<20>

AC33

FBA_CMD<21>

AA32

FBA_CMD<22>

AA33

FBA_CMD<23>

Y28

FBA_CMD<24>

Y29

FBA_CMD<25>

W31

FBA_CMD<26>

Y30

FBA_CMD<27>

AA34

FBA_CMD<28>

Y31

FBA_CMD<29>

Y34

FBA_CMD<30>

Y33
V31

R32
AC32

R28
AC28

FBA_CLK0_DP

R30

FBA_CLK0_DN

R31

FBA_CLK1_DP

AB31

FBA_CLK1_DN

AC31

K31
L30
H34
J34
AG30
AG31
AJ34
AK34

J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33

P1V05S_GPU_FBA_PLLAVDD

U27

IN

FBA_CMD<30..0>

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

61D3

OUT

61C5

OUT

62D3

OUT

62C5

OUT

C5066

0.1UF_16V_2 22UF_6.3V_5

21

BLM18PG181SN1D

C5068

21

64F5 64F1 64E5 64E1 63F6 63F1 63E1

57B1

OUT

64C7 64C3 63C8 63C3

61D861D5
61D361C8
62D862D5
62D862D3

P1V05S_DGPU

L5005

21

76543

N13P-GV;N13M-GS;N13P-GT-GS-LP: PL10K

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

0
1
2
3
4
5
6
7

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

FBC_D<0>
FBC_D<1>
FBC_D<2>
FBC_D<3>
FBC_D<4>
FBC_D<5>
FBC_D<6>
FBC_D<7>
FBC_D<8>
FBC_D<9>
FBC_D<10>
FBC_D<11>
FBC_D<12>
FBC_D<13>
FBC_D<14>
FBC_D<15>
FBC_D<16>
FBC_D<17>
FBC_D<18>
FBC_D<19>
FBC_D<20>
FBC_D<21>
FBC_D<22>
FBC_D<23>
FBC_D<24>
FBC_D<25>
FBC_D<26>
FBC_D<27>
FBC_D<28>
FBC_D<29>
FBC_D<30>
FBC_D<31>
FBC_D<32>
FBC_D<33>
FBC_D<34>
FBC_D<35>
FBC_D<36>
FBC_D<37>
FBC_D<38>
FBC_D<39>
FBC_D<40>
FBC_D<41>
FBC_D<42>
FBC_D<43>
FBC_D<44>
FBC_D<45>
FBC_D<46>
FBC_D<47>
FBC_D<48>
FBC_D<49>
FBC_D<50>
FBC_D<51>
FBC_D<52>
FBC_D<53>
FBC_D<54>
FBC_D<55>
FBC_D<56>
FBC_D<57>
FBC_D<58>
FBC_D<59>
FBC_D<60>
FBC_D<61>
FBC_D<62>
FBC_D<63>

FBC_DQM<0>
FBC_DQM<1>
FBC_DQM<2>
FBC_DQM<3>
FBC_DQM<4>
FBC_DQM<5>
FBC_DQM<6>
FBC_DQM<7>

FBC_DQS0_DP
FBC_DQS1_DP
FBC_DQS2_DP
FBC_DQS3_DP
FBC_DQS4_DP
FBC_DQS5_DP
FBC_DQS6_DP
FBC_DQS7_DP

FBC_DQS0_DN
FBC_DQS1_DN
FBC_DQS2_DN
FBC_DQS3_DN
FBC_DQS4_DN
FBC_DQS5_DN
FBC_DQS6_DN
FBC_DQS7_DN

64F8 64F4 63F8 63F4 57E1

64F8 64F4 63F8 63F4 57E1

64F8 64F4 63F8 63F4 57E1

64F8 64F4 63F8 63F4 57E1

64F8 64F4 63F8 63F4 57E1

U5000

3/19 FBB

G9

FBB_D0

E9

FBB_D1

G8

FBB_D2

F9

FBB_D3

F11

FBB_D4

G11

FBB_D5

F12

FBB_D6

G12

FBB_D7

G6

FBB_D8

F5

FBB_D9

E6

FBB_D10

F6

FBB_D11

F4

FBB_D12

G4

FBB_D13

E2

FBB_D14

F3

FBB_D15

C2

FBB_D16

D4

FBB_D17

D3

FBB_D18

C1

FBB_D19

B3

FBB_D20

C4

FBB_D21

B5

FBB_D22

C5

FBB_D23

A11

FBB_D24

C11

FBB_D25

D11

FBB_D26

B11

FBB_D27

D8

FBB_D28

A8

FBB_D29

C8

FBB_D30

B8

FBB_D31

F24

FBB_D32

G23

FBB_D33

E24

FBB_D34

G24

FBB_D35

D21

FBB_D36

E21

FBB_D37

G21

FBB_D38

F21

FBB_D39

G27

FBB_D40

D27

FBB_D41

G26

FBB_D42

E27

FBB_D43

E29

FBB_D44

F29

FBB_D45

E30

FBB_D46

D30

FBB_D47

A32

FBB_D48

C31

FBB_D49

C32

FBB_D50

B32

FBB_D51

D29

FBB_D52

A29

FBB_D53

C29

FBB_D54

B29

FBB_D55

B21

FBB_D56

C23

FBB_D57

A21

FBB_D58

C21

FBB_D59

B24

FBB_D60

C24

FBB_D61

B26

FBB_D62

C26

FBB_D63

E11

FBB_DQM0

E3

FBB_DQM1

A3

FBB_DQM2

C9

FBB_DQM3

F23

FBB_DQM4

F27

FBB_DQM5

C30

FBB_DQM6

A24

FBB_DQM7

D10

FBB_DQS_WP0

D5

FBB_DQS_WP1

C3

FBB_DQS_WP2

B9

FBB_DQS_WP3

E23

FBB_DQS_WP4

E28

FBB_DQS_WP5

B30

FBB_DQS_WP6

A23

FBB_DQS_WP7

D9

FBB_DQS_RN0

E4

FBB_DQS_RN1

B2

FBB_DQS_RN2

A9

FBB_DQS_RN3

D22

FBB_DQS_RN4

D28

FBB_DQS_RN5

A30

FBB_DQS_RN6

B23

FBB_DQS_RN7

NVIDIA_N13P_GLP_A1_BGA_908P

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8

FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31

FBB_CMD_RFU0
FBB_CMD_RFU1

FBB_DEBUG0
FBB_DEBUG1

FBB_CLK0
FBB_CLK0*

FBB_CLK1
FBB_CLK1*

FBB_WCK01

FBB_WCK01*

FBB_WCK23

FBB_WCK23*

FBB_WCK45

FBB_WCK45*

FBB_WCK67

FBB_WCK67*

FBB_WCKB01

FBB_WCKB01*

FBB_WCKB23

FBB_WCKB23*

FBB_WCKB45

FBB_WCKB45*

FBB_WCKB67

FBB_WCKB67*

FBB_PLL_AVDD

66MA

R5017

FBC_CMD<2>

IN

FBC_CMD<3>

IN

FBC_CMD<5>

IN

FBC_CMD<18>

IN

FBC_CMD<19>

IN

21

10K_5%_2

R5018

21

10K_5%_2

R5019

21

10K_5%_2

R5020

21

10K_5%_2

R5021

21

10K_5%_2

CHANGE by

XXX 21-OCT-2002

FBC_CMD<1>

E14

FBC_CMD<2>

F14

FBC_CMD<3>

A12

FBC_CMD<4>

B12

FBC_CMD<5>

C14

FBC_CMD<6>

B14

FBC_CMD<7>

G15

FBC_CMD<8>

F15

FBC_CMD<9>

E15

FBC_CMD<10>

D15

FBC_CMD<11>

A14

FBC_CMD<12>

D14

FBC_CMD<13>

A15

FBC_CMD<14>

B15

FBC_CMD<15>

C17

FBC_CMD<16>

D18

FBC_CMD<17>

E18

FBC_CMD<18>

F18

FBC_CMD<19>

A20

FBC_CMD<20>

B20

FBC_CMD<21>

C18

FBC_CMD<22>

B18

FBC_CMD<23>

G18

FBC_CMD<24>

G17

FBC_CMD<25>

F17

FBC_CMD<26>

D16

FBC_CMD<27>

A18

FBC_CMD<28>

D17

FBC_CMD<29>

A17

FBC_CMD<30>

B17
E17

C12
C20

G14
G20

FBC_CLK0_DP

D12
E12
E20
F20

F8
E8
A5
A6
D24
D25
B27
C27

D6
D7
C6
B6
F26
E26
A26
A27

H17

OUT

FBC_CLK0_DN

OUT

FBC_CLK1_DP

OUT

FBC_CLK1_DN

OUT

P1V05S_GPU_FBA_PLLAVDD

C5070

0.1UF_16V_2

21

DATE

21

FBC_CMD<0>

D13

FBC_CMD<30..0>

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

63D863D363C5
63D863D363C5
64D764D364C5
64D764C564C3

57F5

IN

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CODE

SIZE

1310xxxxx-0-0

CCS

SHEET

DOC.NUMBER

OUT

57 66

FF

E

64F864F4
57B357A3
63F863F4

D

C

B

A

REV

X01

of

8

7654321

U5000

16/19 GND_1/2

A2

GND_001

AA17

GND_005

AA18

GND_006

AA20

GND_007

AA22

GND_008

AB12

GND_009

AB14

GND_010

AB16

GND_011

AB19

GND_012

AB2

GND_013

AB21

GND_014

A33

GND_002

AB23

GND_015

AB28

GND_016

AB30

GND_017

AB32

GND_018

AB5

GND_019

AB7

GND_020

AC13

GND_021

AC15

GND_022

AC17

GND_023

AC18

GND_024

AA13

GND_003

AC20

GND_025

AC22

GND_026

AE2

GND_027

AE28

GND_028

AE30

GND_029

AE32

GND_030

AE33

E

D

GND_031

AE5

GND_032

AE7

GND_033

AH10

GND_034

AA15

GND_004

AH13

GND_035

AH16

GND_036

AH19

GND_037

AH2

GND_038

AH22

GND_039

AH24

GND_040

AH28

GND_041

AH29

GND_042

AH30

GND_043

AH32

GND_044

AH33

GND_045

AH5

GND_046

AH7

GND_047

AJ7

GND_048

AK10

GND_049

AK7

GND_050

AL12

GND_051

AL14

GND_052

AL15

GND_053

AL17

GND_054

AL18

GND_055

AL2

GND_056

AL20

GND_057

AL21

GND_058

AL23

GND_059

AL24

GND_060

AL26

GND_061

AL28

GND_062

AL30

GND_063

AL32

GND_064

AL33

GND_065

AL5

GND_066

AM13

GND_067

AM16

GND_068

AM19

GND_069

AM22

GND_070

AM25

GND_071

AN1

GND_072

AN10

GND_073

AN13

GND_074

AN16

GND_075

AN19

GND_076

AN22

GND_077

AN25

GND_078

AN30

GND_079

AN34

GND_080

AN4

GND_081

AN7

GND_082

AP2

GND_083

AP33

GND_084

B1

GND_085

B10

GND_086

B22

GND_087

B25

GND_088

B28

GND_089

B31

GND_090

B34

GND_091

B4

GND_092

B7

GND_093

C10

GND_094

C13

GND_095

C19

GND_096

C22

GND_097

C25

GND_098

C28

GND_099

C7

GND_100

D2

GND_101

D31

GND_102

D33

GND_103

E10

GND_104

E22

GND_105

E25

GND_106

E5

GND_107

E7

GND_108

F28

GND_109

F7

GND_110

G10

GND_111

G13

GND_112

G16

GND_113

G19

GND_114

G2

GND_115

G22

GND_116

G25

GND_117

G28

GND_118

G3

GND_119

G30

GND_120

G32

GND_121

G33

GND_122

G5

GND_123

G7

GND_124

K2

GND_125

K28

GND_126

K30

GND_127

K32

GND_128

K33

GND_129

K5

GND_130

K7

GND_131

M13

GND_132

M15

GND_133

M17

GND_134

M18

GND_135

M20

GND_136

M22

GND_137

N12

GND_138

N14

GND_139

N16

GND_140

PVCORE_DGPU

NVIDIA_N13P_GLP_A1_BGA_908P

U5000

17/19 GND_2/2

N19

GND_141

N2

C

B

GND_142

N21

GND_143

N23

GND_144

N28

GND_145

N30

GND_146

N32

GND_147

N33

GND_148

N5

GND_149

N7

GND_150

P13

GND_151

P15

GND_152

P17

GND_153

P18

GND_154

P20

GND_155

P22

GND_156

R12

GND_157

R14

GND_158

R16

GND_159

R19

GND_160

R21

GND_161

R23

GND_162

T13

GND_163

T15

GND_164

T17

GND_165

T18

GND_166

T2

GND_167

T20

GND_168

T22

GND_169

GND_F

Optional CMD GNDs (2)
NC for 4-Lyr cards

NVIDIA_N13P_GLP_A1_BGA_908P

GND_OPT_1
GND_OPT_2

T28

GND_170

T32

GND_171

T5

GND_172

T7

GND_173

U12

GND_174

U14

GND_175

U16

GND_176

U19

GND_177

U21

GND_178

U23

GND_179

V12

GND_180

V14

GND_181

V16

GND_182

V19

GND_183

V21

GND_184

V23

GND_185

W13

GND_186

W15

GND_187

W17

GND_188

W18

GND_189

W20

GND_190

W22

GND_191

W28

GND_192

Y12

GND_193

Y14

GND_194

Y16

GND_195

Y19

GND_196

Y21

GND_197

Y23

GND_198

AH11AG11

GND_H

C16
W32

A

8

76543

U5000

14/19 NVVDD

AA12

VDD_001

AA14

VDD_002

AA16

VDD_003

AA19

VDD_004

AA21

VDD_005

AA23

VDD_006

AB13

VDD_007

AB15

VDD_008

AB17

VDD_009

AB18

VDD_010

AB20

VDD_011

AB22

VDD_012

AC12

VDD_013

AC14

VDD_014

AC16

VDD_015

AC19

VDD_016

AC21

VDD_017

AC23

VDD_018

M12

VDD_019

M14

VDD_020

M16

VDD_021

M19

VDD_022

M21

VDD_023

M23

VDD_024

N13

VDD_025

N15

VDD_026

N17

VDD_027

N18

VDD_028

N20

VDD_029

N22

VDD_030

P12

VDD_031

P14

VDD_032

P16

VDD_033

P19

VDD_034

P21

VDD_035

P23

VDD_036

R13

VDD_037

R15

VDD_038

R17

VDD_039

R18

VDD_040

R20

VDD_041

R22

VDD_042

T12

VDD_043

T14

VDD_044

T16

VDD_045

T19

VDD_046

T21

VDD_047

T23

VDD_048

U13

VDD_049

U15

VDD_050

U17

VDD_051

U18

VDD_052

U20

VDD_053

U22

VDD_054

V13

VDD_055

V15

VDD_056

V17

VDD_057

V18

VDD_058

V20

VDD_059

V22

VDD_060

W12

VDD_061

W14

VDD_062

W16

VDD_063

W19

VDD_064

W21

VDD_065

W23

VDD_066

Y13

VDD_067

Y15

VDD_068

Y17

VDD_069

Y18

VDD_070

Y20

VDD_071

Y22

VDD_072

NVIDIA_N13P_GLP_A1_BGA_908P

U5000

10/19 XVDD

CONFIGURABLE
POWER
CHANNELS

NVIDIA_N13P_GLP_A1_BGA_908P

XVDD_001
XVDD_002
XVDD_003
XVDD_004
XVDD_005
XVDD_006
XVDD_007
XVDD_008

XVDD_009
XVDD_010
XVDD_011
XVDD_012
XVDD_013
XVDD_014
XVDD_015
XVDD_016

XVDD_017
XVDD_018
XVDD_019
XVDD_020
XVDD_021
XVDD_022

XVDD_023
XVDD_024
XVDD_025
XVDD_026
XVDD_027
XVDD_028
XVDD_029
XVDD_030

XVDD_031
XVDD_032
XVDD_033
XVDD_034
XVDD_035
XVDD_036
XVDD_037
XVDD_038

PVCORE_DGPU

FF

C5085

C5086

C5087

C5088

C5081

C5080

21

4.7UF_6.3V_3

C5091

C5090

21

22UF_6.3V_5

C5094

C5093

21

0.1UF_16V_2

C5082

21

21

4.7UF_6.3V_3

C5092

21

21

22UF_6.3V_5

C5095

21

21

0.1UF_16V_2

C5083

4.7UF_6.3V_3

22UF_6.3V_5

C5096

21

0.1UF_16V_2

C5084

21

21

4.7UF_6.3V_3

0.1UF_16V_2

4.7UF_6.3V_3

21

21

4.7UF_6.3V_3

4.7UF_6.3V_3

21

4.7UF_6.3V_3

C5089

21

21

4.7UF_6.3V_3

4.7UF_6.3V_3

E

D

P1V5S_DGPU

U5000

15/19 FBVDDQ

AA27

FBVDDQ_01

AA30

FBVDDQ_02

AB27

FBVDDQ_03

AB33

FBVDDQ_04

AC27

FBVDDQ_05

AD27

FBVDDQ_06

AE27

FBVDDQ_07

AF27

FBVDDQ_08

AG27

FBVDDQ_09

B13

FBVDDQ_10

B16

U1
U2
U3
U4
U5
U6
U7
U8

V1
V2
V3
V4
V5
V6
V7
V8

W2
W3
W4
W5
W7
W8

Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8

AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8

FBVDDQ_11

B19

FBVDDQ_12

E13

FBVDDQ_13

E16

FBVDDQ_14

E19

FBVDDQ_15

H10

FBVDDQ_16

H11

FBVDDQ_17

H12

FBVDDQ_18

H13

FBVDDQ_19

H14

FBVDDQ_20

H15

FBVDDQ_21

H16

FBVDDQ_22

H18

FBVDDQ_23

H19

FBVDDQ_24

H20

FBVDDQ_25

H21

FBVDDQ_26

H22

FBVDDQ_27

H23

FBVDDQ_28

H24

FBVDDQ_29

H8

FBVDDQ_30

H9

FBVDDQ_31

L27

FBVDDQ_32

M27

FBVDDQ_33

N27

FBVDDQ_34

P27

FBVDDQ_35

R27

FBVDDQ_36

T27

FBVDDQ_37

T30

FBVDDQ_38

T33

FBVDDQ_39

V27

FBVDDQ_40

W27

FBVDDQ_41

W30

FBVDDQ_42

W33

FBVDDQ_43

Y27

FBVDDQ_44

NVIDIA_N13P_GLP_A1_BGA_908P

FB_VDDQ_SENSE

FB_GND_SENSE

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

R5130

F1

0_5%_2

F2

J27 21

H27

H25

P1V5S_DGPU

21

R5024

40.2_1%_2

R5025

42.2_1%_2

51.1_1%_2

P1V5S_DGPU

C5060

21

0.1UF_16V_2

C5074

21

1UF_6.3V_2

C5061

21

0.1UF_16V_2

C5075

21

1UF_6.3V_2

C5062

21

0.1UF_16V_2

C5076

21

C5063

21

0.1UF_16V_2

C5077

4.7UF_6.3V_3

C5065

C5064

21

0.1UF_16V_2

C5100

21

4.7UF_6.3V_3

C5072

21

21

0.1UF_16V_2

C5101

21

21

10UF_6.3V_3

C5073

0.1UF_16V_2

C5102

10UF_6.3V_3

21

0.1UF_16V_2

C5103

21

21

10UF_6.3V_3

10UF_6.3V_3

C

B

P1V5S_DGPU

21

R5026

21

CHANGE by

XXX 21-OCT-2002

DATE

21

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CODE

SIZE

CCS

1310xxxxx-0-0

SHEET

DOC.NUMBER

58 66

A

REV

X01

of

8

7654321

U5000

FF

6/19 IFPAB

ALL PINS NC FOR GF117

AJ8

IFPAB_RSET

AH8

21

IFPAB_PLLVDD

10K_5%_2

R5031

E

AG8

IFPA_IOVDD

AG9

IFPB_IOVDD

21

R5036

10K_5%_2

IFPAB

D

NVIDIA_N13P_GLP_A1_BGA_908P

U5000

9/19 IFPEF

IFPA_TXD0*

IFPA_TXD1*

IFPA_TXD2*

IFPA_TXD3*

IFPB_TXD4*

IFPB_TXD5*

IFPB_TXD6*

IFPB_TXD7*

IFPA_TXC*

IFPA_TXD0

IFPA_TXD1

IFPA_TXD2

IFPA_TXD3

IFPB_TXC*

IFPB_TXD4

IFPB_TXD5

IFPB_TXD6

IFPB_TXD7

IFPA_TXC

IFPB_TXC

AN6
AM6

AN3
AP3

AM5
AN5

AK6
AL6

AH6
AJ6

AH9
AJ9

AP5
AP6

AL7
AM7

AM8
AN8

AL8
AK8

N4

GPIO14

21

R5048

100K_5%_2

10K_5%_2

10K_5%_2

R5039

R5002

ALL PINS NC FOR GF117

DVI-DL DVI-SL/HDMI DP

C

AB8

AD6

21

AC7

AC8

21

IFPEF_PLLVDD

IFPEF_RSET

IFPE_IOVDD

IFPF_IOVDD

R5033

10K_5%_2

B

R5034

10K_5%_2

IFPE

IFPF

I2CY_SDA

I2CY_SDA

I2CY_SCL I2CY_SCL

TXC

TXC

TXC

TXC

TXD0

TXD0

TXD0

TXD0

TXD1

TXD1

TXD1

TXD1

TXD2

TXD2
TXD2

TXD2

HPD_E

HPD_E

I2CZ_SDA
I2CZ_SCL

TXC
TXC

TXD0

TXD3

TXD0

TXD3

TXD1

TXD4

TXD1

TXD4

TXD2

TXD5

TXD2

TXD5

IFPE_AUX_I2CY_SDA*

IFPE_AUX_I2CY_SCL

IFPF_AUX_I2CZ_SDA*

IFPF_AUX_I2CZ_SCL

HPD_F

A

8

76543

NVIDIA_N13P_GLP_A1_BGA_908P

AB4
AB3

AC5

IFPE_L3*

AC4

IFPE_L3

AC3

IFPE_L2*

AC2

IFPE_L2

AC1

IFPE_L1*

AD1

IFPE_L1

AD3

IFPE_L0*

AD2

IFPE_L0

R1

GPIO18

R5049

100K_5%_2

AF2
AF3

AF1

IFPF_L3*

AG1

IFPF_L3

AD5

IFPF_L2*

AD4

IFPF_L2

AF5

IFPF_L1*

AF4

IFPF_L1

AE4

IFPF_L0*

AE3

IFPF_L0

P3

GPIO19

21 21

R5050

100K_5%_2

10K_5%_2

R5042

10K_5%_2

U5000

7/19 IFPC

ALL PINS NC FOR GF117

AF8

2121

IFPC_RSET

AF7

IFPC_PLLVDD

AF6

IFPC_IOVDD

NVIDIA_N13P_GLP_A1_BGA_908P

IFPC

DVI/HDMI DP

I2CW_SDA

IFPC_AUX_I2CW_SDA*

I2CW_SCL

IFPC_AUX_I2CW_SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

AG2
AG3

AG4

IFPC_L3*

AG5

IFPC_L3

AH4

IFPC_L2*

AH3

IFPC_L2

AJ2

IFPC_L1*

AJ3

IFPC_L1

AJ1

IFPC_L0*

AK1

IFPC_L0

P2

GPIO15

21

R5051

100K_5%_2

E

D

U5000

8/19 IFPD

ALL PINS NC FOR GF117

AN2

IFPD_RSET

AG7

21

R5041

IFPD_PLLVDD

AG6

21

IFPD_IOVDD

DVI/HDMI

I2CX_SDA
I2CX_SCL

TXC
TXC

TXD0

IFPD

TXD0

TXD1
TXD1

TXD2
TXD2

NVIDIA_N13P_GLP_A1_BGA_908P

IFPD_AUX_I2CX_SDA*

IFPD_AUX_I2CX_SCL

DP

AK2
AK3

AK5

IFPD_L3*

AK4

IFPD_L3

AL4

IFPD_L2*

AL3

IFPD_L2

AM4

IFPD_L1*

AM3

IFPD_L1

AM2

IFPD_L0*

AM1

IFPD_L0

M6

GPIO17

21

R5054

100K_5%_2

C

B

A

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CHANGE by

XXX 21-OCT-2002

CODE

SIZE

CCS

DATE

21

1310xxxxx-0-0

SHEET

of

59 66

REV

X01

8

4.7UF_6.3V_3

C5110

P3V3S_DGPU

L5003

BLM18PG181SN1D

21

P3V3S_GPU_DACA_VDD

21

C5111

4.7UF_6.3V_3

0.1UF_16V_2

21

C5112

21

7654321

P3V3S_DGPU

21

R5053R5052

2.2K_5%_2

21

TP30

1

TP5005

TP30

1

TP5006

21

R5068R5067

21

R5069

21

60B6
60B6
60B6
60B6
60B6

75_1%_2

GPU_STRAP0

IN

GPU_STRAP1

IN

GPU_STRAP2

IN

GPU_STRAP3

IN

GPU_STRAP4

IN

40.2K_1%_2

U5000

13/19 MISC2

J2

STRAP0

J7

STRAP1

J6

STRAP2

J5

STRAP3

J3

STRAP4

R5058

21

J1 L3

MULTI_STRAP_REF0_GND

ROM_SCLK

P3V3S_DGPU

R5065

10K_5%_2

21

H6

ROM_CS*

GPU_ROM_SI

H5

ROM_SI

GPU_ROM_SO

H7

ROM_SO

GPU_ROM_SCLK

H4

L2

BUFRST*

CEC

21

10K_5%_2

60B4

OUT

60B4

OUT

60B4

OUT

R5057

21

124_1%_2

AG10

AP9

AP8

R5066

U5000

4/19 DACA

GF108/GKx GF117

DACA_VDD

TSEN_VREF

DACA_VREF

DACA_RSET

NVIDIA_N13P_GLP_A1_BGA_908P

DACA_BLUE

I2CA_SCL
I2CA_SDA

DACA_RED

75_1%_2

2.2K_5%_2

R4
R5

AM9
AN9

AK9

AL10

AL9

75_1%_2

GF108/GKxGF117

NCNC
NC

NC

NC

DACA_HSYNC

NC

DACA_VSYNC

NC

NC

DACA_GREEN

NC

FF

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO16
GPIO20
GPIO21

60D3

60D3

T4
T3

R2
R3

R7
R6

P6
M3
L6
P5
P7
L7
M7
N8
M1
M2
L1
M5
N3
M4
R8
P4
P1

DGPU_SMB2_CLK
DGPU_SMB2_DATA

NVIDIA_N13P_GLP_A1_BGA_908P

2.2K_5%_2

DGPU_SMB2_CLK

IN

DGPU_SMB2_DATA

IN

R5055
R5056

R5091
R5092

DGPU_VID4
DGPU_VID3

DGPU_VID1
DGPU_VID2

R5073
R5074

DGPU_VID0

DGPU_VID5

R5094R5093

2.2K_5%_2

21

21

OUT
OUT

21

2.2K_5%_2

21

2.2K_5%_2

21

2.2K_5%_2

21

2.2K_5%_2

OUT
OUT

OUT
OUT

OUT
OUT

21
21

13A4
13A4

13A4
13A4

13A4

13A4
60C2

2

10K_5%_2
10K_5%_2

P3V3S_DGPU

1

G

60E4
60D4

60C2
60C2

INV_PWM_GPU
LCM_VDDEN_GPU
LCM_BKLTEN_GPU

60C2
60C2

60C2

3

DS

2

Q5003

SSM3K7002FU

DS

P3V3S_DGPU

100K_5%_2

Q5000

G

SSM3K7002FU

3

R5063

1

2

21

DCIN_WLED#

1

Q5002

G

SSM3K7002FU

3

DS

OUT
OUT
OUT

EC_SMB2_CLK

EC_SMB2_DATA

60D2
60D2
60D2

19A7 21B6

IN

P3V3S_DGPU

21D35A7 21D2

OUT

5A7

21D3 21D2

OUT

10K_5%_2

10K_5%_2

10K_5%_2

R5047

21

R5061

21

R5062

21

INV_PWM_GPU

60D3

IN

LCM_VDDEN_GPU

60C3

IN

LCM_BKLTEN_GPU

60C3

IN

P3V3S_DGPU

60C4

60C4

60C4

60D4 13A4

60C4

R5161
21

DGPU_VID0

13A4

IN

DGPU_VID1

13A4

IN

DGPU_VID2

13A4

IN

DGPU_VID3

13A460D4

IN

DGPU_VID4

IN

DGPU_VID5

13A4

IN

2.2K_5%_2

R5163

21

R5168

21

2.2K_5%_2

2.2K_5%_2

R5170

21

R5165

21

2.2K_5%_2

2.2K_5%_2

R5172
21

2.2K_5%_2

E

U5000

11/19 MISC1

D

TP5007

TP30

1

K4

TP5008

TP5000
TP5001
TP5002
TP5003
TP5004

21

R5064

THERMDN

TP30

1

K3

THERMDP

TP30

1

AM10

JTAG_TCK

TP30

1

AP11

JTAG_TMS

TP30

1

AM11

JTAG_TDI

TP30

1

AP12

JTAG_TDO

TP30

1

AN11

JTAG_TRST*

I2CS_SCL
I2CS_SDA

I2CC_SCL
I2CC_SDA

I2CB_SCL
I2CB_SDA

10K_5%_2

C

NVIDIA_N13P_GLP_A1_BGA_908P

E

D

C

P3V3S_DGPU

R5086

30K_1%_234.8K_1%_2

2121

RSC_0402_DY

P3V3S_DGPU

R5087

RSC_0402_DY

2121

R5090

15K_1%_2

B

2121

2121

R5080

B

GPU_STRAP0

60F4

IN

GPU_STRAP1

60F4

IN

GPU_STRAP2

60F4

GPU_STRAP3

60F4

IN

GPU_STRAP4

60F4

IN

R5079

45.3K_1%_2

R5082

R5081

RSC_0402_DY

2121

R5083 R5045

R5084

34.8K_1%_2RSC_0402_DY

RSC_0402_DYRSC_0402_DY

2121

R5059

R5044

RSC_0402_DY

4.99K_1%_210K_1%_2

2121

R5060

20K_1%_2

GPU_ROM_SI

60F2

ININ

GPU_ROM_SO

60F2

IN

GPU_ROM_SCLK

60F2

IN

R5085

2121

R5088 R5089

RSC_0402_DY

A

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CSC

CHANGE by

8

76543

XXX 21-OCT-2002

DATE

21

1310xxxxx-0-0

SHEET

60 66

A

REV

X01

of

8

7654321

BI

61D8 61D5 57C5

61C8 61C5

FBA_CMD<30:0>

61E5 61B8

61D5 61B8

FBA_CMD<9>

9

FBA_CMD<11>

11

FBA_CMD<8>

8

FBA_CMD<25>

25

FBA_CMD<10>

10

FBA_CMD<24>

24

FBA_CMD<22>

22

FBA_CMD<7>

7

FBA_CMD<21>

21

FBA_CMD<6>

6

FBA_CMD<29>

29

FBA_CMD<23>

23

FBA_CMD<28>

28

FBA_CMD<20>

20

FBA_CMD<4>

4

FBA_CMD<14>

14

FBA_CMD<12>

12

FBA_CMD<27>

27

FBA_CMD<26>

26

FBA_CMD<2>

2

FBA_CMD<0>

0

FBA_CMD<30>

30

FBA_CMD<15>

15

FBA_CMD<13>

13

FBA_CMD<5>

5

FBA_CMD<3>

3

FBA_CLK0_DP

IN

FBA_CLK0_DN

57C5

IN

FBA_DQM<0>

57D8

BI

FBA_DQS0_DP

57C7

BI

FBA_DQS0_DN

57C7

BI

FBA_DQM<3>

57D8

BI

FBA_DQS3_DP

57C7

BI

FBA_DQS3_DN

57C7

BI

R5106

21L8

243_1%_2

FBA_VREFDQ0

IN

FBA_VREFCA0

IN

U5004

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10_AP

R7

A11

N7

A12_BC#

T3

A13

T7

A14_NC

M7

A15

M2

BA0

N8

BA1

M3

BA2

K1

ODT

L2

CS#

J3

RAS#

K3

CAS#

L3

WE#

T2

RESET#

K9

CKE

J7

CK

K7

CK#

D3

DMU

C7

DQSU

B7

DQSU#

E7

DML

F3

DQSL

G3

DQSL#

ZQ

J1

NC_J1

L1

NC_L1

J9

NC_J9

L9

NC_L9

H1

VREFDQ

M8

VREFCA

HYNIX_H5TQ2G63BFR_12C_FBGA_96P

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

VDD_B2

VDD_D9

VDD_G7

VDD_K2

VDD_K8

VDD_N1

VDD_N9

VDD_R1

VDD_R9

VDDQ_A1

VDDQ_A8

VDDQ_C1

VDDQ_C9

VDDQ_D2

VDDQ_E9

VDDQ_F1

VDDQ_H2

VDDQ_H9

VSS_A9

VSS_B3

VSS_E1

VSS_G8

VSS_J2

VSS_J8

VSS_M1

VSS_M9

VSS_P1

VSS_P9

VSS_T1

VSS_T9

VSSQ_B1

VSSQ_B9

VSSQ_D1

VSSQ_D8

VSSQ_E2

VSSQ_E8

VSSQ_F9

VSSQ_G1

VSSQ_G9

FBA_D<26>

E3

FBA_D<27>

F7

FBA_D<24>

F2

FBA_D<25>

F8

FBA_D<31>

H3

FBA_D<29>

H8

FBA_D<28>

G2

FBA_D<30>

H7

FBA_D<0>

D7

FBA_D<7>

C3

FBA_D<2>

C8

FBA_D<3>

C2

FBA_D<1>

A7

FBA_D<5>

A2

FBA_D<4>

B8

FBA_D<6>

A3

P1V5S_DGPU

B2

D9

G7

K2

K8

N1

N9

R1

R9

A1

A8

C1

C9

D2

E9

F1

H2

H9

A9

B3

E1

G8

J2

J8

M1

M9

P1

P9

T1

T9

B1

B9

D1

D8

E2

E8

F9

G1

G9

FBA_D<24:31>

26

27

24

25

31

29

28

30

FBA_D(0:7)

0

7

2

3

1

5

4

6

57F8

BI

FF

BI

E

D

C

B

P1V5S_DGPU

P1V5S_DGPU

0.01UF_50V_2

21

P1V5S_DGPU

0.01UF_50V_2

21

1.33K_1%_2

21

1.33K_1%_2

2121 21

21

R5105

162_1%_2

62F8 62F4 61F8 57E5 57B7 57A7

R5101

C5156R5102

R5103

C5157

62F4
57E5

FBA_CMD<30:0>

57A7

BI

57B7
61F3
62F8

E

D

57C5

61D5 61D3

61D3 61C5 57C5

57D8

57C7

C

57C7

57D8

57C7

57C7

FBA_CMD<9>

9

FBA_CMD<11>

11

FBA_CMD<8>

8

FBA_CMD<25>

25

FBA_CMD<10>

10

FBA_CMD<24>

24

FBA_CMD<22>

22

FBA_CMD<7> FBA_D<20>

7

FBA_CMD<21>

21

FBA_CMD<6>

6

FBA_CMD<29>

29

FBA_CMD<23>

23

FBA_CMD<28>

28

FBA_CMD<20>

20

FBA_CMD<4>

4

FBA_CMD<14>

14

FBA_CMD<12>

12

FBA_CMD<27>

27

FBA_CMD<26>

26

FBA_CMD<2>

2

FBA_CMD<0>

0

FBA_CMD<30>

30

FBA_CMD<15>

15

FBA_CMD<13>

13

FBA_CMD<5>

5

FBA_CMD<3>

3

FBA_CLK0_DP

IN

FBA_CLK0_DN

IN

FBA_DQM<1>

BI

FBA_DQS1_DP

BI

FBA_DQS1_DN

BI

FBA_DQM<2>

BI

FBA_DQS2_DP

BI

FBA_DQS2_DN

BI

R5100

21

243_1%_2

B

61E5 61B3

61D5 61B3

FBA_VREFDQ0

IN

FBA_VREFCA0

IN

U5003

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10_AP

R7

A11

N7

A12_BC#

T3

A13

T7

A14_NC

M7

A15

M2

BA0

N8

BA1

M3

BA2

K1

ODT

L2

CS#

J3

RAS#

K3

CAS#

L3

WE#

T2

RESET#

K9

CKE

J7

CK

K7

CK#

D3

DMU

C7

DQSU

B7

DQSU#

E7

DML

F3

DQSL

G3

DQSL#

L8

ZQ

J1

NC_J1

L1

NC_L1

J9

NC_J9

L9

NC_L9

H1

VREFDQ

M8

VREFCA

HYNIX_H5TQ2G63BFR_12C_FBGA_96P

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

VDD_B2

VDD_D9

VDD_G7

VDD_K2

VDD_K8

VDD_N1

VDD_N9

VDD_R1

VDD_R9

VDDQ_A1

VDDQ_A8

VDDQ_C1

VDDQ_C9

VDDQ_D2

VDDQ_E9

VDDQ_F1

VDDQ_H2

VDDQ_H9

VSS_A9

VSS_B3

VSS_E1

VSS_G8

VSS_J2

VSS_J8

VSS_M1

VSS_M9

VSS_P1

VSS_P9

VSS_T1

VSS_T9

VSSQ_B1

VSSQ_B9

VSSQ_D1

VSSQ_D8

VSSQ_E2

VSSQ_E8

VSSQ_F9

VSSQ_G1

VSSQ_G9

FBA_D<21>

F7

FBA_D<16>

F2

FBA_D<19>

F8

FBA_D<22>

H3

FBA_D<23>

H8

FBA_D<17>

G2

H7

FBA_D<12>

D7

FBA_D<9>

C3

FBA_D<14>

C8

FBA_D<11>

C2

FBA_D<13>

A7

FBA_D<10>

A2

FBA_D<15>

B8

FBA_D<8>

A3

P1V5S_DGPU

B2

D9

G7

K2

K8

N1

N9

R1

R9

A1

A8

C1

C9

D2

E9

F1

H2

H9

A9

B3

E1

G8

J2

J8

M1

M9

P1

P9

T1

T9

B1

B9

D1

D8

E2

E8

F9

G1

G9

FBA_D<18>

E3

18

21

16

19

22

23

17

20

12

9

14

11

13

10

15

8

FBA_D<16:23>

FBA_D<8:15>

57F8

BI

57F8

BI

FBA_VREFDQ0

61B361B8

IN

1.33K_1%_2

61D8 61D3 57C5

61D3 61C8 57C5

FBA_VREFCA0

IN

R5104

1.33K_1%_2

FBA_CLK0_DP

IN

FBA_CLK0_DN

IN

61B8 61B3

P1V5S_DGPU

C5158

C5159

C5160

C5161

C5162

C5150

21

A

21

0.1UF_16V_2

0.1UF_16V_2

21

21

0.1UF_16V_2

8

21

21

1UF_6.3V_2

0.1UF_16V_2

1UF_6.3V_2

76543

21

21

0.1UF_16V_2

0.1UF_16V_2

CHANGE by

XXX 21-OCT-2002

21

0.1UF_16V_2

C5155

C5154

C5153

C5152

C5151

C5163

21

21

21

1UF_6.3V_2

0.1UF_16V_2

DATE

1UF_6.3V_2

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

1310xxxxx-0-0

C

CS

SHEET

21

61 66

A

REV

X01

of

8

61F8
57E5

FBA_CMD<30:0>

57A7

BI

57B7
61F3
62F4

9

11

8

25

10

24

22

7

21

6

29

23

28

20

4

14

FBA_CMD<9>

FBA_CMD<11>

FBA_CMD<8>

FBA_CMD<25>

FBA_CMD<10>

FBA_CMD<24>

FBA_CMD<22>

FBA_CMD<7>

FBA_CMD<21>

FBA_CMD<6>

FBA_CMD<29>

FBA_CMD<23>

FBA_CMD<28>

FBA_CMD<20>

FBA_CMD<4>

FBA_CMD<14>

E

FBA_CMD<12>

12

FBA_CMD<27>

27

FBA_CMD<26>

26

FBA_CMD<18>

18

FBA_CMD<16>

16

FBA_CMD<30>

30

FBA_CMD<15>

15

FBA_CMD<13>

13

D

62D5 62D3 57C5

62D3 62C5 57C5

57D8

57C7

57C7

62E5 62B3

62D5 62B3

57D8

57C7

57C7

C

B

FBA_CMD<5>

5

FBA_CMD<19>

19

FBA_CLK1_DP

IN

FBA_CLK1_DN

IN

FBA_DQM<7>

BI

FBA_DQS7_DP

BI

FBA_DQS7_DN

BI

FBA_DQM<4>

BI

FBA_DQS4_DP

BI

FBA_DQS4_DN

BI

R5107

21

243_1%_2

FBA_VREFDQ1

IN

FBA_VREFCA1

IN

7654321

BI

62D8 62D5 57C5

62D8 62C5 57C5

FBA_CMD(30:0)

57D8

57C7

57C7

57D8

57C7

57C7

62E5 62B8

62D5 62B8

FBA_CMD<9>

9

FBA_CMD<11>

11

FBA_CMD<8>

8

FBA_CMD<25>

25

FBA_CMD<10>

10

FBA_CMD<24>

24

FBA_CMD<22>

22

FBA_CMD<7>

7

FBA_CMD<21>

21

FBA_CMD<6>

6

FBA_CMD<29>

29

FBA_CMD<23>

23

FBA_CMD<28>

28

FBA_CMD<20>

20

FBA_CMD<4>

4

FBA_CMD<14>

14

FBA_CMD<12>

12

FBA_CMD<27>

27

FBA_CMD<26>

26

FBA_CMD<18>

18

FBA_CMD<16>

16

FBA_CMD<30>

30

FBA_CMD<15>

15

FBA_CMD<13>

13

FBA_CMD<5>

5

FBA_CMD<19>

19

FBA_CLK1_DP

IN

FBA_CLK1_DN

IN

FBA_DQM<6>

BI

FBA_DQS6_DP

BI

FBA_DQS6_DN

BI

FBA_DQM<5>

BI

FBA_DQS5_DP

BI

FBA_DQS5_DN

BI

R5111

21L8

243_1%_2

FBA_VREFDQ1

IN

FBA_VREFCA1

IN

U5006U5005

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10_AP

R7

A11

N7

A12_BC#

T3

A13

T7

A14_NC

M7

A15

M2

BA0

N8

BA1

M3

BA2

K1

ODT

L2

CS#

J3

RAS#

K3

CAS#

L3

WE#

T2

RESET#

K9

CKE

J7

CK

K7

CK#

D3

DMU

C7

DQSU

B7

DQSU#

E7

DML

F3

DQSL

G3

DQSL#

ZQ

J1

NC_J1

L1

NC_L1

J9

NC_J9

L9

NC_L9

H1

VREFDQ

M8

VREFCA

HYNIX_H5TQ2G63BFR_12C_FBGA_96P

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

VDD_B2

VDD_D9

VDD_G7

VDD_K2

VDD_K8

VDD_N1

VDD_N9

VDD_R1

VDD_R9

VDDQ_A1

VDDQ_A8

VDDQ_C1

VDDQ_C9

VDDQ_D2

VDDQ_E9

VDDQ_F1

VDDQ_H2

VDDQ_H9

VSS_A9

VSS_B3

VSS_E1

VSS_G8

VSS_J2

VSS_J8

VSS_M1

VSS_M9

VSS_P1

VSS_P9

VSS_T1

VSS_T9

VSSQ_B1

VSSQ_B9

VSSQ_D1

VSSQ_D8

VSSQ_E2

VSSQ_E8

VSSQ_F9

VSSQ_G1

VSSQ_G9

FBA_D<43>

F7

FBA_D<44>

F2

FBA_D<41>

F8

FBA_D<47>

H3

FBA_D<40>

H8

FBA_D<46>

G2

FBA_D<45>

H7

FBA_D<51>

D7

FBA_D<53>

C3

FBA_D<48>

C8

FBA_D<54>

C2

FBA_D<49>

A7

FBA_D<55>

A2

FBA_D<50>

B8

FBA_D<52>

A3

P1V5S_DGPU

B2

D9

G7

K2

K8

N1

N9

R1

R9

A1

A8

C1

C9

D2

E9

F1

H2

H9

A9

B3

E1

G8

J2

J8

M1

M9

P1

P9

T1

T9

B1

B9

D1

D8

E2

E8

F9

G1

G9

FBA_D<42>

E3

FBA_D(40:47)

42

43

44

41

47

40

46

45

FBA_D(48:55)

51

53

48

54

49

55

50

52

57F8

BI

57F8

BI

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10_AP

R7

A11

N7

A12_BC#

T3

A13

T7

A14_NC

M7

A15

M2

BA0

N8

BA1

M3

BA2

K1

ODT

L2

CS#

J3

RAS#

K3

CAS#

L3

WE#

T2

RESET#

K9

CKE

J7

CK

K7

CK#

D3

DMU

C7

DQSU

B7

DQSU#

E7

DML

F3

DQSL

G3

DQSL#

L8

ZQ

J1

NC_J1

L1

NC_L1

J9

NC_J9

L9

NC_L9

H1

VREFDQ

M8

VREFCA

HYNIX_H5TQ2G63BFR_12C_FBGA_96P

62F8 61F8 61F3 57E5 57B7 57A7

21

21

FBA_CLK1_DP

FBA_CLK1_DN

P1V5S_DGPU

R5108

1.33K_1%_2

2121

C5170R5156

0.01UF_50V_2

P1V5S_DGPU

R5109

1.33K_1%_2

2121

C5171R5160

0.01UF_50V_2

21

R5110

162_1%_2

FBA_D<36>

E3

DQL0

FBA_D<34>

F7

DQL1

FBA_D<33>

F2

DQL2

FBA_D<38>

F8

DQL3

FBA_D<35>

H3

DQL4

FBA_D<37>

H8

DQL5

FBA_D<32>

G2

DQL6

FBA_D<39>

H7

DQL7

D7

FBA_D<62>

DQU0

C3

FBA_D<61>

DQU1

C8

FBA_D<58>

DQU2

C2

FBA_D<60>

DQU3

A7

FBA_D<63>

DQU4

A2

FBA_D<56>

DQU5

B8

FBA_D<59>

DQU6

A3

FBA_D<57>

DQU7

VDD_B2

VDD_D9

VDD_G7

VDD_K2

VDD_K8

VDD_N1

VDD_N9

VDD_R1

VDD_R9

VDDQ_A1

VDDQ_A8

VDDQ_C1

VDDQ_C9

VDDQ_D2

VDDQ_E9

VDDQ_F1

VDDQ_H2

VDDQ_H9

VSS_A9

VSS_B3

VSS_E1

VSS_G8

VSS_J2

VSS_J8

VSS_M1

VSS_M9

VSS_P1

VSS_P9

VSS_T1

VSS_T9

VSSQ_B1

VSSQ_B9

VSSQ_D1

VSSQ_D8

VSSQ_E2

VSSQ_E8

VSSQ_F9

VSSQ_G1

VSSQ_G9

P1V5S_DGPU

B2

D9

G7

K2

K8

N1

N9

R1

R9

A1

A8

C1

C9

D2

E9

F1

H2

H9

A9

B3

E1

G8

J2

J8

M1

M9

P1

P9

T1

T9

B1

B9

D1

D8

E2

E8

F9

G1

G9

36

34

33

38

35

37

32

39

62

61

58

60

63

56

59

57

FBA_D<32:39>

FBA_D(56:63)

57F8

BI

57F8

BI

IN

FBA_VREFDQ1

62B8 62B3

1.33K_1%_2

IN

FBA_VREFCA1

62B8 62B3

1.33K_1%_2

62D8 62D3 57C5

62D8 62D3 57C5

IN

IN

FF

E

D

C

B

P1V5S_DGPU

C5164

21

0.1UF_16V_2

21

21

0.1UF_16V_2

0.1UF_16V_2

21

21

0.1UF_16V_2

1UF_6.3V_2

21

1UF_6.3V_2

C5169

C5168

C5167

C5166

C5165

A

8

76543

P1V5S_DGPU

C5172

21

0.1UF_16V_2

C5173

21

0.1UF_16V_2

C5174

21

0.1UF_16V_2

CHANGE by

C5175

21

0.1UF_16V_2

C5176

21

1UF_6.3V_2

C5177

21

1UF_6.3V_2

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

1310xxxxx-0-0

DATE

21-OCT-2002XXX

21

CSC

SHEET

A

REV

X01

of

66

62

8

7654321

64F8 64F4
57B3 57A3
63F4 57E1

E

D

C

B

BI

63D3 63C5 57C2

63D3 63C5 57C2

FBC_CMD<30:0>

57D4

57C4

57C4

57D4

57C4

57C4

63D6 63B3

63E6 63B3

64F8 64F4 63F8 57E1 57B3 57A3

FBC_CMD<9>

9

FBC_CMD<11>

11

FBC_CMD<8>

8

FBC_CMD<25>

25

FBC_CMD<10>

10

FBC_CMD<24>

24

FBC_CMD<22>

22

FBC_CMD<7>

7

FBC_CMD<21>

21

FBC_CMD<6>

6

FBC_CMD<29>

29

FBC_CMD<23>

23

FBC_CMD<28>

28

FBC_CMD<20>

20

FBC_CMD<4>

4

FBC_CMD<14>

14

FBC_CMD<12>

12

FBC_CMD<27>

27

FBC_CMD<26>

26

FBC_CMD<2>

2

FBC_CMD<0>

0

FBC_CMD<30>

30

FBC_CMD<15>

15

FBC_CMD<13>

13

FBC_CMD<5>

5

FBC_CMD<3>

3

FBC_CLK0_DP

IN

FBC_CLK0_DN

IN

FBC_DQM<0>

BI

FBC_DQS0_DP

BI

FBC_DQS0_DN

BI

FBC_DQM<3>

BI

FBC_DQS3_DP

BI

FBC_DQS3_DN

BI

R5112

21

243_1%_2

FBC_VREFCA0

IN

FBC_VREFDQ0

IN

U5007

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10_AP

R7

A11

N7

A12_BC#

T3

A13

T7

A14_NC

M7

A15

M2

BA0

N8

BA1

M3

BA2

K1

ODT

L2

CS#

J3

RAS#

K3

CAS#

L3

WE#

T2

RESET#

K9

CKE

J7

CK

K7

CK#

D3

DMU

C7

DQSU

B7

DQSU#

E7

DML

F3

DQSL

G3

DQSL#

L8

ZQ

J1

NC_J1

L1

NC_L1

J9

NC_J9

L9

NC_L9

H1

VREFDQ

M8

VREFCA

HYNIX_H5TQ2G63BFR_12C_FBGA_96P

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD_B2

D9

VDD_D9

G7

VDD_G7

K2

VDD_K2

K8

VDD_K8

N1

VDD_N1

N9

VDD_N9

R1

VDD_R1

R9

VDD_R9

A1

VDDQ_A1

A8

VDDQ_A8

C1

VDDQ_C1

C9

VDDQ_C9

D2

VDDQ_D2

E9

VDDQ_E9

F1

VDDQ_F1

H2

VDDQ_H2

H9

VDDQ_H9

A9

VSS_A9

B3

VSS_B3

E1

VSS_E1

G8

VSS_G8

J2

VSS_J2

J8

VSS_J8

M1

VSS_M1

M9

VSS_M9

P1

VSS_P1

P9

VSS_P9

T1

VSS_T1

T9

VSS_T9

B1

VSSQ_B1

B9

VSSQ_B9

D1

VSSQ_D1

D8

VSSQ_D8

E2

VSSQ_E2

E8

VSSQ_E8

F9

VSSQ_F9

G1

VSSQ_G1

G9

VSSQ_G9

FBC_D<24>

FBC_D<25>

FBC_D<26>

FBC_D<30>

FBC_D<28>

FBC_D<29>

FBC_D<27>

FBC_D<31>

FBC_D<6>

FBC_D<5>

FBC_D<0>

FBC_D<1>

FBC_D<3>

FBC_D<7>

FBC_D<2>

FBC_D<4>

P1V5S_DGPU

FBC_D<24:31>

24

25

26

30

28

29

27

31

6

5

0

1

3

7

2

4

FBC_D<0:7>

57F4

BI

BI

63B8 63B3

63B8 63B3

63D8 63D3 57C2

63D8 63D3 57C2

57F4

P1V5S_DGPU

R5113

1.33K_1%_2

21

2121

C5184R5114

0.01UF_50V_2

IN

FBC_VREFDQ0

1.33K_1%_2

P1V5S_DGPU

R5115

1.33K_1%_2

21

2121

C5185R5116

0.01UF_50V_2

21

R5117

162_1%_2

IN

FBC_VREFCA0

1.33K_1%_2

IN

IN

FBC_CLK0_DP

FBC_CLK0_DN

FBC_CMD<30:0>

BI

63D8 63C5 57C2

63D8 63C5 57C2

63E6 63B8

63D6 63B8

FBC_CMD<9> FBC_D<19>

9

FBC_CMD<11>

11

FBC_CMD<8>

8

FBC_CMD<25>

25

FBC_CMD<10>

10

FBC_CMD<24>

24

FBC_CMD<22>

22

FBC_CMD<7>

7

FBC_CMD<21>

21

FBC_CMD<6>

6

FBC_CMD<29>

29

FBC_CMD<23>

23

FBC_CMD<28>

28

FBC_CMD<20>

20

FBC_CMD<4>

4

FBC_CMD<14>

14

FBC_CMD<12>

12

FBC_CMD<27>

27

FBC_CMD<26>

26

FBC_CMD<2>

2

FBC_CMD<0>

0

FBC_CMD<30>

30

FBC_CMD<15>

15

FBC_CMD<13>

13

FBC_CMD<5>

5

FBC_CMD<3>

3

FBC_CLK0_DP

IN

FBC_CLK0_DN

IN

FBC_DQM<1>

57D4

BI

FBC_DQS1_DP

57C4

BI

57C4

57D4

57C4

57C4

FBC_DQS1_DN

BI

FBC_DQM<2>

BI

FBC_DQS2_DP

BI

FBC_DQS2_DN

BI

R5118

21

243_1%_2

FBC_VREFDQ0

IN

FBC_VREFCA0

IN

U5008

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10_AP

R7

A11

N7

A12_BC#

T3

A13

T7

A14_NC

M7

A15

M2

BA0

N8

BA1

M3

BA2

K1

ODT

L2

CS#

J3

RAS#

K3

CAS#

L3

WE#

T2

RESET#

K9

CKE

J7

CK

K7

CK#

D3

DMU

C7

DQSU

B7

DQSU#

E7

DML

F3

DQSL

G3

DQSL#

L8

ZQ

J1

NC_J1

L1

NC_L1

J9

NC_J9

L9

NC_L9

H1

VREFDQ

M8

VREFCA

HYNIX_H5TQ2G63BFR_12C_FBGA_96P

E3

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

VDD_B2

VDD_D9

VDD_G7

VDD_K2

VDD_K8

VDD_N1

VDD_N9

VDD_R1

VDD_R9

VDDQ_A1

VDDQ_A8

VDDQ_C1

VDDQ_C9

VDDQ_D2

VDDQ_E9

VDDQ_F1

VDDQ_H2

VDDQ_H9

VSS_A9

VSS_B3

VSS_E1

VSS_G8

VSS_J2

VSS_J8

VSS_M1

VSS_M9

VSS_P1

VSS_P9

VSS_T1

VSS_T9

VSSQ_B1

VSSQ_B9

VSSQ_D1

VSSQ_D8

VSSQ_E2

VSSQ_E8

VSSQ_F9

VSSQ_G1

VSSQ_G9

FBC_D<20>

F7

FBC_D<17>

F2

FBC_D<22>

F8

FBC_D<21>

H3

FBC_D<18>

H8

FBC_D<16>

G2

FBC_D<23>

H7

FBC_D<14>

D7

FBC_D<11>

C3

FBC_D<15>

C8

FBC_D<8>

C2

FBC_D<12>

A7

FBC_D<10>

A2

FBC_D<13>

B8

FBC_D<9>

A3

P1V5S_DGPU

B2

D9

G7

K2

K8

N1

N9

R1

R9

A1

A8

C1

C9

D2

E9

F1

H2

H9

A9

B3

E1

G8

J2

J8

M1

M9

P1

P9

T1

T9

B1

B9

D1

D8

E2

E8

F9

G1

G9

FBC_D<16:23>

19

20

17

22

21

18

16

23

FBC_D<8:15>

14

11

15

8

12

10

13

9

57F4

BI

FF

57F4

BI

E

D

C

B

P1V5S_DGPU

P1V5S_DGPU

C5183

C5182

C5181

C5180

C5179

C5178

21

0.1UF_16V_2

21

21

0.1UF_16V_2

0.1UF_16V_2

21

A

8

76543

0.1UF_16V_2

21

21

1UF_6.3V_2

1UF_6.3V_2

C5186

21

0.1UF_16V_2

C5188

C5187

21

0.1UF_16V_2

C5189

21

21

0.1UF_16V_2

C5191

C5190

21

1UF_6.3V_2

0.1UF_16V_2

CHANGE by

XXX 21-OCT-2002

21

1UF_6.3V_2

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

C

DATE

21

CS

SHEET

A

REV

X011310xxxxx-0-0

of

6663

8

FBC_CMD<30:0>

57A357B357E163F463F8

BI

64F4

E

D

64C5

57C264D3

IN

57C2

64C364C5

IN

57D4

BI

57C4

BI

57C4

C

B

BI

57D4

BI

57C4

BI

57C4

BI

64B364E5

IN

64B364D5

IN

7654321

FBC_CMD<30:0>

57A357B357E163F463F864F8

BI

FBC_CMD<9>

9

FBC_CMD<11>

11

FBC_CMD<8>

8

FBC_CMD<25>

25

FBC_CMD<10>

10

FBC_CMD<24>

24

FBC_CMD<22>

22

FBC_CMD<7>

7

FBC_CMD<21>

21

FBC_CMD<6>

6

FBC_CMD<29>

29

FBC_CMD<23>

23

FBC_CMD<28>

28

FBC_CMD<20>

20

FBC_CMD<4>

4

FBC_CMD<14>

14

FBC_CMD<12>

12

FBC_CMD<27>

27

FBC_CMD<26>

26

FBC_CMD<18>

18

FBC_CMD<16>

16

FBC_CMD<30>

30

FBC_CMD<15>

15

FBC_CMD<13>

13

FBC_CMD<5>

5

FBC_CMD<19>

19

57C264C564D7

57C264C564D7

57D4

57C4

57C4

57D4

57C4

57C4

64B764E5

64B764D5

FBC_CLK1_DP

IN

FBC_CLK1_DN

IN

FBC_DQM<7>

BI

FBC_DQS7_DP

BI

FBC_DQS7_DN

BI

FBC_DQM<4>

BI

FBC_DQS4_DP

BI

FBC_DQS4_DN

BI

R5125

21

243_1%_2

FBC_VREFDQ1

IN

FBC_VREFCA1

IN

U5010

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10_AP

R7

A11

N7

A12_BC#

T3

A13

T7

A14_NC

M7

A15

M2

BA0

N8

BA1

M3

BA2

K1

ODT

L2

CS#

J3

RAS#

K3

CAS#

L3

WE#

T2

RESET#

K9

CKE

J7

CK

K7

CK#

D3

DMU

C7

DQSU

B7

DQSU#

E7

DML

F3

DQSL

G3

DQSL#

L8

ZQ

J1

NC_J1

L1

NC_L1

J9

NC_J9

L9

NC_L9

H1

VREFDQ

M8

VREFCA

HYNIX_H5TQ2G63BFR_12C_FBGA_96P

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

VDD_B2

VDD_D9

VDD_G7

VDD_K2

VDD_K8

VDD_N1

VDD_N9

VDD_R1

VDD_R9

VDDQ_A1

VDDQ_A8

VDDQ_C1

VDDQ_C9

VDDQ_D2

VDDQ_E9

VDDQ_F1

VDDQ_H2

VDDQ_H9

VSS_A9

VSS_B3

VSS_E1

VSS_G8

VSS_J2

VSS_J8

VSS_M1

VSS_M9

VSS_P1

VSS_P9

VSS_T1

VSS_T9

VSSQ_B1

VSSQ_B9

VSSQ_D1

VSSQ_D8

VSSQ_E2

VSSQ_E8

VSSQ_F9

VSSQ_G1

VSSQ_G9

FBC_D<33>

F7

FBC_D<38>

F2

FBC_D<34>

F8

FBC_D<36>

H3

FBC_D<32>

H8

FBC_D<37>

G2

FBC_D<35>

H7

FBC_D<56>

D7

FBC_D<62>

C3

FBC_D<59>

C8

FBC_D<61>

C2

FBC_D<58>

A7

FBC_D<60>

A2

FBC_D<57>

B8

FBC_D<63>

A3

P1V5S_DGPU

B2

D9

G7

K2

K8

N1

N9

R1

R9

A1

A8

C1

C9

D2

E9

F1

H2

H9

A9

B3

E1

G8

J2

J8

M1

M9

P1

P9

T1

T9

B1

B9

D1

D8

E2

E8

F9

G1

G9

FBC_D<39>

E3

39

33

38

34

36

32

37

35

56

62

59

61

58

60

57

63

FBC_D<32:39>

FBC_D<56:63>

BI

BI

9

11

8

25

10

24

22

7

21

6

29

23

28

20

4

14

12

27

26

18

16

30

15

13

5

19

FBC_CMD<9>

FBC_CMD<11>

FBC_CMD<8>

FBC_CMD<25>

FBC_CMD<10>

FBC_CMD<24>

FBC_CMD<22>

FBC_CMD<7>

FBC_CMD<21>

FBC_CMD<6>

FBC_CMD<29>

FBC_CMD<23>

FBC_CMD<28>

FBC_CMD<20>

FBC_CMD<4>

FBC_CMD<14>

FBC_CMD<12>

FBC_CMD<27>

FBC_CMD<26>

243_1%_2

FBC_CMD<18>

FBC_CMD<16>

FBC_CMD<30>

FBC_CMD<15>

FBC_CMD<13>

FBC_CMD<5>

FBC_CMD<19>

FBC_CLK1_DP

FBC_CLK1_DN

FBC_DQM<6>

FBC_DQS6_DP

FBC_DQS6_DN

FBC_DQM<5>

FBC_DQS5_DP

FBC_DQS5_DN

R5119

FBC_VREFDQ1

FBC_VREFCA1

U5009

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10_AP

R7

A11

N7

A12_BC#

T3

A13

T7

A14_NC

M7

A15

M2

BA0

N8

M3

K1

L2

J3

K3

L3

T2

K9

J7

K7

D3

C7

B7

E7

F3

G3

L8

21

J1

L1

J9

L9

H1

M8

VDD_B2

BA1

VDD_D9

BA2

VDD_G7

VDD_K2

VDD_K8

ODT

VDD_N1

CS#

VDD_N9

RAS#

VDD_R1

CAS#

VDD_R9

WE#

VDDQ_A1

VDDQ_A8

VDDQ_C1

RESET#

VDDQ_C9

CKE

VDDQ_D2

VDDQ_E9

CK

VDDQ_F1

CK#

VDDQ_H2

VDDQ_H9

DMU

VSS_A9

DQSU

VSS_B3

VSS_E1

DQSU#

VSS_G8

VSS_J2

DML

VSS_J8

VSS_M1

DQSL

VSS_M9

VSS_P1

DQSL#

VSS_P9

VSS_T1

ZQ

VSS_T9

NC_J1

VSSQ_B1

NC_L1

VSSQ_B9

NC_J9

VSSQ_D1

NC_L9

VSSQ_D8

VSSQ_E2

VSSQ_E8

VREFDQ

VSSQ_F9

VREFCA

VSSQ_G1

VSSQ_G9

HYNIX_H5TQ2G63BFR_12C_FBGA_96P

FBC_D<44>

E3

DQL0

FBC_D<46>

F7

DQL1

FBC_D<41>

F2

DQL2

FBC_D<43>

F8

DQL3

FBC_D<42>

H3

DQL4

FBC_D<47>

H8

DQL5

FBC_D<40>

G2

DQL6

FBC_D<45>

H7

DQL7

FBC_D<51>

D7

DQU0

FBC_D<54>

C3

DQU1

FBC_D<49>

C8

DQU2

FBC_D<55>

C2

DQU3

FBC_D<48>

A7

DQU4

FBC_D<53>

A2

DQU5

FBC_D<50>

B8

DQU6

FBC_D<52>

A3

DQU7

P1V5S_DGPU

B2

D9

G7

K2

K8

N1

N9

R1

R9

A1

A8

C1

C9

D2

E9

F1

H2

H9

A9

B3

E1

G8

J2

J8

M1

M9

P1

P9

T1

T9

B1

B9

D1

D8

E2

E8

F9

G1

G9

44

46

41

43

42

47

40

45

51

54

49

55

48

53

50

52

FBC_D<40:47>

FBC_D<48:55>

57F4

BI

57F4

BI

P1V5S_DGPU

R5120

1.33K_1%_2

21

2121

C5199R5121

0.01UF_50V_2

FBC_VREFDQ1

64B364B7

IN

1.33K_1%_2

P1V5S_DGPU

R5122

1.33K_1%_2

21

2121

C5198R5123

0.01UF_50V_2

21

R5124

162_1%_2

FBC_VREFCA1

64B364B7

IN

1.33K_1%_2

FBC_CLK1_DP

57C264D364D7

IN

FBC_CLK1_DN

57C264C364D7

IN

57F4

FF

57F4

E

D

C

B

P1V5S_DGPU

C5197

C5196

C5195

C5194

C5193

C5192

21

21

A

8

0.1UF_16V_2

76543

0.1UF_16V_2

21

21

0.1UF_16V_2

21

0.1UF_16V_2

21

1UF_6.3V_2

1UF_6.3V_2

P1V5S_DGPU

C5200

21

0.1UF_16V_2

C5201

21

0.1UF_16V_2

C5202

21

0.1UF_16V_2

C5204

C5203

21

21

1UF_6.3V_2

0.1UF_16V_2

CHANGE by

XXX 21-OCT-2002

C5205

21

1UF_6.3V_2

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CSC

DATE

21

1310xxxxx-0-0 X01

SHEET

64 66

A

REV

of

87

REFERENCE 9000~9999(SMALL BOARD)

65

4

32 1

D

D

POWER BUTTON

SW9000
4
5
6

MISAKI_NTC017_DA1G_E160T_6P

DGND_PWRSW_DB

AB

1
2
3

DC

2

1

3

D9000

PHP_PESD5V2S2UT_SOT23_3P_DY

C9000

1000PF_50V_2_DY

21

B

FIX9005FIX9004FIX9003FIX9002FIX9001FIX9000

1

1

FIX_MASK FIX_MASKFIX_MASKFIX_MASKFIX_MASK

FIX_MASK

1

1

1

1

PAD9000

1

PAD9001

1

SMDPAD_1P_40X120

SMDPAD_1P_40X120

CC

B

S9000

1

SCREW540_700_NP_1P

S9001
1

SCREW540_700_NP_1P

DGND_PWRSW_DB

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6665

87

65

4

32 1

D

D

CC

B

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

76

54

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

6666