Inventec Everest-M 6050A2447101 Schematic

8 7

6 5

4 3

2

1

D

D

CC

EVEREST-M

WS BULID

BB

2010.01.04

AA

INVENTEC

TITLE

EVEREST-M

COVER PAGE

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Tue Jan 04 11:08:28 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

1

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

D

TABLE OF CONTENTS

PAGE

1. COVER PAGE

2. INDEX

3. BLOCK DIAGRAM

4. SMB DIAGRAM

5. POWER SEQUENCE BLOCK

6. POWER FLOW

7. PCB SCREW

8. POWER CHARGER

9. POWER BATTERY

10. POWER +3A/+5A

11. POWER +V1.5/+V0.75S

12. POWER VCCP/+V1.05_LAN_M

13. POWER +V0.85S/+V1.8S

14. POWER VCORE

15. POWER VCORE

16. POWER GPU NVVDD

17. POWER +V3S/+V5S/+V1.5S

18. POWER SEQ

19. POWER SEQ

20. CPU 1

21. CPU 2

22. CPU 3 DRAM

23. CPU 4 POWER

24. CPU 5 POWER

25. CPU 6 GND

26. DDR3 DIMM0

27. DDR3 DIMM1

PAGE

28. PCH 1

29. PCH 2

30. PCH 3

31. PCH 4 AXG

32. PCH 5 USB

33. PCH 6 MISC

34. PCH 7 POWER

35. PCH 8 POWER

36. PCH 9 GND

37. EC

38. FAN & THERMAL

39. LAN

40. RJ45 & TRANSFORMER

41. AUDIO CODEC

42. AUDIO AMP

43. TPM

44. LCM CONN

45. CRT CONN

46. HDMI CONN

47. DP CONN

48. eDP CONN

49. DB CONN USB & CARDREADER

50. SATA HDD/SSD & ODD CONN

51. E-SATA CONN

52. USB CONN

53. K/B & TP/B CONN

54. BLUETOOTH CONN

PAGE

55. MINI1 WLAN/Debug Card

56. MINI2 3G

57. HALL SENSOR

58. LED

59. CLOCK GENERATOR

60. XDP

61. ME JTAG

62. PICK BUTTON BOARD

63. TOUCH PAD SW BOARD

64. POWER BUTTON BOARD

65. CARDREADER & USB BOARD

66. EMI

67. GPU SW/POWER

68. GPU-1

69. GPU-2

70. GPU-3

71. GPU-4

72. GPU-5

73. VRAM

74. VRAM

75. VRAM

76. VRAM

CC

BB

AA

INVENTEC

TITLE

EVEREST-M
INDEX

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Mon Dec 27 16:49:48 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

2

of

1

REV

97

A01

EDP

3D PANEL

15.6 WXGA LED

78

56

34

2

1

IVY BRIDGE

DDR3@1.5/0.75V

(1600MHZ)

204-PIN SODIMM X2
MAX MEMORY 8GB X2

MUX

PERICOM

eDP

eDP

QC 45W OR DC 35W

VT & TXT

SOCKET-RPGA989

37.5 X 37.5 X 5 mm

DUAL CHANNEL

D

VRAM*4(64Mb*32)

TOTAL:1GB GDDR5

HDR

HDMI 1.4

HDMI

AMD

ATI WHISTLER XT

35W

PEGX16

FDI

DMI 2.0

JTAG

JTAG

60-PIN CPU XDP

(TEST ONLY)

60-PIN PCH XDP

(TEST ONLY)

29MM X 29MM

HDR
VGA

C C

HDR(DONGLE)

HDMI 1.4

RJ45

B B

SIM CARD

CONNECTOR

RGB

R

RGB

R

HDR

DISPLAYPORT 1.1

(TEST ONLY)

HDR

LVDS

(TEST ONLY)

Gbe Phy

(100/1000)

LEWISVILLE

INTEL 82579LM_BAM271

PCIE_3: WIFI
PCIE_4: 3G/mSATA

DP

LVDS

PCIE_6

PCIE

PCH

COUGAR POINT

TDP 3.9W

25 X 25 X 2.3 mm

JTAG

HDA

SPI

USB 2.0

LS

AUDIO CODEC

REALTEK

ALC269Q_VC

SPI FLASH 8MB

WINB_W25Q64BVSSIG

RJ-11ME JTAG

INTERNAL MIC IN

EXT MIC IN
HEADPHONE/LINEOUT

USB_0 RESERVE FOR USB3.0
USB_2 RESERVE FOR USB3.0
USB_1 eSATA PORT
USB_5 Minicard WLAN
USB_10 Webcam

USB_12 Bluetooth
USB_13 Minicard 3G

HDR

(TEST ONLY)

D

USB 3.0

TI_TUSB7320

PCIE_1

SATA

USB3.0

LPC

CONN A

A A

CONN B

CARD READER

RTS5209

PCIE_2

SPI

EC WINDBOND

BATTERY CHARGER &

NPCE791LA0DX

TPM V1.2

SLB9635TT1.2_FW3.17

SPI Flash 1MB

WINB_W25Q80BVSSIG

SATA3_0: SSD
SATA3_1: HDD
SATA2_2: ZERO POWER ODD
SATA2_3: eSATA
SATA2_4: mSATA

DC/DC & IMVP 7
LI-ION BATTERY

6-Cell

8

TOUCH PADKEYBOARD

CHANGE by

67

45

3

Frank Hu

Mon Dec 27 16:50:03 2010

DATE

2

INVENTEC

TITLE

EVEREST-M

BLOCK DIAGRAM

SIZE

C

CODE

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

3

of

1

REV

97

A01

8 7

6 5

4 3

2

1

+V3A

+V5S

RES 2.2K

D

SMB_CLK

SMB_DATA

RES 2.2K

SMB_CLK
SMB_DATA

RES 2.2K

SSM3K7002

SSM3K7002

+V3S

RES 2.2K

SMB_CLK_S2

SMB_DATA_S2

CK505

SO-DIMM 0 SO-DIMM 1

PCIE

1

USB3.0_TUSB7320

2

CardReader_RTS5209

WLAN

3

MINICARD3G

4

NC

5

LAN

6
7

NC

8

NC

SATA

01SSD

HDD

2

ODD
eSATA

3
4

mSATA

NC

5

D

XDP

PCH

SML0CLK
SML0DATA

SML0_CLK

SML0_DATA

RES 2.2K

+V3A

RES 2.2K

LEWISVILLE

LAN PHY

SMB_CLK_S3
SMB_DATA_S3

SMB_CLK_A1
SMB_DATA_A1

PEG

MINICARD

WIFI

MINICAR

3G

SCL1

SDA1

RES 3.3K RES 3.3K

EC_SMB1_CLK

EC_SMB1_DATA

+V3LA

0

1
2
3

4

5
6

7
8

9

10

11

12

13

BATTERY

USB

Reserve for USB3.0
eSATA

Reserve for USB3.0

NC
NC
MINICARD WLAN

NC

NC
NC
NC
WEBCAM
NC

BLUE TOOTH

MINICARD 3G

CC

BB

SML1CLK

SML1DATA

8

SML1_CLK

SML1_DATA

RES 2.2K

7 6

+V3A

RES 2.2K

+V3A

SSM3K7002

SSM3K7002

RES 2.2K

+V3LA

RES 2.2K

EC_SMB3_CLK

EC_SMB3_DATA

5 4

EC

SCL2

SDA2

RES 1.8K

EC_SMB2_CLK

EC_SMB2_DATA

+V3LA

3

RES 1.8K

CHANGE by

Frank Hu

Mon Dec 27 16:50:16 2010

DATE

2

CHARGE IC

THERMAL IC

GPU THERMAL

INVENTEC

TITLE

EVEREST-M
SMB DIAGRAM

CODE

SIZE

CS

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

4

of

1

AA

REV

97

A01

8 7

6 5

4 3

2

1

+V3LA

SLP_S3#_5R

+V3S

PC6014

AM4825P

D

ADAPTER

PMOS

0.01 OHM
AM4825P

ADP_PRES

KBC_PW_ON

5/3.3V

(TPS51125)

PMOS

+VPACK

VO

BATT_CLK

BATT_DATA

CHARGER

SCL
SDA

ACOK

0.01 OHM

ACIN#

TPS51218

EN_PSV

+V5A

+V1.5

+V1.05S

PC6014

G2997

PC6014

SLP_S3#_5R

SLP_S3#_5R

SLP_S5#_5R

+V5S

D

+V0.75S

+V1.5S

CC

+GFX_VDD

+V0.85S

GFX_VDD_PG

VCCSA_PG

PGOOD

TPS51217

D0

EN_PSV

EN

VCCDRE_EN

VR_SVID_DATA

VR_SVID_CLK

VR_SVID_ALRT#

VTT_SELECT

VR_ON
VDIO
VCLK
ALERT#

TPS51218

EN_PSV

TPS51218

D0

EN_PSV

MAX17039

VO

VO

VR_HOT#

VOUT

VO

+V1.05_VCCP

H_PROCHOT#

VR_PWRGD
+GFX_PWRGD

+VCC_CORE

+VGFX

BB

AA

INVENTEC

TITLE

EVEREST-M

POWER SEQUENCE BLOCK

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Mon Dec 27 16:50:27 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

5

of

1

REV

97

A01

8 7

6 5

EVEREST PWROWSEQUENCE

4 3

2

1

VADPTR (-7START)

D

V5LA

VCC

MAX_MAX17435ETG

ACIN
ACOK#

ACPRES

ACPRES

NMOS

EN

EC_PW_ON

(-2)

V3A(-1)

AM3423E

(0)

PWR_SWIN#_3

EC_PCH_PWROK

8

VPACK

VBAT (-6)

NMOS

GPIO03

GPIO75

GPIO01

GPO84_XORTR#

(15)

VBAT

VSEN

VCC

GMT_G686LT11U

RESET#

LRESET#

GPIO36

GPIO50_TD0

GPIO43_TMS

GPIO32_D_PWM

PSDAT2_GPIO27

DAO_GPIO94

DA2_GPIO96

GPIO02

99ms

EC

GPO82_TEEST#

EC_DGPU_PWR_EN#

(13)

V5A

VIN

SEMTECH

SC475A

EN

7 6

VBAT

VCC

V5LA (-5)

(-4)

+V5AUXON

PLT_RST# (21)

EC_PWRSW# (2)

(1)

RSMRST#

SLP_S5#_3R

SLP_S4#_3R (3)

SLP_LAN#_3R (4)

SLP_A_3R (5)

SLP_S3#_3R (6)

(12)

MAIN_PWRGD

SLP_A_3R

INVERTER

SLP_S3_5R

INVERTER

V5A

VIN

AM3423P

EN

V1.5

VIN

AO4406

EN

(14)

GPU_VDD

V1.5

VIN

EN

PLERST#

SLP_LAN#_3R (4)

SLP_S3#_5R

(8)

V1.5_CPU

AM4430N

PWRBTN#

RSMRST#

SLP_S5#

SLP_S4#

SLP_LAN#

SLP_A#

SLP_S3#

V5A

VIN

TPS51218DSCR

EN

VIN

G5694F11U

EN

(7)

V5S

SLP_A_3R (5M)

(14)

GPU_1.5S

VBAT

EN2

TI_TPS51125

EN1

XDPLAN

RST#RST#

V02

V01

VREG5

VGA

RST#

PCH

VBAT

VCC

PGD

V3A

VCC

PGD

V3LA

VIN

AM3423P

EN

V1.5

VIN

AO4406

EN

(3A)

V1.5

V5A

V1.5_PG

V1.05_LAN_M (4A)

V1.05S_VCCP

(7)

V3S

(8)

V1.5S V3.3M (4A)

PGD

V1.05S

VIN

EN

AM4430N

GPU_1.5S

5 4

V3LA (-3)

V5A (-1)

V5LA (-5)

BUFFER

VIN

GMT_G2997F6U

EN

VIN

EN

VIN

AO4406

EN

V1.05_LAN_VR_PWRGD

AND GATE

V3S

(14)

VIN

EN

BUF_PLT_RST#

DRAMPWROK

PROCPWRGD

SYS_PWROK

VCC

AM3423P

PWROK

APWROK

(3B)

(5A)

(11)

MINICARD X2

RST#

PM_DRAM_PWRGD (20)

H_CPUPWRGD (16)

EC_PCH_PWROK (15)

VCORE

PM_APWROK (5B)

M_VREF

V0.75S

V3A

V1.05M

(7)

V1.05S

(5A)

EN

(14)

GPU_V3S

VIN

AM3423PAO4406

EN

VIN

GMT

G5694F11U

AND GATE

CHANGE by

3

ALLSYS_PWROK (19)

IMVP7

(4A)

V3.3M

VDDR_PWRGD

(7)
V1.8S

PM_APWROK (5B)

Frank Hu

RSTIN#

SM_DRAMPWROK

SM_DRAMPWROK

VCORE_PWRGOOD (18)

SVID

EN

PWRGD

AND GATE

AND GATE

Mon Dec 27 16:50:39 2010

DATE

2

TPM

RST#

CPU

CLK

EN

V0.85S

V1.05S_VCCP

(9)

SLP_S3#3R

INVENTEC

TITLE

EVEREST-M
POWER FLOW

CODE

SIZE

C

CS

SHEET

VCORE

SVID

SVID

AND

GATE

PGD

TI

TPS51218DSCR

TI

TPS51218DSCR

+V1.05S_VCCP_EN

AND GATE

DOC.NUMBER

CS_1310AXXXXXX-MTR

6

of

1

(17)

EN

(11)

PGD
EN

97

(10)

REV

A01

D

CC

BB

AA

8 7

6 5

4 3

2

1

FIX1

1

FIX_MASK

D

1

1

1

FIX2

1

FIX_MASK FIX_MASK

S1

SCREW330_600_800_1P

S24

SCREW300_700_1P

S3

SCREW300_1000_1P

S14

FIX3

1

FIX4

1

FIX_MASK FIX_MASK

S10

SCREW330_600_800_1P

1

S4

SCREW300_1000_1P

1

S12

SCREW300_1000_1P

1

FIX5

1

FIX6

1

FIX_MASK

S18

SCREW330_600_800_1P

1

S20

SCREW300_1000_1P

1

FIX_MASK

FIX7

1

FIX8

1

FIX_MASK

1

S22

SCREW330_600_800_1P

S23
SCREW300_1000_1P

1

CPU

S25

SCREW500_1000_1P

1

S26

SCREW300_1000_1P

1

D

MB

CC

SCREW120_500_0_1P

1

S7

SCREW120_0_500_1P

1

S17

SCREW120_0_500_1P

1

S9

SCREW320_500_400_1P

1

MINI CARD

S16

SCREW120_0_500_1P

1

S27

SCREW120_0_500_1P

1

S11
SCREW320_500_400_1P

1

FAN

PCH

S19
SCREW320_500_400_1P

1

S33
SCREW320_500_400_1P

1

BB

GPU

AA

INVENTEC

TITLE

EVEREST-M

PCB SCREW

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:56 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

7

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

NFE31PT222Z1E9L

1

L6001

4

3

(OVP MAX : 24.67V)

(OVP MIN : 23.106V)

45.3K_1%_2

(1.68V)

4.3K_1%_3

2

D6004

1

R6012

2

1

R6013

12.6V : 3140H

1

2

2

C6028

0.1UF_25V_3

0X15

8.4V : 40D0H

16.8V : 41A0H

1

R6017
RSC_0603_DY

2

1

R6018
RSC_0603_DY

2

D

G1

G2

ACES_91302_0047L_1_4P

8A_125V

CN6000

G1

G2

1

1

2

2

3

3

4

4

FUSE6000

1

1000PF_50V_2

2

1

C6035

2

1
2

C6033

10PF_50V_2

C6003

CSC0402_DY

1

2

R6019

1

RSC_0402_DY

2

NEAR EC

3A

R6005

4.7K_5%_3

2

1

Q6003

1

S

1

R6042

2

1 1

DIODES_SMAJ20A_13_F_2P

0_5%_2_DY

2
3
4 5

2

R6008

10K_5%_2

G

NMOS_4D3S

AM4410NC

0_5%_2

1

2

R6043

8

D

7
6

2

3

8>

0X14

512MA : 0200H_512MA

1.5A : 0600H_1.54A
3A : 0C00H_3.07A

1

D6001
BAT54C_30V_0.2A

17435_LDO

A1

OUT

10_5%_2

C

R6014

TP6002

8

D

7
6

NMOS_4D3S

1

R6036

150_5%_3

2

3

Q6004

DS

SSM3K7002BFU

2

A2

1

1UF_10V_2

2

Q6002

S

G

AM4410NC

NEAR IC

R6016

1

10_5%_5

1

G

2

1

1

C6025

2

1
2
3
45

2

IN

R6007

10K_5%_2

1

2

C6022

1UF_10V_2

1

0.1UF_25V_2

2

2

C6021

1UF_10V_2

C6811

P_GATE

3

1
2

R6020

0.01_1%_6

C6029

1

1UF_25V_3

1

4.7_5%_3

CHG_HG
CHG_SW
CHG_LG

0.01UF_50V_2

1

2

2
43

CHG_VBAT_SEN_N

1

2

2

R6000

2

C6007

1

C6008

0.1UF_16V_2

2

R6010
1K_1%_2

0.1UF_25V_3

1

2

C6006

1

2

FDMC8884

2

1

C6813

0.1UF_25V_2_DY

C6026

0.1UF_16V_2

Q6000

1

C6814

CSC0402_DY

2

1

2

2

2

PAD6000

1

POWERPAD_2_0610

1

2A

5 6 7 8

NMOS_4D3S

G

3 214

5 6 7 8

NMOS_4D3S

G

3 214

NEAR EC

D

S

D

S

1

2

Q6001
FDMC8884

D6003

SBR3U40P1

C6002

0.1UF_25V_3

1

2

R6044

1
1

0_5%_2_DY

1

C6005

4.7UF_25V_5

2

1

2

1

C6009

2

R6045

R6004

4.7_5%_3

2200PF_50V_2

RSC_0402_DY

0_5%_2

2
2

1

C6001

2

PCMC063T_3R3MN

1

1

1

C6030

1

0.1UF_25V_2

2

1

C6023

2

1UF_25V_3

2

D6000

BAV99

C6812

0.01UF_25V_2_DY

2

14

16

15

3

CHG_VBAT_SEN_P

1

DCIN

PDSL

CSSP

CSSN

19

ACIN

10

ACOK

4

LDO

21

VAA

23

GND

22

VCC

1

SCL

2

SDA

U6000
MAX_MAX17435ETG+_TQFN_24P

24

P3V3_AL

1

R6003

10K_5%_2

2

PGND-PAD

ADAPTLIM

EN

BST
DHI

LX

DLO

CSIP
CSIN
BATT

CC

IINP

ITHR

R6002

10K_5%_2

7
9
8
5
25

12
11
13
17

18

6
20

L6000

2

R6046

1

1

C6000

4.7UF_25V_5_DY4.7UF_25V_5

2

2

CHG_CHG_SEN_P

2
3
4

1

R6006

RSC_0603_DY

2

R6001

1

0.02_1%_6

CHG_CHG_SEN_N

Q6005

1

S

G

PMOS_4D3S

TPC8121

8

D

7
6
5

CC

2
43

C6016

1

4.7UF_25V_5

2

1

C6817

4.7UF_25V_5

2

BB

AA

1

17435_LDO

OUT

1

TP6000

8

7 6

5 4

8>

INVENTEC

TITLE

EVEREST-M
POWER CHARGER

CODE

SIZE

CS

CHANGE by

Frank Hu

3

Mon Jan 03 10:52:57 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

8

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

FUSE6100
LITTLEFUSE_R451015_15A_65V

R6101
R6102

1

1

C6106

1000PF_50V_2

2

R6110

1

715K_1%_2

2

1

33_5%_2

2

1

33_5%_2

2

1

D6100
EZJZ0V500AA

2

R6109

1

102K_1%_3

R6108

2

1

2

360K_1%_2

2

1

1K_5%_2

1

D6099
EZJZ0V500AA_DY

2

1

D6101
EZJZ0V500AA

2

R6100

2

CN6100
SYN_200045GR009G15JZR_9P

1

BATT+

2

BATT+

3

ID

4

B-I

5

TS

6

SMD

7

SMC

8

GND

9

GND

G1

G

G2

G

G3

G

G4

G

D

CC

BB

1

2

D6102

NC

1

BAT54_30V_0.2A_DY

3

U6100

1

RESET

2

GND

3

VCCMRVSEN

GMT_G686LT11U_SOT23_5P

1

C6107

0.1UF_16V_2

2

R6105
10K_5%_2

2

R6039

1

2

5
4

0_5%_2

1

R6104
510K_1%_2

2

1

R6103
100K_1%_2

2

AA

INVENTEC

TITLE

EVEREST-M
POWER BATTERY

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Mon Jan 03 10:53:36 2011

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

9

of

1

REV

97

A01

8 7

6 5

4 3

2

1

Q6200

8

D

1

Q6203

G

7
6

NMOS_4D3S

AON7410

3

DS

2

R6201

R6212

100K_5%_2

D

1

2

SSM3K7002BFU

100K_5%_2

Q6202

1

G

10<

3

DS

2

EC_PW_ON#

37>

1

2

1

C6211

2200PF_50V_2

2

R6200

1

0_5%_2

2

1

C6215

2

CSC0402_DY

IN

SSM3K7002BFU

1

A1

3

C

D6201
BAT54C_30V_0.2A

S

G

1

R6210

120K_1%_2

2

1
2
3
45

37>

10<

EC_PW_ON#

PAD6205

1

1

POWERPAD_2_0610

2

2

Q6805

IN

1

SSM3K7002BFU

1

R6202
200_5%_2

2

3

G

2

10>

DS

VCLK

IN

P5V_A

C6219

0.1UF_25V_2

C6216

0.1UF_25V_2

2

1

2

1

2

D6202

3

BAV99

C6218

0.1UF_25V_2

0.1UF_25V_2

1

C6217

1

D

2

D6203

3

BAV99

2

1

2

1

C6220

1UF_25V_3

1

2

CC

10A

PAD6200

1

1

POWERPAD_2_0610

2

R6207

6.8K_1%_2

R6208

10K_1%_2

8

1

1

PAD6203

2

POWERPAD_2_0610

2

A2

2

1

R6209

130K_1%_2

2

1

1

PAD6202
POWERPAD_2_0610

2

2

SKIPSEL

TONSEL

>>VRE3 OR VRE5=OOA

>>VREF=ASKIP
>>GND=PWM

>>VRE5=365/460
>>VRE3=300/375
>>VREF=245/305

REV

A01

BB

AA

>>GND=200/250

1

1

VO1
PGOOD
VBST1
DRVH1

LL1
DRVL1

18

VCLK

OUT

C6209

0.22UF_6.3V_2

2

24
23
22

VR5A_HG

20

VR5A_PH

19

VR5A_LG

C6213

1

1

2

2

1

10UF_6.3V_3

2

C6207

0.1UF_25V_3

2

1

10<

PAD6204

POWERPAD1X1M

3.8A

Q6206

AON7410

5 6 7

NMOS_4D3S

G

3 214

5 6 7 8

G

3 214

8

D

S

D

S

4.7UF_25V_5

Q6207

TPC8A05_H

C6203

1

2

C6201

1

2

4.7UF_25V_5

L6200

1

PCMC063T_3R3MN

3

4.7UF_25V_5

2

330UF_6.3V

C6214

1
2

C6200

CHANGE by

1

+

2

Frank Hu

1

POWERPAD_2_0610

1

R6205

15.4K_1%_2

2

1

R6206
10K_1%_2

2

DATE

7A

PAD6201

1

2

2

Mon Jan 03 10:54:36 2011

2

INVENTEC

TITLE

EVEREST-M
POWER +3A/+5A

SIZE

C

CODE

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

10

of

1

97

1

C6205

4.7UF_25V_5

2

1

C6204

4.7UF_25V_5

2

1

2

1

2

1

C6202

1

2

2

+

330UF_6.3V

L6201

2

1

PCMC063T_3R3MN

Q6205

TPC8A05_H

7 6

4A

56

78

D

S

D

S

32

3214

4

5678

NMOS_4D3S

G

G

Q6204

AON7410

C6212

2

0.1UF_25V_3

1

TI_TPS51125_QFN_24P

1

2

VR3AL_HG
VR3AL_PH
VR3AL_LG

C6206

1UF_6.3V_2

U6200

RSC_0603_DY

1

2

25

TML

7

VO2

8

VREG3
VBST2

10 21

DRVH2

11

LL2

12

DRVL2

R6037

2

1

CSC0805_DY
C6210

R6204

RSC_0402_DY

5 4

35294

6

ENTRIP2

VFB2

TONSEL

VREF

VFB1

ENTRIP1

SKIPSEL

VREG5

13

GND

VIN

14

15

1

2

VCLK

17

16

C6208

2.2UF_25V_5

EN0

1

2

8 7

6 5

4 3

2

1

1

1

PAD6301

2

D

POWERPAD_2_0610

2

22A

D

3.7A

8765

D

NMOS_4D3S

G

S

2

1

4 3

8765

D

G

S

TPCA8A02_H

1

23

4

Q6301

1

C6303

4.7uF_25V_5

2

2

R6047

PCMC104T_1R0MN

4.7_5%_3

1

1

C6815

2200PF_50V_2

2

1

C6300

4.7uF_25V_5

2

L6300

1

3

1

2

2
4

R6304

11.5K_1%_2

C6309

4.7uF_25V_5

1

2

1

+

C6304

560uF_2.5V

PAD6303

1

1

2

POWERPAD_2_0610

PAD6302

1

1

2

POWERPAD_2_0610

2

2

CC

2

37<

11<

30>

SLP_S4#

3.7A

P3V3_S

1

R6314

RSC_0402_DY

2

18<

V1.5_PG

1

IN

R6302

0_5%_2

2

OUT

TI_TPS51218DSCR_SON_10P

U6302

1

PGOOD

2

TRIP

3

EN

4

VFB

5

RF

10

VBST

VR15_HG

9

DRVH

8

VR15_PH

SW

7

V5IN

6

VR15_LG

DRVL

GND

R6301

2.2_5%_3

1

2

C6305

0.1uF_25V_3

1

1

C6301

CSC0402_DY

2

1

R6311

95.3K_1%_2

2

1 1

R6310

200K_1%_2

2

11

C6302

2.2uF_6.3V_3

2

Q6300

TPCA8065_H

2

30>

17<18<37<

SLP_S3#

+V1.5S_CPUDDR_PG

IN

37<

IN

11<

30>

R6307

1

0_5%_2_DY

R6306

1

0_5%_2

SLP_S4#

2

2

20/20 mil

IN

C6312

1000PF_50V_2_DY

1

0.1UF_16V_2

2

C6311

P3V3_A

1

1

2

2

C6308

1uF_10V_2

U6300

11

TML

10

VIN

9

S5

8 4

GND

7

S3

6

VTTREF

GMT_G2997F6U_MSOP10_10P

VDDQSNS

VLDOIN

VTT

PGND

VTTSNS

R6303

10K_1%_2

1

2

BB

P1V5

1
2
3

5

1.5A

1

C6307

22uF_6.3V_5

2

1

C6306

2

22uF_6.3V_5

PAD6300

1

1

2

POWERPAD_2_0610

2

1.5A

AA

INVENTEC

TITLE

EVEREST-M
POWER +V1.5/+V0.75S

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Mon Jan 03 17:25:55 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

11

of

1

REV

97

A01

8 7

6 5

4 3

1

1

PAD6403

2

POWERPAD_2_0610

2

1

P3V3_S

5 6 7 8

D

10K_5%_2

13<

1

0_5%_2

VTT_PG

R6402

2

C6413

CSC0402_DY

OUT

1

1

R6405

44.2K_1%_2

2

2

R6400

1

2

TI_TPS51218DSCR_SON_10P

U6400

1

PGOOD

2

TRIP

3

EN

4

VFB

5

RF

1

R6411

470K_1%_2

2

R6403

10

VBST

9

VRVCCP_HG

DRVH

VRVCCP_PH

8

SW

7

V5IN

VRVCCP_LG

6

DRVL

GND

1

2.2_5%_3

2

C6410

0.22UF_25V_3

1

2

11

C6411

1

2.2UF_6.3V_3

2

3.3A

23>

VSS_SENSE_VTT

NMOS_4D3S

G

3 214

5 6 8

NMOS_4D3S

G

3 214

D

Q6401

TPCA8065_H

S

7

D

Q6400
TPCA8057_H

S

2

1

C6403

4.7UF_25V_5

2

1000PF_50V_2_DY

IN

C6406

1

4.7UF_25V_5

2

1
3

PAN_ETQP4LR36WFC_4P

C6414

1

1

2

L6403

1

R6410

RSC_0402_DY

2

1

2

R6415

0_5%_2

C6401

4.7UF_25V_5

2
4

2

1

C6415

0.1UF_10V_2_DY

2

1

R6413

9.53K_1%_2

2

1

R6414
20K_1%_2

2

1

R6416

R6417

1

200_1%_2

PAD6402

1

1

POWERPAD_2_0610

PAD6401

1

1

POWERPAD_2_0610

2

2

2

2

28A

D

1

C6407

+

560UF_2.5V

2

CC

2

IN

VCC_SENSE_VTT

23>

100_5%_2

2

BB

P3V3_A

0.5A

+V1.05_LAN_M

1

37< 19<

30>

SLP_LAN#

C6452

1

R6452

10_5%_3

2

R6454

2

IN

1

0_5%_2

1

C6453

0.1UF_16V_2

2

10UF_6.3V_3

2

U6401
GMT_G5694F11U_SOP_8P

8

VIN

1

VCC

5

EN

PGND

673

9

TML

LX

4

FB

2

REF

GND

C6454

1

0.1UF_16V_2

2

L6450

1

LTF5022T_2R2N3R2_LC

2

1

R6450

3.09K_1%_2

2

1

R6451
10K_1%_2

2

1

C6451

CSC0402_DY

2

1

C6450

22UF_6.3V_5

2

PAD6400

1

1

POWERPAD_2_0610

2

1.5A

2

AA

INVENTEC

TITLE

EVEREST-M

POWER VCCP/+V1.05_LAN_M

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Mon Jan 03 17:26:41 2011

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

12

of

1

REV

97

A01

8 7

6 5

4 3

PVBAT

1

1

PAD6500

2

POWERPAD_2_0610

2

1

P3V3_A

5

6 7 8

D

10K_5%_2

R6502

2

1

0_5%_2

1

1

C6505

CSC0402_DY

R6508

78.7K_1%_2

2

2

R6501

1

2

1

2

1

C6510

47PF_50V_2

2

TI_TPS51217DSCR_SON_10P

1
2
3
4
5

R6509
1K_1%_2

PGOOD

TRIP

EN

VFB

TRAN

U6500

11

R6500

10

VBST

9

DRVH

8

SW

7

V5IN

6

DRVL

GND

VR85_HG

VR85_PH

VR85_LG

C6504

1

2.2UF_6.3V_3

2

1

0_5%_3

2

C6503

0.22UF_25V_3

1

2

Q6500

AON7410

NMOS_4D3S

G

3 2

4

5 7 8

6

G

3 2

4

D

S

1

D

Q6501

TPC8A05_H

S

1

P5V_A

2

1

C6501

4.7UF_25V_5

2

C6506

1000PF_50V_2_DY

1

C6502

4.7UF_25V_5

2

1

C6500

4.7UF_25V_5

2

L6500

2

1

PCMC063T_3R3MN

1

R6503
RSC_0402_DY

2

1

1

C6507

0.1UF_10V_2_DY

2

1

200_1%_2

1

R6504

6.49K_1%_2

2

R6506

D

6A

PAD6503

1

1

POWERPAD_2_0610

1

C6508

+

330UF_2V_9MR_PANA_-35%

2

2

2

2

CC

2

R6510

20K_1%_2

1

2

1

2

R6507

40.2K_1%_2

1

R6505
20K_1%_2

2

24>

VCCSA_SEL

IN

LOW - 0.9V
HIGH - 0.8V

R6511

2

200_1%_2

1

B

LMBT3904LT1G

C E

Q6502

1

2 3

3

DS

G

Q6503

SSM3K7002BFU

2

BB

1

1.6A

1

C6514

1

R6517
10_5%_3

2

1

C6515

2

0.1UF_16V_2

1

R6516
10K_5%_2

2

10UF_6.3V_3

2

U6502
GMT_G5694F11U_SOP_8P

8

VIN

1

VCC

5

EN

PGND

673

9

TML

LX

4

FB

2

REF

GND

1

C6511

0.1UF_16V_2

2

L6502

1

LTF5022T_2R2N3R2_LC

2

1

R6514
13K_1%_2

2

1

R6515
10K_1%_2

2

1

C6513

CSC0402_DY

2

1
2

C6512

22UF_6.3V_5

PAD6501

1

1

POWERPAD_2_0610

2

3A

2

AA

INVENTEC

TITLE

EVEREST-M

POWER +V0.85S/+V1.8S

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Mon Jan 03 17:27:17 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

13

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

+VBAT_CPU

1

R6622

178K_1%_2

2

P3V3_A

1

R6620
0_5%_2

2

8

FOLLOW BERLIN 10RG

1

R6621

20.5K_1%_2

2

C6615

1

470PF_50V_2

2

IN

VSSSENSE

23>

+VBAT_CPU

1

R6617

178K_1%_2

2

7 6

1

R6619
0_5%_2 115K_1%_2

2

1

R6618

2

14<

FOLLOW BERLIN 10RG

P3V3_A

1

R6608
0_5%_2

2

1

R6609

20.5K_1%_2

2

P5V_A

1

C6612

470PF_50V_2

2

IN

VSSAXG_SENSE

1

R6624

4.87K_1%_2

2

1

R6626

100K_5%_2

2

P5V_A

TONA
IMAXA
IMONA
CCVA
VBOOTA

14<

SRA
THERMA

14<

14<

14<
14<

14<

14<

R6611

2K_5%_2

IN
IN
IN
IN
IN
IN
IN

P5V_A

1

R6623

P5V_A

1

R6625

4.87K_1%_2

2

24>

1

R6606

2

14<

1

R6607
0_5%_2 115K_1%_2 100K_5%_2

2

1

R6627

2

14<

14<

PH3_SKIP#

PH3_PWM

IN
IN

1

C6619

1UF_6.3V_2

2

P3V3_S

1

1

R6610
2K_5%_2

2 2

2

10K_5%_2

R6038

15<

14<

1

IN
IN
IN
IN
IN
IN
IN

VRCPU_PH2

14<

2

TONB
IMAXB
IMONB

CCVB
VBOOTB
SRB
THERMB

IMAXA
IMAXB

0_5%_2

14<

14<

14<

14<
14<

14<

14<

IN

IN
IN

5 4

U6602

MAX_MAX8791GTA+_TQFN_8P

2

PWM

6

SKIP

5

VDD

BST

GND

PAD

9

1

C6618

2.2UF_6.3V_2

2

43

LXA2

44

VRA_READY

45

VRB_READY

46

CSPA1

47

CSNA1

48

CSNA2

49

CSPA2

50

CSPA3

51

CSNA3

52

IMAXA

53

IMAXB

54

TMAX

55

VR_HOT#

56

AGND

P5V_A

2.2UF_6.3V_2

8

DH

1
7

LX

4

DL

3

P5V_A

15<

15<

15<

15<

VRCPU_HG2

CPU_BST2

VRCPU_LG2

IN

IN

IN

404142

38

39

DLA2

DHA2

VDDA

DLA1

BSTA2

MAX_MAX17039GTN+_TQFN_56P

ALERT#

VDIO

VCLK

VCC

TONA

1

564

3

2

14<

1

C6616

2

PVBAT

15<

VRCPU_LG1

CPU_BST1

INININ

37

BSTA1

U6600

TONB

IN

TONA

TONB

14<

IN

15<

36

DHA1

CSPB

7

VRCPU_HG1

15<

IN

35

LXA1

CSNB

8

10A

IN
IN
IN
IN

14<

PH3_PWM

VRCPU_PH1

IN

IN

34

333132

PWM_OUT

VR_ENABLE

9

10

1

TP6601

TP24

1

POWERPAD_2_0610

VRCPU_HG3
CPU_BST3
VRCPU_PH3
VRCPU_LG3

14<

14<

14<

14<

14<

14<

IMONA

PH3_SKIP#

CCVA

GNDSA

IN

IN

IN

30

CCVA

IMONA

GNDSA

DRSKIP

DLG

VDDB

DLB

BSTB

12

13

11

INININ

GPU_BST1

VRAXG_LG1

15<

15<

1

C6617

2.2UF_6.3V_2

2

PAD6600

1

FBB

GNDSB

14<

FBA

IN

29

FBA

VBOOTB
VBOOTA

CCI2
CCI1

THERMA
THERMB

N.C.

GNDSB
IMONB

CCVB

DHB

14

VRAXG_HG1

15<

SRA
SRB

FBB

LXB
GND

15<

15<
15<

2

15<

OUT
OUT

28
27
26
25
24
23
22
21
20
19
18
17
16
15
57

2

2

4.7UF_25V_5

P5V_A

3

1

C6601

4.7UF_25V_5 4.7UF_25V_5

R6605

1

9.53K_1%_2

IN
IN

IN
IN
IN
IN

IN
IN
IN
IN
IN

14<

FBA

14<

GNDSA

CHANGE by

1

C6600

2

1000PF_50V_2

2

1000PF_50V_2

VBOOTB
VBOOTA

SRA
SRB
THERMA
THERMB

FBB
GNDSB

IMONB

CCVB
VRAXG_PH1

IN
IN

C6609

C6608

14<
14<

14<
14<

14>

14>
14<

14<

Frank Hu

1
2

14<

C6602

2

1

1

2

470PF_50V_2

470PF_50V_2

15<

R6616

5.1K_1%_2

1

+VBAT_CPU

1

C6603

2

4.7UF_25V_5 4.7UF_25V_5 4.7UF_25V_5 4.7UF_25V_5

1

C6604

2

1

C6605

2

PVAXG

22

R6604

R6603

10_1%_2

1

1

R6601

10_1%_2

2

2

100_1%_2

1

CATCH R

CATCH R

R6602

100_1%_2

1

C6610

R6614

10_1%_2

1

1

R6612

10_1%_2

23>

2

2

1

1

C6611

2

2

1000PF_50V_2

2

1000PF_50V_2

VCCSENSE

IN

1

TP6600

2

C6614

1

1

C6613

2

INVENTEC

TITLE

CODE

SIZE

CS

Mon Jan 03 17:28:44 2011

DATE

2

C

SHEET

1

14<

C6606

1
2

2

4.7UF_25V_5

C6607

EVEREST-M
POWER VCORE

DOC.NUMBER

CS_1310AXXXXXX-MTR

14

of

1

D

CC

BB

AA

REV

97

A01

8 7

6 5

4 3

2

1

PVCORE

Q6705

+VBAT_CPU

NMOS_4D3S

G

4123

NMOS_4D3S

G

4123

8765

D

TPCA8065_H

S

8765

D

S

Q6704

1

2
1

2

R6711

4.7_5%_3

C6709

3300PF_50V_2

1

2

+

C6701

1500UF_2V

3

L6702

1

2

1

10K_5%_NTC

1

3 4

PAN_ETQP4LR36ZFC_4P

R6712

2

2.37K_1%_2

1

C6704

+

2

3

R6713

2

R6715

1

RSC_0402_DY

C6710

1

0.47UF_6.3V_2

470UF_2V

R6714

1

3.6K_1%_2

2

2

D

2

CC

+VBAT_CPU

14<

CPU_BST1

D

14<

VRCPU_HG1

14<

VRCPU_PH1

14<

VRCPU_LG1

IN

IN
IN

IN

1

2.2_5%_3

0.22UF_25V_3

2

C6707

Q6703

TPCA8057_H

2

1

R6710

8765

D

NMOS_4D3S

Q6702

G

TPCA8065_H

S

60A

4123

L6701

1

2

R6706

3 4

PAN_ETQP4LR36ZFC_4P

8765

D

NMOS_4D3S

G

S

4123

1

R6705

4.7_5%_3

2
1

C6706

3300PF_50V_2

2

2.37K_1%_2 10K_5%_NTC

2

2

R6709

C6708

R6708

1

3.6K_1%_2

2

2

2

1

R6707

1

1

RSC_0402_DY

1

0.47UF_6.3V_2

14<

14<
14<

14<

CPU_BST2

VRCPU_HG2
VRCPU_PH2

VRCPU_LG2

IN

IN
IN

IN

R6716

1

2.2_5%_3

2

2

C6711

0.22UF_25V_3

1

TPCA8057_H

14<

14<
14<

14<

CPU_BST3

VRCPU_HG3
VRCPU_PH3

VRCPU_LG3

IN

IN
IN

IN

R6717

1

2.2_5%_3
C6712

0.22UF_25V_3

2

2

1

Q6701

TPCA8057_H

+VBAT_CPU

NMOS_4D3S

G

23

4

NMOS_4D3S

G

4123

8765

D

TPCA8065_H

S

1

8765

D

S

Q6700

1

R6700

4.7_5%_3

2

1

C6700

3300PF_50V_2

2

L6700

1

2

1

10K_5%_NTC

1

3 4

PAN_ETQP4LR36ZFC_4P

R6701

2

2.37K_1%_2

R6702

2

R6704

1

RSC_0402_DY

C6703

1

0.47UF_6.3V_2

R6703

1

3.6K_1%_2

2

2

+VBAT_CPU

8765

14<

14<

GPU_BST1

VRAXG_HG1
VRAXG_PH1

VRAXG_LG1

1

IN

2.2_5%_3

IN
IN

IN

2

2

C6714

0.22UF_25V_3

1

TPCA8057_H

Q6707

R6723

2

D

NMOS_4D3S

Q6706

4 23

4123

TPCA8065_H

S

1

8765

D

S

1

R6718

4.7_5%_3

2
1

C6713

3300PF_50V_2

2

14<

GPU_CSP1

14<

GPU_CSN1

1

3 4

PAN_ETQP4LR36ZFC_4P

R6719

2

2.37K_1%_2

IN

IN

L6703

1

2

R6720

1

10K_5%_NTC

1

RSC_0402_DY

1

0.47UF_6.3V_2

2

R6722

C6715

R6721

1

3.6K_1%_2

2

2

G

NMOS_4D3S

G

33A

BB

2

AA

INVENTEC

TITLE

EVEREST-M

POWER VCORE

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Mon Jan 03 17:29:38 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

15

of

1

REV

97

A01

8 7

6 5

4 3

1

1

2

PAD6801

POWERPAD_2_0610

2

2

1

3.5A

D

U6800

1

R6805

86.6K_1%_2

2

TI_TPS51217DSCR_SON_10P

1

PGOOD

2

TRIP

3

EN

4 7

VFB

5

TRAN

1

R6806

1K_1%_2

2

1

C6809

2

47PF_50V_2

1

2

R6804

1

0_5%_3

C6800

2.2UF_6.3V_3

10

VBST

VRGPU_HG

9

DRVH

8

VRGPU_PH

SW

V5IN

6

VRGPU_LG

DRVL

GND

11

2

0.1UF_25V_2

C6804

1

2

5 6 7 8

NMOS_4D3S

G

G

3 214

678

3

214 5

D

TPCA8065_H

S

D

S

Q6800

Q6801

TPCA8A02_H

G

678

3

214 5

D

S

Q6802

TPCA8A02_H

1

C6803

2

4.7UF_25V_5

1

2

1

1

R6807

40.2K_1%_2

2

C6816

100PF_50V_2

2

1

C6805

2

4.7UF_25V_5

1

PAN_ETQP4LR36WFC_4P

D6800

SBR3U40P1_DY

C6802

CSC0402_DY

L6800

1

C6807

4.7UF_25V_5

2

2
43

1

R6810

100_5%_2

2

1
2

1

R6809

10.2K_1%_2

2

1

R6808

28.7K_1%_2

2

CONNECT TO GPU

1

C6808

470UF_2V

2

R6803

1

0_5%_2

+

PAD6800

1

POWERPAD_2_0610

1

POWERPAD_2_0610

2

1

PAD6803

1

2

2

OUT

30A

2

2

68>

1

C6810

+

470UF_2V470UF_2V

2

1

C6806

+

2

FOR OPTIMUS SHUTDOWN SOLUTION

+GPU_NVVDD_L

D

CC

BB

3

Q6803

R6040

0_5%_2

2

SSM3K7002BFU

1

DS

1

G

2

NVVDD

2

R6048

33.2K_1%_2

VID0

VID1

VOLTAGE LEVEL

1

0.825V

AA

1V

0.975V

R6041

1

0_5%_2

0

0

3

Q6804

2

1

SSM3K7002BFU

DS

G

0

1

1

0

2

INVENTEC

TITLE

EVEREST-M
POWER GPU NVVDD

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Tue Jan 04 00:17:23 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

16

of

1

REV

97

A01

8 7

6 5

4 3

2

1

P15V_A

WS

D

P5V_AL

100K_5%_2

1

R7035

10K_5%_2

2

SLP_S3_5R

37<

SLP_S3#

18<
30>
11<

OUT

IN

Q7088

1

SSM3K7002BFU

3

DS

G

SSM3K7002BFU

2

R7036

Q7090

1

1

2

R7039

1

0_5%_2

3

DS

G

2

OUT

SLP_S3#_15R

P3V3_AL

2

Q7005

1

D

2
5

AO6402AL

C7030

CSC0402_DY

NMOS_4D1S

1

2

19<18<17<

24<

POWERPAD_2_0610

1

2

1

1

2

2

C7026

22UF_6.3V_5

PAD7001

2

R7033

200_5%_3

1

Q7001

3

DS

1

2

SSM3K7002BFU

G

OUT

SLP_S3_5R

17> 17< 19<

D

4

S

36

G

1

C7029

22UF_6.3V_5

2

CC

P3V3_S

SLP_S3#_15R

P5V_A

IN

1
2
5

Q7004

D

NMOS_4D1S

AO6402AL

R7034

1

0_5%_2

P1V5

P5V_S

1

1

2

PAD7002

POWERPAD_2_0610

2

4

S

36

G

24<

19< 18<

17<

17>

SLP_S3#_15R

11.5A

IN

8
7
6

Q7002

D

NMOS_4D3S

AON7410

R7037

1

750K_1%_2

17>19<

S

G

2

SLP_S3_5R

1
2
3
45

IN

P0V75_S

1

R7032
22_5%_2

2

1

C7028

680PF_50V_2

2

PAD7000

1

1

POWERPAD_2_0610

2

3

1

C7027

CSC0402_DY

19< 17< 17>

SLP_S3_5R

OUT

DS

Q7000

1

G

SSM3K7002BFU

2

2

2

Q7003

1

G

SSM3K7002BFU

P1V5_S

1

R7038
200_5%_2

2

3

DS

2

BB

2

AA

INVENTEC

TITLE

EVEREST-M

POWER +V3S/+V5S/+V1.5S

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:26 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

17

of

1

REV

97

A01

8 7

18>

+V1.05_LAN_PG

P3V3_A

5

U7000

+

1

2

-

3

TC7SZ08FU

4

C7025

10K_5%_2

2

1

2

37<

19<

18<

30>

SLP_A#

R7028

IN

1

D

+V3M

R7005

1

100K_5%_2

2

1UF_6.3V_2

6 5

37< 30>

18<19<

SLP_A#

IN

P3V3_A

1

C7009

0.1UF_16V_2

2

5

U7001

+

1
2

-

3

TC7SZ08FU

4 3

2

D7001

R7029

1

IN

2

0_5%_2

BAT54_30V_0.2A

NC

3

1

OUT

PM_APWROK

30<

P3V3_A

2

P3V3_A

1

1

C7010

0.1UF_16V_2

1

C7011

0.1UF_16V_2

2

C7012

1

0.1UF_16V_2

2

D

2

5

R7001

4

1

2

3.3K_5%_2

1

C7000

0.1UF_16V_2

2

U7002

+

1

4

2

-

3

TC7SZ08FU

R7004

1

0_5%_2

2

1

C7001

0.1UF_10V_2_DY

2

5

U7003

+

1

4

2

-

3

TC7SZ08FU

OUT

+V1.05S_VCCP_EN

12<

P3V3_A

VCCSA_PG

R7002

1

10K_5%_2_DY

2

+V1.5S_CPUDDR_PG

20<

11>

37<

V1.5_PG

59<

R7006

IN

1

10K_5%_2

2

OUT

MAIN_PWRGD

60>

14<

1

C7002

0.1UF_16V_2

2

+V1.05_LAN_M

R7009

1

110K_1%_2

2

1

C7004

0.1UF_10V_2_DY

2

IN
IN

309K_1%_2

1

2

R7000

1

1M_1%_2

R7007

C7005

1000PF_50V_2

1

R7003

0_5%_2

2

1

2

1

R7008
100K_1%_2

2

2

P3V3_A

C7003

1
2

0.1UF_16V_2

U7005

+

5

1

+

4

OUT

3

-

-

2

AZV331KTR_E1

P3V3_A

1

R7010
10K_1%_2

2

37<

17< 11<

OUT

30>

SLP_S3#

38<

14>

VR_PWRGD

37>30<

EC_PCH_PWROK

+V1.05_LAN_PG

P3V3_A

18<

IN

IN
IN

P3V3_A

1

2

5

U7004

+

-

TC7SZ08FU

3

CC

1

C7013

0.1UF_16V_2

2

4

OUT

ALLSYS_PWROK

BB

WS

OUT

DRAMRST_CNTRL_CPU

P1V5

19<
17>

SLP_S3#_15R

17<
24<

P1V5_CPUDDRS

8

1

R7015

P3V3_SP3V3_A

R7016

2

1

R7024
10K_5%_2

2

D7000

2

BAT54_30V_0.2A

IN

3

R7023

1

330_5%_2

NC

1

Q7064

2

LMBT3904LT1G

SSM3K7002BFU

C E

1

B

2 3

7 6

1

R7025
10K_5%_2

2

Q7065

3

DS

1

G

2

R7030

0_5%_2

2

1

2

OUT

C7006

1000PF_50V_2

+V1.5S_CPUDDR_PG

11<

20<

18<

1

5 4

DRAMRST_CNTRL_EC

DRAMRST_CNTRL_PCH

IN

IN

1

0_5%_2_DY

R7026

1

0_5%_2

C7008

470PF_50V_2

1K_5%_2

2

3

Q7053

2

1

BSH111

1

2

CHANGE by

G

Frank Hu

2

DS

1

R7014

4.99K_1%_2

2

3

1

R7013
1K_5%_2

2

R7027

1

1K_5%_2

R7031

1

0_5%_2

Fri Dec 31 10:16:27 2010

DATE

2

2

OUT

DDR3_DRAMRST#

26>
27>

AA

2

OUT

CPU_DRAMRST#

20>

INVENTEC

TITLE

EVEREST-M

POWER SEQ

SIZE

C

CODE

CS

CS_1310AXXXXXX-MTR

SHEET

DOC.NUMBER

18

of

1

REV

97

A01

8 7

6 5

4 3

2

1

P3V3_A

P5V_A

+V1.05_LAN_M

P5V_A

+V1.05M

D

37<

18< 30>

SLP_A#

Q7062

8

D

R7022

10K_1%_2

1

2

2

220K_5%_2

R7020

1

7
6

NMOS_4D3S

AON7410

3

DS

Q7061

G

1

3

DS

IN

1

G

Q7063

SSM3K7002BFU

2

SSM3K7002BFU

2

1

2

C7016

680PF_50V_2

S

G

1
2
3
45

C7024

1

0.1UF_10V_2_DY

1

C7018

10UF_6.3V_3

2

2

1

R7021
200_5%_2

2

3

DS

G

Q7060

SSM3K7002BFU

2

1

P1V05_VCCPS

PAD7003

1

1

POWERPAD_2_0610

+V1.05S

2

2

1

C7019

10UF_6.3V_3

2

12<

30>37<

SLP_LAN#

IN

2

R7019

47K_5%_2

1

R7018

1

100K_5%_2

3

DS

G

Q7059

SSM3K7002BFU

2

1

2

P3V3_A

1

C7014

2

0.01UF_50V_2

S

G

PMOS_4D1S

AM3423P

C7015

2

1

330PF_50V_2_DY

Q7006

D

1

4

3 6

G

1
2
5

+V3M

1

2

2

R7017
200_5%_3

1

3

DS

Q7058

SSM3K7002BFU

2

D

C7017

10UF_6.3V_3

CC

P1V5_CPUDDRS

BB

AA

24<

17<

18< 17>

SLP_S3#_15R

P1V5

IN

17>17<

Q7052

8

D

7
6

AON7410

SLP_S3_5R

NMOS_4D3S

R7011

1

0_5%_2

1

S

2
3
45

G

1

R7012

200_5%_2

1

C7007

470PF_50V_2

2

2

IN

SSM3K7002BFU

2

Q7051

3

DS

1

G

2

C7023

1
2

0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2

C7022

1
2

C7021

1
2

C7020

1

2

0.1UF_16V_2

P1V5_CPUDDRS

P1V5

INVENTEC

TITLE

EVEREST-M
POWER SEQ

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:27 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

19

of

1

REV

97

A01

8 7

6 5

4 3

2

1

REMOVE CLKOUT_DMI_CLKGEN_DP

CN4500

D

C26

AN34

AL33

AN33

AL32

AN32

AM34

AP33

V8

AR33

PROC_SELECT#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

CLOCKS

DPLL_REF_CLK

DPLL_REF_CLK#

THERMAL MISC

MISCDDR3

PWR MANAGEMENT

JTAG & BPM

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

20>

H_SNB_IVB#

DMI&FDI TerminationVoltage

Set toVss when LOW

NV_CLE

Set toVcc when HIGH

18>

30>

PM_DRAM_PWRGD

+V1.5S_CPUDDR_PG

18<

P1V8_S

1

2

OUT

100K_5%_2_DY

IN
IN

R4537

2.2K_5%_2

Place close to CPT and NVRAM connector

R4538

1

4.7K_5%_2

(Default)

P3V3_A

1

R4512

2

NXP_74AHC1G09GV_SOT753_5P

2

1

R4511

200_5%_2

2

U4502

1

2
3

OUT

NV_CLE

14>

H_PROCHOT#

P3V3_A

5

VCC

B
A

GND

4

Y

32>

47PF_50V_2

C4570

1

0.1UF_16V_2

2

P1V05_VCCPS

R4510

62_5%_2

OUT

C4504

P1V5_CPUDDRS

R4532

200_5%_2

R4513

39_5%_2

1

37<>

2

1

2

33<

PM_THRMTRIP#

1

60>
33>

2

1

2

20>

H_SNB_IVB#

1

33>

H_PECI

LOW IN C6/C7

30<>

H_PM_SYNC

H_CPUPWRGD

R4500

1

130_1%_2

20>

BUF_PLT_RST#_CPU

R4517

0_5%_2_DY

OUT

OUT

2

2

BI

IN

OUT

TP4500

H_CATERR#_R

R4516

1

43_5%_2

1

56_5%_2

R4535

1

0_5%_2

R4536

1

1

0_5%_2

2

2

2

R4534

0_5%_2

R4533

PM_THRMTRIP#_R

PM_DRAM_PWRGD_R

1

H_PECI_R

H_PROCHOT#_R

H_PM_SYNC_R

2

H_CPUPWRGD_R

2

IN

3

SLP_S3_5R

Q4500

IN

SSM3K7002BFU

1

DS

G

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

2

CLKOUT_DMI_PCH_R_DP

A28

BCLK

A27

BCLK#

CLKOUT_DMI_PCH_R_DN

CLK_DP_PCH_CPU_R_DP

A16
A15

CLK_DP_PCH_CPU_R_DN

R8

AK1
A5
A4

AP29

PRDY#

AP27

PREQ#

AR26

TCK

AR27

TMS

AP30

TRST#

AR28

TDI

AP26

TDO

AL35

DBR#

AT28

BPM#[0]

AR29

BPM#[1]

AR30

BPM#[2]

AT30

BPM#[3]

AP32

BPM#[4]

AR31

BPM#[5]

AT31

BPM#[6]

AR32

BPM#[7]

CLKOUT_DMI_CLKGEN_DN

2

R4542
R4541

R4531
R4530

1
1

1
1

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

SYS_RESET#_R

OUT

IN
IN

IN
IN

IN

OUT

2

2
2

R4507
R4506
R4505

R4529

1

0_5%_2

0_5%_2

0_5%_2
0_5%_2

1
1
1

H_PRDY#
H_PREQ#

H_TCK
H_TMS
H_TRST#
H_TDI
H_TDO

0_5%_2

2

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

WS

CLK_DMI_PCH_DP

IN
IN

CLK_DMI_PCH_DN

CLK_DP_PCH_CPU_DP

IN
IN

CLK_DP_PCH_CPU_DN

OUT

CPU_DRAMRST#

140_1%_2

2

2

25.5_1%_2

2

200_1%_2

60<

20<60>

60> 20<

20<60>

60<

OUT

20<60>
20<60>

SYS_RESET#

P1V05_VCCPS

60<>

60<>

60<>

H_BPM0_XDP#
H_BPM1_XDP#
H_BPM2_XDP#
H_BPM3_XDP#
H_BPM4_XDP#
H_BPM5_XDP#
H_BPM6_XDP#
H_BPM7_XDP#

60<
60<
60<
60<
60<
60<
60<
60<

18>

60> 30<

29>

D

29>

29>
29>

CC

BB

P3V3_S

H_CPUPWRGD_R

R4556

60<>

1

C4559

0.1UF_16V_2

2

IN

U4501

1

10K_5%_2

2

R4557

BUF_PLT_RST#

56< 55<

32<>
43<

1

IN

2
3

TSB_TC7SZ07FU_SSOP_5P

NC

IN-A

GND

VCC

OUT-Y

P1V05_VCCPS

5

4

1

R4558

75_5%_2

2

R4509

1

43_5%_2

2

1

R4508
0_5%_2_DY

BUF_PLT_RST#_CPU

OUT

20<

60>20<

20< 60>

20< 60>

20< 60>

2

60>20<

H_PREQ#

60<>

H_TMS
H_TDI

H_TCK

H_TRST#

TITLE

1

IN
IN
IN

IN
IN

R4555

1

R4552

1

R4554

1
1

R4553

INVENTEC

EVEREST-M

51_5%_2

2

51_5%_2

2

51_5%_2_DY

2

51_5%_2

2
2

51_5%_2

AA

CPU 1

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:28 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

20

of

1

REV

97

A01

8 7

6 5

P1V05_VCCPS

4 3

2

1

DMI_TX_DN<3..0>

D

DMI_TX_DP<3..0>

DMI_RX_DN<3..0>

DMI_RX_DP<3..0>

FDI_TX_DN<7..0>

FDI_TX_DP<7..0>

P1V05_VCCPS

R4544

24.9_1%_2

IN

IN

0

1

2

3

OUT

OUT

0

1
2
3

0

1
2
3

OUT

0

1

2
3
4
5
6
7

OUT

30>

FDI_FSYNC0

30>

FDI_FSYNC1

30>

FDI_INT

30>

FDI_LSYNC0

30>

1

2

48>

FDI_LSYNC1

+V1.05S_VCCP_eDP_COMPIO

48>

EDP_HPD#

48<>

EDP_AUX_DP

48<>

EDP_AUX_DN

48>

EDP_TX0_DP

EDP_TX0_DN

0

1

2
3
4
5
6
7

OUT

DMI_TX_DN<0>

0

DMI_TX_DN<1>

1

DMI_TX_DN<2>

2

DMI_TX_DN<3>

3

DMI_TX_DP<0>
DMI_TX_DP<1>
DMI_TX_DP<2>
DMI_TX_DP<3>

DMI_RX_DN<0>
DMI_RX_DN<1>
DMI_RX_DN<2>
DMI_RX_DN<3>

DMI_RX_DP<0>
DMI_RX_DP<1>

DMI_RX_DP<2>
DMI_RX_DP<3>

FDI_TX_DN<0>

FDI_TX_DN<1>

FDI_TX_DN<2>
FDI_TX_DN<3>

FDI_TX_DN<4>
FDI_TX_DN<5>

FDI_TX_DN<6>
FDI_TX_DN<7>

FDI_TX_DP<0>
FDI_TX_DP<1>
FDI_TX_DP<2>
FDI_TX_DP<3>
FDI_TX_DP<4>
FDI_TX_DP<5>
FDI_TX_DP<6>
FDI_TX_DP<7>

IN
IN

IN
IN

IN

IN

BI
BI

OUT

B27
B25
A25
B24

B28
B26
A24
B23

G21
E22
F21
D21

G22
D22
F20
C21

A21
H19
E19
F18
B21
C20
D18
E17

A22
G19
E20
G18
B20
C19
D19
F17

J18
J17

H20
J19

H17

A18
A17
B16

C15
D15

C17
F16
C16
G15

C18
E16
D16
F15

CN4500

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

FDI0_FSYNC
FDI1_FSYNC

FDI_INT

FDI0_LSYNC
FDI1_LSYNC

eDP_COMPIO
eDP_ICOMPO
eDP_HDP#

eDP_AUX
eDP_AUX#

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

DMI

Intel(R) FDI

eDP

PCI EXPRESS* - GRAPHICS

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

+V1.05S_VCCP_PEG_ICOMPI

IN

PEG_RX15_DN

IN

PEG_RX14_DN

IN

PEG_RX13_DN

IN

PEG_RX12_DN

IN

PEG_RX11_DN

IN

PEG_RX10_DN

IN

PEG_RX9_DN

IN

PEG_RX8_DN

IN

PEG_RX7_DN

IN

PEG_RX6_DN

IN

PEG_RX5_DN

IN

PEG_RX4_DN

IN

PEG_RX3_DN

IN

PEG_RX2_DN

IN

PEG_RX1_DN

IN

PEG_RX0_DN
PEG_RX15_DP

IN
IN

PEG_RX14_DP

IN

PEG_RX13_DP

IN

PEG_RX12_DP

IN

PEG_RX11_DP

IN

PEG_RX10_DP

IN

PEG_RX9_DP

IN

PEG_RX8_DP

IN

PEG_RX7_DP

IN

PEG_RX6_DP

IN

PEG_RX5_DP

IN

PEG_RX4_DP

IN

PEG_RX3_DP

IN

PEG_RX2_DP

IN

PEG_RX1_DP

IN

PEG_RX0_DP
PEG_TX15_C_DN

OUT
OUT

PEG_TX14_C_DN

OUT

PEG_TX13_C_DN

OUT

PEG_TX12_C_DN

OUT

PEG_TX11_C_DN

OUT

PEG_TX10_C_DN

OUT

PEG_TX9_C_DN

OUT

PEG_TX8_C_DN

OUT

PEG_TX7_C_DN

OUT

PEG_TX6_C_DN

OUT

PEG_TX5_C_DN

OUT

PEG_TX4_C_DN

OUT

PEG_TX3_C_DN

OUT

PEG_TX2_C_DN

OUT

PEG_TX1_C_DN

OUT

PEG_TX0_C_DN
PEG_TX15_C_DP

OUT
OUT

PEG_TX14_C_DP

OUT

PEG_TX13_C_DP

OUT

PEG_TX12_C_DP

OUT

PEG_TX11_C_DP

OUT

PEG_TX10_C_DP

OUT

PEG_TX9_C_DP

OUT

PEG_TX8_C_DP

OUT

PEG_TX7_C_DP

OUT

PEG_TX6_C_DP

OUT

PEG_TX5_C_DP

OUT

PEG_TX4_C_DP

OUT

PEG_TX3_C_DP

OUT

PEG_TX2_C_DP

OUT

PEG_TX1_C_DP

OUT

PEG_TX0_C_DP

1

2

R4545

24.9_1%_2

68>
68>
68>
68>
68>
68>

68>
68>
68>
68>
68>
68>
68>
68>
68>
68>

68>
68>
68>
68>
68>
68>

68>
68>
68>
68>
68>
68>
68>
68>
68>
68>

21<
21<
21<
21<
21<
21<
21<
21<
21<

21<
21<
21<
21<
21<
21<
21<
21<
21<

21<

21<

21<
21<
21<
21<
21<
21<

21<
21<
21<
21<
21<
21<

PEG_TX15_C_DN
PEG_TX14_C_DN
PEG_TX13_C_DN

PEG_TX12_C_DN
PEG_TX11_C_DN

PEG_TX10_C_DN

PEG_TX9_C_DN

PEG_TX8_C_DN
PEG_TX7_C_DN
PEG_TX6_C_DN

PEG_TX5_C_DN
PEG_TX4_C_DN
PEG_TX3_C_DN
PEG_TX2_C_DN
PEG_TX1_C_DN

PEG_TX0_C_DN

PEG_TX15_C_DP
PEG_TX14_C_DP
PEG_TX13_C_DP
PEG_TX12_C_DP
PEG_TX11_C_DP
PEG_TX10_C_DP

PEG_TX9_C_DP
PEG_TX8_C_DP
PEG_TX7_C_DP
PEG_TX6_C_DP
PEG_TX5_C_DP
PEG_TX4_C_DP
PEG_TX3_C_DP
PEG_TX2_C_DP
PEG_TX1_C_DP
PEG_TX0_C_DP

CLOSE to CPU

C4546

IN

C4545

IN

C4544

IN

C4543

IN

C4542

IN

C4541

IN

C4540

IN

C4539

IN

C4538

IN

C4537

IN

C4536

IN

C4535

IN

C4534

IN

C4533

IN

C4532

IN

C4531

IN

C4530

IN

C4529

IN

C4528

IN

C4527

IN

C4526

IN

C4525

IN

C4524

IN

C4523

IN

C4522

IN

C4521

IN

C4520

IN

C4519

IN

C4518

IN

C4517

IN

C4516

IN

C4515

IN

1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2

2
2
2
2

2
2
2
2
2
2
2
2
2
2
2
2

2
2
2
2

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

OUT

PEG_TX15_DN

OUT

PEG_TX14_DN

OUT

PEG_TX13_DN

OUT

PEG_TX12_DN

OUT

PEG_TX11_DN

OUT

PEG_TX10_DN

OUT

PEG_TX9_DN

OUT

PEG_TX8_DN

OUT

PEG_TX7_DN

OUT

PEG_TX6_DN

OUT

PEG_TX5_DN

OUT

PEG_TX4_DN
PEG_TX3_DN

OUT
OUT

PEG_TX2_DN

OUT

PEG_TX1_DN

OUT

PEG_TX0_DN

OUT

PEG_TX15_DP

OUT

PEG_TX14_DP

OUT

PEG_TX13_DP

OUT

PEG_TX12_DP

OUT

PEG_TX11_DP

OUT

PEG_TX10_DP

OUT

PEG_TX9_DP

OUT

PEG_TX8_DP

OUT

PEG_TX7_DP

OUT

PEG_TX6_DP

OUT

PEG_TX5_DP

OUT

PEG_TX4_DP

OUT

PEG_TX3_DP

OUT

PEG_TX2_DP

OUT

PEG_TX1_DP

OUT

PEG_TX0_DP

68<
68<
68<
68<
68<
68<

68<
68<
68<
68<

68<
68<
68<
68<
68<
68<

68<
68<
68<
68<

68<
68<
68<
68<
68<
68<

68<
68<
68<
68<
68<
68<

D

CC

BB

AA

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

INVENTEC

TITLE

EVEREST-M

CPU 2

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:57 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

21

of

1

REV

97

A01

8 7

6 5

4 3

2

1

M_A_DQ<63..0>

D

BI

26<

M_A_BS0

26<

M_A_BS1

26<

M_A_BS2

26<

M_A_CAS#

26<

M_A_RAS#

26<

M_A_WE#

M_A_DQ<0>

0

M_A_DQ<1>

1

M_A_DQ<2>

2

M_A_DQ<3>

3

M_A_DQ<4>

4

M_A_DQ<5>

5

M_A_DQ<6>

6

M_A_DQ<7>

7

M_A_DQ<8>

8

M_A_DQ<9>

9

M_A_DQ<10>

10

M_A_DQ<11>

11

M_A_DQ<12>

12

M_A_DQ<13>

13

M_A_DQ<14>

14

M_A_DQ<15>

15

M_A_DQ<16>

16

M_A_DQ<17>

17

M_A_DQ<18>

18

M_A_DQ<19>

19

M_A_DQ<20>

20

M_A_DQ<21>

21

M_A_DQ<22>

22

M_A_DQ<23>

23

M_A_DQ<24>

24

M_A_DQ<25>

25

M_A_DQ<26>

26

M_A_DQ<27>

27

M_A_DQ<28>

28

M_A_DQ<29>

29

M_A_DQ<30>

30

M_A_DQ<31>

31

M_A_DQ<32>

32

M_A_DQ<33>

33

M_A_DQ<34>

34

M_A_DQ<35>

35

M_A_DQ<36>

36

M_A_DQ<37>

37

M_A_DQ<38>

38

M_A_DQ<39>

39

M_A_DQ<40>

40

M_A_DQ<41>

41

M_A_DQ<42>

42

M_A_DQ<43>

43

M_A_DQ<44>

44

M_A_DQ<45>

45

M_A_DQ<46>

46

M_A_DQ<47>

47

M_A_DQ<48>

48

M_A_DQ<49>

49

M_A_DQ<50>

50

M_A_DQ<51>

51

M_A_DQ<52>

52

M_A_DQ<53>

53

M_A_DQ<54>

54

M_A_DQ<55>

55

M_A_DQ<56>

56

M_A_DQ<57>

57

M_A_DQ<58>

58

M_A_DQ<59>

59

M_A_DQ<60>

60

M_A_DQ<61>

61

M_A_DQ<62>

62

M_A_DQ<63>

63

OUT
OUT
OUT

OUT
OUT
OUT

SOCKET,CPU,989P,TIN,3.0MM,STR,SMD,TR

CN4500

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15

AE10
AF10

AE8
AD9
AF9

F10
G10

N10

M10

AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8

V6

C5
D5
D3
D2
D6
C6
C2
C3

F8
G9

F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8

N8
N7

M9
N9
M7

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

SA_CS#[0]

SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

SA_ODT[0]

SA_ODT[1]
RSVD_TP[9]

RSVD_TP[10]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4]

SA_DQS[5]

SA_DQS[6]

SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

M_A_DQS_DN<0>
M_A_DQS_DN<1>
M_A_DQS_DN<2>
M_A_DQS_DN<3>
M_A_DQS_DN<4>
M_A_DQS_DN<5>

M_A_DQS_DN<6>
M_A_DQS_DN<7>

M_A_DQS_DP<0>
M_A_DQS_DP<1>
M_A_DQS_DP<2>
M_A_DQS_DP<3>
M_A_DQS_DP<4>
M_A_DQS_DP<5>
M_A_DQS_DP<6>
M_A_DQS_DP<7>

M_A_A<0>
M_A_A<1>
M_A_A<2>
M_A_A<3>
M_A_A<4>
M_A_A<5>
M_A_A<6>
M_A_A<7>
M_A_A<8>
M_A_A<9>
M_A_A<10>
M_A_A<11>
M_A_A<12>
M_A_A<13>
M_A_A<14>
M_A_A<15>

27<>

M_B_DQ<63..0>

M_CLK_DDR0_DP

OUT
OUT

M_CLK_DDR0_DN

OUT

M_CKE0

M_CLK_DDR1_DP

OUT
OUT

M_CLK_DDR1_DN

OUT

M_CKE1

M_CS#0

OUT
OUT

M_CS#1

OUT

M_ODT0

OUT

M_ODT1

BI

0

1
2
3
4
5
6
7

BI

0

1
2
3
4
5
6
7

OUT

0

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15

26<
26<

26<
26<

M_A_DQS_DN<7..0>

M_A_DQS_DP<7..0>

M_A_A<15..0>

27<
27<
27<

27<
27<
27<

BI

26<

26<
26<

26<
26<
26<

26<>

M_B_BS0
M_B_BS1
M_B_BS2

M_B_CAS#
M_B_RAS#
M_B_WE#

0

M_B_DQ<0>

1

M_B_DQ<1>

2

M_B_DQ<2>

3

M_B_DQ<3>

4

M_B_DQ<4>

5

M_B_DQ<5>

6

M_B_DQ<6>

7

M_B_DQ<7>

8

M_B_DQ<8>
M_B_DQ<9>

9

M_B_DQ<10>

10

M_B_DQ<11>

11

M_B_DQ<12>

12

M_B_DQ<13>

13

M_B_DQ<14>

14

M_B_DQ<15>

15

M_B_DQ<16>

16

M_B_DQ<17>

17

M_B_DQ<18>

18

M_B_DQ<19>

19

M_B_DQ<20>

20

M_B_DQ<21>

21

M_B_DQ<22>

22

M_B_DQ<23>

23

M_B_DQ<24>

24

M_B_DQ<25>

25

M_B_DQ<26>

26

M_B_DQ<27>

27

M_B_DQ<28>

28

M_B_DQ<29>

29

M_B_DQ<30>

30

M_B_DQ<31>

31

M_B_DQ<32>

32

M_B_DQ<33>

33

M_B_DQ<34>

34

M_B_DQ<35>

35

M_B_DQ<36>

36

M_B_DQ<37>

37

M_B_DQ<38>

38

M_B_DQ<39>

39

M_B_DQ<40>

40

M_B_DQ<41>

41

M_B_DQ<42>

42

M_B_DQ<43>

43

M_B_DQ<44>

44

M_B_DQ<45>

45

M_B_DQ<46>

46

M_B_DQ<47>

47

M_B_DQ<48>

48

M_B_DQ<49>

49

M_B_DQ<50>

50

M_B_DQ<51>

51

M_B_DQ<52>

52

M_B_DQ<53>

53

M_B_DQ<54>

54

M_B_DQ<55>

55

M_B_DQ<56>

56

M_B_DQ<57>

57

M_B_DQ<58>

58

M_B_DQ<59>

59

M_B_DQ<60>

60

M_B_DQ<61>

61

M_B_DQ<62>

62

M_B_DQ<63>

63

OUT
OUT
OUT

OUT
OUT
OUT

CN4500

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]

AM5

SB_DQ[32]

AM6

SB_DQ[33]

AR3

SB_DQ[34]

AP3

SB_DQ[35]

AN3

SB_DQ[36]

AN2

SB_DQ[37]

AN1

SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]

AN9

SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]

AN8

SB_DQ[45]

AR6

SB_DQ[46]

AR5

SB_DQ[47]

AR9

SB_DQ[48]

AJ11

SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]

AH11

SB_DQ[52]

AR8

SB_DQ[53]

AJ12

SB_DQ[54]

AH12

SB_DQ[55]

AT11

SB_DQ[56]

AN14

SB_DQ[57]

AR14

SB_DQ[58]

AT14

SB_DQ[59]

AT12

SB_DQ[60]

AN15

SB_DQ[61]

AR15

SB_DQ[62]

AT15

SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

AA10

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

DDR SYSTEM MEMORY B

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

SB_CS#[0]

SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

SB_ODT[0]

SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AE2
AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

M_B_DQS_DN<0>
M_B_DQS_DN<1>
M_B_DQS_DN<2>
M_B_DQS_DN<3>
M_B_DQS_DN<4>
M_B_DQS_DN<5>
M_B_DQS_DN<6>
M_B_DQS_DN<7>

M_B_DQS_DP<0>
M_B_DQS_DP<1>
M_B_DQS_DP<2>
M_B_DQS_DP<3>
M_B_DQS_DP<4>
M_B_DQS_DP<5>
M_B_DQS_DP<6>
M_B_DQS_DP<7>

M_B_A<0>
M_B_A<1>
M_B_A<2>
M_B_A<3>
M_B_A<4>
M_B_A<5>
M_B_A<6>
M_B_A<7>
M_B_A<8>
M_B_A<9>
M_B_A<10>
M_B_A<11>
M_B_A<12>
M_B_A<13>
M_B_A<14>
M_B_A<15>

M_CLK_DDR2_DP

OUT

M_CLK_DDR2_DN

OUT
OUT

M_CKE2

M_CLK_DDR3_DP

OUT
OUT

M_CLK_DDR3_DN

OUT

M_CKE3

OUT

M_CS#2

OUT

M_CS#3

27<

27<
27<

27<

27<

27<

27<

D

27<

CC

OUT

M_ODT2

OUT

M_ODT3

BI

0
1
2
3
4
5
6
7

BI

0
1
2
3
4
5
6
7

M_B_A<15..0>

OUT

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15

27<
27<

M_B_DQS_DN<7..0>

M_B_DQS_DP<7..0>

27<>

BB

AA

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

INVENTEC

TITLE

EVEREST-M

CPU 3 DRAM

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:57 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

22

of

1

REV

97

A01

8 7

6 5

4 3

2

1

PVCORE

1

C4580

10uF_6.3V_3 10uF_6.3V_3

1

C4579

2

2

D

1

C4584

2

10uF_6.3V_3 10uF_6.3V_3

1

C4586

2

10uF_6.3V_3

1

C4578

2

1

2

1

C4587

2

10uF_6.3V_3

1

2

C4583

C4577

22uF_6.3V_5 22uF_6.3V_5

1

C4591

2

1

C4590

2

22uF_6.3V_5 22uF_6.3V_5

1

C4574

2

1

C4573

2

22uF_6.3V_5 22uF_6.3V_5

1

C4564

2

22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5

1

C4565

2

1

C4582

2

1

C4594

2

10uF_6.3V_3 10uF_6.3V_3

1

C4593

2

22uF_6.3V_5

1

C4589

2

22uF_6.3V_5 22uF_6.3V_5

1

C4572

2

22uF_6.3V_5

1

C4576

2

8

1

C4581

2

10uF_6.3V_310uF_6.3V_3

1

C4585

2

1

C4592

2

22uF_6.3V_5

1

C4588

2

1

C4571

2

22uF_6.3V_5

1

C4575

2

7 6

CN4500

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

POWER

PEG AND DDR

CORE SUPPLY

SVID

SENSE LINES

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

5 4

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

AJ29
AJ30
AJ28

AJ35
AJ34

B10
A10

1

C4569

+

2

3

1

2

470UF_2V

+V1.05S_VCCP_VCCIO40

20mil

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

VCCSENSE_R
VSSSENSE_R

C4599

1

C4596

2

1

C4598

2

1

C4597

2

1

C4557

2

1

2

22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5

1

C4563

22uF_6.3V_5 22uF_6.3V_5

2

22uF_6.3V_5

C4560

1

C4562

2

1

2

C4561

22uF_6.3V_5

1

2

P1V05_VCCPS

1

R4528

2

0_5%_2

P1V05_VCCPS

CLOSE TO POWER IC

1

R4546

130_1%_2

2

OUT
OUT
OUT

14<
14<

VCC_SENSE_VTT
VSS_SENSE_VTT

Fri Dec 31 10:16:58 2010

DATE

2

R4527

R4526

1

2

1

1

R4525

130_1%_2

R4551
R4549
R4550

2

2

1
1

1

PVCORE

0_5%_2

0_5%_2

R4548

54.9_1%_2

2

43_1%_2

2

0_5%_2

2

0_5%_2

1

R4504

100_1%_2

2

1

R4503

100_1%_2

2

P1V05_VCCPS

R4502

10_1%_2

10_1%_2

1

2

1

R4501

2

3

1

2

OUT
OUT

WS

CHANGE by

1

R4547

75_1%_2

2

VCCSENSE
VSSSENSE

OUT
OUT

Frank Hu

P1V05_VCCPS

C4503

1

2

22uF_6.3V_5

C4566

22uF_6.3V_5

VR_SVID_ALRT#
VR_SVID_CLK
VR_SVID_DATA

INVENTEC

TITLE

CODE

SIZE

C

C4558

1

2

14<

14<>

EVEREST-M

CPU 4 POWER

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

23

of

D

CC

BB

AA

REV

97

A01

1

8 7

6 5

4 3

2

1

WS

Function

xxVccSA_Select[1]
[[ CPU PIN# C24

VID0 of VR ]]
SNB HIGH
IVB HIGH

SNB LOW

D

IVB LOW

0
0

1
1

xxVccSA_Select[0]

[[ CPU PIN# C22
VID1 of VR ]]

0
1

0

1

VCCSA VR Vout

0.90V

0.725V

0.80V

0.675V

SLP_S3#_15R

PVAXG

CN4500

SM_VREF

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

AK35
AK34

AL1

B4
D1

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

M27
M26
L26
J26
J25
J24
H26
H25

1

1

C4509

2

C4600

1

2

22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5

1

2

C4510

2

C4601

1
2

C4604

22uF_6.3V_5_DY

1

+

32

C4506
470UF_2V

1

C4511

2

C4602

1

2

1

22uF_6.3V_5_DY

2

1

+

C4605

32

C4505
470UF_2V

1

C4512

2

22uF_6.3V_522uF_6.3V_5 22uF_6.3V_522uF_6.3V_5

C4603

1
2

22uF_6.3V_5

WS

1

C4513

2

22uF_6.3V_5

1

C4507

2

22uF_6.3V_5

1

C4514

2

22uF_6.3V_5

1

C4508

2

22uF_6.3V_5

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

POWER

LINES

GRAPHICS

VAXG_SENSE

VSSAXG_SENSE

SENSE

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

DDR3 -1.5V RAILS

P0V75_VREF_M

20/20 mil

IN

VAXG_SENSE

OUT
OUT

VSSAXG_SENSE

P0V75_VREF_M_H

6A

1

C4554

2

10uF_6.3V_3

R4524

1

0_5%_2

14<

14<

20/20 mil

CPU_CHA_VREFDQ

1

C4556

2

10uF_6.3V_3

Q4501

1
2
5

2

1

2

10uF_6.3V_3

D

NMOS_4D1S

AO6402AL

C4555

4

S

36

G

20/20 mil

1

2

CPU_CHB_VREFDQ

1

C4553

2

10uF_6.3V_3

1

C4502

2

10uF_6.3V_3

C4595

470pF_50V_2

1

C4552

2

10uF_6.3V_3

1

C4501

2

10uF_6.3V_3

WS

P1V8_S

P0V75_VREF_M_H

1

2

P1V5_CPUDDRS

1

C4551

2

10uF_6.3V_3

1

C4500

2

10uF_6.3V_3

R4523

100K_5%_2

1

C4568

2

P0V85_S

C4567

D

CC

+

220UF_2.5V

BB

1

+

2

220UF_2.5V

L4500

2

FBM_11_160808_181A15T

1

8

1

C4547

2

22uF_6.3V_5

1.1A

1

C4549

2

1uF_6.3V_2 1uF_6.3V_2

7 6

1

C4548

2

1

2

10uF_6.3V_3

VCCPLL

C4550

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

1.8V RAIL
MISC VREFSA RAIL

5 4

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

VCCIO_SEL

H23

C22
C24
A19

1

R4559

0_5%_2_DY

AA

OUT

VCCSA_SENSE

R4543

OUT

2

VCCSA_SEL

13<

1

WS

10K_5%_2

2

WS

INVENTEC

TITLE

EVEREST-M

CPU 5 POWER

CODE

SIZE

C

CHANGE by

Frank Hu

3

Mon Jan 03 17:28:06 2011

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

24

of

1

REV

97

A01

8 7

CN4500

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

D

AR19

AR16
AR13
AR10

AR7
AR4

AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10

AP7

AP4

AP1

AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AN7

AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10

AM7

AM4

AM3

AM2

AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AL7

AL4

AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AK7

AK4
AJ25

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96

VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28

AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2

W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26

N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27

K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10

G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

6 5

CN4500

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

4 3

60<

60<

60<
60<
60<
60<

60<
25<
60<
25<
25<
25<
25<
60<
60<
60<
60<

60<
60<

CFG<0>
CFG<1>
CFG<2>
CFG<3>
CFG<4>
CFG<5>
CFG<6>
CFG<7>
CFG<8>
CFG<9>
CFG<10>
CFG<11>
CFG<12>
CFG<13>
CFG<14>
CFG<15>
CFG<16>
CFG<17>

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

PEG Static Lane Reversal

CFG(2)

LOW eDP ENABLE

CFG(4)

1: (Default) Normal operation
0: Lane Reversed

1: (Default) eDP Disabled

0: eDP Enabled

PEG Defer Training

CN4500

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29

AJ31
AH31
AJ33
AH33

AJ26

CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

RSVD5

VCC_DIE_SENSE
VSS_DIE_SENSE

RESERVED

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

RSVD28
RSVD29
RSVD30
RSVD31
RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9

RSVD_NCTF10

RSVD51
RSVD52

BCLK_ITP

BCLK_ITP#

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

KEY

L7
AG7
AE7
AK2
W8

AT26
AM33
AJ27

AH27
AH26

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AN35
AM35

AT2
AT1
AR1

B1

2

1

D

CC

IN

CLK_XDP_CLKGEN_DP

IN

CLK_XDP_CLKGEN_DN

BB

AA

PEG Static Lan Reversal

LOW eDP ENABLE

PCIE Port Bifurcation

PEG Defer Training

STRAP PIN

8

R4522

R4521

R4520

R4519

R4518

25>60<

CFG<2>

CFG<4>
CFG<5>

CFG<6>
CFG<7>

IN
IN
IN

IN
IN

7 6

1K_1%_2

1

1

1
1

1

2

1K_1%_2

2

2

1K_1%_2_DY

2

1K_1%_2_DY

2

1K_1%_2_DY

CFG(7)

1: (Default) PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

PCIE Port Bifurcation Straps

CFG[6:5]

5 4

11: (Default) x16 - Device 1 function 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled
00: x8, x4, x4 - Device 1 function 1 and 2 enabled

INVENTEC

TITLE

EVEREST-M

CPU 6 GND

CODE

SIZE

CS

CHANGE by

Frank Hu

3

Fri Dec 31 10:16:59 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

25

of

1

REV

97

A01

8 7

6 5

CHA

4 3

2

1

22>

M_A_A<15..0>

D

22>
22>
22>

22>

26<
26<

SA0_DIM0
SA1_DIM0

60< 27<

22<>

22<>

OUT
OUT

59<> 29<>

M_A_DQS_DP<7..0>

M_A_DQS_DN<7..0>

BI

22>

M_A_BS0

22>

M_A_BS1

22>

M_A_BS2

22>

M_CS#0

22>

M_CLK_DDR0_DP

M_CLK_DDR0_DN

M_CLK_DDR1_DP
M_CLK_DDR1_DN

M_CS#1

M_CKE0

22>

M_CKE1

22>

22>

M_A_CAS#

22>

M_A_RAS#

22>

M_A_WE#

PCH_3S_SMCLK

PCH_3S_SMDATA

22>

M_ODT0

22>

M_ODT1

IN

IN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15

M_A_DQS_DP<0>

0

M_A_DQS_DP<1>

1

M_A_DQS_DP<2>

2

M_A_DQS_DP<3>

3

M_A_DQS_DP<4>

4

M_A_DQS_DP<5>

5

M_A_DQS_DP<6>

6

M_A_DQS_DP<7>

7

M_A_DQS_DN<0>

0

M_A_DQS_DN<1>

1

M_A_DQS_DN<2>

2

M_A_DQS_DN<3>

3

M_A_DQS_DN<4>

4
5

M_A_DQS_DN<5>
M_A_DQS_DN<6>

6

M_A_DQS_DN<7>

7

M_A_A<0>
M_A_A<1>
M_A_A<2>
M_A_A<3>
M_A_A<4>
M_A_A<5>

M_A_A<6>
M_A_A<7>

M_A_A<8>
M_A_A<9>
M_A_A<10>
M_A_A<11>
M_A_A<12>
M_A_A<13>

M_A_A<14>
M_A_A<15>

107

119

109
108

114
121
101
103
102
104

115
110
113

197
201
202
200

116

120

136

153

170

187

137

154

171

188

135

152

169

186

98
97
96
95
92
91
90
86
89
85

84
83

80
78

79

73
74

11
28
46
63

12
29
47
64

10
27
45
62

CN4101

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

BELLW_80001_6021_204P

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

5
7

15

17
4
6

16

18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70

129

131

141

143

130

132

140

142

147

149

157

159

146

148

158

160

163

165

175

177

164

166

174

176

181

183

191

193

180

182

192

194

M_A_DQ<0>

M_A_DQ<1>

M_A_DQ<2>

M_A_DQ<3>
M_A_DQ<4>
M_A_DQ<5>
M_A_DQ<6>
M_A_DQ<7>
M_A_DQ<8>
M_A_DQ<9>
M_A_DQ<10>
M_A_DQ<11>
M_A_DQ<12>
M_A_DQ<13>
M_A_DQ<14>
M_A_DQ<15>
M_A_DQ<16>
M_A_DQ<17>
M_A_DQ<18>
M_A_DQ<19>
M_A_DQ<20>
M_A_DQ<21>
M_A_DQ<22>
M_A_DQ<23>
M_A_DQ<24>
M_A_DQ<25>
M_A_DQ<26>
M_A_DQ<27>
M_A_DQ<28>
M_A_DQ<29>
M_A_DQ<30>
M_A_DQ<31>
M_A_DQ<32>
M_A_DQ<33>
M_A_DQ<34>
M_A_DQ<35>
M_A_DQ<36>
M_A_DQ<37>
M_A_DQ<38>
M_A_DQ<39>
M_A_DQ<40>
M_A_DQ<41>
M_A_DQ<42>
M_A_DQ<43>
M_A_DQ<44>
M_A_DQ<45>
M_A_DQ<46>
M_A_DQ<47>
M_A_DQ<48>
M_A_DQ<49>
M_A_DQ<50>
M_A_DQ<51>
M_A_DQ<52>
M_A_DQ<53>
M_A_DQ<54>
M_A_DQ<55>
M_A_DQ<56>
M_A_DQ<57>
M_A_DQ<58>
M_A_DQ<59>
M_A_DQ<60>
M_A_DQ<61>
M_A_DQ<62>
M_A_DQ<63>

C4126

1

2

2.2UF_6.3V_2

22<>

C4122

1

2

1UF_6.3V_2

P3V3_S

1

2

P1V5

C4125

1
2

C4127

0.1UF_16V_2

DIMM0_VREF_DQ

1
2

C4119

1
2

0.1UF_16V_2

C4124

LAYOUT NOTE: PLACE
THESE CAPS NEAR
SO-DIMM0 POWER PIN

C4123

1
2

1UF_6.3V_21UF_6.3V_21UF_6.3V_2

C4140

1
2

1

C4137

2

26< 27>

18>
27>

DIMM0_VREF_CA

C4120

1
2

2.2UF_6.3V_2 0.1UF_16V_2

C4139

1
2

10UF_6.3V_310UF_6.3V_3

1

C4136

10UF_6.3V_310UF_6.3V_3

2

PM_EXTTS#1_R

DDR3_DRAMRST#

C4121

1
2

PLACE THESE CAPS
CLOSE TO VTT1 AND
VTT2

C4138

1
2

10UF_6.3V_3

1

C4135

10UF_6.3V_3

2

OUT
OUT

20/20 MIL

20/20 MIL

75
76
81
82
87
88
93
94

99
100
105
106
111
112
117
118
123
124

199

77
122
125

198

30

1

126

2
3
8

9
13
14
19

20
25
26
31
32
37
38
43

BELLW_80001_6021_204P

CN4101

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

VDDSPD

NC1
NC2
NCTEST

EVENT#
RESET#

VREF_DQ
VREF_CA

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

VTT1
VTT2

44
48
49
54
55
60
61
65
66
71
72

127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

1.5A

203
204

G1

G1

G2

G2

NOTE:PLACE C4100
ON COMMON PATH

FOR BOTH DIMM'S

C4110

1
2

C4100

1
2

1UF_6.3V_21UF_6.3V_2

1

2

C4109

1UF_6.3V_2

P0V75_S

C4128

1
2

1UF_6.3V_2

D

CC

BB

M_A_DQ<63..0>

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

21
22
23
24

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

BI

NOTE:

IF SA0_DIM0=0 , SA1_DIM0=0
SO-DIMMA SPD ADDRESS IS 0XA0
SO-DIMMA TS ADDRESS IS 0X30

IF SA0_DIM0=1 , SA1_DIM0=0
SO-DIMMA SPD ADDRESS IS 0XA2
SO-DIMMA TS ADDRESS IS 0X32

8

7 6

P3V3_S

1

1

R4102

10K_5%_2_DY

R4100

10K_5%_2 10K_5%_2

2

2

1

1

2

2

R4125

10K_5%_2_DY

R4101

IN

IN

SA0_DIM0

SA1_DIM0

26>

26>

26>27>

PM_EXTTS#1_R

IN

5 4

1

0_5%_2

R4127

2

P3V3_S

1

R4126

10K_5%_2

2

OUT

PM_EXTTS#1

WS

REMOVE 1UF CAP 1PCS

AA

INVENTEC

TITLE

EVEREST-M
DDR3 DIMM0

CODE

SIZE

CS

CHANGE by

Frank Hu

3

Fri Dec 31 10:17:00 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

26

of

1

REV

97

A01

8 7

6 5

4 3

2

1

CHB

22>

M_B_A<15..0>

D

22>

22>

22>

22>

27<
27<

SA0_DIM1
SA1_DIM1

60<

22<>

22<>

OUT
OUT

29<>

59<>

26<

M_B_DQS_DP<7..0>

M_B_DQS_DN<7..0>

BI

22>

M_B_BS0

22>

M_B_BS1

22>

M_B_BS2

22>

M_CS#2

22>

M_CLK_DDR2_DP

M_CLK_DDR2_DN

M_CLK_DDR3_DP

M_CLK_DDR3_DN

PCH_3S_SMDATA

M_CS#3

22>

M_CKE2

22>

M_CKE3

22>

M_B_CAS#

22>

M_B_RAS#

22>

M_B_WE#

PCH_3S_SMCLK

22>

M_ODT2

22>

M_ODT3

IN

IN

107

119

109
108

114
121
101
103
102
104

115
110
113

197
201
202
200

116

120

136

153

170

187

137

154

171

188

135

152

169

186

98
97
96
95
92
91
90
86
89
85

84
83

80
78

79

73
74

11
28
46
63

12
29
47
64

10
27
45
62

CN4100

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

BELLW_80001_2021_204P

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

M_B_DQ<0>
M_B_DQ<1>

M_B_DQ<2>
M_B_DQ<3>

M_B_DQ<4>
M_B_DQ<5>
M_B_DQ<6>
M_B_DQ<7>
M_B_DQ<8>
M_B_DQ<9>
M_B_DQ<10>

M_B_DQ<11>
M_B_DQ<12>
M_B_DQ<13>

M_B_DQ<14>
M_B_DQ<15>
M_B_DQ<16>
M_B_DQ<17>

M_B_DQ<18>
M_B_DQ<19>
M_B_DQ<20>
M_B_DQ<21>
M_B_DQ<22>
M_B_DQ<23>
M_B_DQ<24>
M_B_DQ<25>
M_B_DQ<26>
M_B_DQ<27>
M_B_DQ<28>
M_B_DQ<29>
M_B_DQ<30>
M_B_DQ<31>
M_B_DQ<32>
M_B_DQ<33>
M_B_DQ<34>
M_B_DQ<35>
M_B_DQ<36>
M_B_DQ<37>
M_B_DQ<38>
M_B_DQ<39>
M_B_DQ<40>
M_B_DQ<41>
M_B_DQ<42>
M_B_DQ<43>
M_B_DQ<44>
M_B_DQ<45>

M_B_DQ<46>
M_B_DQ<47>
M_B_DQ<48>
M_B_DQ<49>
M_B_DQ<50>
M_B_DQ<51>

M_B_DQ<52>
M_B_DQ<53>

M_B_DQ<54>
M_B_DQ<55>

M_B_DQ<56>
M_B_DQ<57>

M_B_DQ<58>
M_B_DQ<59>

M_B_DQ<60>
M_B_DQ<61>

M_B_DQ<62>
M_B_DQ<63>

0

1

2
3
4
5

6

7

8

9
10
11
12
13
14
15
16

17
18
19

20

21

22
23

24

25

26
27
28
29

30
31
32
33
34

35
36
37
38
39
40
41
42

43
44

45
46
47
48
49

50

51
52
53
54
55
56
57
58
59
60
61
62
63

M_B_A<0>

0

1

M_B_A<1>
M_B_A<2>

2

M_B_A<3>

3

M_B_A<4>

4

M_B_A<5>

5

M_B_A<6>

6

M_B_A<7>

7

M_B_A<8>

8

M_B_A<9>

9

M_B_A<10>

10

M_B_A<11>

11

M_B_A<12>

12

M_B_A<13>

13

M_B_A<14>

14
15

M_B_A<15>

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

M_B_DQS_DP<0>

0

M_B_DQS_DP<1>

1

M_B_DQS_DP<2>

2

M_B_DQS_DP<3>

3

M_B_DQS_DP<4>

4

M_B_DQS_DP<5>

5

M_B_DQS_DP<6>

6

M_B_DQS_DP<7>

7

M_B_DQS_DN<0>

0

M_B_DQS_DN<1>

1

M_B_DQS_DN<2>

2

M_B_DQS_DN<3>

3

M_B_DQS_DN<4>

4
5

M_B_DQS_DN<5>
M_B_DQS_DN<6>

6

M_B_DQS_DN<7>

7

M_B_DQ<63..0>

BI

WS

REMOVE CPU_CHB_VREFDQ

NOTE:

SO-DIMMB SPD ADDRESS IS 0XA4

SO-DIMMB TS ADDRESS IS 0X34

SA1_DIM1

27>

IN

R4104

10K_5%_2

R4123

10K_5%_2_DY

22<>

C4112

1
2

1UF_6.3V_2

DIMM1_VREF_DQ

P3V3_S

1

1

R4124
10K_5%_2_DY

2

2

1

1

R4103
10K_5%_2

2

2

P1V5

1
2

IN

C4115

1UF_6.3V_2

1
2

SA0_DIM1

C4116

27>

C4114

1

2

1UF_6.3V_2

C4113

1

2

1UF_6.3V_2

P3V3_S

C4117

1
2

0.1UF_16V_22.2UF_6.3V_2

0.1UF_16V_2

LAYOUT NOTE: PLACE

THESE CAPS NEAR

SO-DIMM0 POWER PIN

C4134

1
2

10UF_6.3V_3

C4131

1
2

10UF_6.3V_3

PM_EXTTS#1_R

DDR3_DRAMRST#

1

C4104

DIMM1_VREF_CA

2

C4133

1
2

10UF_6.3V_3

C4130

1
2

10UF_6.3V_3 10UF_6.3V_3

C4105

1
2

2.2UF_6.3V_2

C4132

1
2

10UF_6.3V_3

C4129

1
2

1
2

PLACE THESE CAPS
CLOSE TO VTT1 AND
VTT2

OUT
OUT

20/20 MIL

20/20 MIL

C4106

0.1UF_16V_2

CN4100

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

BELLW_80001_2021_204P

C4108

1

2

1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2

20/20 MIL

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

VTT1
VTT2

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

1.5A

203
204

G1

G1

G2

G2

C4107

1
2

PLACE THESE CAPS
CLOSE TO VTT1 AND
VTT2

P0V75_S

C4102

1

2

C4101

1
2

D

CC

BB

CPU_CHA_VREFDQ

R4128

1K_5%_2_DY

DRAMRST_CNTRL_CPU

8

P0V75_VREF_M

P1V5_CPUDDRS

R4130

C4103

P1V5

1

2

1

2

DIMM1_VREF_DQ

1

R4122

1K_1%_2

2

1

R4121

1K_1%_2

2

R4143

2

1

0_5%_2_DY

1

R4119

0_5%_2

CPU_CHB_VREFDQ

R4120

2

1

0_5%_2_DY

2

1

R4110

1

0_5%_2

R4141
0_5%_2_DY

2

Q4101

1

D

2
5

NMOS_4D1S

AO6402AL

4

S

36

G

2

IN

5 4

1

2

P1V5

DIMM0_VREF_DQ

R4114

2

1

0_5%_2_DY

Q4100

4

S

1

2

3 6

G

NMOS_4D1S

AO6402AL

R4115

1

1

D

2

0_5%_2

5

IN

R4111

1

2

0_5%_2

R4142

1

0_5%_2_DY

R4144

1

0_5%_2_DY

R4118

1K_1%_2

2

R4117

1K_1%_2

1

2

2

1

1

2

2

2

2

R4129

1K_5%_2_DY

C4118

0.1UF_16V_2

1K_5%_2_DY

0.1UF_16V_2

1

7 6

DIMM0_VREF_CA

1K_5%_2_DY

R4131

1K_5%_2_DY

DRAMRST_CNTRL_CPU

1K_5%_2_DY

P1V5

R4132

R4133

1

R4136
0_5%_2

2

1

1

R4137

0_5%_2

2

2

1

2

1

2

R4138

1

C4141

0.1UF_16V_2

0_5%_2_DY

R4105

2

1

2

3

DIMM1_VREF_CA

R4139

2

1

0_5%_20_5%_2

1

2

CHANGE by

R4140

1

0_5%_2

R4116
0_5%_2_DY

2

1

0_5%_2_DY

Frank Hu

R4112

P1V5

1

R4134

1K_5%_2_DY

2

2

1

R4135

1K_5%_2_DY

2

Fri Dec 31 10:16:30 2010

DATE

2

1

C4142

0.1UF_16V_2_DY

2

INVENTEC

TITLE

CODE

SIZE

C

WS

EVEREST-M

DDR3 DIMM1

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

27

AA

REV

97

of

A01

1

8 7

P3V3_AL

1

2

NC

3

1

RTC BATTERY

2

D

U4703

1

+

2

-

MAXELL_ML1220_T10_2P

H-VCC VRM=1.5V
L- (Default) VCC VRM=1.8V

HDA_3S_SYNC

PCSPKR_PCH_3

No Reboot
1: No Reboot enabled

0: (Default) No Reboot disabled

HDA_3S_SDOUT

STRAP
Flash Override

Disable - (Default)Internal pull-down

Enable - pull-up

HDA_3S_SYNC_R

PCH_SPI_SI

FLASH DESCRIPTOR SECURITY OVERIDE

HDA_3S_SDOUT_R

FLASH_OVERRIDE

28<>
28<>

28<>

PCH_SPI_CS0#

28<>

PCH_SPI_SO

1

2

SIG442

1K_5%_2_DY

BI

OUT

OUT

OUT

BI

R4893

1

0_5%_2

IN

Q4705

AM2321P_DY

PCH_SPI_CS0#

PCH_SPI_SO

8

D4704

BAT54_30V_0.2A

+V_RTC

R4777

150_1%_3

R4778

1.2K_1%_3

P3V3_S

1

R4782

2

R4851

2

10K_5%_2_DY

R4783

2

1K_5%_2

P3V3_S

1

R4785

10K_5%_2_DY

2

HIGH:ENABLE
LOW:DISABLE

2

OUT

3

1

G

S D

2

BI
BI

+V3M_SPI

2

R4764

3.3K_5%_2

1

BI
BI

+V_RTC

C4762

1uF_6.3V_2

WS

P5V_S

1

Q4703

G

3

2

DS

SSM3K7002FU

P3V3_A

1

1

WS

STRAP PIN
HIGH - ENABLE ANTITHEFT
LOW - Internal

WS

HDA_3S_SDOUT_R

P3V3_A

R4892

1

2

1K_5%_2_DY

WINB_W25Q64BVSSIG_SOIC_8P

CN4701

1
2
3
4

ACES_91960_0084L_8P

2

10K_5%_2

1

1
2
3
4

CE#
SO
WP#
VSS

R4765

U4702

/CS
DO_IO1
/WP_IO2
GND

VDD

HOLD#

SCK

SI

/HOLD_IO3

DIO_ID0

7 6

R4762

1

20K_1%_2

R4760

1

1

R4761

1M_5%_2

20K_1%_2

1

2

2

STRAP

HDA_3S_BITCLK

HDA_3S_RST#

HDA_3S_SDIN0

HDA_3S_SDOUT

37>

EC_SMI

28<>

PCH_SPI_CLK

28<>

PCH_SPI_CS0#

PCH_SPI_CS1#

+V3M_SPI

VCC

CLK

28<>

28<>

8
7

6

5

BI
BI

8

R4766

7
6

BI

5

BI

2

1

1uF_6.3V_2

2

2

1

1uF_6.3V_2

2

R4813

BI

OUT

IN

OUT

IN

R4773

1

60>

60<>

PCH_TCK

61>

PCH_SPI_SI

PCH_SPI_SO

PCH_SPI_CLK
PCH_SPI_SI

3.3K_5%_2

1

2

PCH_SPI_CLK
PCH_SPI_SI

6 5

+V_RTC

C4763

330K_5%_3

C4761

R4759

1

2

+V_RTC_RTCRST#

+V_RTC_SRTCRST#

+V_RTC_INTRUDER#

R4767

R4770

R4769

WS

2

60<>

60<>

BI
BI

0_5%_2_DY

2

1

C4779

1

12pF_50V_2

51_5%_2

OUT

R4812

R4755

1

1

60>

60>

Q4704

2

SSM3K7002FU

2

1

28>

28>

1
1

33_1%_2

2

33_1%_2

2

33_1%_2

2

P5V_S

1

G

3

DS

dgnd

TP4713

PCH_TMS
PCH_TDI
PCH_TDO

33_5%_2

2

0_5%_2

2

HDA_3S_BITCLK_R

HDA_3S_SYNC_R

HDA_3S_RST#_R

1

33_1%_2

1

61>

61<

OUT

33_5%_2

1

BI
BI

28<>
28<>

+V3M_SPI

28<>

28<>

R4756

R4754

37<

37<

37<

1

C4764

0.1UF_16V_2

2

1

2

33_5%_2

2

37>

EC_SPI_CLK

EC_SPI_CS0#

37>

EC_SPI_SI

37>

EC_SPI_SO

1

R4772

10M_5%_2

2

RTCX1
RTCX2

R4768

2

HDA_3S_SDOUT_R

OUT
OUT
OUT

PCH_SPI_CLK_R

PCH_SPI_CS0#_R

PCH_SPI_MOSI_R

OUT

OUT

OUT

CLOSED TO EC

4

X4701

32.768KHZ

1

2 3

U4700

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN#/GPIO33

N32

HDA_DOCK_RST#/GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

ITL_PANTHERPOINT_FCBGA_989P

R4800

1

33_5%_2_DY

33_5%_2_DY

33_5%_2_DY

1

0_5%_2_DY

R4799

1

R4798

1

R4797

2

2

2

1

0_5%_2_DY

1

0_5%_2_DY

1

0_5%_2_DY

1

0_5%_2_DY

CLOSED TO PCH

5 4

4 3

+V3M

C4766

2

18pF_50V_2

C4765

2

18pF_50V_2

JTAG

R4804

R4803

R4802

R4801

1

1

RTC

IHDA

SPI

2

22

2

2

INTVRMEN-

high- Enable Internal VRs
low-Enable External VRs

LPC

SATA 6G

SATA

BI

PCH_SPI_CLK

BI

PCH_SPI_CS0#

BI

PCH_SPI_SI

BIIN

PCH_SPI_SO

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

R4786

1

0_5%_3

1.05V VRM Enable

C38
A38
B37
C37

D36
E36

K36
V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11
Y10

AB12
AB13

AH1

P3
V14
P1

+V3M_SPI

2

BI
BI
BI
BI

OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

+V1.05S_SATAICOMPO

+V1.05S_SATA3RCOMPO

PCH_XDPFN10
PCH_XDPFN11

R4850

1K_5%_2_DY

28<>

STRAP PIN

28<>

PCH_SPI_CS1#

28<>

28<>

CHANGE by

3

2

P3V3_A

+V1.05S

60> 28>

61>

60<>

PCH_TDI

60>

28>

PCH_TMS

61>

60<>
60>

28>

PCH_TDO

61<

60<>

LPC_3S_AD<0>
LPC_3S_AD<1>
LPC_3S_AD<2>
LPC_3S_AD<3>

R4707

1

0_5%_2

R4708

1

RSC_0402_DY

LPC_3S_FRAME#

R4758

1

10K_5%_2

BI

PCI_3S_SERIRQ

SATA_SSD_RX_DN
SATA_SSD_RX_DP
SATA_SSD_TX_DN
SATA_SSD_TX_DP

SATA_HDD_RX_DN
SATA_HDD_RX_DP
SATA_HDD_TX_DN

SATA_HDD_TX_DP
SATA_ODD_RX_DN

SATA_ODD_RX_DP
SATA_ODD_TX_DN
SATA_ODD_TX_DP

SATA_ESATA_RX_DN
SATA_ESATA_RX_DP

SATA_ESATA_TX_DN
SATA_ESATA_TX_DP

SATA_mSATA_RX_DN
SATA_mSATA_RX_DP

SATA_mSATA_TX_DN
SATA_mSATA_TX_DP

R4890

1

750_1%_2

1
2

OUT

Frank Hu

2

2

OUT

PCH_XDPFN11

R4763

1

RSC_0402_DY

DATE

Sun Jan 02 19:22:09 2011

2

2

OUT
OUT
OUT

37<>
37<>
37<>

55<
37<>
43<

WS

R4757

1

37.4_1%_2

R4891

1

49.9_1%_2

R4852

10K_5%_2

2

2

Placememt note

1

R4706

210_1%_2

2

1

R4705

100_1%_2

2

55<

43<

55<43<

43< 55<

P3V3_S

37<>

55<

43<

SATA SSD

SATA HDD

SATA ODD

eSATA

mSATA

+V1.05S

2

+V1.05S

2

P3V3_S

121

2

28>

1

R4823

0_5%_2_DY

2

INVENTEC

TITLE

SIZE

C

1

R4704

210_1%_2

2

1

R4703

100_1%_2

2

R4771

10K_5%_2

OUT

LED_3S_SATA#

OUT

PCH_XDPFN10

EVEREST-M
PCH 1

CODE

CS

CS_1310AXXXXXX-MTR

SHEET

2

1

2

DOC.NUMBER

28

1

1

R4702

210_1%_2

R4701

100_1%_2

of

1

D

CC

Distance between the PCH and

cap on the "P" signal should be
identical distance between the
PCH and cap on the "N" signal

for same pair

BB

58<

28>

AA

REV

A01

97

8 7

6 5

4 3

2

1

WS

CLKREQ_USB3#

CLKREQ_CR#

D

CLKREQ_WLAN#

27<
59<>
26<
60<

PCH_3S_SMCLK

29<>

PCH_3A_SMCLK

PCH_3A_SMDATA

55<>

PCH_3S_SMDATA

IN

IN

IN

CLKREQ_LAN#

IN

STUFF FOR INTEGRATED CLK

CLKIN_DMI_PCH_DN

CLKIN_DMI_PCH_DP

CLKIN_BUF_DOT96_DN

CLKIN_BUF_DOT96_DP

CLKIN_PCH14

CLKIN_SATA1_DP
CLKIN_SATA1_DN

R4745

2.2K_5%_2

BI

BI

BI

BI

8

10K_5%_2_DY

10K_5%_2_DY

P3V3_S

1

1

2

2

R4894

1

10K_5%_2

R4895

1

10K_5%_2

R4731

1

10K_5%_2

R4730

1

R4748

1

R4744

2.2K_5%_2

R4743

2.2K_5%_2

P3V3_S

2

2

P3V3_A

2

2

2

R4796

IN

R4795

IN

R4794

IN

R4793

IN

R4792

IN

R4788

IN

R4787

IN

P3V3_A

1

1

2

2

USB3.0

CARD READER

WLAN

2

1

1

2

1

2

1

2

1

2

1

2

1

2

P5V_S

R4742

2.2K_5%_2

2

1

G

DS

Q4703

3

SSM3K7002BFU

3

DS

1

G

Q4702

2

SSM3K7002BFU

60<

CLK_XDP_DN
CLK_XDP_DP

60<

7 6

3G

LAN

10K_5%_2

10K_5%_2

10K_5%_2

10K_5%_2

10K_5%_2

10K_5%_2

10K_5%_2

PCIE_USB3_RX_DN
PCIE_USB3_RX_DP
PCIE_USB3_TX_DN
PCIE_USB3_TX_DP

PCIE_CR_RX_DN
PCIE_CR_RX_DP
PCIE_CR_TX_DN
PCIE_CR_TX_DP

PCIE_WLAN_RX_DN
PCIE_WLAN_RX_DP

PCIE_WLAN_TX_DN
PCIE_WLAN_TX_DP

PCIE_3G_RX_DN
PCIE_3G_RX_DP
PCIE_3G_TX_DN
PCIE_3G_TX_DP

WS

PCIE_LAN_RX_DN
PCIE_LAN_RX_DP
PCIE_LAN_TX_DN
PCIE_LAN_TX_DP

P3V3_A

CLK_PCIE_LAN_DN

CLK_PCIE_LAN_DP

CLKREQ_LAN#

OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

C4780
C4781

C4782
C4783

C4758
C4757

C4784
C4785

C4760
C4759

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

P3V3_A

WS

1

CLK_PCIE_USB3_DN
CLK_PCIE_USB3_DP

CLKREQ_USB3#

CLK_PCIE_CR_DN
CLK_PCIE_CR_DP

CLKREQ_CR#

CLK_PCIE_WLAN_DN

CLK_PCIE_WLAN_DP

CLKREQ_WLAN#

WS

CLK_PCIE_3G_DN
CLK_PCIE_3G_DP

CLKREQ_3G#

R4814

R4774

OUT
OUT

1

1

R4816
R4815

2

2

1
1

10K_5%_2

10K_5%_2

2
2

IN

1

10K_5%_2

2

1
1

0_5%_2

2

0_5%_2

2

REMOVE CLK_XDP_CLKGEN_DN

REMOVE CLK_XDP_CLKGEN_DP

WS

R4889
R4859

R4858

PCIE_USB3_TX_C_DN

2

1

PCIE_USB3_TX_C_DP

2

1

1

2

2

1

PCIE_WLAN_TX_C_DN

211

PCIE_WLAN_TX_C_DP

2

PCIE_3G_TX_C_DN

1

2

PCIE_3G_TX_C_DP

1

2

PCIE_LAN_TX_C_DN

1

2

PCIE_LAN_TX_C_DP

1

2

TP4711

R4740

TP4703

0_5%_2
0_5%_2

TP4705

CLKOUT_ITPXDP_DN
CLKOUT_ITPXDP_DP

PCIE_CR_TX_C_DN
PCIE_CR_TX_C_DP

TP4712

1

1

10K_5%_2

2

OUT
OUT

IN

OUT
OUT

IN

OUT
OUT

IN

OUT
OUT

IN

TP4704

CLK_PCIE_LAN_R_DN
CLK_PCIE_LAN_R_DP

1

TP4706

1

1

1

U4700

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40
Y39

J2

PCIECLKRQ0#/GPIO73

AB49
AB47

M1

PCIECLKRQ1#/GPIO18

AA48

AA47

V10

PCIECLKRQ2#/GPIO20

Y37
Y36

A8

PCIECLKRQ3#/GPIO25

Y43
Y45

L12

PCIECLKRQ4#/GPIO26

V45
V46

L14

PCIECLKRQ5#/GPIO44

AB42
AB40

E6

PEG_B_CLKRQ#/GPIO56

V40

V42

T13

PCIECLKRQ6#/GPIO45

V38
V37

K12

PCIECLKRQ7#/GPIO46

AK14
AK13

CLKOUT_PCIE0N
CLKOUT_PCIE0P

CLKOUT_PCIE1N
CLKOUT_PCIE1P

CLKOUT_PCIE2N
CLKOUT_PCIE2P

CLKOUT_PCIE3N
CLKOUT_PCIE3P

CLKOUT_PCIE4N
CLKOUT_PCIE4P

CLKOUT_PCIE5N
CLKOUT_PCIE5P

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

PCI-E*

ITL_PANTHERPOINT_FCBGA_989P

5 4

CLOCKS

P3V3_A

2

PCH_3A_SMCLK

29<>

PCH_3A_SMDATA

DRAMRST_CNTRL_PCH
SML0_CLK

39<>

39<>

SML0_DATA

SML1ALERT#
SML1_CLK
SML1_DATA

CL_CLK
CL_DATA
CL_RST#

29<

29<>

29<>

55>

55>

55>

29<>

29<

29<

55<>

55<>

SML1ALERT#

39<>

37<>

EC_SMB3_CLK

29>

SML1_DATA

37<>

EC_SMB3_DATA

29>

39<>

SML0_CLK

29>

SML0_DATA

29>

SML1_CLK

P3V3_A

R4741

IN

1

10K_5%_2

1

2.2K_5%_2

1

2.2K_5%_2

IN

IN

BI

BI

BI

BI

1

2.2K_5%_2

1

2.2K_5%_2

2

SSM3K7002BFU

DS

3

2

SSM3K7002BFU

DS

3

R4752

R4751

R4750

R4749

G

Q4701

Q4700

2

2

2

2

2

D

P3V3_A

1

1

G

SMBUS

SML1ALERT#/PCHHOT#/GPIO74

Link

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

10K_5%_2

E12
H14
C9

A12
C8
G12

C13
E14
M16

M7

T11

P10

R4753

1

BI
BI

IN
OUT
OUT

IN
OUT
OUT

OUT

OUT

OUT

Controller

CC

BB

AA

FLEX CLOCKS

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

M10

AB37
AB38

AV22
AU22

AM12
AM13

BF18
BE18

BJ30
BG30

G24
E24

AK7
AK5

K45

H45

V47
V49

IN

OUT
OUT

OUT
OUT

OUT
OUT

IN

IN

IN
IN

IN
IN

IN

IN

OUT
OUT

Y47

K43
F47

CLK_GPU_27M_SS_R

H47
K49

OUT

CLKREQ_GPU_PEG#
CLK_PEG_GPU_REF_DN

CLK_PEG_GPU_REF_DP
CLK_DMI_PCH_DN

CLK_DMI_PCH_DP
CLK_DP_PCH_CPU_DN

CLK_DP_PCH_CPU_DP
CLKIN_DMI_PCH_DN

CLKIN_DMI_PCH_DP

CLKIN_BUF_DOT96_DN
CLKIN_BUF_DOT96_DP

CLKIN_SATA1_DN
CLKIN_SATA1_DP

CLKIN_PCH14

59> 29<

29<59>

CLKIN_PCI_FB
XTAL25_IN

XTAL25_OUT

R4747

1

90.9_1%_2

1

22_5%_2

DGPU_PRSNT#

29>

2

CLOSE TO PCH

R4700

2

29>

OUT

67<

20<

18pF_50V_2

1

R4854

10K_5%_2

2

+V1.05S

CLK_GPU_27M

C4777

1

R4855

10K_5%_2

2

OUT

1

R4849

X4700

1

25MHz

1

2

CLKIN_BUF_CPYCLK_DN

IN
IN

CLKIN_BUF_CPYCLK_DP

2

2

1

C4776

18pF_50V_2

2

1M_5%_2

OUT

XTAL25_OUT

29>

29>

XTAL25_IN

INVENTEC

TITLE

EVEREST-M
PCH 2

CODE

SIZE

C

CHANGE by

Frank Hu

3

Sun Jan 02 15:32:31 2011

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

29

of

1

REV

97

A01

8 7

6 5

4 3

2

1

DSWVRMEN- Deep S4/S5 Well On-Die Voltage Regulator Enable

high-Enabled(Default)

low-Disabled

U4700

BC24

21>

DMI_RX_DN<0>

21>

DMI_RX_DN<1>

21>

DMI_RX_DN<2>

21>

DMI_RX_DN<3>

D

+V1.05S

1

R4739

49.9_1%_2

2

21>

DMI_RX_DP<0>

21>

DMI_RX_DP<1>

21>

DMI_RX_DP<2>

21>

DMI_RX_DP<3>

21<

DMI_TX_DN<0>

21<

DMI_TX_DN<1>

21<

DMI_TX_DN<2>

21<

DMI_TX_DN<3>

21<

DMI_TX_DP<0>

21<

DMI_TX_DP<1>

21<

DMI_TX_DP<2>

21<

DMI_TX_DP<3>

IN
IN
IN
IN

IN
IN
IN
IN

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

1

750_1%_2

R4888

2

BE20
BG18
BG20

BE24
BC20
BJ18
BJ20

AW24
AW20
BB18
AV18

AY24
AY20
AY18
AU18

BJ24
BG25
BH21

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

DMI

FDI

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

P3V3_S

60>

20>

SYS_RESET#

1

R4734

10K_5%_2

2

EC

SUSACK#_EC

IN

IN

R4887

1

0_5%_2_DY

2

SUSACK#_R

C12

K3

SUSACK#

SYS_RESET#

CLOSE TO IC

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT/GPIO31

E10

BATLOW#/GPIO72

A10

RI#

ITL_PANTHERPOINT_FCBGA_989P

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

System Power Management

SLP_LAN#/GPIO29

SUS_PWR_ACK_R

37>

EC_PWRSW#

60>

XDP_PWRSW#

IN

IN

BAT54_30V_0.2A

IN

LOW_BAT#_3

D4702

3

R4847

1

0_5%_2

2

NC

IN

2

1

OUT

SUSACK#_R

P3V3_A

1

R4738

10K_5%_2

2

R4846

1

0_5%_2

2

D4703

3

BAT54_30V_0.2A

ALLSYS_PWROK
EC_PCH_PWROK

18>

PM_APWROK

PM_DRAM_PWRGD

37>

SUS_PWR_ACK

2

NC

1

RSMRST#

37<

30<

ACPRESENT

30<

IN

IN

IN

OUT

IN

OUT

PM_RI#

2

C4778

0.1UF_10V_2_DY

2

C4769

0.1UF_10V_2_DY

0.1UF_10V_2_DY

1

1

C4768

R4886

0_5%_2

R4848

0_5%_2

2

2

2

IN

IN

1

1

1

RSMRST#_R

SUS_PWR_ACK_R

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

DSWVRMEN

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16
AV12
BC10
AV14
BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

P3V3_A

R4883

1

0_5%_2

37<

19<

37<

21<

21<

21<

21<

55<>

30<

37>

37<

17<11< 18<

37<

20<>

21>
21>
21>
21>
21>
21>
21>
21>

21>
21>
21>
21>
21>
21>
21>
21>

2

37<>

37<

19<12<

C4767

0.1UF_10V_2_DY

30<

37<30>

IN

FDI_TX_DN<0>

IN

FDI_TX_DN<1>

IN

FDI_TX_DN<2>

IN

FDI_TX_DN<3>

IN

FDI_TX_DN<4>

IN

FDI_TX_DN<5>

IN

FDI_TX_DN<6>

IN

FDI_TX_DN<7>

IN

FDI_TX_DP<0>

IN

FDI_TX_DP<1>

IN

FDI_TX_DP<2>

IN

FDI_TX_DP<3>

IN

FDI_TX_DP<4>

IN

FDI_TX_DP<5>

IN

FDI_TX_DP<6>

IN

FDI_TX_DP<7>

OUT

FDI_INT

OUT

FDI_FSYNC0

OUT

FDI_FSYNC1

OUT

FDI_LSYNC0

OUT

FDI_LSYNC1

2

IN

RSMRST#_R

IN

PCIE_WAKE#

BI

PCI_3S_CLKRUN#

OUT

SUS_STAT#

OUT

FM_32KHZ

OUT

SLP_S5#

OUT

SLP_S4#

OUT

SLP_S3#

OUT

SLP_A#

OUT

SLP_SUS#

BI

H_PM_SYNC

OUT

SLP_LAN#

21<

37>

11<

18<

STRAP PIN

+V_RTC

1

330K_5%_2

2

1

330K_5%_2_DY

2

CLOSE TO IC

1

43<

D

R4885

R4884

CC

BB

P3V3_A

R4732

1

8.2K_5%_2

8

7 6

2

ISOLATION

30<

55<>

19< 12<

30<37<

ACPRESENT

SUS_PWR_ACK

30<

PM_RI#

PCIE_WAKE#

30>37<

SLP_LAN#

IN
IN

IN

IN

OUT

PCI_3S_CLKRUN#

5 4

IN

R4776

R4735

R4736

R4775

R4824

R4733

2

10K_5%_2

1

2

10K_5%_2

1

2

10K_5%_2

1

2

10K_5%_2

1

10K_5%_2_DY

2

1

P3V3_S

1

8.2K_5%_2

2

CHANGE by

Frank Hu

3

Sun Jan 02 18:04:44 2011

DATE

2

INVENTEC

TITLE

EVEREST-M
PCH 3

SIZE

C

CODE

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

30

of

1

97

REV

A01

AA

8 7

6 5

4 3

2

1

1

P3V3_S

R4845

2

D

1

R4842

2

PCH_LVDS_DDCDATA - LVDS DETECT
HIGH-LVDS ENABLED

LOW-LVDS DISABLED (DEFAULT)

1

R4841

2.2K_5%_22.2K_5%_2

2

67<

67<

48<

PCH_LCM_BKLTEN

48<67<

PCH_LCM_VDDEN

48<

PCH_LCM_INVPWM

OUT
OUT

OUT

67<

PCH_LVDS_DDCCLK

PCH_LVDS_DDCDATA

R4882

2

1

2.37K_1%_2

67<

PCH_LVDS_TXCL_DN

67<

PCH_LVDS_TXCL_DP

67<

PCH_LVDS_TXDL0_DN

67<

PCH_LVDS_TXDL1_DN

67<

PCH_LVDS_TXDL2_DN

67<

PCH_LVDS_TXDL0_DP

67<

PCH_LVDS_TXDL1_DP

67<

PCH_LVDS_TXDL2_DP

1

R4843

0_5%_2

1

R4844
100K_5%_2100K_5%_2

2

PCH_LCM_INVPWM_R

2

OUT
OUT

OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

J47
M45

P45

T40
K47

T45
P39

AF37
AF36

AE48
AE47

AK39
AK40

AN48
AM47
AK47
AJ48

AN47
AM49
AK49
AJ47

AF40
AF39

AH45
AH47
AF49
AF45

AH43
AH49
AF47
AF43

U4700

L_BKLTEN
L_VDD_EN

L_BKLTCTL

L_DDC_CLK

L_DDC_DATA

L_CTRL_CLK

L_CTRL_DATA

LVD_IBG
LVD_VBG

LVD_VREFH
LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

LVDS

Digital Display Interface

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_INTN
SDVO_INTP

SDVO_CTRLCLK
SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_CTRLCLK
DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

PCH_DUAL_DDCDATA - DP DETECTED
HIGH-DP ENABLED

LOW-DP DISABLED (DEFAULT)

PCH_DUAL_DDCCLK

BI
BI

PCH_DUAL_DDCDATA

PCH_DP_AUX_DN

BI
BI
IN

PCH_DP_HPD
PCH_DP_LANE0_DN

OUT

PCH_DP_LANE0_DP

OUT
OUT

PCH_DP_LANE1_DN

OUT

PCH_DP_LANE1_DP

OUT

PCH_DP_LANE2_DN

OUT

PCH_DP_LANE2_DP

OUT

PCH_DP_LANE3_DN

OUT

PCH_DP_LANE3_DP

PCH_DP_AUX_DP

47>

47<>
47<>

47<>

47<
47<
47<
47<
47<
47<
47<
47<

D

CC

47<>

BB

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

AA

45<

PCH_CRT_BLUE

45<

PCH_CRT_GREEN

45<

PCH_CRT_RED

OUT
OUT
OUT

R4791

1

150_1%_2

R4790

1

150_1%_2

R4789

1

150_1%_2

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

2

2

2

45<

PCH_CRT_DDCCLK

45<

PCH_CRT_DDCDATA

45<

PCH_CRT_HSYNC

45<

PCH_CRT_VSYNC

CLOSE TO PCH

R4729

1K_1%_2

OUT
OUT

OUT
OUT

1

2

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

ITL_PANTHERPOINT_FCBGA_989P

CRT

DDPD_CTRLCLK
DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

INVENTEC

TITLE

EVEREST-M
PCH 4 AXG

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Sat Jan 01 18:30:03 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

31

of

1

REV

97

A01

8 7

6 5

4 3

2

1

1
1
1

1
1

1

1

1

1
1
1

1

GPIO19

BBS_BIT0

1
0
1
0

2

8.2K_5%_2

2

8.2K_5%_2

2

8.2K_5%_2

2

8.2K_5%_2

2

10K_5%_2_DY

2

10K_5%_2_DY

2

10K_5%_2_DY

2

10K_5%_2_DY

2
2
2

10K_5%_2

2

10K_5%_2

GPIO51

BBS_BIT1

0

1
1

0

D

P3V3_S

R4711

R4725

R4724

R4723

R4722

R4721

R4720

R4719 10K_5%_2
R4718

R4717 10K_5%_2

R4818

R4780

P3V3_S

1

R4878
10K_5%_2

2

32<>

54>

BTMDL#

37<39<60<68<

BI

PLT_RST#

BUF_PLT_RST#

BI

BI

100K_5%_2

1

R4877

1K_5%_2_DY

2

R4727

8

BOOT BIOS

DESTINATION

RESERVED(NAND)

-

SPI (DEFAULT)

LPC

PCI_3S_INTA#

BI

PCI_3S_INTB#

BI

PCI_3S_INTC#

BI
BI

PCI_3S_INTD#

RUNSCI0#

IN

PCI_3S_INTG#

BI
BI

PCI_3S_INTH#

IN

DGPU_HOLD_RST#

IN

EC_DGPU_PWR_EN#

IN

DGPU_SELECT#

IN

SATA_ODD_DA#

IN

DGPU_PWR_EN#

R4728

1K_5%_2_DY

STP_A16OVR

TOP-BLOCK SWAP OVERRIDE

C4772

1

2

0.1UF_16V_2

U4701

4

1

TC7SZ08FU

2

32<>
32<>
32<>

32<>

37>

33>

32<>
32<>

32<>

BBS STRAP

BBS_BIT1

1

2

P3V3_A

5

+

1

2

-

3

7 6

37>32>

67<

37>

67<32>

50>

37<32>

STP_A16OVR

1

R4716

1K_5%_2_DY

2

LOW=A16 SWAP OVERRIDE
HIGH=DEFAULT

37<>
43<

CLK_PCI_TPM

29<

CLKIN_PCI_FB

55<

CLK_PCI_DEBUG

DGPU_PWM_SELECT#

CLK_PCI_EC

Routed with 90 ohms impedance
Total length no longer than 11 inches

P3V3_A

OUT
OUT
OUT

OUT

WS

32<
67<

37< 32<

OUT

32<

32<>
32<>
32<>
32<>

37>
32<

32<>
32<>

TP4702

USB3_P1_RX_DN
USB3_P3_RX_DN
USB3_P1_RX_DP
USB3_P3_RX_DP
USB3_P1_TX_DN
USB3_P3_TX_DN
USB3_P1_TX_DP
USB3_P3_TX_DP

PCI_3S_INTA#
PCI_3S_INTB#
PCI_3S_INTC#
PCI_3S_INTD#

DGPU_HOLD_RST#

DGPU_SELECT#
DGPU_PWR_EN#

1

R4821

54>

32<>

50>

BTMDL#
SATA_ODD_DA#
PCI_3S_INTG#
PCI_3S_INTH#

R4714

1

10K_5%_2_DY

R4881
R4879
R4880

1

R4715

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI

OUT
OUT
OUT

2

DGPU_PWM_SELECT#_R

0_5%_2

BI
BI
BI
BI

2

1
1

1

1

2
2
2

2

22_5%_2
22_5%_2
22_5%_2

22_5%_2

+V3A_PME#

CLK_PCI_EC_R
CLK_PCI_TPM_R
CLK_PCI_FB_R

CLK_PCI_DEBUG_R

U4700

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3RN1

BC30

USB3RN2

BE32

USB3RN3

BJ32

USB3RN4

BC28

USB3RP1

BE30

USB3RP2

BF32

USB3RP3

BG32

USB3RP4

AV26

USB3TN1

BB26

USB3TN2

AU28

USB3TN3

AY30

USB3TN4

AU26

USB3TP1

AY26

USB3TP2

AV28

USB3TP3

AW30

USB3TP4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1#/GPIO50

C44

REQ2#/GPIO52

E40

REQ3#/GPIO54

D47

GNT1#/GPIO51

E42

GNT2#/GPIO53

F46

GNT3#/GPIO55

G42

PIRQE#/GPIO2

G40

PIRQF#/GPIO3

C42

PIRQG#/GPIO4

D44

PIRQH#/GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4 OC7#/GPIO14

ITL_PANTHERPOINT_FCBGA_989P

SMC_WAKE_SCI#

RSVD

PCI

OUT

5 4

NVRAM

DEBUG PORT

DEBUG PORT

USB

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43

OC5#/GPIO9

OC6#/GPIO10

RSVD1
RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD23

RSVD24

RSVD25

RSVD26
RSVD27

RSVD28
RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

P3V3_A

1

R4832
10K_5%_2

2

AY7
AV7
AU3
BG4

AT10
BC8

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AV5

AV10
AT8
AY5

BA2
AT12

BF3

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

C33

B33

A14
K20
B17
C16
L16
A16
D14
C14

D

WS

USB_P0_DN

BI

USB_P0_DP

BI

USB_P1_DN

BI

USB_P1_DP

BI

USB_P2_DN

BI

USB_P2_DP

BI

USB_P5_DN

BI
BI

USB_P5_DP

TP4714

1

TP4715

1

1

22.6_1%_3

R4726

2

BI
BI

BI
BI
BI
BI

USB_P10_DN
USB_P10_DP

USB_P12_DN
USB_P12_DP
USB_P13_DN
USB_P13_DP

CLOSE TO PCH

1

R4839

1

R4840
R4838

1

R4837

1

R4836

1

R4835

1

R4834

1
1

R4833

RESERVE FOR USB3.0
eSATA
RESERVE FOR USB3.0

WLAN

WEBCAM

BT
3G

2

10K_5%_2_DY

2

10K_5%_2_DY

2

IN
IN
IN
IN
IN
IN
IN
IN

0_5%_2

2

0_5%_2

10K_5%_2

2

10K_5%_2

2

10K_5%_2

2

10K_5%_2

2

10K_5%_2

2
2

0_5%_2

PCH_XDPFN0
PCH_XDPFN1

PCH_XDPFN2
PCH_XDPFN3

PCH_XDPFN4
PCH_XDPFN5
PCH_XDPFN6

PCH_XDPFN7

IN
IN
IN

IN

TITLE

P3V3_A

R4817

1

R4896

1

USB_OC#_0
USB_OC#_1
USB_OC#_2

SMC_WAKE_SCI#

WS

RESERVE FOR USB3.0

FOR eSATA

RESERVE FOR USB3.0

P3V3_A

INVENTEC

EVEREST-M

CC

BB

AA

PCH 5 USB

CODE

SIZE

C

CHANGE by

Frank Hu

3

Sun Jan 02 17:15:21 2011

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

32

of

1

REV

97

A01

8 7

6 5

4 3

2

1

P3V3_A

STRAP PIN

HOST_ALERT#1 - TLS CONFIDENTIALITY

LOW - (DEFAULT) INTEL ME CRYPTO TRANSPORT LAYER SECURITY(TLS) CIPHER SUITE WITH NO CONFIDENTIALITY

1

2

R4831

STRAP PIN
INTEGRATED CLOCKING

D

1K_5%_2

OUT

P3V3_A

1

R4779

HOST_ALERT#1

10K_5%_2_DY

R4820

1

2

1K_5%_2

2

OUT

ICC_EN#

LOW - (DEFAULT) ENABLE INTEGRATED CLK
HIGH - DISABLE INTEGRATED CLK

P3V3_S

1

R4870

R4864

R4862

R4830

R4826

R4825

R4861

R4865

R4873

R4827

P3V3_S

FDI_OVRVLTG

2

10K_5%_2

2

1

10K_5%_2

1

2

10K_5%_2_DY

1

2

200K_1%_2

1

2

10K_5%_2_DY

1

2

10K_5%_2

1

10K_5%_2

2

1

2

10K_5%_2_DY

1

2

10K_5%_2_DY

1

2

100K_5%_2

STRAP PIN

R4828

1

1

R4829

LOW- TX,RXTERMINATED TO SAME VOLTAGE

1

R4781

2

BIOS_REC

OUT
OUT

MFG_MODE

IN

TEST_DET

OUT

SATA_ODD_PRSNT#

OUT

GFX_CRB_DET

OUT

CRIT_TEMP_REP#

IN
IN
IN

OUT

1K_5%_2_DY

2

2

10K_5%_2

(DC COUPLING MODE) DEFAULT

10K_5%_2_DY

33> 33<

33> 33<

33> 33<

33>

TEST_DET

MFG_MODE

BIOS_REC

GFX_CRB_DET

OUT

FDI_OVRVLTG

IN

PCH_XDPFN8

33>

33>

33>

STRAP

PCH_XDPFN8 - ON DIE PLL VOLTAGE REGULATOR

HIGH-ENABLED (DEFAULT)
LOW-DISABLED

8

7 6

HIGH - INTEL ME CRYPTO TLS CIPHER SUITE WITH CONFIDENTIALITY

33>
59<

37>

P3V3_S

32<

39<>

33>

33>

59<

LAN_PHY_PWR

HOST_ALERT#1

RUNSCI0#

ICC_EN#

OUT
OUT
OUT
OUT

P3V3_A

50>

33>

67<

16>

33>

37>

1:DEFAULT/0:ENABLE

DGPU_PWROK

33>

BIOS_REC

33<

BI
OUT

P3V3_S

33<

33>

33<

33>

33>

50> 33>

PCH_XDPFN8

SATA_ODD_PRSNT#

33>

FDI_OVRVLTG

33>33<

33>

GFX_CRB_DET

33>37>

CRIT_TEMP_REP#

33<

MFG_MODE

TEST_DET

OUT

OUT
OUT
OUT
OUT

OUT
OUT

P3V3_S

R4876

R4872

R4871

R4819

R4875

R4874

R4869

R4784

R4811

R4868

R4867

R4866

R4863

1

2

10K_5%_2

1

2

10K_5%_2

1

2

10K_5%_2

1

2

0_5%_2

1

2

0_5%_2

1

2

10K_5%_2

1

2

10K_5%_2

1

2

10K_5%_2

1

2

10K_5%_2

1

2

10K_5%_2

2

1

0_5%_2

0_5%_2

1

2

0_5%_2

1

2

PCH_XDPFN17

DGPU_HPD_INTR#_R

ICC_EN#_R

PCH_XDPFN16

PCH_XDPFN14

PCH_XDPFN9

PCH_XDPFN12

PCH_XDPFN13

PCH_XDPFN15

U4700

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49/TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

ITL_PANTHERPOINT_FCBGA_989P

5 4

GPIO

D

A20GATE

PECI

RCIN#

DF_TVS

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

C40
B41
C41
A40

P4
AU16
P5
AY11
AY10
T14

AY1
AH8
AK11
AH10
AK10
P37

WS

BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49

R4860

PCH_PECI

R4853

THRMTRIP#_R

FOLLOW EDS1.0

1

1

2

1.5K_1%_1/16W

2

0_5%_2_DY

P1V05_VCCPS

R4712

1

390_5%_2

BOTH THESE SHOULD BE
CLOSE TO PCH

OUT

SATA_ODD_PWREN

IN

EC_3S_A20GATE

OUT

IN

OUT

1

R4713
56_5%_2_DY

2

2

OUT

20>

H_PECI

37>

KBRST#

H_CPUPWRGD

IN

20>

NV_CLE

50<

37<

37<>

60> 20<

PM_THRMTRIP#

WS

20>

CC

38<

BB

AA

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

PROCPWRGD

THRMTRIP#

INIT3_3V#

CPU/MISC

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

NCTF

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

INVENTEC

TITLE

EVEREST-M

PCH 6 MISC

CODE

SIZE

C

CHANGE by

Frank Hu

3

Sun Jan 02 17:58:29 2011

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

33

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

10uF_6.3V_3

+V1.05S

C4754

10uF_6.3V_3

+V1.05S

C4746

1

2

1

1uF_6.3V_2

2

C4753

1uF_6.3V_2

P1V05_VCCPS

1

C4755

2

C4711

1uF_6.3V_2

3A

1

1uF_6.3V_2 1uF_6.3V_2

2

1

C4752

2

+V1.05S

1

1uF_6.3V_2

2

C4749

0.1UF_16V_2

+V1.05S

+V1.05S

C4751

P3V3_S

C4710

1

2

1

2

0_5%_2_DY

1.3A

1

2

+V1.05S

R4810

1

0_5%_2_DY

C4750

1uF_6.3V_2

+VCCAFDI_VRM

R4809

2

1

20mil

+V1.05S_VCCAPLLEXP

2

1

2

15mil

15mil

+V1.05S_VccAFDIPLL

20mil

15mil

U4700

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

AN19

BJ22

AN16
AN17

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

VCCIO[28]

VCCAPLLEXP

VCCIO[15]

VCCIO[16]

POWER

CRT

VCC CORE

LVDS

HVCMOS

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3] VCCDFTERM[2]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

ITL_PANTHERPOINT_FCBGA_989P

VCCIO

FDI

DMI

NAND / SPI

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCDFTERM[1]

VCCDFTERM[3]

VCCDFTERM[4]

VCCSPI

U48

U47

AK36
AK37

AM37
AM38
AP36
AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

15mil

15mil

+VCCAFDI_VRM

15mil

15mil

C4775

1

1UF_6.3V_2_DY

15mil

15mil

P3V3_S

1

2

15mil

C4708

0.01UF_50V_2

2

1

C4744

1uF_6.3V_2

2

15mil

+V3M

1

2

0.1UF_16V_2

15mil

1

C4756

10uF_6.3V_3

2

C4707

0.01UF_50V_2

C4747

1

2

+V1.05S

1

C4745

0.1UF_16V_2

2

1

C4748

0.01UF_50V_2

2

1

C4706

22uF_6.3V_5

2

P1V8_S

C4732

1

1uF_6.3V_2

1

C4709

0.1UF_16V_2

2

1

FBM_11_160808_121T

1

FBM_11_160808_121T

L4700

2

P3V3_S

P1V05_VCCPS

2

L4701

P3V3_S

2

D

P1V8_S

CC

BB

AA

+VCCAFDI_VRM

R4808

1

0_5%_3

2

P1V5_S

INVENTEC

40mil

CHANGE by

8

7 6

5 4

3

Frank Hu

Sat Jan 01 18:30:57 2011

DATE

2

SIZE

C

TITLE

EVEREST-M
PCH 7 POWER

CODE

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

34

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

+V1.05S

FBM_11_160808_121T

FBM_11_160808_121T

C4705

0.1UF_16V_2

L4704

1

1

L4703

2

22UF_6.3V_5_DY

2

22UF_6.3V_5_DY

+V1.05_LAN_M

P1V05_VCCPS

C4743

4.7uF_6.3V_3

8

P3V3_S

1

2

C4713

C4712

R4805

1

2

C4704

10uF_6.3V_3

+V1.05M

+V1.05M

1
2

1
2

+V1.05S

1

0.1UF_16V_2

1

2

+V1.05S

1.1A

C4728

1uF_6.3V_2

C4726

1uF_6.3V_2

2

0_5%_2_DY

C4720

C4719

+V1.05S

P3V3_A

15mil

C4774

20mil

+V1.05S

20mil

C4771

22uF_6.3V_5

1

C4703

2

1UF_6.3V_2_DY

1

C4718

0.1UF_16V_2

1uF_6.3V_2

C4727

C4725

C4724

C4723

C4722
C4721

1

2

1uF_6.3V_2

1

2

10uF_6.3V_3

1

2

10uF_6.3V_3

2

1

0.1UF_16V_2

2

7 6

R4806

1

0_5%_2_DY

1

C4715

C4731

1

2

1

2

2

2

2
2

+V_RTC

C4741

R4807

1

0_5%_2_DY

2

0.1UF_10V_2_DY

2

+V1.05S_VCCACLK

2

0.1UF_16V_2

2

1

C4717

1

+V1.05S_VCCAPLLDMI2

1uF_6.3V_2_DY

2

1

C4714

22uF_6.3V_5

2

1

2

C4730

1uF_6.3V_2

C4729

0.1UF_16V_2

+VCCAFDI_VRM

VCCADPLLA

VCCADPLLB

1uF_6.3V_2

1

1

1uF_6.3V_2

1

1uF_6.3V_2

1

0.1UF_16V_2

+V1.05_LAN_M_DCPSUS<1>

1

2

1uF_6.3V_2

C4702

1
2

1

2

1

2

1

2

15mil

15mil

15mil

20mil

15mil

15mil

10mil

C4742

0.1UF_16V_2

+V1.05S

AD49

T16

V12

T38

BH23
AL29

AL24

AA19
AA21
AA24
AA26
AA27
AA29
AA31
AC26
AC27
AC29
AC31
AD29
AD31

W21
W23
W24
W26
W29
W31
W33

N16

Y49

BD47
BF47

AF17
AF33
AF34
AG34

AG33

V16

U4700

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3[5]

VCCAPLLDMI2

VCCIO[14]

DCPSUS[3]

VCCASW[1]

VCCASW[2]

VCCASW[3]

VCCASW[4]

VCCASW[5]

VCCASW[6]

VCCASW[7]

VCCASW[8]

VCCASW[9]

VCCASW[10]

VCCASW[11]

VCCASW[12]

VCCASW[13]

VCCASW[14]

VCCASW[15]

VCCASW[16]

VCCASW[17]

VCCASW[18]

VCCASW[19]

VCCASW[20]

DCPRTC

VCCVRM[4]

VCCADPLLA

VCCADPLLB

VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

VCCSSC

DCPSST

POWER

Clock and Miscellaneous

SATA

USB

PCI/GPIO/LPC

VCCIO[29]

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCAPLLSATA

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

V5REF

N26
P26
P28
T27
T29

T23
T24
V23
V24
P24

T26
M26

AN23
AN24

P34

N20
N22
P20
P22

AA16
W16
T34

AJ2
AF13

AH13
AH14

AF14
AK1

AF11

AC16
AC17
AD17

3A

10mil

C4740

1

0.1UF_16V_2

10mil

C4738

VSREF_SUS

C4770

10mil

V5REF

20mil

+V1.05S_VCCAPLLSATA

1

20mil

C4773

C4735

C4701

2

2

10mil

C4736

1

1uF_10V_2

20mil

20mil

1

1uF_6.3V_2

10mil

1

1

C4716

1uF_10V_2

2

2

0.1UF_16V_2

1uF_6.3V_2_DY

1

2

1

1

2

C4734

2

20mil

C4700

1

1uF_6.3V_2

P3V3_A

P3V3_A

10mil

10mil

2

0.1UF_16V_2

2

0.1UF_16V_2

0.1UF_16V_2

L4702

1

0603_DY

2

+V1.05S

P3V3_A

P3V3_S

2

P3V3_A

P3V3_S

+V1.05S

D4701

3

R4710

C4739

D4700

3

R4709

C4737

1
1

P3V3_S

+V1.05S

+VCCAFDI_VRM

+V1.05S

2

NC

BAT54_30V_0.2A

1

P3V3_A

D

P5V_A

1

1

2

10_5%_5

0.1UF_16V_2

2

2

NC

BAT54_30V_0.2A

1

P3V3_S

P5V_S

2

10_5%_5

1uF_10V_2

2

CC

BB

AA

T17

DCPSUS[1]

V19

DCPSUS[2]

MISC

BJ8

V_PROC_IO

CPU

A22

1

VCCRTC

ITL_PANTHERPOINT_FCBGA_989P

RTC

HDA

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

2

5 4

T21

V21

T19

P32

10mil

20mil

P3V3_A

1

C4733

2

0.1UF_16V_2

+V1.05M

3

CHANGE by

Frank Hu

Sat Jan 01 18:31:14 2011

DATE

2

INVENTEC

TITLE

EVEREST-M

PCH 8 POWER

SIZE

C

CODE

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

35

of

1

REV

97

A01

8 7

U4700

H5

VSS[0]

AA17

AA33
AA34
AB11
AB14
AB39

AB43

D

AC19
AC21

AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39

AD40
AD42
AD43
AD45
AD46

AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38

AF42
AF46

AG19
AG31

AG48
AH11

AH36
AH39
AH40
AH42
AH46

AJ19
AJ21
AJ24
AJ33
AJ34
AK12

AA2
AA3

AB4
AB5

AB7
AC2

AD4

AD8
AE2
AE3

AF4

AF5
AF7
AF8

AG2

AH3

AH7

AK3

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

ITL_PANTHERPOINT_FCBGA_989P

8

7 6

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

6 5

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

5 4

4 3

U4700

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

ITL_PANTHERPOINT_FCBGA_989P

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

2

1

D

CC

BB

AA

INVENTEC

TITLE

EVEREST-M
PCH 9 GND

CODE

SIZE

CS

CHANGE by

Frank Hu

3

Sun Jan 02 18:04:06 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

36

of

1

REV

97

A01

8 7

2

D302

10<

9>

+V5AUXON

3

BAT54_30V_0.2A

D

P3V3_AL

1

R352

2

WLON#

10<

29<>

EC_SMB3_CLK

29<>

EC_SMB3_DATA

1.8K_5%_2

BI
BI

55<

GPO76_SHBM - Enable shared BIOS Memory

low-Enabled

R377

1

10K_5%_2_DY

2

BI

ECSTRAP110

STRAP PIN

HIGH - (Default) NORMAL MODE
LOW - TEST MODE

P3V3_AL

EC_SMB1_DATA
EC_SMB1_CLK

H_PROCHOT#

1.Battery

R321

1
1

R319

EC_SMB1

Close EC

2

3.3K_5%_2

2

3.3K_5%_2

BI

BI

OUT

3

2

EC_SMB2

1.Charge

2.GPU Thermal

8

P5V_S

53<>

53<>

Q300

DS

1

G

SSM3K7002BFU

P3V3_AL

1

R316

100K_5%_2

2

NC

1

1

R353

2

1.8K_5%_2

PWR_SWIN#_3

OUT

1

R331

EC_PW_ON#

72<>

8>

72<>

IM_DAT_5
IM_CLK_5

EC_SMB2_DATA

8>

EC_SMB2_CLK

R322
R323

1

R356

100K_5%_2

2

EC_SMB3

1.CPU Thermal

OUTOUT

VCC_POR#

37<

8>

37<

8>

37<

9>

37>

H_PROCHOT#_EC

44<48<

SW_LCM_BKLTEN

R302

10K_5%_2

IN

1

2

11<

18<

17<

EC_PCH_PWROK

EC_LCM_INVPWM

8>
58<
57>

NUM_LED#_3

10K_5%_2_DY

2

OUT

100K_5%_2

R300

USB1_PWREN

1

37<>

ECSTRAP110

55>

54<>

2

SCROLL_LED#_3

37<>

30>

MAIN_PWRGD

BAT_BLED1#

58<

72<>

DCIN_BLED#

38>

FAN_PWMA

38>37<

FAN_TACH

30>

R303
R341

2

47K_5%_2
47K_5%_2

2

11<

1
1

BOARDID0
BOARDID1

SLP_S4#

2.2K_1%_2

2

2.2K_1%_2

2

BI
BI

37< 38>

IN
IN

12<

19<

FAN_TACH

P3V3_AL

1
1

BI

BI

IN

H_PROCHOT#_EC

7 6

6 5

+V3LA_EC

R339

1

HW_I_ADC
HW_V_ADC

BATT_IN

EC_BKLTEN

SLP_A#

30>

SLP_S3#

ACPRES#
PWR_BLED#
LID_SW#_3

BOARDID1

EC_MUTE#

BTIFON#

FM_32KHZ

OUT
OUT
OUT

IN
IN

58<

CAPS_LED#_3

EC_SPI_SO
EC_SPI_SI

EC_SPI_CS0#
SMC_WAKE_SCI#
EC_SPI_CLK

30>

SLP_LAN#

30>

SLP_SUS#

IN

Close EC

1

1

1
1

2

2

2

1.5K_1%_1/16W

2

R380

R362

R379
R361

R340

10K_5%_2

4.7K_5%_2

2

IN

IN
OUT
OUT
OUT

IN

IN

R355

IN

OUT

IN

OUT

IN

OUT

OUT

IN
BI
OUT
OUT

OUT

IN
IN

R314
R301

R375

53<

TP_ON#

WL_OLED#

28<
37>

28>
37<

IN
IN

1

C314

680pF_50V_2

2

1.5K_1%_2_DY
10K_5%_2

10K_5%_2_DY

P3V3_S

R374

R373
R371

R372

R370

2
2
1

R359

R358

P3V3_A

1

2

+V3LA_EC_VREF

0_5%_2

2

1

0_5%_2_DY

2

1

0_5%_2

2

1

2

1

0_5%_2

0_5%_2

2

1

2

1

0_5%_2

1

0_5%_2

1

0_5%_2

2

OUT
OUT

OUT

IN

OUT
OUT

OUT
OUT

2

1

2

1

1uF_6.3V_2

EC_SPI_CS0#

20mil

+V3LA_EC

19

887646

VCC3

VCC2

VCC1

NEED 0.1UF

AGND

103

115

VCC5

VCC4

GPO83_SOUT_CR_TRIST#

KBSOUT15_GPIO61_XOR_OUT

GND6

GND2

GND1

5

18

0_5%_2

0_5%_2
0_5%_2

C301

104

100
108

101
105
106
107

119
109
120

112
110

114

118

117

97
98
99

96

81
64

95
93
94

84
83
82

73

77
79
30

62
32

63
31

65
66

68
67
69
70

86
87

90
91
92

11
10
71
72

44

VREF

AD0_GPIO90
AD1_GPIO91
AD2_GPIO92
AD3_GPIO93
GPIO05
GPIO04
DA0_GPIO94
DA1_GPIO95
DA2_GPIO96
GPIO97

GPIO66_G_PWM

GPIO01
GPIO03
GPIO06
GPIO07
GPIO23_SCL3
GPIO30
GPIO31_SDA3

GPIO77
GPO76_SHBM
GPIO75

GPO84_XORTR#
GPO82_TEST#
GPIO70

6

GPIO24

GPIO16

GPIO00_EXTCLK
GPIO02
CLKOUT_GPIO55

C_PWM_GPIO13
B_PWM_GPIO21
A_PWM_GPIO15
TB1_GPIO14
TA1_GPIO56
TA2_GPIO20

GPIO32_D_PWM
GPIO33_H_PWM

GPIO74_SDA2
GPIO73_SCL2
GPIO22_SDA1
GPIO17_SCL1

F_SDIO1
F_SDIO0

F_CS0#
GPIO81
F_SCK

PSDAT2_GPIO27
PSCLK2_GPIO26
GPIO35_PSDAT1
GPIO37_PSCLK1

VCORF

1

2

P3V3_AL

GND_KBC_ALG

P3V3_AL

IN

EC_SPI_SO

OUT

5 4

R376

R336

P3V3_S

102

4

80

VDD

AVCC

GPIO41

GPIO10_LPCPD#

LRESET#

LFRAME#

GPIO11_CLKRUN#

KBRST#_GPIO86

GPIO85_GA20

ECSCI#_GPIO54

GPIO65_SMI#

GPIO67_PWUREQ#

SDA4_GPIO53

SCL4_GPIO47

GPIO87_SIN_CR

GPIO45_E_PWM
GPIO40_F_PWM

GPIO42_TCK
GPIO43_TMS
GPIO44_TDI

GPIO46_TRST#

PSCLK3_GPIO50_TDO

GPIO52_PSDAT3_RDY#

R333

VCC_POR#

KBSOUT0_JENK#

KBSOUT1_TCK
KBSOUT2_TMS
KBSOUT3_TDI

KBSOUT4_JEN0#

KBSOUT5_TDO

KBSOUT6_RDY#

KBSOUT7

KBSOUT8
KBSOUT9_SDP_VIS#
KBSOUT10_P80_CLK
KBSOUT11_P80_DAT

KBSOUT12_GPIO64
KBSOUT13_GPIO63
KBSOUT14_GPIO62

KBSOUT16_GPIO60
KBSOUT17_GPIO57

GND5

GND4

GND3

WINB_NPCE791LA0DX_LQFP_128P

897845

116

1

1

1

4 3

OUT

LOW_BAT#_3

U301

14

GPIO34

LCLK

LAD0
LAD1
LAD2
LAD3

SERIRQ

GPIO71
GPIO72

GPIO36
GPIO51

PECI

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

2

2

2

124
7
2
3
126
127
128
1
125
8
122
121
29
9
123
74
75
111
28
15
26
24
113

12

VTT

13
22

16
17

20
21
23
25
27
85

54
55
56
57
58
59
60
61
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33

10K_5%_2
0_5%_2

33_5%_2

R368
R367

PECI

2

R366
R365

R364
R363

R311
R310
R309
R308
R307
R306
R305
R304

1
2
3
4

R369

0_5%_2

2
2

1

2
2

2
2

1
1

1
1
1
1
1
1

U300

CS#
DO
WP#
GND

1

R378

43_1%_2

HOLD#

WINB_W25Q80BVSSIG_SOIC_8P

VCC

CLK

1
1

2
2

2
2
2
2
2
2

DI

OUT

OUT
OUT

0_5%_2
0_5%_2

2

1

1
1

1

30<

IN

ACPRESENT
SUS_STAT#

IN

PLT_RST#

BI

CLK_PCI_EC

BI

LPC_3S_FRAME#

BI

LPC_3S_AD<0>

BI

LPC_3S_AD<1>

BI

LPC_3S_AD<2>

BI

LPC_3S_AD<3>

BI

PCI_3S_SERIRQ

BI

PCI_3S_CLKRUN#

EC_DGPU_PWR_EN#

DGPU_HOLD_RST#

IN

CHG_EN

OUT

BOARDID0

IN
OUT
OUT
OUT

IN

BI

OUT

IN

0_5%_2

OUT

0_5%_2

OUT
OUT

0_5%_2

OUT

0_5%_2

OUT
OUT

IN

8
7
6
5

SCAN_IN<0>
SCAN_IN<1>
SCAN_IN<2>
SCAN_IN<3>
SCAN_IN<4>
SCAN_IN<5>
SCAN_IN<6>
SCAN_IN<7>

1

R330
R334

1

R335

1

220_5%_2
220_5%_2
220_5%_2

220_5%_2
220_5%_2
220_5%_2
220_5%_2
220_5%_2

1

R312

100K_5%_2

DGPU_PWR_EN#
EC_PWRSW#
FLASH_OVERRIDE

3G_ON#

PM_EXTTS#1

H_PECI

BAT_OLED#

SUS_OLED#

CRIT_TEMP_REP#
SLP_S5#

USB0_PWREN
DRAMRST_CNTRL_EC

RSMRST#

EC_EDP_MUX_IC_SEL

VCC_POR#

0
1
2
3
4
5
6

PAD300

1

7

2

SCAN_OUT<0>
SCAN_OUT<1>
SCAN_OUT<2>

SCAN_OUT<3>
SCAN_OUT<4>
SCAN_OUT<5>
SCAN_OUT<6>
SCAN_OUT<7>
SCAN_OUT<8>
SCAN_OUT<9>
SCAN_OUT<10>
SCAN_OUT<11>
SCAN_OUT<12>
SCAN_OUT<13>
SCAN_OUT<14>
SCAN_OUT<15>
SCAN_OUT<16>
SCAN_OUT<17>

1

30<

30>

32<>

32>

20>

2

2

39<
60< 68<

10K_5%_2

28<>
55<

28<>
28<>

28<>

30<>
30< 43<

26>

33>

58<
58<

52<

IN

0

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17

2

32<

POWERPAD1x1m

GND_KBC_ALG

P3V3_AL

3.3K_5%_2

2

33_5%_2

2

33_5%_2

2

CHANGE by

3

EC_SPI_CLK

IN
IN

EC_SPI_SI

Frank Hu

OUT

1

OUT

R313

10K_5%_2

P3V3_S

R354

43<

55<43<
55<43<

43<
55<

P3V3_S P3V3_A

2

R345

10K_5%_2

1

WS

P1V05_VCCPS

SCAN_IN<7..0>

SCAN_OUT<17..0>

OUT

37<

8>

HW_I_ADC

37<

8>

HW_V_ADC

BATT_IN

0.1UF_16V_2

Tue Jan 04 11:09:01 2011

DATE

2

EC_LCM_INVPWM

37>

RSMRST#

2

R360

10K_5%_2

1

30<

2

1

P3V3_AL

C308
C305
C311
C300

C304
C303

P3V3_S

WS

C313
C306

0.1UF_16V_2

CLOSE TO EC

C317

IN

C316

IN

C315

OUT

2

R357

10K_5%_2_DY

1

37>28>

1

37>28>

C307

2

INVENTEC

TITLE

SIZE

C

2

1

P3V3_A

2

R329

10K_5%_2_DY

1

KBRST#

OUTOUT

IN

EC_3S_A20GATE

OUT

RUNSCI0#

OUT

EC_SMI

CLOSE IC PIN

1
1

1
1
1

1

4.7uF_6.3V_3

2
2

0.1UF_16V_2

0.1UF_16V_2

2
2

0.1UF_16V_2

2

0.1UF_16V_2

0.1UF_16V_2

2

CLOSE IC PIN

2

1

1

0.1UF_16V_2

2

4.7uF_6.3V_3

+V3LA_EC

FBM_11_160808_121T

1

1

2

C312

4.7uF_6.3V_3

2

C310

CLOSE IC PIN

GND_KBC_ALG

1
1

SCAN_OUT<0>

OUT

0.1UF_16V_2

2

0.1UF_16V_2

0.1UF_16V_2

2

1

2

STRAP PIN

0: JTAG select

1: (Default)

EVEREST-M
EC

CODE

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

37

of

1

1

33<

28<

L300

P3V3_AL

2

97

53>37>

REV

A01

D

CC

BB

AA

8 7

6 5

4 3

2

1

D

P3V3_S

R4304

4.7K_5%_2

2

1

37<

FAN_TACH

OUT

P5V_S

30mil

CN4300

1

1

2

2

3

3

4

4

D

C4303

2
1

G1

G

G2

G

0.1UF_16V_2

2

C4304

4.7UF_10V_3

1

1

C4302

1000PF_50V_2_DY

R4305

4.7K_5%_2

2

P3V3_S

2

ACES_50273_0047N_001_4P

CC

1

P5V_AL

1

150_5%_2

0.1UF_16V_2

R4303

C4301

10mil

+THM_VDD

2

1

2

U4411

5

VCC SET

HYST

GMT_G708T1U_SOT23_5P

GND

1
2

34

OT

R4302

37>

FAN_PWMA

32.4K_1%_2

2

1

OUT

THRM_SHUTDWN#

OUT

PM_THRMTRIP#

14>18<

VR_PWRGD

R4301

IN

1

330_5%_2

IN

1

R4300
2M_5%_2

2

Q4301

2

1

B

LMBT3904LT1G

C E

2 3

SSM3K7002BFU

1

C4300
CSC0402_DY

Q4300

1

3

DS

G

2

OUT

THRM_SHUTDWN#

BB

2

GM Thermal shutdown at 80.8℃ +/-3℃ from 60℃ to 100℃
PM Thermal shutdown at 86℃ +/-3℃ from 60℃ to 100℃
RSET=0.0012*T2-0.9308*T+96.147
Hysteresis is 30C

8

7 6

5 4

AA

INVENTEC

TITLE

EVEREST-M
FAN & THERMAL

CODE

SIZE

C

CHANGE by

Frank Hu

3

Fri Dec 31 10:16:37 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

38

of

1

REV

97

A01

8 7

30MIL

6 5

4 3

2

1

D

+V3M_LAN

C411

33PF_50V_2

+V3M

C416

0.1UF_16V_2

R417

2

10K_5%_2_DY

R416

2

10K_5%_2_DY

1
2

1

2

1

1

2

1
2

X400

25MHZ

C414

0.1UF_16V_2

1

33PF_50V_2

C412

R412

1

0_5%_2

R415

1

0_5%_5

1
2

2

C415

22UF_6.3V_5

0805

LAN_JTAG_TMS

BI

LAN_JTAG_TCK

BI

33>

2

+V3M_LAN

1

2

LAN_PHY_PWR

OUT

OUT

C413

1
2

0.1UF_16V_2

39<>

39<>

BI

LAN_X1

LAN_X2

68<

60< 37<

29>
29>

29<
29<

29>
29>

29<

39<

39<

29<

CLKREQ_LAN#

32<>

PLT_RST#

CLK_PCIE_LAN_DP
CLK_PCIE_LAN_DN

PCIE_LAN_RX_DP
PCIE_LAN_RX_DN

PCIE_LAN_TX_DP
PCIE_LAN_TX_DN

29>

SML0_CLK

29>29<

SML0_DATA

R405

2

1

0_5%_2

OUT

IN
IN

IN

OUT
OUT

IN
IN

BI
BI

+V3M_LAN

1

R407
10K_5%_2

2

1

R406
0_5%_2_DY

2

R410

R418

C404

C403

R408
R409

40<

LED_R3S_LANLINK#

39<>
39<>

2

1

0_5%_2
0_5%_2

2

1

0.1UF_16V_2

2

1

2

0.1UF_16V_2

1

2

1

0_5%_2

2

1

0_5%_2

LED_R3S_LANACT#

LAN_JTAG_TMS
LAN_JTAG_TCK

39>

LAN_X1

39>

LAN_X2

CLKREQ_LAN#_R

PLT_RST#_R

PCIE_LAN_RX_C_DP

PCIE_LAN_RX_C_DN

SMB_CLK_LAN
SMB_DATA_LAN

BI
BI

BI
BI

IN
IN

R404

1K_5%_2

P3V3_A

1

R411
10K_5%_2

2

LAN_ENABLE

1

TP402

1

TP401

1

1

3.01K_1%_2

2

R403

TP400

D

U400

48
36

44
45

38
39

41
42

28
31

26
27
25

32
34
33
35

10

30

12

1

2

CLK_REQ_N
PE_RST_N

PE_CLKP
PE_CLKN

PETp
PETn

PERp
PERn

SMB_CLK
SMB_DATA

3

LAN_DISABLE_N

LED0
LED1
LED2

JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TCK

9

XTAL_OUT
XTAL_IN

TEST_EN

RBIAS

PCIE

SMBUS

LED

JTAG

MDI

MDI_PLUS0

MDI_MINUS0

MDI_PLUS1

MDI_MINUS1

MDI_PLUS2

MDI_MINUS2

MDI_PLUS3

MDI_MINUS3

RSVD_NC

RSVD_VCC3P3_1
RSVD_VCC3P3_2

VDD3P3_IN

VDD3P3_OUT

VDD3P3_15
VDD3P3_19
VDD3P3_29

VDD1P0_47
VDD1P0_46
VDD1P0_37

VDD1P0_43

VDD1P0_11

VDD1P0_40
VDD1P0_22
VDD1P0_16

VDD1P0_8

CTRL_1P0

VSS_EPAD

ITL_LEWISVILLE_PQFN_48P

13
14

17
18

20
21

23
24

+V3M_LAN_RSVD_NC

6

+V3M_LAN_RSVD_VCC3P3_1

1

2

+V3M_LAN_RSVD_VCC3P3_2

5
4

15
19

29

47
46
37

15MIL

43

11

40
22

16

8

+V1.05_LAN_CTRL_1P0

15MIL

15MIL

7
49

4.7UH

22UF_6.3V_5

R413

1

0_5%_2

+V1.05_LAN

L400

2

1

0603_DY

C401

40<
40<

40<
40<

40<
40<

40<
40<

CC

+V3M_LAN

R414

R401
R400

BI
BI

BI
BI

BI
BI

BI
BI

1

1
1

LAN_TRD0_DP
LAN_TRD0_DN

LAN_TRD1_DP
LAN_TRD1_DN

LAN_TRD2_DP
LAN_TRD2_DN

LAN_TRD3_DP
LAN_TRD3_DN

2

0_5%_2_DY

2

4.7K_5%_2

2

4.7K_5%_2

15MIL

2

1
2

+V1.05_LAN

1

2

C400

1UF_10V_2

C402

1
2

0.1UF_16V_2

1

R402

0_5%_5

BB

+V1.05_LAN_M

2

15MIL

AA

INVENTEC

TITLE

EVEREST-M

LAN

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:38 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

39

of

1

REV

97

A01

8 7

LED_R3S_LANACT#

+V3M_LAN

6 5

R477

IN

1

RSC_0603_DY

2

4 3

2

1

D

R478

1

RSC_0603_DY

R476

1

RSC_0603_DY

R475

1

RSC_0603_DY

2

2

IN

LED_R3S_LANLINK#

LAN_TRD3_CN_DP
LAN_TRD3_CN_DN
LAN_TRD2_CN_DP
LAN_TRD1_CN_DP
LAN_TRD1_CN_DN
LAN_TRD2_CN_DN

LAN_TRD0_CN_DP
LAN_TRD0_CN_DN

IN
IN
IN
IN
IN
IN
IN
IN

SYN_100073HR008G13CZL_8P

2

+V3M_LAN

WS

1
2
3
4
5
6
7
8

JACK470

TX+
TX­RX+
P4
P5
RX­P7
P8

G1

G

G2

G

G3

G

G4

G

D

CC

1

R472

0_5%_2_DY

2

WS

LAN_TRD3_DN
LAN_TRD3_DP

LAN_TRD2_DN
LAN_TRD2_DP

LAN_TRD1_DN
LAN_TRD1_DP

LAN_TRD0_DN

LAN_TRD0_DP

+V3M_LAN_TRANSFORMER

IN
IN

IN
IN

IN
IN

IN
IN

U470

1
3
2
4
6
5
7
9
8

10
12
11

BOTH_GST5009_SOP_24P

TCT1
TD1­TD1+
TCT2
TD2­TD2+
TCT3
TD3­TD3+
TCT4
TD4­TD4+

MCT1
MX1­MX1+
MCT2
MX2­MX2+
MCT3
MX3­MX3+
MCT4
MX4­MX4+

24
22
23
21
19
20
18
16
17
15
13
14

LAN_TRD0_CN_DN

OUT
OUT

LAN_TRD0_CN_DP

OUT

LAN_TRD1_CN_DN

OUT

LAN_TRD1_CN_DP

OUT

LAN_TRD2_CN_DN

OUT

LAN_TRD2_CN_DP

OUT

LAN_TRD3_CN_DN

OUT

LAN_TRD3_CN_DP

40<
40<

40<
40<

40<
40<

40<
40<

BB

1

C409

2 2

0.1UF_16V_2

1

C408

0.1UF_16V_2

1

2

0.1UF_16V_2

C407

1

C406

2

0.1UF_16V_2 1UF_6.3V_2

1

2

C405

1

R473

75_5%_3 75_5%_3

2

1

R474

2

1

R470

75_5%_3

2

1

R471

75_5%_3

2

8152 OPEN

1

C410

1000PF_2000V_6

2

AA

INVENTEC

TITLE

EVEREST-M
RJ45 & TRANSFORMER

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Tue Jan 04 00:15:14 2011

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

40

of

1

REV

97

A01

8 7

D

R501 ONLY NEEDED FOR -11Z
AND IF SUPPLY TO VAUX_3.3
IS REMOVED DURING SYSTEM RE-START.
11/16 MODIFY FOR VENDOR COMMAND

RESERVE FOR EMI (10-22PF)

10K_5%_2_DY

10UF_6.3V_5

R501

R513

R500

R502

P3V3_A

C509

1

2

1

1

1

1

2

2

0_5%_2
33_5%_2

2

33_5%_2

2

CSC0402_DY

10 MIL

1

C507

10UF_6.3V_5

2

C506

1

2

1

C510

0.1UF_16V_2

2

1

2

CSC0402_DY

C508

0.1UF_16V_2

1

C532

2

HDA_3S_SDIN0_R

PCSPKR_PCH_3_R

1

C533

CSC0402_DY

2

P3V3_A

C511

1UF_6.3V_2

6 5

1

R511

5.11K_1%_2

1

R512

100_5%_2

2

40

39

SPDIF

DMIC_CLK

LPWR_5.0

LEFT+

111312

38

GPIO0-EAPD#

LEFT-

2

37

GPIO1-SPK_MUTE#

U500

RIGHT-

14

36

SENSE_A

RPWR_5.0

15

353433

PORTB_L

PORTB_R

CLASS-D_REF

RIGHT+

17

16

B_BIAS

DVDD_3.3

18

1

39.2K_1%_2

1

C504

1

0.1UF_16V_2

R508

R507

10K_1%_2

1
2
3
4
5
6
7
8
9

10

2

2

2

DMIC1-2
VAUX_3.3
FILT_1.8
SDATA_OUT
BIT_CLK
SDATA_IN
VDD_IO
SYNC
RESET#
PC_BEEP

10 MIL

1

C512

1

0.1UF_16V_2

2

2

1

C529

0.1UF_16V_2

2

2
1

31

32

C_BIAS

PORTC_R

FILT_1.65

AVDD_3.3

FLY_N

FLY_P

PORTC_L

AVDD_5V

AVDD_HP

PORTA_R
PORTA_L

AVEE

GND

30
29
28
27
26
25

NC

24

NC

23
22
21

41

CONEX_CX20671_21Z_QFN_40P

19

20

C522
1UF_6.3V_2

4 3

OUT

C_BIAS

42<

LDO_OUT_3.3V

10 MIL

C518

1

10UF_6.3V_5

2

1

2

C530

10UF_6.3V_5

1

C531

0.1UF_16V_2

2

1

2

1

C516

1UF_6.3V_2

2

1

C515

0.1UF_16V_2

2

C519

0.1UF_16V_2

NEAR CODEC

1

C517

0.1UF_16V_2

2

10 MIL

1

C514

0.1UF_16V_2

2

P3V3_S

1

C513

10UF_6.3V_5

2

2

PORT CONFIGURATION

PORT A: HEADPHONE JACK
PORT B: INTERNAL MIC
PORT C: MICROPHONE JACK

1

D

CC

BB

0OHM_5% 1206 PAD

C520

1

2

1A

10UF_6.3V_5

1

C521

0.1UF_16V_2

2

AA

C534

CSC0402_DY

1

2

CSC0402_DY

C535

1

2

CSC0402_DY

C536

1

2

CSC0402_DY

C537

R509

1

2

0_5%_6

0_5%_2

0_5%_2

0_5%_2

0_5%_2

1

2

R506

R505

1

2

R504

1

2

R503

1

2

SPK_OUT_L+_R

SPK_OUT_L-_R

SPK_OUT_R-_R

SPK_OUT_R+_R

+V5S_LPWR_5.0

C526

1

0.1UF_16V_2

2

C527

1

0.1UF_16V_2

2

C528

1

10UF_6.3V_5

2

1

2

C525

10UF_6.3V_3

PLACE BYPASS CAPS CLOSE TO DEVICE.

1

2

RESERVE FOR EMI, CLOSE TO CODEC

120 OHMS@100MHZ

INVENTEC

TITLE

EVEREST-M
AUDIO CODEC

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Sun Jan 02 13:16:19 2011

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

41

of

1

REV

97

A01

8 7

6 5

AUDIO JACKS

41>

C_BIAS

4 3

2

1

PORT C
EXTENAL MICROPHONE

IN

D

1

C609

2

1

2

1
2

R600

3.3K_5%_2

D601

VARISTOR_DY

Recommended for protection

R605

R604

1

1

D602

VARISTOR_DY

2

2

100_5%_2

2

1

100_5%_2

2

1

C603

C602

2.2UF_6.3V_2

2

1

2.2UF_6.3V_2

2

1

JACK600

SINGA_2SJ_T351_019_6P

5
4
3
6
2

1
G1
G2

C608

CSC0402_DY

3.3K_5%_2

1

CSC0402_DY

2

R601

D

CC

INTERNAL SPEAKERS

1

2

1

C607 C605

CSC0402_DY

C606

CSC0402_DY CSC0402_DY

2

Reserve for EMI, place close to connector

CN600

1

1

2

2

3

3

4

4

1

2

1

ACES_50224_0040N_001_4P

C604

CSC0402_DY

2

G1

G1

PHP_PESD5V2S2UT_SOT23_3P

D600

2

G2

G2

3

1

PORT A
HEADPHONE

BB

JACK601

G2
G1

R603

5.1_5%_2

1

2

R602

2

1

5.1_5%_2

1

1

D604

VARISTOR_DY

1

D603

VARISTOR_DY

2

2

2

C600

CSC0402_DY

1
2

C601

CSC0402_DY

1
2
6
3
4
5

SINGA_2SJ_T351_019_6P

AA

INVENTEC

TITLE

EVEREST-M
AUDIO AMP

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Sun Jan 02 13:17:10 2011

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

42

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

15mil

LPCPD# SHOULD BE CONNECT TO VDD

P3V3_S

P3V3_S

55<
55<
55<
55<

55<

56< 55<

37<>
37<>
37<> 28<>

37<>

20<

37<>

37<>

28<>
28<>

28<>37<>

32>

28>

32<>

55<
28<>

30<>

PCI_3S_CLKRUN#

30<

LPC_3S_AD<0>
LPC_3S_AD<1>
LPC_3S_AD<2>
LPC_3S_AD<3>

CLK_PCI_TPM

LPC_3S_FRAME#

BUF_PLT_RST#

PCI_3S_SERIRQ

U3500

26

IN
IN
IN
IN

IN
IN

R3502

0_5%_2

2

IN

IN
IN

R3501

1

4.7K_5%_2

1

2

LAD0

23

LAD1

20

LAD2

17

LAD3

21

LCLK

22

LFRAME#

16

LRESET#

28

LPCPD#

27

SERIRQ

15

CLKRUN#

9

TESTBI_BADD

8

TESTI

INFINEON_SLB9635TT1.2_FW3.16_TSSOP_28P

XTALI_32K_IN

VSB

VDD
VDD

GND
GND
GND
GND

XTALO

GPIO

GPIO2

5

1

10

NC

19
24

4
11
18
25

7

PP

1

NC

3

NC

12

NC

13
14
6
2

P3V3_A

1

2

R3500

0_5%_2_DY

TPM_XTALI
TPM_XTALO

0.1UF_16V_2

2

C3502

R3500
NC FOR SUPPORT VPRO

STUFF FOR FW1.2

C3504

0.1UF_16V_2

4

32

1

P3V3_S

1

C3503

0.1UF_16V_2

2

X3500

32.768KHZ

1

C3505

0.1UF_16V_2

2

1

R3503

10M_5%_2

2

15mil

1

2

C3501

1

10PF_50V_2

C3500

1

10PF_50V_2

D

CC

2

2

TPM1.2

FW VERSION

1.02

3.16

P/N

6019B0101801

6019B0761601

(SUPPORT VPRO)

BB

AA

INVENTEC

TITLE

EVEREST-M
TPM

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:39 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

43

of

1

REV

97

A01

PCH_LCM_VDDEN

SSM3K7002BFU

IN

Q3002

1

47K_5%_2

SSM3K7002BFU

3

DS

G

2

1

R3010

Q3001

P3V3_S

8 7

R?

1

0_5%_2_DY

2

IN
IN

120_5%_2_DY

R?

R?

1

R?

1
1R?2

12R?

R?

1

R?

1

R?

1

R?12

120_5%_2

R?

R?

1

1

P3V3_S

1

2

-

3 5

2

2
2

0_5%_2_DY

2

2

2

2

C3001

U3000

+

TC7SZ08FU

0_5%_2_DY
0_5%_2_DY

0_5%_2_DY

0_5%_2_DY

0_5%_2_DY

0_5%_2
0_5%_2

0_5%_2

+VBAT_LVDS

IN

IN

1

C3005

0.1UF_16V_2

2

1

4 2

100_5%_2

100K_5%_2

R3005

R3004

CN?

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

1

1

P3V3_S

R3000

R3002

2

2

2.2K_5%_2

2.2K_5%_2

25

26 G2

26

27

27

28

28

29

29

30

30

ACES_50252_03001_002_30P

G1

G

G

D

C3007

0.1UF_16V_2

SW_LVDS_DDCDATA
SW_LVDS_TXDL1_DN
SW_LVDS_TXDL1_DP

SW_LVDS_TXCL_DN
SW_LVDS_TXCL_DP

GPU_LVDS2_TXDL1_DN
GPU_LVDS2_TXDL1_DP
GPU_LVDS2_TXCL_DN
GPU_LVDS2_TXCL_DP

P3V3_S

20mil

1

32<>

44<

32<>

44<

2

USB_P10_DN
USB_P10_DP

67>
67>

67>
67>

IN

BI
IN
IN

IN
IN

IN
IN

IN
IN

+VBAT_LVDS

IN
IN

1
2

C3000

0.1UF_16V_2

1

1

C3002

CSC0402_DY

2

2

P3V3_S

8

7 6

PCH_LVDS_TXDL0_DN

PCH_LVDS_TXDL1_DN
PCH_LVDS_TXDL0_DP
PCH_LVDS_TXDL1_DP
PCH_LVDS_TXDL2_DN

PCH_LVDS_TXCL_DN

PCH_LVDS_TXDL2_DP

PCH_LVDS_TXCL_DP

EDP_TX1_DN

EDP_TX0_DN
EDP_TX1_DP

IN
IN
IN
IN
IN
IN
IN
IN

IN
IN
IN
IN

P3V3_S

1

2

R3009

1

3

470K_5%_2

DS

G

2

2

2

0.01UF_50V_2

1

C3008

680pF_50V_2

2

C3006

1

Place as close as possible to connector

Q3000

3 6

G

4

S

AM3423P

PMOS_4D1S

D

100_5%_2

30mil

5
2
1

1

R3006

0.1UF_16V_2

C3003

1

2

2

1

2

C3004

10uF_6.3V_3

+V3S_PCH_LCM_VDDEN

PVBAT

KC_FBM_11_160808_101A20T_2P

for LED panel

40mil

1

0.1uF_25V_3

2

C3009

IN

1000PF_50V_2

1

2

L3001

1

PCH_LCM_INVPWM

30mil

2

C3010

4.7uF_25V_5

PCH_LVDS_DDCCLK

PCH_LVDS_DDCDATA

EC_EDP_MUX_IC_SEL

37>48<

EC_BKLTEN

6 5

CN3000

G1

G1

1

2

1

2

4

3

3

4

6 5

5

6

8 7

7

8

9

10

9

10

12 11

11

12

1314

14

13

16 15

15

16

18 17

17

18

20

19

19

20

22

21

21

22

24 23

23

24

26

25

25

26

28 27

27

28

30

29

29

30

31

32

31

32

34 33

33

34

36 35

36

35

38

37

37

38

40

39

39

40

42

41

41

42

4344

44

43

46 45

45

46

G2

G2

ACES_88242_4600_46P

BI
IN
IN

IN
IN

IN
IN

IN
IN

IN

R3001

1

2

IN

33_5%_2

U3001

1

VIO

VIO

2

VBUSGND

3

VIO

NXP_IP4223CZ6_SOT457_6P_DY

VIO

SW_LVDS_DDCCLK
SW_LVDS_TXDL0_DN
SW_LVDS_TXDL0_DP

SW_LVDS_TXDL2_DN
SW_LVDS_TXDL2_DP

GPU_LVDS2_TXDL0_DN
GPU_LVDS2_TXDL0_DP

GPU_LVDS2_TXDL2_DN
GPU_LVDS2_TXDL2_DP

R3003

MIC_IN_CLK

MIC_IN_DATA

2

100_5%_2

1

44<41>

IN

SW_LCM_INVPWM

P5V_S

USB_P10_DN

6
5

USB_P10_DP

4

5 4

4 3

P3V3_S

1

R3008

10K_5%_2_DY

2
1

R3007

CPT PANEL

10K_5%_2

2

32<>

IN

32<>

IN

LOW:DISABLE
HI:ENABLE

41>44<

44<

IN

41>44<

IN

44<

MIC_IN_DATA

MIC_IN_CLK

3

CHANGE by

1

D3000

VARISTOR_DY

2

Frank Hu

2

1

2

Tue Jan 04 11:07:56 2011

DATE

2

D3001

VARISTOR_DY

INVENTEC

TITLE

SIZE

C

EVEREST-M
LCM CONN

CODE

CS
SHEET

1

DOC.NUMBER

CS_1310AXXXXXX-MTR

44

of

1

D

CC

BB

AA

REV

A01

97

8 7

6 5

4 3

2

1

1

C3050

22PF_50V_2

2

1

1

1

R3052

0_5%_2

R3053

0_5%_2

R3054

0_5%_2

2

2

2

1

2

C3062

10PF_50V_2

1

2

C3061

10PF_50V_2

1

2

C3060

10PF_50V_2

OUT

OUT

OUT

CRT_R_CN

CRT_G_CN

CRT_B_CN

45<

45<

D

45<

CC

31>

PCH_CRT_RED

31>

PCH_CRT_GREEN

31>

D

PCH_CRT_BLUE

31>

PCH_CRT_VSYNC

31>

PCH_CRT_HSYNC

31>

PCH_CRT_DDCDATA

31>

PCH_CRT_DDCCLK

71>

71>

71>

71>

GPU_CRT_VSYNC

71>

GPU_CRT_HSYNC

71>

GPU_CRT_DDCDATA

71>

GPU_CRT_DDCCLK

GPU_CRT_R

GPU_CRT_G

GPU_CRT_B

IN
IN
IN

IN
IN

IN
IN

R3077

R3076

R3075

R3074

R3073

R3072

R3071

IN
IN

IN
IN
IN
IN

IN

R3070

R3069

R3068

R3067

R3066

R3065

R3064

0_5%_2

2

1

0_5%_2

2

1

0_5%_2

2

1

0_5%_2

2

1

0_5%_2

2

1

0_5%_2

2

1

0_5%_2

2

1

0_5%_2_DY

2

1

0_5%_2_DY

2

1

0_5%_2_DY

2

1

OUT
OUT
OUT

OUT
OUT

OUT
OUT

45<

CRT_R

45<

CRT_G

45<

CRT_B

CRT_VSYNC

CRT_HSYNC

CRT_DDCDATA

CRT_DDCCLK

45<
45<

45<

45<

45>

45>

45>

CRT_R

CRT_G

CRT_B

IN

IN

IN

1

R3061

150_1%_2

2

1

R3060

150_1%_2

2

1

R3059

150_1%_2

2

1

C3065

10PF_50V_2

2

1

C3064

10PF_50V_2

2

1

2

FOLLOW INTEL DESIGN GUIDE

0_5%_2_DY

2

1

0_5%_2_DY

2

1

0_5%_2_DY

1

2

0_5%_2_DY

2

1

1

LOW18ANR12G00BD

1

LOW18ANR12G00BD

1

LOW18ANR12G00BD

C3063

10PF_50V_2

L3052

L3051

L3050

2

2

2

1

2

C3052

22PF_50V_2

CRT_R_L

CRT_G_L

CRT_B_L

1

2

C3051

22PF_50V_2

0.22UF_6.3V_2

P3V3_S

P5V_S

C3055

1
2

C3054

1
2

0.22UF_6.3V_2

P5V_S

45<

C3053

1
2

0.22UF_6.3V_2

45>
45<

45>
45>
45<

CRT_R_CN
CRT_G_CN
CRT_B_CN

CO-LAYOUT

U3050

1

VCC-SYNC SYNC_OUT2

2

VCC-VIDEO

3

IN
IN
IN

VIDEO_1

4

VIDEO_2

5

VIDEO_3

6

GND

7

VCC-DCC
BYP

TI_TPD7S019_15DBQR_SSOP_16P

SYNC_IN2

SYNC_OUT1

SYNC_IN1
DCC_OUT2

DDC_IN2
DDC_IN1

DDC_OUT1

16

CRT_VSYNC_R

15
14

CRT_HSYNC_R

13
12
11
10
98

P3V3_S

1

1

R3063

2.2K_5%_2 2.2K_5%_2

R3062

2

2

R3051

R3050

P5V_S

2

BB

D3050

33_5%_2

2

1

33_5%_2

2

1

IN

OUT

IN
IN

OUT

CRT_HSYNC
CRT_DDCDATA_R
CRT_DDCDATA
CRT_DDCCLK
CRT_DDCCLK_R

45>

45>

CRT_VSYNC_CN

OUT

CRT_VSYNC

IN

OUT

CRT_HSYNC_CN
45>

45<>

45>

45>

45<>

CRT_DDCDATA_R

CRT_DDCCLK_R

45>

45<

45<

BI

BI

P5V_S

1

R3058

2.2K_5%_2 2.2K_5%_2

2

1

R3057

2

1

33_5%_2

1

33_5%_2

R3056

R3055

+V5S_CRTCONNPWR_D

2

2

1

1

C3057

12PF_50V_2_DY

2

2

SBR3U40P1

1

(40 MILS)

1

45>

CRT_HSYNC_CN

45>

CRT_VSYNC_CN

C3056

12PF_50V_2_DY

45<
45>

45>45<

FUSE3050

2

1A_32V_0467001

+V5S_CRTCONNPWR_FUSE

0.1UF_10V_2_DY 0.1UF_10V_2_DY

45>45<

IN
IN

1

C3059

2

CRT_R_CN
CRT_G_CN
CRT_B_CN

CRT_DDCDATA_CN

CRT_DDCCLK_CN

1

C3058

2

CN3050

1

IN
IN
IN

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12
13
14
15

SYN_070546FR015S251ZR_15P

G1

12

G2

13
14
15

G1
G2

AA

INVENTEC

TITLE

EVEREST-M
CRT CONN

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:17:01 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

45

of

1

REV

97

A01

8 7

6 5

4 3

2

1

R3173

R3172

C3153

C3152

C3155

C3154

C3157

C3156

C3159

C3158

1

R3175

4.7K_5%_2

2

R3171

R3170

R3169

R3168

R3167

R3166

1

1

1

1

1

1

1

1

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

P3V3_GPUS

1

R3165

D

71>

71>

71>

71>

71>

71>

71>

71>

71<>

71<>

1M_5%_2

GPU_HDMI_TX2_DP

GPU_HDMI_TX2_DN

GPU_HDMI_TX1_DP

GPU_HDMI_TX1_DN

GPU_HDMI_TX0_DP

GPU_HDMI_TX0_DN

GPU_HDMI_TXC_DP

GPU_HDMI_TXC_DN

2

GPU_HDMI_DDCCLK

GPU_HDMI_DDCDATA

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

1

G

DS

2

Q3152

SSM3K7002BFU

1

1

33_5%_2

3

R3160

33_5%_2

R3164

2

2

499_1%_2

2

1

499_1%_2

2

1

499_1%_2

2

1

499_1%_2

2

1

499_1%_2

2

1

499_1%_2

2

1

499_1%_2

2

1

499_1%_2

1

2

SEM_0544M_MSOP_10P_DY

5

LINE4

4

LINE3

3

GND

2

LINE2

1

LINE1

D3154

VCC

6

NC

7

NC

8
9

NC

10

NC

D

CLOSE TO CONNECTOR

R3157

1

0_5%_2

R3156

1

0_5%_2

R3155

1

0_5%_2

R3154

1

0_5%_2

R3153

1

0_5%_2

R3152

1

0_5%_2

R3151

1

0_5%_2

R3150

1

0_5%_2

+V5S_HDMI

46<>
46<>

D3153

1

SBR3U40P1

GPU_HDMI_HPDET

46<>

46<>

GPU_HDMI_TX2_R_DP

2

GPU_HDMI_TX2_R_DN

2

GPU_HDMI_TX1_R_DP

2

GPU_HDMI_TX1_R_DN

2

2

GPU_HDMI_TX0_R_DP

GPU_HDMI_TX0_R_DN

2

GPU_HDMI_TXC_R_DP

2

2

GPU_HDMI_TXC_R_DN

HDMI_CN_DDCCLK

HDMI_CN_DDCDATA

OUT

1

R3163

100K_5%_2

2

BI
BI

1

R3158

1K_5%_2

2

1

D3152

2

VARISTOR_DY

FUSE3150

1

1A_32V_0467001

TP3150

2

+V5LA_HDMI_CONNPWR

1

D3151

2

VARISTOR_DY

VARISTOR_DY

CC

CN3150

1

TMDS-DATA2+

2

TMDS-DATA2-SHIELD

3

TMDS-DATA2-

4

TMDS-DATA1+

5

TMDS-DATA1-SHIELD

6

TMDS-DATA1-

7

TMDS-DATA0+

8

TMDS-DATA0-SHIELD

9

TMDS-DATA0-

10

TMDS-CLOCK+

11

TMDS-CLOCK-SHIELD

12

TMDS-CLOCK-

TP35

1

1

D3150

2

13
14
15
16
17
18
19

1

C3151

22PF_50V_2_DY

2

CEC
RESERVED
DDC-CLOCK
DDC-DATA
DDC-CEC-GND
+5V-POWER
HOT-PLUG-DETECT

SYN_100042MR019M153ZL_19P

G1

G1

G2

G2

G3

G3

G4

G4

BB

AA

INVENTEC

TITLE

EVEREST-M

1

R3174

4.7K_5%_2

2

S

G

G

Q3150

SSM3K17FU

P3V3_GPUS

S

D

DS

GPU_HDMI_TX2_C_DP

GPU_HDMI_TX2_C_DN

GPU_HDMI_TX1_C_DP

GPU_HDMI_TX1_C_DN

GPU_HDMI_TX0_C_DP

GPU_HDMI_TX0_C_DN

GPU_HDMI_TXC_C_DP

GPU_HDMI_TXC_C_DN

10

9
8
7
6

SEM_0544M_MSOP_10P_DY

0_5%_2_DY

4.7K_5%_2

G

G

D

DS

Q3151

SSM3K17FU

NC

LINE1

NC

LINE2
VCC
NC

LINE3
NC

LINE4

+V5S_HDMI

R3162

R3161

D3155

GND

P5V_S

1
2
3
4
5

2

40MIL

C3150

1

2

71<

100PF_50V_2

CLOSE TO CONNECTOR

2

1

2
1

2

D3156

SBR3U40P1

1
1

R3159

4.7K_5%_2

2

HDMI_CN_DDCCLK

BI

BI

HDMI_CN_DDCDATA

HDMI CONN

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:40 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

46

of

1

REV

97

A01

8 7

6 5

4 3

2

1

PCH_DP_LANE0_C_DP
PCH_DP_LANE0_C_DN
PCH_DP_LANE1_C_DP

PCH_DP_LANE1_C_DN

PCH_DP_LANE2_C_DP

PCH_DP_LANE2_C_DN
PCH_DP_LANE3_C_DP

PCH_DP_LANE3_C_DN

P3V3_S

40mil

DDC_AUX_EN#

DDCCLK_AUXP_CN

DDCDATA_AUXN_CN

D3300

2

SBR3U40P1

1

FUSE3300

+V3S_DPCONNPWR_D

OUT

BI
BI

PCH_DP_HPD_CN

1

2

1A_32V_0467001

OUT

+V3S_DPCONNPWR_FUSE

1

R3307

100K_5%_2

2

1

R3300
1M_5%_2

2

1

R3308

5.1M_5%_2

2

1

R3309

0_5%_2

2

CN3300

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17
18
19

20

MLX_105020_6001_20P

G1

17

G2

18

G3

19

G4

20

G1
G2
G3
G4

D

CC

1

1

1

1

1

1

1

1

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

PCH_DP_LANE0_DP
PCH_DP_LANE0_DN

PCH_DP_LANE1_DP
PCH_DP_LANE1_DN

PCH_DP_LANE2_DP

D

PCH_DP_LANE2_DN

PCH_DP_LANE3_DP

PCH_DP_LANE3_DN

IN

IN
IN
IN

IN
IN
IN

IN

C3309

C3308
C3307
C3306

C3305
C3304

C3303

C3302

P5V_S

31<

PCH_DP_HPD

SSM3K17FU

OUT

S

Q3300

G

G

DS

D

IN

PCH_DP_HPD_CN

PIN 14 :DDC buffer ID

distinguish from HDMI &DVI Adapter

PCH_DP_AUX_DP

PCH_DP_AUX_DN

PCH_DUAL_DDCCLK

PCH_DUAL_DDCDATA

PCH_DP_AUX_C_DP

BI

BI

C3301

C3300

0.1UF_16V_2

1

2

PCH_DP_AUX_C_DN

0.1UF_16V_2

2

1

SSM3K17FU

P3V3_S

1

R3301

2.2K_5%_2

SSM3K17FU

2

SSM3K17FU

D

D

Q3301

Q3310

S

DS

G

G

DS

G

G

Q3309

S

PCH_DP_AUX_M_DP

PCH_DP_AUX_M_DN

S

PCH_DUAL_DDCCLK_M

D

D S

G

G

SSM3K17FU

SSM3K17FU

P3V3_S

1

R3304

2.2K_5%_2

BI

2

SSM3K17FU

S

Q3308

PCH_DUAL_DDCDATA_M

D

D S

G

G

S

Q3306

S

Q3305

D

Q3304

D

Q3307

G

G

DS

G

G

DS

G

G

G

D

D S

D

D S

G

S

SSM3K17FU

S

SSM3K17FU

1

R3303

100K_5%_2

2

P3V3_S

BIBI

1

R3302

100K_5%_2

2

BI

DDCCLK_AUXP_CN

DDCDATA_AUXN_CN

47<>

47<>

1

R3306

10K_5%_2

2

P5V_S

2

1

R3305

10K_5%_2

BB

AA

PCH Dual-mode

8

7 6

5 4

Q3303

3

DS

1

G

SSM3K7002BFU

2

3

3

DS

2

CHANGE by

Q3302

1

G

SSM3K7002BFU

Frank Hu

IN

DDC_AUX_EN#

Fri Dec 31 10:16:41 2010

DATE

2

47>

INVENTEC

TITLE

EVEREST-M

DP CONN

SIZE

C

CODE

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

47

of

1

REV

97

A01

8 7

P3V3_S

6 5

4 3

2

1

1

P3V3_S

Q3350

3 6

G

4

S

AM3423P

PMOS_4D1S

D

+V3S_eDPCONNPWR

5
2

1

D

1

C3357

2

10uF_6.3V_3

1
2

40mil

C3352

0.1UF_16V_2

1

D

R3354

47K_5%_2

2

R3353

2

C3359

1

2

680pF_50V_2

PCH_LCM_VDDEN

SSM3K7002BFU

IN

Q3352

1

470K_5%_2

2

1

G

D S

3

C3358

2

0.01UF_50V_2

1

R3350

2

100_5%_2

21<>

EDP_AUX_DP

21<>

EDP_AUX_DN

SSM3K7002BFU

Q3351

C3361

BI

BI

1

0.1UF_16V_2
C3360

1

0.1UF_16V_2

1

2

2

G

P3V3_S

2

1

2

3

DS

2

1

R3360

100K_5%_2_DY

R3359

100K_5%_2_DY

PCH_LCM_BKLTEN

37>44<

EC_BKLTEN

1

R3358

2

100K_5%_2_DY

IN

IN

1

R3357

2

100K_5%_2_DY

IN
IN

EDP_AUX_C_DP

EDP_AUX_C_DN

P3V3_S

1

2

1

2

5

U3350

+

-

TC7SZ08FU

3

PVBAT

48>

48>

C3350

0.1UF_16V_2

21>

EDP_TX0_DN

21>

EDP_TX0_DP

R3352

4

1

100_5%_2

KC_FBM_11_160808_101A20T_2P

2

1

L3350

1

R3351

100K_5%_2

2

2

OUT
OUT

4.7uF_25V_5

C3354

2

1

C3351

EDP_HPD#_CN

1

C3356

CSC0402_DY

2

40mil

C3355

0.1UF_16V_2

2

1

0.1UF_16V_2

+VBAT_eDP

1

1

C3353

0.1uF_25V_3

2

2

OUT

EDP_TX0_C_DN
EDP_TX0_C_DP

EDP_HPD#_CN

CN3350

G1

G1

1

3

9
11
13
15
17
19

21
23

G2

ACES_87216_2406_24P

2

1

3

4

5

6
87

10

9

12

11

14

13

16

15

18

17

20

19

22

21

24

23

G2

IN

2
4
65
87

10
12
14
16

18
20
22
24

2

1

R3356

100K_5%_2

OUT
OUT

IN

P1V05_VCCPS

Q3353

1

SSM3K7002BFU

EDP_AUX_C_DP
EDP_AUX_C_DN

PCH_LCM_INVPWM

1

R3355

1K_5%_2

2

OUT

EDP_HPD#

3

DS

G

2

48<
48<

CC

BB

21<

AA

INVENTEC

TITLE

EVEREST-M
EDP CONN

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Tue Jan 04 11:08:43 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

48

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

D

CARDREADER/USB CONNECTOR

P3V3_S

CC

BB

USB1_PWREN

32<>

USB_P1_DP

32<>

USB_P1_DN

32<>

USB_P2_DP

32<>

USB_P2_DN

32<>

USB_P8_DP

32<>

USB_P8_DN

32<

USB_OC#_1

58<

LED_3IN1

IN
IN
IN

IN
IN

IN
IN

IN

OUT

30mil

P5V_A

1.5A

ACES_50503_0184N_001_18P

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

CN255

G2

G2

G1

G1

AA

INVENTEC

TITLE

EVEREST-M

DB CONN USB & CARDREADER

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:17:02 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

49

of

1

REV

97

A01

8 7

6 5

4 3

2

1

P3V3_S

1

CLOSE TO SATA CONN

C1704

C1702

1

1

0.01UF_50V_2

2

0.01UF_50V_2

2

D1702

VARISTOR_DY

1

1

D1703

VARISTOR_DY

2

2

D1701

VARISTOR_DY

1

2

1
2

1

2

C1706

22UF_6.3V_5

D1700
VARISTOR_DY

P5V_S

28>

SATA_HDD_TX_DP

28>

D

SATA_HDD_TX_DN

28<

SATA_HDD_RX_DN

28<

SATA_HDD_RX_DP

IN
IN

OUT
OUT

C1705

C1703

1

1

0.01UF_50V_2

2

0.01UF_50V_2

2

R1700
RSC_0603_DY

2

SATA_HDD_TX_C_DP
SATA_HDD_TX_C_DN

SATA_HDD_RX_C_DN
SATA_HDD_RX_C_DP

+V3S_SATAHDDCONN

40MILS

C1701

1
2

22UF_6.3V_5 0.1UF_16V_2

C1700

1

2

CN1700

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V3.3

9

V3.3

10

V3.3

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

RESERVED

19

GND

20

V12

21

V12

22

V12

SYN_127043HR022M22SZR_22P

G1
G2

D

G1
G2

28<

SATA_ODD_RX_DP

28<

SATA_ODD_RX_DN

28>

SATA_ODD_TX_DN

28>

SATA_ODD_TX_DP

SATA_ODD_PWREN

OUT
OUT

IN
IN

8

P3V3_S

1

R1753

10K_5%_2

2

IN

1

SSM3K7002BFU

CLOSE TO SATA CONN

C1755

0.01UF_50V_2

2

1

C1756

0.01UF_50V_2

2

1

P5V_S

Q1751

G

C1757

DS

C1754

1

R1751
1M_5%_2

2

3

2

1

1

R1752

1

1M_5%_2

32<

0.01UF_50V_2

2

0.01UF_50V_2

2

1

2

C1753

1

2

1000PF_50V_2

2

G

PMOS_4D1S

6 5 2

32<>

SATA_ODD_DA#

33>

SATA_ODD_PRSNT#

D1751

VARISTOR_DY VARISTOR_DY VARISTOR_DY VARISTOR_DY

1

D1753

2

7 6

43

S

AM3423P

Q1750

D

1

+V5S_SATAODDCONN_MOS

OUT

OUT

1

D1750

2

C1750

1
2

10UF_6.3V_3

1

C1751

1
2

1UF_6.3V_2 1UF_6.3V_2

R1750

2

0_5%_2

SATA_ODD_RX_C_DP
SATA_ODD_RX_C_DN

SATA_ODD_TX_C_DN
SATA_ODD_TX_C_DP

1

D1752

2

1.1A

C1752

1
2

SATA_ODD_R_DA#

CN1750

P6

GND

P5

GND

P4

MD

P3

+5V

P2

+5V

P1

DP

S7

GND

S6

B+

S5

B-

S4

GND

S3

A-

S2

A+

S1

GND

SYN_127382FR013G503ZR_13P

G1

G1

G2

G2

SATA ODD

5 4

SATA HDD

28>

SATA_SSD_TX_DP

28>

SATA_SSD_TX_DN

28<

SATA_SSD_RX_DN

28<

SATA_SSD_RX_DP

IN
IN

OUT
OUT

C1903

C1905

1

1

3

C1904

C1906

1

1

0.01UF_50V_2

2

0.01UF_50V_2

2

0.01UF_50V_2

2

0.01UF_50V_2

2

P5V_S

C1900

1
2

22UF_6.3V_5 0.1UF_16V_2

CHANGE by

1

2

Frank Hu

SATA_SSD_TX_C_DP
SATA_SSD_TX_C_DN

SATA_SSD_RX_C_DN
SATA_SSD_RX_C_DP

+V3S_SATASSDCONN

C1901

22UF_6.3V_5

DATE

P3V3_S

1

R1900

RSC_0603_DY

2

C1902

1
2

SATA SSD

SIZE

Sun Jan 02 18:54:06 2011

2

C

CN1900

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

ACES_88501_1601_16P

G1

G

G2

G

INVENTEC

TITLE

EVEREST-M

SATA HDD/SSD & ODD CONN

CODE

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

50

of

1

97

REV

A01

CC

BB

AA

8 7

6 5

E-SATA

4 3

2

1

D

28>

SATA_ESATA_TX_DN

28>

SATA_ESATA_TX_DP

IN

IN

C1811

2

0.01UF_50V_2
C1810

2

0.01UF_50V_2

1

1

SATA_ESATA_TX_C_DN

SATA_ESATA_TX_C_DP

SATA_ESATA_RX_C_DN

SATA_ESATA_RX_C_DP

P3V3_S

CLOSE TO IC PINS

P3V3_S

C1809

1

2

1UF_6.3V_2 1UF_6.3V_2

1
2

C1808

C1807

1

2

0.1UF_16V_2

C1806

1
2

0.1UF_16V_2

REDRIVER_ESATA_TX_DP

REDRIVER_ESATA_TX_DN

OUT

OUT

20
19
18
17
16 10

TML
VCC
GND
GND
GND
VCC

1

2

RX_0N

RX_0P

U1800

TX_0P

TX_0N

15

142111

5

4

3

GND

TX_1P

TX_1N

VCC

EN
D1
D0

VCC

GND

RX_1N

RX_1P

TI_SN75LVCP412RTJR_QFN_20P

12

13

6
7
8
9

REDRIVER_ESATA_RX_DP

IN

REDRIVER_ESATA_RX_DN

IN

C1803

2

0.01UF_50V_2
C1802

2

0.01UF_50V_2

1

1

OUT

SATA_ESATA_RX_DN

SATA_ESATA_RX_DP

OUT

28<

28<

D

P3V3_S

1

R1804

4.7K_5%_2 4.7K_5%_2

2

1

R1803

2

1

R1802

4.7K_5%_2_DY

2

EN

0

D0

X

D1

X

FUNCTION

STANDBY

CC

R1800

RSC_0402_DY

51>

51>

1

2

1

R1801

4.7K_5%_2

2

1
1

1

0

1

0

0

0

1

DEFAULT

CH0->5DB

CH1->5DB

32<>
32<>

USB_P0_DN
USB_P0_DP

1

1

1

+USB_VCC0

40MIL

L1800

BI
BI

WCM_2012_900T

34
2

1

USB_P0_L_DN

USB_P0_L_DP

CN1800

1

VCC

GND

2 6

USB_N

TXP

3

USB_P

TXN

4

G1
G2
G3
G4

TWIN_EU103_117CRL_TW_11P

GND

G1
G2
G3
G4

GND

RXN

RXP

GND

5

REDRIVER_ESATA_TX_C_DP

REDRIVER_ESATA_TX_C_DN

7
8
9

REDRIVER_ESATA_RX_C_DN

10

REDRIVER_ESATA_RX_C_DP

11

1

D1801
VARISTOR_DY

2

1

D1803

VARISTOR_DY VARISTOR_DY VARISTOR_DY

2

1

D1802

2

1

2

D1800

C1805

C1804

C1801

C1800

2

2

2

2

0.01UF_50V_2

1

0.01UF_50V_2

1

0.01UF_50V_2

1

0.01UF_50V_2

1

IN

REDRIVER_ESATA_TX_DP
REDRIVER_ESATA_TX_DN

IN

OUT

REDRIVER_ESATA_RX_DN

OUT

REDRIVER_ESATA_RX_DP

51>

51>

51<

51<

CH0,1->5DB

BB

AA

INVENTEC

TITLE

EVEREST-M
E-SATA CONN

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:42 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

51

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

ESATA POWER

+USB_VCC0

U1801

1
2
3
4

GMT_G547G1P81U_MSOP_8P

GND

IN
IN

OUT
OUT
OUT
OC#EN

40MIL

8
7
6
5

C1813

1
2

22UF_6.3V_5 0.1UF_16V_2

1
2

CLOSE TO ESATA CONNECTOR

C1812

1

R1805

RSC_0402_DY

2

37>

USB0_PWREN

P5V_A

IN

PAD1800

1

1

2

POWERPAD1X1M

2

+V5A_ESATAPWR_IN

40MIL

C1815

1

2

0.01UF_50V_2

C1814

1
2

0.1UF_16V_2

D

CC

P3V3_AL

1

R1806

10K_5%_2

2

OUT

USB_OC#_1

BB

AA

INVENTEC

TITLE

EVEREST-M
USB CONN

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Sun Jan 02 18:04:58 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

52

of

1

REV

97

A01

8 7

6 5

4 3

2

1

P3V3_S

14" KEYBOARD

SCAN_OUT<17..0>

D

2

1

CAPS_LED#_3

SCROLL_LED#_3

NUM_LED#_3

OUT
OUT

OUT

R251
R252

R253

200_5%_2

2

1

200_5%_2
200_5%_2

2

1

D260

EZJZ0V120JA_DY EZJZ0V120JA_DY EZJZ0V120JA_DY

OUT

SCAN_OUT<16>

16

SCAN_OUT<17>

17

SCAN_OUT<4>

4
2

SCAN_OUT<2>

SCAN_OUT<13>

13
15

SCAN_OUT<15>

SCAN_OUT<1>

1
0

SCAN_OUT<0>

11

SCAN_OUT<11>
SCAN_OUT<9>

9
5

SCAN_OUT<5>

SCAN_OUT<6>

6

SCAN_OUT<10>

10

SCAN_OUT<14>

14
8

SCAN_OUT<8>

12

SCAN_OUT<12>

7

SCAN_OUT<7>

3

SCAN_OUT<3>

53< 37<
53< 37<

37<53<
53< 37<
53< 37<
53< 37<

53< 37<

37<53<

1

1

D259

2

2

R254

1

SCAN_IN<7>
SCAN_IN<2>

SCAN_IN<3>
SCAN_IN<4>
SCAN_IN<0>
SCAN_IN<5>

SCAN_IN<6>
SCAN_IN<1>

1

D258

2

0_5%_2

2

IN
IN

IN
IN
IN
IN

IN
IN

PTWO_AFF340_A2G1V_P _34P

34
33
32
31

30
29
28
27

26
25
24
23

22
21
20
19

18
17
16
15

14
13
12
11

10

34
33
32
31

G2

30

G1
29
28
27

26
25
24
23

22
21
20
19

18
17
16
15

14
13
12
11

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

G2
G1

CN251

53<

53<

53<

53<

53<

53<

53<

37<

37<

37<

37<

37<

37<

37<

53<

37<

SCAN_IN<2>

SCAN_IN<1>
SCAN_IN<0>

SCAN_IN<3>
SCAN_IN<5>

SCAN_IN<6>
SCAN_IN<4>

SCAN_IN<7>

IN

D262

D250

2

D

2

1

EZJZ0V120JA_DY

1

EZJZ0V120JA_DY

IN

IN

D251

D252

2

2

1

EZJZ0V120JA_DY

1

EZJZ0V120JA_DY

IN
IN

D253

D254

2

2

1

EZJZ0V120JA_DY

1

EZJZ0V120JA_DY

CC

IN

IN

D255

D256

2

2

BB

1

EZJZ0V120JA_DY

1

EZJZ0V120JA_DY

IN

CN200

G1

CN250

G1

G

1
2
3
4
5

G2

6

G

ACES_88502_060N_6P

25mil

1
2
3
4
5
6

P5V_S

14" TOUCH PAD

IN

TP_ON#

37>

1

2

C250

CSC0402_DY

1

2

BI
BI

C252

CSC0402_DY

IM_CLK_5
IM_DAT_5

37<>
37<>

G1

G2

G2

ENTERY_3703_Q02N_03R_2P

4
5
6

MISAKI_NTC017_DA1G_E160T_6P

PUT ON BOTTOM SIDE

2

SW200

A

1

1

2

1

2

OUT

PWR_SWIN#_3

D200
VARISTOR_DY

53>

37<

AA

1

B

2
3

DC

OUT

PWR_SWIN#_3

INVENTEC

TITLE

EVEREST-M

K/B & TP/B CONN

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:43 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

53

of

1

REV

97

A01

8 7

6 5

4 3

BLUETOOTH

2

1

D

P3V3_S

C2100

1
2

0.1UF_16V_2

20MIL

ACES_87213_0600N_6P

6

6

5

5

4

4

3

3

2

2

1

1

CN2100

G2

G

G1

G

ALWAYS STUFF

32<>
32<>

55> 37>

USB_P12_DP
USB_P12_DN

BTIFON#

32<>

BTMDL#

BI
BI
BI

OUT

P3V3_S

1

R2105

100K_5%_2

2

C2104

1
2

22UF_6.3V_5

D

CC

BB

USB_P
USB_N
BTMDL

VCC

DISABLE

1
3
5
7

9

2

4

6

8

10

GND
CH_CLK

RST#

CH_DATA#

GND

AA

INVENTEC

TITLE

EVEREST-M

BLUETOOTH CONN

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:17:02 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

54

of

1

REV

97

A01

8 7

6 5

4 3

2

1

WXMIT_OFF#

Wireless & Debug card

D

OUT

3

Q1300

DS

1

G

2

SSM3K7002BFU

IN

WLON#

37>

D

P1V5_S

25mil

1

C1302

2

22uF_6.3V_5 0.1UF_16V_2

1

C1306

2

1

C1305

2

0.1UF_16V_2

1

C1304

2

0.1UF_16V_2

1

C1303

2

0.1UF_16V_2

1

C1301

2

22uF_6.3V_5

SUPPORT IAMT NEED +V3A

P3V3_S

54<>

37>

BTIFON#

OUT

SSM3K7002FU_DY

R1301

1

0_5%_2

Q1301

1

30<

PCIE_WAKE#

BI

R1300

0_5%_2

2

1

2

29>

29>

CL_DATA

29>

CL_RST#

OUT

CL_CLK

IN
IN

IN
IN

OUT
OUT

IN
IN

OUT
OUT
OUT

IN

CLKREQ_WLAN#

CLK_PCIE_WLAN_DN

CLK_PCIE_WLAN_DP

20<

3

DS

G

43<55<

2

32<>

BUF_PLT_RST#

56<

CLK_PCI_DEBUG

PCIE_WLAN_RX_DN
PCIE_WLAN_RX_DP

PCIE_WLAN_TX_DN

PCIE_WLAN_TX_DP

PCI_3S_SERIRQ

CN1300

1

WAKE#

3

RESERVED

5

RESERVED

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

RESERVED

19

RESERVED

21

GND

23

PERN0

25

PERP0

27

GND

29

GND

31

PETN0

33

PETP0

35

GND

37

RESERVED

39

RESERVED

41

RESERVED

43

RESERVED

45

RESERVED

47

RESERVED

49

RESERVED

51

RESERVED

RESERVED
RESERVED
RESERVED
RESERVED
RESERVED

RESERVED

+3.3VAUX

SMB_CLK

SMB_DATA

LED_WWAN#
LED_WLAN#
LED_WPAN#

G1

BELLW_80051_1021_52P

3.3V

1.5V

PERST#

1.5V

USB_D­USB_D+

1.5V

3.3V

GND

GND

GND

GND

GND

GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

G2

GG

R1303
R1302

1

1

LPC_3S_FRAME#

IN
IN

LPC_3S_AD<3>

IN

LPC_3S_AD<2>

IN

LPC_3S_AD<1>

IN

LPC_3S_AD<0>

IN

WXMIT_OFF#

IN

BUF_PLT_RST#

0_5%_2

2

2

0_5%_2

BI

USB_P5_DN

BI

USB_P5_DP

OUT

WIMAX_LED#

BI
BI

2.7A

28>

37<>

43<
43<

37<>28<>

43<

37<>28<>

20<

43<

43<
43<

28<> 37<>
28<> 37<>

55>

32<>
56<

PCH_3A_SMCLK

PCH_3A_SMDATA

32<>
32<>

55<

29<>

CC

29<>

BB

MINI CARD 1

8

7 6

5 4

Note:

3.3V

1.5V

Peak(max)mA Normal(max)mA

2,750mA

500mA

CHANGE by

3

Frank Hu

1,100mA
375mA

DATE

Fri Dec 31 10:16:43 2010

2

INVENTEC

TITLE

EVEREST-M

MINI1 WLAN/DEBUG CARD

SIZE

C

CODE

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

55

of

1

AA

REV

97

A01

8 7

6 5

4 3

2

1

3G/GPS

Q1401

D

P3V3_S

1A

1

C1400

0.1UF_16V_2

2

CN1401

1

WAKE#

3

RESERVED

5

RESERVED

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

RESERVED

19

RESERVED

21

GND

23

PERN0

25

PERP0

27

GND

29

GND

31

PETN0

33

PETP0

35

GND

37

RESERVED

39

RESERVED

41

RESERVED

43

RESERVED

45

RESERVED

47

RESERVED

49

RESERVED

51

RESERVED

G1

BELLW_80051_1021_52P

1

C1401

0.1UF_16V_2

2

3.3V
GND

1.5V
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED

GND

RESERVED

PERST#

+3.3VAUX

GND

1.5V

SMB_CLK

SMB_DATA

GND
USB_D­USB_D+

GND

LED_WWAN#
LED_WLAN#
LED_WPAN#

1.5V
GND

3.3V

1

C1402

2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

G2

GG

P1V5_S

25mil

2

1

C1407

22uF_6.3V_522uF_6.3V_5

1

C1406

0.1UF_16V_2

2

UIM_PWR

BI
BI

UIM_DATA

BI

UIM_CLK

BI

UIM_RST

IN

3G_OFF#

IN

BUF_PLT_RST#

BI

USB_P13_DN

BI

USB_P13_DP

56<>

56<>

56>

56<>
56<>

32<>
32<>

1

C1405

0.1UF_16V_2

2

32<>

43< 55<20<

56<>

UIM_DATA

37>

3G_ON#

IN

SSM3K7002BFU

CLOSE TO SIM CONNECTOR

U1402

1

VIO

GND

3

VIO VIO

NXP_IP4223CZ6_SOT457_6P_DY

P5
P6

BI

P7
G2

TAI_PMPAT5_06GLBS7N14_6P

CN1400

GND
VPP
I_O

G

VCC
RST
CLK

1

VBUS

G

3

DS

G

2

6

VIO

52
4

P1
P2
P3

G1

OUT

3G_OFF#

1

2

56<

C1403

4.7uF_6.3V_3

P3V3_S

BI

BI

BI

1

2

UIM_PWR
UIM_RST
UIM_CLK

C1404

0.1UF_16V_2

56<>

56<>

56<>

D

CC

BB

MINI CARD 2

8

7 6

5 4

AA

INVENTEC

TITLE

EVEREST-M

MINI2 3G

CODE

SIZE

C

CHANGE by

Frank Hu

3

Fri Dec 31 10:17:03 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

56

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

HALL SENSOR

P3V3_AL

D

CC

15mil

U50

1

GND

VDD

OUT

2

3

MAG_MH248BESO_SOT23_3P

1

R52

100K_5%_2

2

1

C50

1000PF_50V_2

2

1

L50

VARISTOR_DY

2

OUT

LID_SW#_3

37<

BB

AA

INVENTEC

TITLE

EVEREST-M
HALL SENSOR

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:17:03 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

57

of

1

REV

97

A01

8 7

6 5

4 3

2

1

P5V_A

D151

BAT_BLED1#

D

IN

1

C151

CSC0402_DY

2

P3V3_A

37>

BAT_OLED#

IN

1

C150

CSC0402_DY

2

37<

SUS_OLED#

D154

IN

1

C159

CSC0402_DY

2

1

HT_191UY

2

R160

1

150_5%_2

2

1

19_217_T1D_CP1Q2QY_3T

D155

1

HT_191UY

2

2

R153

1

220_5%_2

R154

1

150_5%_2

2

P3V3_AL

D

2

BATTERY LED

Suspend LED

CC

P3V3_S

37>

PWR_BLED#

P5V_S

D159

IN

1

C154

CSC0402_DY

2

1

19_217_T1D_CP1Q2QY_3T

2

R150

1

220_5%_2

2

37>

WL_OLED#

IN

1

C155

CSC0402_DY

2

POWER LED

D156

1

HT_191UY

2

R155

2

150_5%_2

1

Wireless & BT LED

LED_3S_SATA#

72<>

37>

DCIN_BLED#

8

P5V_S

5

U150

+

IN

1

2

-

TC7SZ08FU

3

4

1

2

19_217_T1D_CP1Q2QY_3T

C153

CSC0402_DY

D150

1

2

R151

1

220_5%_2

HDD LED

D152

IN

1

C152

CSC0402_DY

2

1

19_217_T1D_CP1Q2QY_3T

2

R152

1

220_5%_2

P5V_S

P5V_S

2

1

C149

0.1UF_16V_2

2

5

U191

+

49>

LED_3IN1

IN

P5V_A

2

1

2

-

TC7SZ08FU

3

4

1

CSC0402_DY

2

DC-IN LED

WIMAX LED

D153

1

19_217_T1D_CP1Q2QY_3T

C156

CARD READER LED

BB

P5V_S

2

R156

1

220_5%_2

2

AA

INVENTEC

TITLE

EVEREST-M

LED

REV

97

A01

7 6

5 4

CODE

SIZE

CS

CHANGE by

Frank Hu

3

Fri Dec 31 10:16:44 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

58

of

1

8 7

6 5

4 3

2

1

P3V3_S

D

15mil

FBM_11_160808_121T

1

L4001

+V3S_CLK_VDD

2

1

C4006

2

10uF_6.3V_3

Layout note: All decoupling 0.1uF disperse closed to pin

1

C4005

2

0.1UF_16V_2 0.1UF_16V_2

1

C4007

2

1

2

0.1UF_16V_2

C4008

1

C4009

2

0.1UF_16V_2 0.1UF_16V_2

1

C4010

2

D

P3V3_S

1

P3V3_S

R4001

1

10K_5%_2

2

CLKIN_BUF_DOT96_DP
CLKIN_BUF_DOT96_DN

CLKIN_SATA1_DP

CLKIN_SATA1_DN

CLKIN_DMI_PCH_DP

CLKIN_DMI_PCH_DN

OUT
OUT

OUT
OUT

OUT
OUT

R4013
R4012

R4011
R4010

R4009
R4008

1
1

1
1

1
1

33_5%_2_DY

2

33_5%_2_DY

2

33_5%_2_DY

2

33_5%_2_DY

2

33_5%_2_DY

2

33_5%_2_DY

2

CLK_BUF_DOT96_R_DP
CLK_BUF_DOT96_R_DN

CLK_SATA1_R_DP
CLK_SATA1_R_DN

CLKIN_DMI_PCH_R_DP
CLKIN_DMI_PCH_R_DN

U4000

1

VDDDOT96MHz_3.3

2

GNDDOT96MHz

3

DOT96T_LPR

4

DOT96C_LPR

5

VDD_27MHz

6

27MHz_nonSS

7

27MHz_SS

8

GND27MHz

9

GNDSATA

10

SATAT_LPR

11

SATAC_LPR

12

GNDSRC

13

SRCT1_LPR

14

SRCC1_LPR

15

VDDSRC_IO

16

CPU_STOP#

IDT_ICS9LRS3197AKLFT_MLF_32P

SCLK_3.3

SDATA_3.3

REF_3L-FSLC_3.3

VDDREF_3.3

CLKPWRGD-PD#_3.3

GNDREF

VDDCPU_3.3

CPUT0_LPR
CPUC0_LPR

GNDCPU
CPUT1_LPR
CPUC1_LPR
VDDCPU_IO

VDDSRC_3.3

GND

33
32
31
30

CLK_R3S_PCH14_R

29
28

X1
X2

CKG_X1
CKG_X2

27
26
25

CLKPWRGD_R

24
23

CLKOUT_DMI_CLKGEN_R_DP

22

CLKOUT_DMI_CLKGEN_R_DN

21
20

CLK_BUF_CPYCLK_R_DP

19

CLK_BUF_CPYCLK_R_DN

18
17

R4002

10K_5%_2_DY

2

R4000

R4007
R4006

R4005

R4017
R4016

R4015
R4014

PCH_3S_SMCLK

BI
BI

33_5%_2_DY

1

2

0_5%_2

2

1

2

1

1
1

1

1
1

33_5%_2_DY
33_5%_2_DY

2

0_5%_2_DY

2

0_5%_2_DY

2

0_5%_2_DY

2

0_5%_2_DY

2

PCH_3S_SMDATA

OUT

CLKIN_PCH14

CLKPWRGD

OUT

CLKOUT_DMI_CLKGEN_DP

OUT
OUT

CLKOUT_DMI_CLKGEN_DN

OUT

CLKIN_BUF_CPYCLK_DP

OUT

CLKIN_BUF_CPYCLK_DN

OUT

CLK_XDP_CLKGEN_DP

OUT

CLK_XDP_CLKGEN_DN

59>

27<
29<>
26<
60<

X4000

1

14.31818MHz

2

30PPM

1

C4004

2

33pF_50V_2 33pF_50V_2

1

2

C4003

CC

P1V05_VCCPS

8

L4000

1

FBM_11_160808_121T

2

+V1.05S_VCCP_VDD

15mil

1

C4002

2

10uF_6.3V_3

7 6

1

C4000

2

CLOSE TO IC PIN15,18

BB

R4004

1

0_5%_2_DY

Please place close to CLKGEN within 500mils

2

P3V3_A

1

C4001

2

0.1UF_16V_20.1UF_16V_2

5

U4001

+

MAIN_PWRGD

33>

ICC_EN#

IN
IN

1

2

-

TC7SZ08FU

3

1

C4011

0.1UF_16V_2

2

4

OUT

CLKPWRGD

59>

AA

1

R4003

2

1K_5%_2_DY

INVENTEC

TITLE

EVEREST-M
CLOCK GENERATOR

REV

97

A01

5 4

CODE

SIZE

C

CHANGE by

Frank Hu

3

Tue Jan 04 00:18:17 2011

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

59

of

1

D

P1V05_VCCPS

1

2

R8013

0_5%_2_DY

10mil

27< 26<

8 7

P3V3_S

1

R8012

0_5%_2_DY

2

59<> 29<>

60<>

20<

H_PREQ#

20>

H_PRDY#

H_BPM0_XDP#
H_BPM1_XDP#

H_BPM2_XDP#
H_BPM3_XDP#

25>

CFG<10>

25>

CFG<11>

H_BPM4_XDP#
H_BPM5_XDP#

H_BPM6_XDP#

H_BPM7_XDP#

H_CPUPWRGD
XDP_PWRSW#

60< 25>

CFG<0>

ALLSYS_PWROK

PCH_3S_SMDATA

PCH_3S_SMCLK

20<

60<>

H_TCK1

H_TCK

OUT

OUT
OUT

OUT

OUT
OUT

6 5

CN8000

1

GND0

3

OBSFN_A0

5

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN

2

R8001

Close to CPU

Close to CPU

1
1

1

1

1K_5%_2_DY

0_5%_2_DY

2

2

0_5%_2_DY

2

0_5%_2_DY

H_CPUPWRGD_XDP
XDP_PWRSW#_R

+V1.05S_VCC_OBS_AB

TCK_XDP

R8053

IN

R8014

IN
IN

R8052

OBSFN_A1
GND2

9

OBSDATD_A0

11

OBSDATD_A1
GND4

15

OBSDATD_A2

17

OBSDATD_A4

19

GND6

21

OBSFN_B0

23

OBSFN_B1
GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3
GND12

39

PWRGOOD_HOOK0

41

HOOK1
VCC_OBS_AB

45

HOOK2

47

HOOK3
GND14

51

SDA

53

SCL
TCK1

57

TCK0
GND16

SAMTEC_BSH_030_01_L_D_A_TR_60P

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK_HOOK4

ITPCLK#_HOOK5

VCC_OBS_CD

RESET#_HOOK6

DBR#_HOOK7

GND1

GND3

GND5

GND7

GND9

GND11

GND13

GND15

TRSTn

GND17

TDO

TDI
TMS

2
4
6
87

10
12
1413
16

18
20
22
24
2625
28
30
32
34
36
3837

CLK_XDP_R_DP

40

CLK_XDP_R_DN

42

+V1.05S_VCCP_VCC_OBS_CD

4443
46
48

XDP_DBRESET#

5049
52

TRST#_R

54

TDI_R

5655

TMS_R

58
6059

4 3

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

R8003
R8002

R8054

R8050
R8049
R8048

1

2

1

1

2
2
2

0_5%_2_DY

2

1K_5%_2_DY

1

0_5%_2_DY

1

0_5%_2_DY

1

0_5%_2_DY

0_5%_2_DY

2

IN
IN

IN

OUT
OUT
OUT

Close to CPU

CFG<16>
CFG<17>

CFG<0>
CFG<1>

CFG<2>
CFG<3>

CFG<8>
CFG<9>

CFG<4>

25> 60<
25>

25>

25>
25>

25>

CFG<5>
CFG<6>

CFG<7>

CLK_XDP_DP
CLK_XDP_DN

PLT_RST#

H_TRST#
H_TDI
H_TMS

20<
60<>

25>

25>

25<

25> 25<

25<25>
25<

25>

20<

25<25>

P3V3_S

1

R8055

2

1K_5%_2

29>

32<>
68<

20<

1

2

39<

37<

R8009

2

0_5%_2_DY

2

P1V05_VCCPS

R8011

10K_5%_2_DY

10mil

1

OUT

R8000

1

2

1K_5%_2

1

R8056

51_1%_2_DY

2

TDO_R

SYS_RESET#

1

R8051

2

0_5%_2_DY

1

Close to CPU

20>

30<

IN

H_TDO

20>

60<>

D

60>

61>
60>
28>

60<>

60>
60<>

60>
60>

20>60<
60>20<

60>20<
60<

60<>

H_TDO
H_TCK

H_TCK1

H_TMS
TDO_R

TCK_XDP

TDO_R

TRST#_R

TDI_R
TMS_R

CC

XDP CONNECTOR

SERIES

BI
BI
BI
BI
BI

R8008
R8007
R8006
R8005
R8004

1
1

1
1
1

PCH ONLY

IN
IN
IN
IN
IN

R8047
R8046
R8045
R8044
R8043

1
1
1
1
1

2

0_5%_2_DY

2

0_5%_2_DY

2

0_5%_2

2

0_5%_2_DY

2

0_5%_2_DY

2

0_5%_2_DY

2

0_5%_2

2

0_5%_2

2

0_5%_2

2

0_5%_2

BI
BI
BI
BI
BI

OUT
OUT
OUT
OUT

OUT

PCH_TDI
PCH_TCK

PCH_TCK
PCH_TMS

PCH_TDO

PCH_TCK
PCH_TDO
PCH_TRST#
PCH_TDI
PCH_TMS

28>
61<

28>
60<>

28>
60<>

28>

61>
60>
28>
61>
28>

28>
61>

61>

61>

61>

60<>

61>

H_CPUPWRGD_XDP

BB

+V1.05S

1

R8010

2

10K_5%_2_DY

IN

CLK_XDP_R_DP

Close to CPU

IN

R8015

1

2

0_5%_2_DY

OUT

MAIN_PWRGD

14<18>

59<37<

AA

INVENTEC

TITLE

EVEREST-M

XDP

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:45 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

60

of

1

REV

97

A01

8 7

6 5

4 3

2

1

+V3M

+V3M

15MIL

1

R8040

2.37K_1%_2

2

D

60<>
28>

PCH_TDI

60>
28>

PCH_TCK

60>
60<>

60<>
28>

PCH_TMS

60>

PCH_TRST#

1

R8039
806_1%_2

2

OUT
OUT

OUT
OUT

R8027

R8026

R8025

R8024

C8004

1

2

0.1UF_16V_2

1

1

1
1

2

0_5%_2_DY

2

0_5%_2_DY

2

0_5%_2_DY

2

0_5%_2_DY

PCH_TDI_R

PCH_TCK_R

PCH_TMS_R

PCH_TRST#_R

1

R8037
10K_5%_2

2

1

R8036
10K_5%_2_DY

2

+V3M

C8003

1

2

0.1UF_16V_2

U8001

1

DIR

2

A0

3

A1

4

GTLREF

5

A2

6

A3

7

GND1

PHP_GTL2005_TSSOP_14P

VCC

B0

B1

GND2

B2

B3

GND3

14
13
12
11
10
9
8

1

R8035
10K_5%_2

2

1

R8034

10K_5%_2_DY

2

1

R8033
10K_5%_2

2

1

R8032
10K_5%_2_DY

2

OUT
OUT

OUT
OUT

ME_TDI

ME_TCK

ME_TMS

ME_TRST#

61<

61<

61<

61<

1

R8042

301_1%_2

2

1

R8041

619_1%_2

2

OUT

D

PCH_TCK_R

CC

60<>

+V3M

1

2

1

2

28>60>

R8038

3.24K_1%_2

R8021
1K_5%_2

PCH_TDO

C8002

1

2

0.1UF_16V_2

IN

1

R8020
1K_5%_2 1K_5%_2

2

1

R8019

2

1

2

R8018
1K_5%_2

1

R8022
10K_5%_2_DY

2

1

R8023
10K_5%_2

2

1

R8028
10K_5%_2_DY

2

1

R8029

10K_5%_2

2

BB

+V3M

1

R8030
10K_5%_2_DY

2

1

R8031
10K_5%_2

2

15MIL

JACK8000

1

61>

61>

61>
61>
61>

ME_TCK
ME_TMS
ME_TDI
ME_TDO

ME_TRST#

C8001

1
2

0.1UF_16V_2

U8000

1

DIR

2

A0

3

A1

4

GTLREF

5

A2

6

A3

7

GND1

PHP_GTL2005_TSSOP_14P

VCC

B0

B1

GND2

B2

B3

GND3

14
13
12

R8017

1

22_5%_2

2

11
10
9
8

1

R8016
10K_5%_2

2

C8000

1
2

220PF_50V_2

OUT

ME_TDO

61<

IN
IN
IN
IN
IN

2
3
4
5
6

MLX_85510_5019_6P

1
2
3
4
5

G1
G2

6

G1
G2

AA

INVENTEC

TITLE

EVEREST-M
ME JTAG

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:46 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

61

of

1

REV

97

A01

8 7

6 5

4 3

2

1

PICK BUTTON BOARD

(FOR - TOUCHPAD MODULE, TOUCHPAD SWITCH BOARD, FINGERPRINT MODULE)

D

D

62<>

62<>

FIX9300

1

FIX_MASK

FIX9301

1

FIX_MASK

FIX9302

1

FIX_MASK

CONNECT TO TOUCHPAD MODULE

+TP_5S

TP_IM_CLK_5
TP_IM_DAT_5

LEFT_TP
RIGHT_TP

62>

CN9021

1

1

2

BI

BI

IN
IN

ACES_88766_060N_6P

2

3

3

4

4

5

5

6

6

G1

G1

G2

G2

GND_TP

CONNECT TO TOUCHPAD SWITCH BOARD

62<

DB_TP_ON#

FIX9303

1

FIX_MASK

FIX9304

1

FIX_MASK

FIX9904

1

FIX_MASK

OUT

CN9020

1

1

2

2

ENTERY_3703_Q02N_03R_2P

GND_TP

G1

G1

G2

G2

GND_TP

SCREW300_800_1P

SCREW220_800_1P

1

1

S9020

S9021

CONNECT TO MAINBOARD'S TP CONNECTOR

62<>

TP_IM_CLK_5

62<>

TP_IM_DAT_5

DB_TP_ON#

SW9021

4

A

5
6

MISAKI_NTC017_DA1G_E160T_6P

SW9020

4

A

5
6

MISAKI_NTC017_DA1G_E160T_6P

GND_TP

1

B

2
3

DC

1

B

2
3

DC

62>

BI
BI

IN

+TP_5S

1

2

3

GND_TP

CN9022

6

6

5

5

4

4

3

3

2

2

1

1

ACES_88766_060N_6P

G2

G2

G1

G1

GND_TP

OUT

RIGHT_TP

OUT

LEFT_TP

D9041

PHP_PESD5V2S2UT_SOT23_3P

CC

62<

BB

62<

AA

INVENTEC

TITLE

EVEREST-M
PICK BUTTON BOARD

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:17:03 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

62

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

D

TOUCHPAD SWITCH BOARD

SW9040

4

A

5
6

MISAKI_NTC017_DA1G_E160T_6P

1

B

2
3

DC

D9040

2

1

PHP_PESD5V2S2UT_SOT23_3P_DY

PAD9040

1

SMDPAD_1P_40X120

R9040

2

33_5%_2

1

1

3

C9040

0.01UF_50V_2

PAD9041

1

SMDPAD_1P_40X120

CC

2

GND_PB

GND_PB

FIX9040

1

FIX_MASK FIX_MASK

FIX9041

1

FIX9042

1

FIX_MASK

FIX9043

1

FIX_MASK

GND_PB

GND_PB

S9040

1

SCREW230_700_1P

S9041

1

SCREW230_700_1P

BB

AA

INVENTEC

TITLE

EVEREST-M

TOUCH PAD SW BOARD

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:46 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

63

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

POWER BUTTON

SW9000

1

G1

2

FOX_1BT002_0021L_4P

GND_BTN

3
G2
4

1

2

D9000

PHP_PESD5V2S2UT_SOT23_3P_DY

3

1

C9000

1000PF_50V_2

2

PAD9000

1

SMDPAD_1P_40X120

PAD9001

1

SMDPAD_1P_40X120

D

CC

GND_BTN

GND_BTN

BB

FIX9003

1

FIX_MASK

S9000

SCREW540_700_NP_1P

1

S9001

SCREW540_700_NP_1P

1

FIX9000

1

FIX_MASK FIX_MASK FIX_MASK

FIX9004

1

FIX_MASK FIX_MASK

FIX9001

1

FIX9005

1

FIX9002

1

GND_BTN

AA

INVENTEC

TITLE

EVEREST-M

POWER BUTTON BOARD

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:46 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

64

of

1

REV

97

A01

8 7

6 5

4 3

2

1

+V5A_DB

CARD READER & USB BOARD

+V3S_CARD

L9100

+V3S_CARD

1

BLM18PG600SN1D

+V5A_DB

D

2

1

2

CN9100

1

1

2

2

3

3

4

65<

65<>

USB_DB_P1_DN

65<>

USB_DB_P2_DP

65<

USB_DB_3IN1_DP

65>

SB_USB_1_DB

65<>

USB_DB_P1_DP

USB_DB_P2_DN

65<>

USB_DB_3IN1_DN

65<

USB_OC#_1_DB

65<

LED_3IN1_DB

IN
IN
IN

IN

OUT

IN

IN

IN

OUT

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16
17
18

G1

16

G1

G2

17

G2

18

ACES_50503_0184N_001_18P

1

X9100

12MHZ

GND_CARD

65<

XTIL1

OUT

65<

XTIL0

OUT

1

2

R9101

0_5%_2

2

GND_CARD

C9102

1

47PF_50V_2_DY

2

GND_CARD

R9100

1

270K_5%_2

1

C9100

20PF_50V_2

2

GND_CARD

2

GND_CARD

C9108

0.1UF_16V_2

1

2

65<

65<

USB_DB_3IN1_DN
USB_DB_3IN1_DP

65<

1

2

VREG

C9101

20PF_50V_2

IN

C9104

1

1UF_6.3V_2

2

65>
65>

R9103

1

6.2K_1%_2

GND_CARD

+VBUS

1

C9109

1UF_6.3V_2

2

GND_CARD

GND_CARD

+CARD_3V3

1

C9110

0.1UF_16V_2

2

65<

VREG

+VBUS

1

C9111

2

0.1UF_16V_2

GND_CARD

IN

GND_CARD

65>

GND_CARD

FIX9100

FIX_MASK_0.8 FIX_MASK_0.8 FIX_MASK_0.8 FIX_MASK_0.8 FIX_MASK_0.8 FIX_MASK_0.8

1

FIX9101

1

+VBUS

C9114

10UF_6.3V_3

C9113

1

0.1UF_16V_2

2

GND_CARD

+VBUS

1

R9102

100K_5%_2

2

1

C9103

1UF_6.3V_2

2

GND_CARD

OUT

IN

XTIL0 SD_D3
XTIL1

IN

43

42

45

48

2

IN
IN

LED_3IN1_DB

FIX9102

47

46

XTLI

XTL0

GND

1

AV_PLL

2

RREF

3

NC

4

DM

5

DP

6

GND

7

NC

8

3V3_IN

9
10
11
12

CARD_3V3
VREG
D3V3
GND

XTAL_CTR

GPIO0

EEDO

13

14

IN

FIX9103

1

1

MODE_SEL

EECS

16

44

RST#

SP19

U9100

EEDI

EESK

171518

4140393837

SP18

SP17

SP1

SP2

19

20

FIX9104

1

OUT

SP16

SP15

SP14

SP13

REA_RTS5159_VDD_GR_LQFP_48P

SD_CMD

SP12
SP11
D3V3

GND

SP10

NC
SP9
SP8
SP7
SP6
SP5

MS_D4

MS_D5

SP4

SP3

24

GND_CARD

23

21

22

BI

FIX9105

1

SD_D2

BI
BI

36
35
34
33
32
31
30
29
28
27
26
25

SD_D1

SD_CD#

SD_WP

65>

65>

BI

R9151

2

1

0_5%_2

BI

BI

BI

BI

+VBUS

1

65<>

2

65<>

GND_CARD

65<

SB_USB_1_DB

65<

65<

SD_CMD

65<>

BI

65<>

MS_D3

MS_INS#

MS_D2

BI

SD_D0_MS_D0

BI

MS_D1

65<>

MS_BS

C9112

0.1UF_16V_2

65<>

PAD9150

1

1

2

POWERPAD_2_0610

IN

65<

USB_DB_P1_DN

USB_DB_P1_DP

65<

USB_DB_P2_DN

USB_DB_P2_DP

+CARD_3V3

1

C9106

2.2UF_6.3V_2

2

GND_CARD

SD_CLK_MS_CLK

65<>

65<>

65<>
65<>

+V5A_DB_USB_IN

2

1

1

C9150

C9154

0.01UF_50V_222UF_6.3V_5_DY

2

2

GND_CARD

1

C9151

0.1UF_16V_2

2

GND_CARD

BI

BI

BI

BI

1

2

L9151

1

WCM_2012_900T

L9150

1

WCM_2012_900T

C9105

1UF_6.3V_2

CLOSE TO CN

65<>

SD_WP

SD_D1

SD_D3

SD_CMD

SD_D2

1

1

BI
BI

OUT

65<>

SD_D0_MS_D0

SD_CLK_MS_CLK

65<>

65>

65>

S9101

SCREW300_900_1P

S9102

SCREW480_800_700_1P

GMT_G547G1P81U_MSOP_8P

GND_CARD

34

BI

2

34

BI

2

1

C9107

1UF_6.3V_2

2

BI

BI

BI

OUT

GND_CARD

U9150

1

GND

2

IN

3

IN

4

USB_DB_P1_L_DN

USB_DB_P1_L_DP

BI

USB_DB_P2_L_DN

BI

USB_DB_P2_L_DP

GND_CARD

8

OUT

7

OUT
OUT
OC#EN

65<>

65<>

6
5

65<>

65<>

65<>

65<>

USB_DB_P2_L_DN

65<>

1

C9153

+

330UF_6.3V

2

OUT

USB_OC#_1_DB

USB_DB_P1_L_DN

65<>

USB_DB_P1_L_DP

USB_DB_P2_L_DP

GND_CARD

CN9101

17

SD-VSS

4

MS-VCC

2

MS-VSS

9

SD-VSS

16

MS-VSS

22

SD-WP

19

SD-DAT1

18

SD-DAT0

14

SD-CLK

6

SD-CMD

3

SD-DAT3

1

SD-DAT2

21

SD-CD-WP

11

SD-VDD

MS-BS
MS-DATA1
MS-DATA0
MS-DATA2

MS-INS

MS-DATA3

MS-SCLK

SD-CD

GND
GND

TAIT_R009_040_LM_22P

R9151 R9152

CLOSE TO RTS5159

+USB_VCC1

65>

1

R9150
RSC_0402_DY

2

1

C9152

0.1UF_16V_2

2

GND_CARD

+USB_VCC1

BI

BI

SYN_020133GR004M52CZL_4P

GND_CARD

+USB_VCC1

BI

BI

SYN_020133GR004M52CZL_4P

15
13
12
10
8
7
5

20
G1
G2

GND_CARD

INVENTEC

TITLE

USB

CN9151

1
2
3
4

1
2
3
4

EVEREST-M

VCC
D­D+
G

CN9152

VCC
D­D+
G

BI
BI
BI
BI

BI

G
G
G
G

G
G
G
G

MS_BS

BI

SD_D0_MS_D0

MS_INS#

SD_CLK_MS_CLK

SD_CD#

D

G1
G2
G3
G4

G1
G2
G3
G4

65<>

65<>

MS_D1

65<>

MS_D2

MS_D3

65<>

65<>

65<>

65<>

65<>

BI
BI

CC

BB

AA

CARDREADER & USB BOARD

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:47 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

65

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

D

EMI

P1V5

C7511

2

1

0.1UF_16V_2
C7510

2

1

0.1UF_16V_2
C7509

2

1

0.1UF_16V_2
C7508

2

1

0.1UF_16V_2 0.1UF_16V_2

C7507

1

0.1UF_16V_2
C7506

1

0.1UF_16V_2
C7505

1

0.1UF_16V_2

C7504

1

2

2

2

2

C7503

1

0.1UF_16V_2
C7502

1

0.1UF_16V_2
C7501

1

0.1UF_16V_2
C7500

1

0.1UF_16V_2

2

2

2

2

CC

BB

AA

INVENTEC

TITLE

EVEREST-M
EMI

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:17:04 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

66

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

DGPU_PWROK

67<

10K_5%_2_DY

PCH_LVDS_TXDL0_DN
PCH_LVDS_TXDL0_DP
PCH_LVDS_TXDL1_DN
PCH_LVDS_TXDL1_DP
PCH_LVDS_TXDL2_DN
PCH_LVDS_TXDL2_DP
PCH_LVDS_TXCL_DN
PCH_LVDS_TXCL_DP

GPU_LVDS1_TXDL0_DN
GPU_LVDS1_TXDL0_DP
GPU_LVDS1_TXDL1_DN
GPU_LVDS1_TXDL1_DP
GPU_LVDS1_TXDL2_DN
GPU_LVDS1_TXDL2_DP
GPU_LVDS1_TXCL_DN
GPU_LVDS1_TXCL_DP

DGPU_SELECT#

DGPU_PRSNT#

IN

SSM3K7002BFU

R7414

2

1

HI: B2

LOW: B1

DGPU_SELECT

PER_PI2PCIE2412ZHE_TQFN_42P

2

IN

R7410
R7409

IN

8

Q7406

1

IN
IN
IN
IN
IN
IN
IN
IN

IN
IN
IN
IN
IN
IN
IN
IN

IN

P3V3_S

1

5

U3004

NC

+

-

TC7SH14F

3

1
1

P3V3_A

2

1

3

DS

G

2

38
37
36
35
29
28
27
26

34
33
32
31
25
24
23
22

9

4

10K_5%_2_DY

2

10K_5%_2

2

R7401

2

R7405

10K_5%_2

1

0_5%_2

R7408

1

0_5%_2

OUT

CLKREQ_GPU_PEG#_MOS

2

OUT

CLKREQ_GPU_PEG#

P1V8_S

20mil

U3005

B0
B1
B2
B3
B4
B5
B6
B7

C0
C1
C2
C3
C4
C5
C6
C7

SEL

1

C7403

2

0.1UF_16V_2

OUT

7 6

5

VDD

8

VDD

13

VDD

18

VDD

20

VDD

30

VDD

40

VDD

42

VDD

2

GND
GND
GND
GND
GND
GND
GND
GND
GND
TML

A0
A1
A2
A3
A4
A5
A6
A7

OUT

3

OUT

6

OUT

7

OUT

11

OUT

12

OUT

15

OUT

16

OUT

1
4
10
14
17
19
21
41
39
43

DGPU_SELECT

P3V3_S

SW_LVDS_TXDL0_DN
SW_LVDS_TXDL0_DP
SW_LVDS_TXDL1_DN
SW_LVDS_TXDL1_DP
SW_LVDS_TXDL2_DN
SW_LVDS_TXDL2_DP
SW_LVDS_TXCL_DN
SW_LVDS_TXCL_DP

EC_LCM_INVPWM

GPU_LCM_INVPWM

330uF_2V_15mR_Pana_-35%

DGPU_PWROK_5R

HI: B2
LOW: B1

IN

67<

R3021

1

0_5%_2_DY

R3020

1

0_5%_2

DGPU_SELECT#
GPU_LVDS_DDCCLK

PCH_LVDS_DDCCLK

SW_LVDS_DDCCLK

GPU_LVDS_DDCDATA
PCH_LVDS_DDCDATA

SW_LVDS_DDCDATA

IN

P1V05_VCCPS

1

C7404

2

IN

DGPU_PWROK#

32<
32>

2

2

IN
IN
IN

OUT

IN
IN

OUT

1
2
3
4
5
6
7
8

PHP_CBT3257DS_QSOP_16P

DGPU_PWM_SELECT#

PCH_LCM_INVPWM

SW_LCM_INVPWM

3.55A

P1V05_GPUS

+

Q7409

8

D

7
6

NMOS_4D3S

AM4430N

1

220K_5%_2

R7413

1

S

2
3
45

G

2

IN

1

C7405

680PF_50V_2

2

Q7408

1

SSM3K7002BFU

G

20mil

U3002

S
1B1
1B2
1A
2B1
2B2
2A
GND

VCC

4B1
4B2

3B1
3B2

OE

4A

3A

P5V_S

16
15
14
13
12
11
10

9

IN

GPU_LCM_BKLTEN

IN

PCH_LCM_BKLTEN

OUT

SW_LCM_BKLTEN

IN

GPU_LCM_VDDEN

IN

PCH_LCM_VDDEN

OUT

SW_LCM_VDDEN

20mil

U3003

1

IN

31>

IN

48<

OUT

PHP_CBT3257DS_QSOP_16P

5 4

S

2

1B1

3

1B2

4

1A

5

2B1

6

2B2

7

2A

8

GND

1

R7412

200_5%_2

2

3

DS

2

VCC

OE
4B1
4B2

4A
3B1
3B2

3A

P5V_S

16
15
14
13
12
11
10
9

33<>

67<

16>

DGPU_PWROK

DGPU_PWROK#

DGPU_PWROK_5R

EC_DGPU_PWR_EN#

EC_DGPU_PWR_EN

DGPU_PRSNT#

44<

44<

DGPU_PWR_EN#

DGPU_PWROK

DGPU_HOLD_RST#

DGPU_SELECT#

DGPU_PWM_SELECT#

IN

SSM3K7002BFU

R7403

10K_5%_2

Q7401

1

IN

SSM3K7002BFU

DURING RESET

3

R7402

10K_5%_2

Q7400

1

P3V3_S

2

1

3

DS

G

2

IN

HIGH

LOW

HIGH

CHANGE by

P3V3_S

2

1

3

SSM3K7002BFU

DS

G

2

OUT
OUT

R7404

750K_1%_2

Q7402

1

SSM3K7002BFU

Frank Hu

P5V_S P1V5

R7407

750K_1%_2

Q7405

1

G

P5V_S

2

CSC0402_DY

1

1

3

100K_5%_2

DS

G

2

67<

AFTER RESET

HIGH

LOW

HIGH

Fri Dec 31 10:16:48 2010

DATE

10.72A

P1V5_GPUS

2

1

3

DS

8
7
6

Q7404

D

NMOS_4D3S

AM4430N

0.1UF_25V_2

S

G

C7402

1
2
3
45

1

2

2

Q7403

1

DGPU_PWROK#

IN

SSM3K7002BFU

G

2.5A

P3V3_S

4

1

C7400

3 6

2

R7411

2

EC_DGPU_PWR_EN#

Q7407

S

G

PMOS_4D1S

AM3423P

C7401

2

330PF_50V_2

IN

SSM3K7002BFU

0 : ADDIN CARD PRESENT

1 : ADDIN CARD NOT PLUGGED IN
0 : DGPU POWER SWITCH TURNED ON

1 : POWER SWITCH TURNED OFF

0 : DGPU POWER IS NOT STABLE.

1 : DGPU POWER IS STABLE

0 : KEEP DGPU IN RESET
1 : RESET IS RELEASED

0 : DISPLAY SWITCH ENABLED FOR DGPU

1 : DISPLAY SWITCH ENABLED FOR IGPU
0 : PWM SIGNAL FROM EC

1 : PWM SIGNAL FROM PCH

P3V3_GPUS

1

D

2
5

1

Q7410

1

G

INVENTEC

TITLE

EVEREST-M
GPU SW / POWER

CODE

SIZE

CS

C

SHEET

2

DOC.NUMBER

CS_1310AXXXXXX-MTR

67

of

1

1

R7406

200_5%_2

2

3

DS

2

2

R7400

200_5%_3

1

3

DS

2

97

REV

A01

D

CC

BB

AA

8

7 6 5 4 3 2

1

P3V3_GPUS

E

D

C

B

PEG_RX0_DP
PEG_RX0_DN

PEG_TX0_DP
PEG_TX0_DN

PEG_RX1_DP
PEG_RX1_DN

PEG_TX1_DP
PEG_TX1_DN

PEG_RX2_DP
PEG_RX2_DN

PEG_TX2_DP
PEG_TX2_DN

PEG_RX3_DP
PEG_RX3_DN

PEG_TX3_DP
PEG_TX3_DN

PEG_RX4_DP
PEG_RX4_DN

PEG_TX4_DP
PEG_TX4_DN

PEG_RX5_DP
PEG_RX5_DN

PEG_TX5_DP
PEG_TX5_DN

PEG_RX6_DP
PEG_RX6_DN

PEG_TX6_DP
PEG_TX6_DN

PEG_RX7_DP
PEG_RX7_DN

PEG_TX7_DP
PEG_TX7_DN

PEG_RX8_DP
PEG_RX8_DN

PEG_TX8_DP
PEG_TX8_DN

21<

PEG_RX9_DP

21<

PEG_RX9_DN

PEG_TX9_DP
PEG_TX9_DN

21<

PEG_RX10_DP

21<

PEG_RX10_DN

PEG_TX10_DP
PEG_TX10_DN

21<

PEG_RX11_DP

21<

PEG_RX11_DN

21>

PEG_TX11_DP

21>

PEG_TX11_DN

21<

PEG_RX12_DP

21<

PEG_RX12_DN

21>

PEG_TX12_DP

21>

PEG_TX12_DN

21<

PEG_RX13_DP

21<

PEG_RX13_DN

21>

PEG_TX13_DP

21>

PEG_TX13_DN

21<

PEG_RX14_DP

21<

PEG_RX14_DN

21>

PEG_TX14_DP

21>

PEG_TX14_DN

21<

PEG_RX15_DP

21<

PEG_RX15_DN

21>

PEG_TX15_DP

21>

PEG_TX15_DN

60<
39<
32<>

PLT_RST#

37<

EC_PEG_RST#

CLKREQ_GPU_PEG#_MOS

CLK_PEG_GPU_REF_DP
CLK_PEG_GPU_REF_DN

OUT
OUT

21>

IN

21>

IN

21<

OUT

21<

OUT

21>

IN

21>

IN

21<

OUT

21<

OUT

21>

IN

21>

IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

21<

OUT

21<

OUT

IN
IN

OUT
OUT

IN
IN

21<

OUT

21<

OUT

21>

IN

21>

IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

C5012
C5011

C5010
C5009

C5008
C5007

C5006
C5005

IN
IN

C5036
C5035

C5034
C5033

C5032
C5031

C5030
C5029

C5028
C5027

C5026
C5025

C5024
C5023

C5022
C5021

C5018
C5017

C5014
C5013

C5020
C5019

C5016
C5015

1

C5039

0.1uF_16V_2

U5001

+

4

-

TC7SZ08FU

3

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

0.1uF_6.3V_1

2

DS

2

BI
BI

2

R5000

100K_5%_2

1

2

Q5001

G

SSM3K7002BFU

1

200_1%_2

1

PEG_RX0_C_DP
PEG_RX0_C_DN

PEG_RX1_C_DP
PEG_RX1_C_DN

PEG_RX2_C_DP
PEG_RX2_C_DN

PEG_RX3_C_DP
PEG_RX3_C_DN

PEG_RX4_C_DP
PEG_RX4_C_DN

PEG_RX5_C_DP
PEG_RX5_C_DN

PEG_RX6_C_DP
PEG_RX6_C_DN

PEG_RX7_C_DP
PEG_RX7_C_DN

PEG_RX8_C_DP
PEG_RX8_C_DN

PEG_RX9_C_DP
PEG_RX9_C_DN

PEG_RX10_C_DP
PEG_RX10_C_DN

PEG_RX11_C_DP
PEG_RX11_C_DN

PEG_RX12_C_DP
PEG_RX12_C_DN

PEG_RX13_C_DP
PEG_RX13_C_DN

PEG_RX14_C_DP
PEG_RX14_C_DN

PEG_RX15_C_DP
PEG_RX15_C_DN

5

1
2

3

OUT

P3V3_GPUS

R5076

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

0.1uF_6.3V_1

2

1

2

1

1
1

1
1

1
1

0.1uF_6.3V_1

0.1uF_6.3V_1

2
2

0.1uF_6.3V_1

0.1uF_6.3V_1

2
2

0.1uF_6.3V_1

0.1uF_6.3V_1

2
2

0.1uF_6.3V_1

AM16
AR13

AJ17
AJ18

AR16
AR17

AL17
AM17

AP17
AN17

AM18
AM19

AN19
AP19

AL19
AK19

AR19
AR20

AL20
AM20

AP20
AN20

AM21
AM22

AN22
AP22

AL22
AK22

AR22
AR23

AL23
AM23

AP23
AN23

AM24
AM25

AN25
AP25

AL25
AK25

AR25
AR26

AL26
AM26

AP26
AN26

AM27
AM28

AN28
AP28

AL28
AK28

AR28
AR29

AK29
AL29

AP29
AN29

AM29
AM30

AN31
AP31

AM31
AM32

AR31
AR32

AN32
AP32

AR34
AP34

U5000

1/16 PCI_EXPRESS

PEX_RST*

PEX_CLKREQ*

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT*

PEX_REFCLK
PEX_REFCLK*

PEX_TX0
PEX_TX0*

PEX_RX0
PEX_RX0*

PEX_TX1
PEX_TX1*

GF108

PEX_RX1
PEX_RX1*

PEX_TX2
PEX_TX2*

PEX_RX2
PEX_RX2*

PEX_TX3
PEX_TX3*

PEX_RX3
PEX_RX3*

PEX_TX4
PEX_TX4*

PEX_RX4
PEX_RX4*

PEX_TX5
PEX_TX5*

PEX_RX5
PEX_RX5*

PEX_TX6
PEX_TX6*

PEX_RX6
PEX_RX6*

PEX_TX7
PEX_TX7*

PEX_RX7
PEX_RX7*

PEX_TX8
PEX_TX8*

PEX_RX8
PEX_RX8*

PEX_TX9
PEX_TX9*

PEX_RX9
PEX_RX9*

PEX_TX10
PEX_TX10*

PEX_RX10
PEX_RX10*

PEX_TX11
PEX_TX11*

PEX_RX11
PEX_RX11*

PEX_TX12
PEX_TX12*

PEX_RX12
PEX_RX12*

PEX_TX13
PEX_TX13*

PEX_RX13
PEX_RX13*

PEX_TX14
PEX_TX14*

PEX_RX14
PEX_RX14*

PEX_TX15
PEX_TX15*

PEX_RX15
PEX_RX15*

GT21X

RFU

NVIDIA_N12P_GS_BGA_973P

PEX_SVDD_3V3GT21X

PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5

PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9

PEX_IOVDDQ_10

PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18
PEX_IOVDDQ_19
PEX_IOVDDQ_20
PEX_IOVDDQ_21
PEX_IOVDDQ_22
PEX_IOVDDQ_23
PEX_IOVDDQ_24
PEX_IOVDDQ_25

PEX_SVDD_3V3

PEX_SVDD_3V3_NC

VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5

VDD_SENSE_2
VDD_SENSE_3
VDD_SENSE_1
GND_SENSE_1
GND_SENSE_3
GND_SENSE_2

PEX_PLLVDD

GF108

PEX_PLL_HVDD_NC

PEX_TERMP

TESTMODE

NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26

AK16
AK17
AK21
AK24
AK27

AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24

AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

AG19
F7

A2

NC_1

A7

NC_2

AA4

NC_3

AB4

NC_4

AB7

NC_5

AC5

NC_6

AD6

NC_7

AF6

NC_8

AG6

NC_9

AJ5
AK15
AL7
B7
C7
D5
D6
D7
E5
E7
F4
G5
H32
P6
U7
V6
Y4

J10
J11
J12
J13
J9

D35
P7
AD20
AD19
R7
E35

GND_SENSE_R

+GPU_V1.05S_PEX_PLLVDD

AG14

AG20
AG21

AP35

20mil

1

C5156

0.1uF_16V_2 0.1uF_16V_2

2

1

C5047

22UF_6.3V_5_DY

2

20mil

1

C5155

0.1uF_16V_2

2

15mil

1

C5154

0.1UF_16V_2

2

+GPU_NVVDD_L_R

2.49K_1%_2

1

2

R5075

1

R5017

1

10K_5%_2

R5027

R5026

CLOSE TO POWER IC

C5003

1uF_6.3V_2

2

2

1

10UF_6.3V_3_DY

2

15mil

1

C5153

0.1uF_16V_2

2

1

1

1

C5002

1uF_6.3V_2

2

1

C5152

2

C5046

1

C5151

0.1uF_16V_2

2

P3V3_GPUS

1

C5149

4.7UF_6.3V_3

2

0_5%_2

2

2

100_1%_2

1

C5045

4.7UF_6.3V_3_DY

2

P1V05_GPUS

R5002

1

0_5%_2_DY

1

C5150

0.1uF_16V_2

2

1

C5004

0.1UF_16V_2

2

1

C5148

1uF_6.3V_2

2

1

C5044

1UF_6.3V_2_DY

1

C5144

1uF_6.3V_2

2

2

1

C5147

1uF_6.3V_2 1uF_6.3V_2

2

2

1

C5143

2

P3V3_GPUS

1

C5146

1uF_6.3V_2

2

OUT

+GPU_NVVDD_L

15mil

15mil

1

C5145

1uF_6.3V_2

2

1

C5043

1UF_6.3V_2_DY

2

4.7uF_6.3V_3

1

C5134

4.7uF_6.3V_3

2

1

C5142

4.7uF_6.3V_3

2

1

2

1

C5140

4.7uF_6.3V_3

2

C5158

1

P1V05_GPUS

C5141

4.7uF_6.3V_3

1

C5042

0.1UF_16V_2_DY

2

P1V05_GPUS

P1V05_GPUS

KC_HLM_160808_R10J

1

2

KC_HLM_160808_R10J

1

C5001

0.1uF_16V_2

2

L5009

2

HK1005R10J_T_200mA

1

C5133

10uF_6.3V_3

2

1

C5132

10uF_6.3V_3

2

L5007

1

C5157

10UF_6.3V_3

L5006

1

0.1UF_16V_2

P1V05_GPUS

1

2

10mil

2

1

4700PF_50V_2

2

10mil

2

C5138

CLK_GPU_27M

1

C5139

4.7uF_6.3V_3

2

C5000

0.1uF_16V_2

1

C5159

0.1uF_16V_2

2

+GPU_V1.05S_PLLVDD

1

1

C5137

+GPU_V1.05S_SP_PLLVDD

1

2

2

1

C5136

0.1UF_16V_2

2

C5135

0.1UF_16V_2

2

1

R5074

10K_5%_2

2

IN

1

C5065

22UF_6.3V_5

2

1

C5064

22UF_6.3V_5

2

1

C5063

0.1UF_16V_2

2

1

0_5%_2_DY

R5003

XTAL27_IN

U5000

14/16 XTAL_PLL

AE9

PLLVDD

AD9

VID_PLLVDD

AF9

SP_PLLVDD

D2

XTAL_SSIN

2

B1

XTAL_IN

NVIDIA_N12P_GS_BGA_973P

1

1

C5069

18PF_50V_2

2

X5000

27MHz

XTAL_OUTBUFF

XTAL_OUT

2

18PF_50V_2

C5068

D1

B2

XTAL27_OUT

1

2

R5073

10K_5%_2

FF

E

D

1

2

C

B

A

A

INVENTEC

TITLE

EVEREST
GPU-1

SIZE

CODE

Fri Dec 31 10:16:49 2010

8

7 6 5 4 3

CHANGE by

Frank Hu

DATE

2

C

ES

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

1

REV

A01

of

9768

8

7 6 5 4 3 2

1

74<> 73<>

E

D

C

B

A

FBA_D<63..0>

FBA_DQM<7..0>

FBA_DQS_DP<7..0>

FBA_DQS_DN<7..0>

8

BI

OUT

BI

BI

FBA_D<0>

0

FBA_D<1>

1

FBA_D<2>

2

FBA_D<3>

3

FBA_D<4>

4

FBA_D<5>

5

FBA_D<6>

6

FBA_D<7>

7

FBA_D<8>

8

FBA_D<9>

9

FBA_D<10>

10

FBA_D<11>

11

FBA_D<12>

12

FBA_D<13>

13

FBA_D<14>

14

FBA_D<15>

15

FBA_D<16>

16

FBA_D<17>

17

FBA_D<18>

18

FBA_D<19>

19

FBA_D<20>

20

FBA_D<21>

21

FBA_D<22>

22

FBA_D<23>

23

FBA_D<24>

24

FBA_D<25>

25

FBA_D<26>

26

FBA_D<27>

27

FBA_D<28>

28

FBA_D<29>

29

FBA_D<30>

30

FBA_D<31>

31

FBA_D<32>

32

FBA_D<33>

33

FBA_D<34>

34

FBA_D<35>

35

FBA_D<36>

36

FBA_D<37>

37

FBA_D<38>

38

FBA_D<39>

39
40

FBA_D<40>
FBA_D<41>

41

FBA_D<42>

42

FBA_D<43>

43
44

FBA_D<44>
FBA_D<45>

45

FBA_D<46>

46
47

FBA_D<47>
FBA_D<48>

48

FBA_D<49>

49

FBA_D<50>

50

FBA_D<51>

51
52

FBA_D<52>

53

FBA_D<53>

54

FBA_D<54>
FBA_D<55>

55
56

FBA_D<56>
FBA_D<57>

57

FBA_D<58>

58
59

FBA_D<59>
FBA_D<60>

60
61

FBA_D<61>

62

FBA_D<62>
FBA_D<63>

63

FBA_DQM<0>

0

FBA_DQM<1>

1

FBA_DQM<2>

2

FBA_DQM<3>

3

FBA_DQM<4>

4

FBA_DQM<5>

5

FBA_DQM<6>

6

FBA_DQM<7>

7

0

FBA_DQS_DP<0>
FBA_DQS_DP<1>

1

FBA_DQS_DP<2>

2

FBA_DQS_DP<3>

3

FBA_DQS_DP<4>

4

FBA_DQS_DP<5>

5

FBA_DQS_DP<6>

6

FBA_DQS_DP<7>

7

FBA_DQS_DN<0>

0

FBA_DQS_DN<1>

1

FBA_DQS_DN<2>

2

FBA_DQS_DN<3>

3

FBA_DQS_DN<4>

4

FBA_DQS_DN<5>

5

FBA_DQS_DN<6>

6

FBA_DQS_DN<7>

7

1

0.1UF_16V_2

4.7UF_6.3V_3

2

1

C5085

2

1uF_6.3V_2

FBA_CMD<30..0>

P1V5_GPUS

16mil

1

C5076

0.1UF_16V_2

2

1

C5037

C5061

2

P1V5_GPUS

1

C5082

C5083

4.7UF_6.3V_3

2

73<

74<
74<

1

R5041

60.4_1%_2

2

1

C5060

0.1UF_16V_2

2

L5002

1

FBM_10_160808_301A05T_500mA

10UF_6.3V_3

1

C5059
1UF_6.3V_2

2

P1V05_GPUS

2

75<>

76<>

FBC_D<63..0>

74<73<

74<>73<>

FBC_DQM<7..0>

FBC_DQS_DP<7..0>

FBC_DQS_DN<7..0>

FBM_10_160808_301A05T_500mA

1

C5074

10UF_6.3V_3

2

1

C5058

4.7uF_6.3V_3

2

1

L5000

BI

OUT

OUT

IN

P1V05_GPUS

2

FBC_D<0>

0

FBC_D<1>

1

FBC_D<2>

2

FBC_D<3>

3

FBC_D<4>

4

FBC_D<5>

5

FBC_D<6>

6

FBC_D<7>

7

FBC_D<8>

8

FBC_D<9>

9

FBC_D<10>

10

FBC_D<11>

11

FBC_D<12>

12

FBC_D<13>

13

FBC_D<14>

14

FBC_D<15>

15

FBC_D<16>

16

FBC_D<17>

17

FBC_D<18>

18

FBC_D<19>

19

FBC_D<20>

20

FBC_D<21>

21

FBC_D<22>

22

FBC_D<23>

23

FBC_D<24>

24

FBC_D<25>

25

FBC_D<26>

26

FBC_D<27>

27

FBC_D<28>

28

FBC_D<29>

29

FBC_D<30>

30

FBC_D<31>

31

FBC_D<32>

32

FBC_D<33>

33

FBC_D<34>

34

FBC_D<35>

35

FBC_D<36>

36

FBC_D<37>

37

FBC_D<38>

38

FBC_D<39>

39

FBC_D<40>

40

FBC_D<41>

41

FBC_D<42>

42

FBC_D<43>

43

FBC_D<44>

44

FBC_D<45>

45

FBC_D<46>

46

FBC_D<47>

47

FBC_D<48>

48

FBC_D<49>

49

FBC_D<50>

50

FBC_D<51>

51

FBC_D<52>

52

FBC_D<53>

53

FBC_D<54>

54

FBC_D<55>

55

FBC_D<56>

56
57

FBC_D<57>
FBC_D<58>

58

FBC_D<59>

59

FBC_D<60>
FBC_D<61>

61

FBC_D<62>

62

FBC_D<63>

63

FBC_DQM<0>

0

FBC_DQM<1>

1

FBC_DQM<2>

2

FBC_DQM<3>

3

FBC_DQM<4>

4

FBC_DQM<5>

5

FBC_DQM<6>

6

FBC_DQM<7>

7

0

FBC_DQS_DP<0>
FBC_DQS_DP<1>

1

FBC_DQS_DP<2>

2

FBC_DQS_DP<3>

3

FBC_DQS_DP<4>

4

FBC_DQS_DP<5>

5

FBC_DQS_DP<6>

6

FBC_DQS_DP<7>

7

0

FBC_DQS_DN<0>

1

FBC_DQS_DN<1>

2

FBC_DQS_DN<2>

3

FBC_DQS_DN<3>

4

FBC_DQS_DN<4>

5

FBC_DQS_DN<5>

6

FBC_DQS_DN<6>

7

FBC_DQS_DN<7>

1

C5077

4.7uF_6.3V_3

2

B13
D13
A13
A14
C16
B16
A17
D16
C13
B11
C11
A11
C10

F10
F12
D11

E11
D12
E13
F13
F14
F15
E16
F16
F17
D29
F27
F28
E28
D26
F25
D24
E25
E32
F32
D33
E31
C33
F29
D30
E29
B29
C31
C29
B31
C32
B32
B35
B34
A29
B28
A28
C28
C26
D25
B25
A25

A16
D10
F11
D15
D27
D34
A34
D28

G14
G15
G11
G12
G27
G28
G24
G25

C8
B8
A8
E8
F8

F9
D8

C14

A10
E10
D14
E26
D32
A32

B26

B14
B10

E14
F26
D31
A31
A26

D9

U5000

3/16 FBB

FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63

FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7

FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7

FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7

FBB_WCK0
FBB_WCK0*
FBB_WCK1
FBB_WCK1*
FBB_WCK2
FBB_WCK2*
FBB_WCK3
FBB_WCK3*

U5000

2/16 FBA

L32

FBA_D0

N33

FBA_D1

L33

FBA_D2

N34

FBA_D3

N35

FBA_D4

P35

FBA_D5

P33

FBA_D6

P34

FBA_D7

K35

FBA_D8

K33

FBA_D9

K34

FBA_D10

H33

FBA_D11

G34

FBA_D12

G33

FBA_D13

E34

FBA_D14

E33

FBA_D15

G31

FBA_D16

F30

FBA_D17

G30

FBA_D18

G32

FBA_D19

K30

FBA_D20

K32

FBA_D21

H30

FBA_D22

K31

FBA_D23

L31

FBA_D24

L30

FBA_D25

M32

FBA_D26

N30

FBA_D27

M30

FBA_D28

P31

FBA_D29

R32

FBA_D30

R30

FBA_D31

AG30

FBA_D32

AG32

FBA_D33

AH31

FBA_D34

AF31

FBA_D35

AF30

FBA_D36

AE30

FBA_D37

AC32

FBA_D38

AD30

FBA_D39

AN33

FBA_D40

AL31

FBA_D41

AM33

FBA_D42

AL33

FBA_D43

AK30

FBA_D44

AK32

FBA_D45

AJ30

FBA_D46

AH30

FBA_D47

AH33

FBA_D48

AH35

FBA_D49

AH34

FBA_D50

AH32

FBA_D51

AJ33

FBA_D52

AL35

FBA_D53

AM34

FBA_D54

AM35

FBA_D55

AF33

FBA_D56

AE32

FBA_D57

AF34

FBA_D58

AE35

FBA_D59

AE34

FBA_D60

AE33

FBA_D61

AB32

FBA_D62

AC35

FBA_D63

P32

FBA_DQM0

H34

FBA_DQM1

J30

FBA_DQM2

P30

FBA_DQM3

AF32

FBA_DQM4

AL32

FBA_DQM5

AL34

FBA_DQM6

AF35

FBA_DQM7

L34

FBA_DQS_WP0

H35

FBA_DQS_WP1

J32

FBA_DQS_WP2

N31

FBA_DQS_WP3

AE31

FBA_DQS_WP4

AJ32

FBA_DQS_WP5

AJ34

FBA_DQS_WP6

AC33

FBA_DQS_WP7

L35

FBA_DQS_RN0

G35

FBA_DQS_RN1

H31

FBA_DQS_RN2

N32

FBA_DQS_RN3

AD32

FBA_DQS_RN4

AJ31

FBA_DQS_RN5

AJ35

FBA_DQS_RN6

AC34

FBA_DQS_RN7

P29

FBA_WCK0

R29

FBA_WCK0*

L29

FBA_WCK1

M29

FBA_WCK1*

AG29

FBA_WCK2

AH29

FBA_WCK2*

AD29

FBA_WCK3

AE29

FBA_WCK3*

GF108 GT21X

J27

FB_VREF_NC

NVIDIA_N12P_GS_BGA_973P

FB_VREF

GT21X

FBA_CMD25

FBA_CMD23
FBA_CMD2
FBA_CMD0

FBA_CMD10

FBA_CMD26

FBA_CMD14
FBA_CMD7
FBA_CMD1

FBA_CMD22

FBA_CMD20

FBA_CMD24

FBA_CMD18
FBA_CMD9

FBA_CMD29
FBA_CMD8

FBA_CMD27

FBA_CMD15

FBA_CMD11

FBA_CMD16

FBA_CMD28
FBA_CMD3

FBA_CMD17
FBA_CMD5
FBA_CMD4

FBA_CMD21
FBA_CMD6

FBA_CMD13

FBA_CMD19

FBA_CMD12

FBA_CMD30

N/A

GT21X GF108

RFU
RFU

FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8

FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27

GF108

FBA_CMD0

FBA_CMD1

FBA_CMD2

FBA_CMD3

FBA_CMD4

FBA_CMD5

FBA_CMD6

FBA_CMD7

FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

FBA_CLK0
FBA_CLK0*

FBA_CLK1
FBA_CLK1*

FBA_DEBUG0_CAS2

FBA_DEBUG1

FB_DLLAVDD_1
FB_PLLAVDD_1

FB_DLLAVDD_2
FB_PLLAVDD_2

0.1UF_16V_2

AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27
AJ28
B18
E21
G17
G18
G22
G8
G9
H29
J14
J15
J16
J17
J20
J21
J22
J23
J24
J29

FBA_CMD<25>

U30
V30
U31

FBA_CMD<2>

V32

FBA_CMD<0>

T35

FBA_CMD<10>

U33

FBA_CMD<26>

W32

FBA_CMD<14>

W33

FBA_CMD<7>

W31

FBA_CMD<1>

W34

FBA_CMD<22>

U34

FBA_CMD<20>

U35

FBA_CMD<24>

U32

FBA_CMD<18>

T34

FBA_CMD<9>

T33

FBA_CMD<29>

W30

FBA_CMD<8>

AB30

FBA_CMD<27>
AA30
AB31

FBA_CMD<11>
AA32

FBA_CMD<16>
AB33

FBA_CMD<28>
Y32

FBA_CMD<3>

Y33

FBA_CMD<17>

AB34

FBA_CMD<5>
AB35

FBA_CMD<4>
Y35

FBA_CMD<21>
W35

FBA_CMD<6>
Y34

FBA_CMD<13>
Y31

FBA_CMD<19>
Y30

FBA_CMD<12>

FBA_CMD<30>

W29
Y29

T32
T31
AC31
AC30

+GPU_V1.5S_FBA_DEBUG

T30
T29

AG27
AF27

J19
J18

C5038

R5016

1

2

C5067

0.1UF_16V_2

1

2

1

C5084

0.1UF_16V_2

2

OUT
OUT
OUT
OUT

1

0.1UF_16V_2

2

1

1

1

2

C5080

0.1UF_16V_2

1

C5062

0.1UF_16V_2

2

C5081

2

OUT

25

2

0
10
26
14

7

1
22
20
24
18

9
29

8
27

11
16
28

3
17

5

4
21

6
13
19
12
30

FBA_CLK0_DP
FBA_CLK0_DN
FBA_CLK1_DP
FBA_CLK1_DN

2

10K_5%_2

+GPU_V1.05S_FB_DLLAVDD0

1

C5075

2

1

C5066

0.1UF_16V_2
1UF_6.3V_2

2

7 6 5 4 3

GT21X

FBB_CMD25

FBB_CMD23
FBB_CMD2
FBB_CMD0

FBB_CMD10

FBB_CMD26

FBB_CMD14
FBB_CMD7
FBB_CMD1

FBB_CMD22

FBB_CMD20

FBB_CMD24

FBB_CMD18
FBB_CMD9

FBB_CMD29
FBB_CMD8

FBB_CMD27

FBB_CMD15

FBB_CMD11

FBB_CMD16

FBB_CMD28
FBB_CMD3

FBB_CMD17
FBB_CMD5
FBB_CMD4

FBB_CMD21
FBB_CMD6

FBB_CMD13

FBB_CMD19

FBB_CMD12

FBB_CMD30

N/A

NVIDIA_N12P_GS_BGA_973P

CHANGE by

FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38

GF108

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8

FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31

FBB_CLK0
FBB_CLK0*

FBB_CLK1
FBB_CLK1*

FBB_DEBUG0_CAS2

FBB_DEBUG1

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

Frank Hu

N27
P27
R27
T27
U27
U29
V27
V29
V34
W27
Y27

1

2

0.1UF_16V_2

F18

FBC_CMD<25>
E19
D18

FBC_CMD<2>
C17

FBC_CMD<0>
F19

FBC_CMD<10>

C19

FBC_CMD<26>

B17

FBC_CMD<14>

E20

FBC_CMD<7>

B19

FBC_CMD<1>

D20

FBC_CMD<22>

A19

FBC_CMD<20>

D19

FBC_CMD<24>
FBC_CMD<18>

C20
F20

FBC_CMD<9>

B20

FBC_CMD<29>

G21

FBC_CMD<8>

F22

FBC_CMD<27>
F24
F23

FBC_CMD<11>

C25

FBC_CMD<16>

C23

FBC_CMD<28>

F21

FBC_CMD<3>

E22

FBC_CMD<17>

D21

FBC_CMD<5>

A23

FBC_CMD<4>

D22

FBC_CMD<21>

B23

FBC_CMD<6>

C22

FBC_CMD<13>

B22

FBC_CMD<19>

A22

FBC_CMD<12>

A20

FBC_CMD<30>

G20

E17

OUT

D17

OUT

D23

OUT

E23

OUT

+GPU_V1.5S_FBC_DEBUG

G19
G16

K27
L27
M27

1

R5077

+GPU_V1.5S_FBCAL_PD_VDDQ

1

R5040

60.4_1%_2

2

DATE

1

C5078

0.1UF_16V_2

2

1

C5056

C5057

0.1UF_16V_2

2

FBC_CMD<30..0>

OUT

25

2

0
10
26
14

7

1
2260
20
24
18

9

29

8

27
11

16
28

3

17

5
4

21

6
13
19
12
30

FBC_CLK0_DP
FBC_CLK0_DN
FBC_CLK1_DP
FBC_CLK1_DN

2

10K_5%_2

10mil

1

R5039

40.2_1%_2

2

Fri Dec 31 10:16:50 2010

2

1

C5079

0.1UF_16V_2

2

1

C5072

2

0.1UF_16V_2

75<>

75<

R5038

1

40.2_1%_2

P1V5_GPUS

1

1

C5070

C5071

4.7UF_6.3V_3

4.7UF_6.3V_3

2

2

1

C5073

1UF_6.3V_2

2

75< 76<

76<>

75<
76<
76<

P1V5_GPUS

P1V5_GPUS

2

INVENTEC

TITLE

EVEREST
GPU-2

SIZE

CODE

C

ES

CS_1310AXXXXXX-MTR

SHEET

1

R5037

60.4_1%_2

2

DOC.NUMBER

1

FF

E

D

C

B

A

REV

A01

of

9769

8 7

6 5

4 3

2

1

U5000

AA2

AA5

AC9

AD2

AD5

AG2

AG5
AK2

AK5

AL6
AL9
AN2

AP3

AP6
AP9
B12
B15
B21
B24
B27

B3
B30
B33

B6

B9

C2
C34
E12

15/16 GND
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_081
GND_082
GND_083
GND_084
GND_085
GND_086
GND_087
GND_088
GND_089
GND_090
GND_091
GND_092
GND_093
GND_094
GND_095

GND_096
GND_097
GND_098
GND_099
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191

E15
E18
E24
E27
E30
E6
E9
F2
F31
F34
F5
J2
J31
J34
J5
L9
M11
M13
M15
M17
M19
M2
M21
M23
M25
M31
M34
M5
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24
R2
R31
R34
R5
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
V12
V14
V16
V18
V2
V20
V22
V24
V31
V5
V9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25

PVCORE_GPU

7 6

U5000

L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19

16/16 NVVDD
VDD_001
VDD_002
VDD_003
VDD_004
VDD_005
VDD_006
VDD_007
VDD_008
VDD_009
VDD_010
VDD_011
VDD_012
VDD_013
VDD_014
VDD_015
VDD_016
VDD_017
VDD_018
VDD_019
VDD_020
VDD_021
VDD_022
VDD_023
VDD_024
VDD_025
VDD_026
VDD_027
VDD_028
VDD_029
VDD_030
VDD_031
VDD_032
VDD_033
VDD_034
VDD_035
VDD_036
VDD_037
VDD_038
VDD_039
VDD_040
VDD_041
VDD_042
VDD_043
VDD_044
VDD_045
VDD_046
VDD_047
VDD_048
VDD_049
VDD_050
VDD_051
VDD_052
VDD_053
VDD_054
VDD_055
VDD_056

VDD_057
VDD_058
VDD_059
VDD_060
VDD_061
VDD_062
VDD_063
VDD_064
VDD_065
VDD_066
VDD_067
VDD_068
VDD_069
VDD_070
VDD_071
VDD_072
VDD_073
VDD_074
VDD_075
VDD_076
VDD_077
VDD_078
VDD_079
VDD_080
VDD_081
VDD_082
VDD_083
VDD_084
VDD_085
VDD_086
VDD_087
VDD_088
VDD_089
VDD_090
VDD_091
VDD_092
VDD_093
VDD_094
VDD_095
VDD_096
VDD_097
VDD_098
VDD_099
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110
VDD_111

AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
AD24

NVIDIA_N12P_GS_BGA_973P

P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24

PVCORE_GPU

PVCORE_GPU

1

C5131

4700PF_50V_2

2

1

C5120

0.015UF_10V_2

2

1

C5119

0.047UF_16V_2

2

1

C5114

4.7uF_6.3V_3

2

5 4

1

C5130

0.01UF_50V_2

2

1

C5121

0.015UF_10V_2

2

1

C5118

0.047UF_16V_2

2

1

C5113

10uF_6.3V_3

2

1

C5129

0.01UF_50V_2

2

1

C5122

0.022uF_16V_2

2

1

C5117

1uF_6.3V_2

2

1

C5112

10uF_6.3V_3

2

D

1

C5128

0.01UF_50V_2

2

1

C5123

0.022uF_16V_2

2

1

C5116

0.1UF_16V_2

2

1

C5055

22UF_6.3V_5

1

C5127

0.01UF_50V_2

2

1

C5115

0.1UF_16V_2

2

1

C5124

0.022uF_16V_2

2

1

C5126

6800PF_25V_2

2

1

C5054

0.22UF_6.3V_2

2

1

C5125

0.047UF_16V_2

2

1

C5053

0.22UF_6.3V_2

2

1

C5052

0.22UF_6.3V_2

2

CC

2

BB

AA

INVENTEC

TITLE

EVEREST-M
GPU-3

CODE

SIZE

CS

CHANGE by

Frank Hu

3

Fri Dec 31 10:17:04 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

70

of

1

REV

97

A01

AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19

AA20
AA21
AA22

D

AA23
AA24
AA25
AA34

AB12
AB14
AB16
AB18
AB20
AB22
AB24

AD11
AD13
AD15
AD17

AD21
AD23
AD25
AD31
AD34

AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25

AG31
AG34

AK31
AK34

AL12
AL15
AL18
AL21
AL24
AL27
AL30

AN34
AP12
AP15
AP18
AP21
AP24
AP27

AP30
AP33

NVIDIA_N12P_GS_BGA_973P

8

D

4.7uF_6.3V_3

10K_5%_2

R5029

4.7uF_6.3V_3

P3V3_GPUS

1

C5096

2

1

1

R5069

1K_1%_2_DY

2

2

1

R5028

10K_5%_2

2

8 7

P1V05_GPUS

20mil

L5001

2

+GPU_V1.05S_IFPAB_PLLVDD

1

C5091

1

1

MMZ1608S181AT

C5092

2

L5005

1

MMZ1608S181AT

U5000

9/16 IFPEF

AJ6

IFPEF_PLLVDD

AL1

IFPEF_RSET

AE7

IFPE_IOVDD

AD7

IFPF_IOVDD

IFPEF

4.7uF_6.3V_3

+GPU_V3S_IFPA_IOVDD

2

1

C5095

4.7uF_6.3V_3

2

NVIDIA_N12P_GS_BGA_973P

20mil

DVI-DL

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

HPDE

TXD3
TXD3

TXD4
TXD4

TXD5
TXD5

2

1

C5097

1uF_6.3V_2

2

8

AK9

C5093

1

1

C5094

0.1UF_16V_21uF_6.3V_2

2

1K_1%_2

2

R5072

AJ11

1

2

AG9

DVI-SL
HDMI

SCL

TXC
TXC

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

HPDE

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

HPDF

1

C5098

0.1UF_16V_2

2

DP

IFPE_AUX*

IFPF_AUX*

IFPE_AUX

IFPE_L3*

IFPE_L3

IFPE_L2*

IFPE_L2

IFPE_L1*

IFPE_L1

IFPE_L0*

IFPE_L0

GPIO15

IFPF_AUX

IFPF_L3*

IFPF_L3

IFPF_L2*

IFPF_L2

IFPF_L1*

IFPF_L1

IFPF_L0*

IFPF_L0

GPIO21

1

AG10

C5099

0.1UF_16V_2

2

AD4
AE4

AE5
AE6

AF5
AF4

AG4
AH4

AH5
AH6

L1

AF2
AF3

AH3
AH2

AH1
AJ1

AJ2
AJ3

AL3
AL2

K6

4.7uF_6.3V_3

7 6

6 5

U5000

7/16 IFPAB

DVI-DL

IFPAB_TXD0*
IFPAB_TXD0

IFPAB_TXD1*
IFPAB_TXD1

IFPAB_PLLVDD

IFPAB_RSET

IFPA_IOVDD

IFPB_IOVDD

IFPAB_TXD2*
IFPAB_TXD2

IFPAB_TXC*
IFPAB_TXC

IFPAB_TXD3*
IFPAB_TXD3

IFPAB_TXD4*
IFPAB_TXD4

IFPAB_TXD5*
IFPAB_TXD5

HPDAB

IFPAB

NVIDIA_N12P_GS_BGA_973P

P3V3_GPUS

FBM_10_160808_301A05T_500mA

1

C5106

4.7uF_6.3V_3

2

P3V3_GPUS

L5003

2

C5100

FBM_10_160808_301A05T_500mA

1

1

2

LVDS

IFPA_TXD0*

IFPA_TXD0

IFPA_TXD1*

IFPA_TXD1

IFPA_TXD2*

IFPA_TXD2

IFPA_TXD3*

IFPA_TXD3

IFPA_TXC*

IFPA_TXC

IFPB_TXD4*

IFPB_TXD4

IFPB_TXD5*

IFPB_TXD5

IFPB_TXD6*

IFPB_TXD6

IFPB_TXD7*

IFPB_TXD7

IFPB_TXC*

IFPB_TXC

GPIO0

AL8
AM8

AM9
AM10

AL10
AK10

AL11
AK11

AM12
AM11

AP8
AN8

AN10
AP10

AR10
AR11

AP11
AN11

AN13
AP13

K1

GPU_LVDS1_TXDL0_DN

OUT

GPU_LVDS1_TXDL0_DP

OUT

GPU_LVDS1_TXDL1_DN

OUT

GPU_LVDS1_TXDL1_DP

OUT

GPU_LVDS1_TXDL2_DN

OUT

GPU_LVDS1_TXDL2_DP

OUT

GPU_LVDS1_TXCL_DN

OUT

GPU_LVDS1_TXCL_DP

OUT

GPU_LVDS2_TXDL0_DN

OUT

GPU_LVDS2_TXDL0_DP

OUT

GPU_LVDS2_TXDL1_DN

OUT

GPU_LVDS2_TXDL1_DP

OUT

GPU_LVDS2_TXDL2_DN

OUT
OUT

GPU_LVDS2_TXDL2_DP

GPU_LVDS2_TXCL_DN

OUT

GPU_LVDS2_TXCL_DP

OUT

R5024

1

2

10K_5%_2_DY

IFPCD_PLLVDD

L5008

1

2

1

4.7UF_6.3V_3

2

P1V05_GPUS

1

C5110C5111

0.1UF_16V_2

2

L5004

1

BLM15AG221SN1D_300mA

1

C5105

2

4.7uF_6.3V_3

IFPCD_IOVDD

2

+GPU_V3S_DACA_VDD

1

C5101

4.7uF_6.3V_3

2

1

C5102

2

1

C5041

0.1UF_16V_2_DY

2

1

C5040

2

0.1UF_16V_2_DY1uF_6.3V_2

5 4

4 3

20mil

1

2

0.1UF_16V_2_DY

C5050

1

C5049

0.1UF_16V_2_DY

2

1

C5048

1UF_6.3V_2_DY

2

20mil

1

C5107
1uF_6.3V_2

2

1

C5103

0.1UF_16V_2

2

20mil

1

C5051

0.1UF_16V_2

2

1

C5108

2

0.1UF_16V_2

1

C5104

0.1UF_6.3V_1

2

R5068

124_1%_2

1

C5109

2

0.1UF_16V_2

AJ12
AK12
AK13

1

2

NVIDIA_N12P_GS_BGA_973P

1

2

U5000

4/16 DACA

DACA_VDD

DACA_VREF

DACA_RSET

3

AJ9
AK7

R5071

1K_1%_2

AJ8

R5035

10K_5%_2

10K_5%_2

R5064

1

10K_5%_2

U5000

8/16 IFPC

IFPC_PLLVDD

IFPC_RSET

IFPC_IOVDD

DVI/HDMI

IFPC

NVIDIA_N12P_GS_BGA_973P

I2CA_SCL
I2CA_SDA

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_GREEN

DACA_BLUE

CHANGE by

G1
G4

AM13
AL13

AM15
AM14
AL14

R5067

150_1%_2

Frank Hu

2

AC6
AB6

2

1

R5070

1K_1%_2_DY

1

R5034

2

2

1

U5000

2

AK6
AH7

DACB_VDD

DACB_VREF

DACB_RSET

6/16 DACB

AG7

NVIDIA_N12P_GS_BGA_973P

DP

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

1

2

1

R5066

2

DATE

IFPC_AUX*

IFPC_AUX

IFPC_L3*

IFPC_L3

IFPC_L2*

IFPC_L2

IFPC_L1*

IFPC_L1

IFPC_L0*

IFPC_L0

HPDC

GPU_CRT_HSYNC

OUT
OUT

GPU_CRT_VSYNC

1

R5065

150_1%_2150_1%_2

2

Tue Jan 04 00:15:45 2011

2

U5000

5/16 IFPD

IFPD_PLLVDD

IFPD_RSET

IFPD_IOVDD

IFPD

I2CB_SCL
I2CB_SDA

DACB_HSYNC
DACB_VSYNC

DACB_RED

DACB_GREEN

DACB_BLUE

GPIO1

OUT

GPU_CRT_R

OUT

GPU_CRT_G

OUT

GPU_CRT_B

DVI/HDMI

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

HPDD

NVIDIA_N12P_GS_BGA_973P

P3V3_GPUS

1

1

R5022

R5023

2.2K_1%_2

G3
G2

AM1
AM2

2

2.2K_1%_2

2

AK4
AL4
AJ4

AN3
AP2

AR2

OUT

AP1
AM4

AM3
AM5

AL5
AM6

AM7

K2

GPU_HDMI_TXC_DN

OUT

GPU_HDMI_TXC_DP

OUT

GPU_HDMI_TX0_DN

OUT

GPU_HDMI_TX0_DP

OUT

GPU_HDMI_TX1_DN

OUT

GPU_HDMI_TX1_DP

OUT

GPU_HDMI_TX2_DN

OUT

GPU_HDMI_TX2_DP

IN

GPU_HDMI_HPDET

45<

45<

45<

INVENTEC

TITLE

EVEREST-M

GPU-4

SIZE

C

CODE

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

71

of

1

DP

IFPD_AUX*

IFPD_AUX

IFPD_L3*

IFPD_L3

IFPD_L2*

IFPD_L2

IFPD_L1*

IFPD_L1

IFPD_L0*

IFPD_L0

GPIO19

1

AN4
AP4

AR4
AR5

AP5
AN5

AN7
AP7

AR7
AR8AK8

D

L7

CC

BB

AA

REV

97

A01

8 7

6 5

4 3

2

1

P3V3_GPUS

1

2

1

2

1

R5004

10K_5%_2_DY

2

1

R5009

24.9K_1%_2

2

ROM_SI

ROM_SO

72>

ROM_SCLK

R5012

10K_5%_2_DY

72>

IN

72>

IN
IN

R5013

15K_1%_2

1

R5011

10K_5%_2_DY

2

1

R5014

10K_1%_2

2

1

15K_1%_2

2

1

10K_5%_2_DY

2

1

R5010

2

1

R5015

2

1

R5006

45.3K_1%_2

72<

STRAP0

72<

STRAP1

72<

D

STRAP2

IN
IN

IN

2

1

R5007

10K_5%_2_DY

10K_5%_2_DY

2

R5005

34.8K_1%_2

R5008

24.9K_1% FOR NVIDIA_N12P_GS_BGA_973P

P3V3_GPUS

P3V3_GPUS

20mil

1

C5087

0.1UF_16V_2

2

U5000

10/16 MIOA

P9

MIOA_VDDQ_NC_1

R9

MIOA_VDDQ_NC_2

T9

MIOA_VDDQ_NC_3

U9

MIOA_VDDQ_NC_4

U5

MIOA_CAL_PD_VDDQ_NC

T5

MIOA_CAL_PU_GND_NC

N5

MIOA_VREF_NC

MIOA_D0_NC
MIOA_D1_NC
MIOA_D2_NC
MIOA_D3_NC
MIOA_D4_NC
MIOA_D5_NC
MIOA_D6_NC
MIOA_D7_NC
MIOA_D8_NC

MIOA_D9_NC
MIOA_D10_NC
MIOA_D11_NC
MIOA_D12_NC
MIOA_D13_NC
MIOA_D14_NC

P3V3_GPUS

N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6

20mil

1

C5086

0.1UF_16V_2

2

AA9
AB9

AA7
AA6

AF1

W9
Y9

U5000

11/16 MIOB
MIOB_VDDQ_NC_1
MIOB_VDDQ_NC_2
MIOB_VDDQ_NC_3
MIOB_VDDQ_NC_4

MIOB_CAL_PD_VDDQ_NC

MIOB_CAL_PU_GND_NC

MIOB_VREF_NC

MIOB_D0_NC
MIOB_D1_NC
MIOB_D2_NC
MIOB_D3_NC
MIOB_D4_NC
MIOB_D5_NC
MIOB_D6_NC
MIOB_D7_NC
MIOB_D8_NC

MIOB_D9_NC
MIOB_D10_NC
MIOB_D11_NC
MIOB_D12_NC
MIOB_D13_NC
MIOB_D14_NC

Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6

D

72>

THRM_GPU_DP

72>

THRM_GPU_DN

THRM_SHUTDWN#

72<

THRM_GPU_DN

72<

THRM_GPU_DP

P3V3_GPUS

R5032

10K_5%_2 10K_5%_2

R5030

1

2

0_5%_2_DY

10K_5%_2

PUT TOGETHER

8

IN
IN

OUT

1

2

R5033

0.1UF_16V_2_DY

2200PF_50V_2_DY

OUT

OUT

1

R5031

2

1

1

R5043

10K_5%_2

2

2

C5089

1

AP14
AR14
AN14
AN16
AP16

P3V3_GPUS

1

C5090

2

2

U5000

12/16 MISC1

B4

THERMDN

B5

THERMDP

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST*

NVIDIA_N12P_GS_BGA_973P

1
2
3 6
4

GMT_G784_MSOP_8P__DY

7 6

U4412

VCC
DXP
DXN
THERM#

SMBCLK

SMBDATA

ALERT#

I2CS_SCL
I2CS_SDA

I2CC_SCL
I2CC_SDA

GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO16
GPIO17
GPIO18

GPIO20

GPIO22
GPIO23
GPIO24

GND

8
7

5

R5056

0_5%_2

E2
E1

E3
E4

10K_5%_2

K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6

L2
L4
M4

L5
L6

M6
M7

1

2

R5046

ALERT#

3

Q5000

DS

SSM3K7002BFU

2

R5054
R5053

1

R5055

0_5%_2

2

1

2

G

1
1

P3V3_GPUS

2.2K_1%_2

1

R5025

10K_5%_2

2

R5059

P3V3_GPUS

R5042

1

10K_5%_2

R5049

1

100K_5%_2

1

BI

2

0_5%_2

2

0_5%_2

1

1

R5001

R5020

2.2K_1%_2

2

2

1

R5045
10K_5%_2

2

1

2

2

DCIN_BLED#

R5018

R5019

2

R5021

BI
BI

2

1

1

2

P3V3_GPUS

1

R5044

10K_5%_2

2

R5060

1

0_5%_2_DY

R5052

10K_5%_2

1

37<>

EC_SMB2_CLK
EC_SMB2_DATA

0_5%_2

0_5%_2

2

2

0_5%_2_DY

58<37>

0_5%_2

1

2

BI
BI

1

R5051

10K_5%_2

2

8>

37<>

8>

GPU_LVDS_DDCCLK
GPU_LVDS_DDCDATA

1

R5050

10K_5%_2

2

5 4

OUT

GPU_LCM_INVPWM

OUT

GPU_LCM_VDDEN

OUT

GPU_LCM_BKLTEN

OUT

GPU_VID0

OUT

GPU_VID1

OUT

THRM_SHUTDWN#

P3V3_GPUS

R5062
R5061

NVIDIA_N12P_GS_BGA_973P

16<

R5063

1

2

10K_5%_2

2

40.2K_1%_2

1

40.2K_1%_2

2

1

MIOA_CTL3_NC
MIOA_HSYNC_NC
MIOA_VSYNC_NC

MIOA_DE_NC

MIOA_CLKOUT_NC

MIOA_CLKOUT_NC*

MIOA_CLKIN_NC

P5
N3
L3
N2

R4
T4
N4

U5000

13/16 MISC2

J26

BBIASN_NC

J25

BBIASP_NC

ROM_SCLK

I2CH_SCL

I2CH_SDA

AB5

CEC

SPDIF_NC

N9

MULTI_STRAP_REF0_GND

M9

MULTI_STRAP_REF1_GND

PGOOD_OUT*

NVIDIA_N12P_GS_BGA_973P

CHANGE by

Frank Hu

3

R5048

1

10K_5%_2

ROM_CS*

ROM_SI
ROM_SO

STRAP0
STRAP1
STRAP2

BUFRST*

GND_F
GND_H

2

C3
D3

OUT

C4

OUT

D4

OUT

W5
W7
V7

IN
IN
IN

STRAP0
STRAP1
STRAP2

F6
G6

A5
A4

C5

AK14
K9

R5036

1

36K_5%_2

Fri Dec 31 10:16:52 2010

DATE

2

MIOB_CTL3_NC
MIOB_HSYNC_NC
MIOB_VSYNC_NC

MIOB_DE_NC

MIOB_CLKOUT_NC

MIOB_CLKOUT_NC*

MIOB_CLKIN_NC

NVIDIA_N12P_GS_BGA_973P

ROM_SI
ROM_SO
ROM_SCLK

72<

72<

72<

72<

72<

R5058

72<

2.2K_1%_2

1

2

2

INVENTEC

TITLE

EVEREST-M

GPU-5

CODE

SIZE

CS

C

SHEET

W3
W1
W2
Y5

V4
W4

1

AE1

P3V3_GPUS

1

R5057

2.2K_1%_2

2

CS_1310AXXXXXX-MTR

72

1

2

DOC.NUMBER

of

1

R5047

10K_5%_2

C5088

0.1uF_16V_2

97

2

CC

BB

AA

REV

A01

8 7

6 5

4 3

2

1

U5501

FBA_D<21>

H1

73<

FBA_VREF0

FBA_CMD<30..0>

U5500

H1

73<

FBA_VREF0

FBA_CMD<30..0>

D

69<>

FBA_DQS_DP<3>

69<>

FBA_DQS_DP<0>

69<>
69<>

73<

74<>

73<>

74<

BI

7
20
4
14
17
6
26
3
1
10
21
5
22
18
29
30

12
9
13

0
25

2
24
8
19

FBA_DQM<3>
FBA_DQM<0>

FBA_DQS_DN<3>
FBA_DQS_DN<0>

69>

FBA_CMD<28>

FBA_CMD<7>
FBA_CMD<20>

FBA_CMD<4>
FBA_CMD<14>

FBA_CMD<17>
FBA_CMD<6>
FBA_CMD<26>
FBA_CMD<3>
FBA_CMD<1>

FBA_CMD<10>

FBA_CMD<21>
FBA_CMD<5>
FBA_CMD<22>
FBA_CMD<18>

FBA_CMD<29>
FBA_CMD<30>

FBA_CMD<12>
FBA_CMD<9>
FBA_CMD<13>

FBA_CMD<0>

FBA_CMD<25>
FBA_CMD<2>
FBA_CMD<24>
FBA_CMD<8>
FBA_CMD<19>

BI

BI
BI

BI

BI
BI

IN

10K_5%_2

73< 69>

R5527

IN

FBA_CLK0_DP
FBA_CLK0_DN

1

2

243_1%_2

R5528

IN
IN

1

2

M8

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M2
N8
M3

J7
K7
K9

K1
L2
J3
K3
L3

F3
C7

E7
D3

G3
B7

T2
L8

J1
L1
J9
L9

VREFDQ
VREFCA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12_BC#
A13
A14
A15

BA0
BA1
BA2

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#

ZQ

NC#J1
NC#L1
NC#J9
NC#L9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

E3
F7

FBA_D<27>

F2

FBA_D<24>

F8

FBA_D<30>

H3

FBA_D<28>

H8

FBA_D<31>

G2

FBA_D<25>

H7

FBA_D<29>

D7

FBA_D<6>

C3

FBA_D<3>

C8

FBA_D<7>

C2

FBA_D<0>

A7

FBA_D<4>

A2

FBA_D<2>

B8

FBA_D<5>

A3

FBA_D<1>

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

26
27
24
30
28
31
25
29

6
3
7
0
4
2
5
1

FBA_D<26>

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

FBA_D<24..31>

BI

BI

FBA_D<0..7>

P1V5_GPUS

1.5A

P1V5_GPUS

73< 69>

FBA_CLK0_DP

69>73<

FBA_CLK0_DN

73<>74<>

74<> 73<>

69<>

69<>

74<

73<

69>

FBA_CMD<25>

69>

FBA_CMD<27>

69<>
69<>

73<>74<>

BI

7
20

69<>

69<>

FBA_DQS_DP<2>
FBA_DQS_DP<1>

FBA_DQM<2>
FBA_DQM<1>

4

14

17
6
26
3

1

10
21
5
22

18
29
30

12
9

13

0
25

2
24
8

19

FBA_DQS_DN<2>
FBA_DQS_DN<1>

69>

FBA_CMD<28>

IN

IN

IN

IN

FBA_CMD<7>
FBA_CMD<20>

FBA_CMD<4>
FBA_CMD<14>
FBA_CMD<17>
FBA_CMD<6>
FBA_CMD<26>
FBA_CMD<3>
FBA_CMD<1>
FBA_CMD<10>
FBA_CMD<21>
FBA_CMD<5>
FBA_CMD<22>
FBA_CMD<18>
FBA_CMD<29>
FBA_CMD<30>

FBA_CMD<12>
FBA_CMD<9>
FBA_CMD<13>

73<

FBA_CMD<0>
FBA_CMD<25>

FBA_CMD<2>
FBA_CMD<24>
FBA_CMD<8>
FBA_CMD<19>

BI

BI
BI

BI

BI
BI

IN

1

R5524

160_1%_2

2

R5525

1

10K_5%_2

R5526

1

10K_5%_2

69>

FBA_CLK0_DP
FBA_CLK0_DN

2

2

IN

R5529

243_1%_2

IN
IN

1

2

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

M8

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M2
N8
M3

J7
K7
K9

K1
L2
J3
K3
L3

F3
C7

E7
D3

G3
B7

T2
L8

J1
L1
J9
L9

VREFDQ
VREFCA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12_BC#
A13
A14
A15

BA0
BA1
BA2

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#

ZQ

NC#J1
NC#L1
NC#J9
NC#L9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

E3
F7

FBA_D<16>

F2

FBA_D<23>

F8

FBA_D<18>

H3

FBA_D<22>

H8

FBA_D<17>

G2

FBA_D<20>

H7

FBA_D<19>

D7

FBA_D<14>

C3

FBA_D<11>

C8

FBA_D<15>

C2

FBA_D<10>

A7

FBA_D<12>

A2

FBA_D<8>

B8

FBA_D<13>

A3

FBA_D<9>

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

21

16

23

18

22

17

20

19

14
11
15
10
12

8

13

9

FBA_D<16..23>

BI

BI

FBA_D<8..15>

P1V5_GPUS

1.5A

P1V5_GPUS

69<>

69<>

D

CC

BB

C5559

0.1UF_16V_2

P1V5_GPUS

1
2

0.1UF_16V_2

8

C5558

1
2

C5557

0.1UF_16V_2

FBA_VREF0

1
2

0.1UF_16V_2

C5555

1

2

0.1UF_16V_2

C5556

P1V5_GPUS

1

R5505

IN

R5504

1.1K_1%_2

1.1K_1%_2

1

2

0.01UF_50V_2

C5501

2
1

2

7 6

1
2

1uF_6.3V_2

C5554

1
2

1uF_6.3V_2

P1V5_GPUS

C5553

1

2

C5552

0.1UF_16V_2

5 4

1

0.1UF_16V_2

2

C5551

1

0.1UF_16V_2

2

74<

FBA_VREF1

C5550

1

2

0.1UF_16V_2

IN

R5500

1.1K_1%_2

C5549

1

0.01UF_50V_2

2

3

1

2

0.1UF_16V_2

P1V5_GPUS

R5501

1.1K_1%_2
C5503

CHANGE by

C5548

1

2

1

2

Frank Hu

1

1uF_6.3V_2

2

DATE

C5547

1

1uF_6.3V_2

2

Fri Dec 31 10:16:52 2010

2

C5546

1

2

INVENTEC

TITLE

EVEREST-M

VRAM

SIZE

C

CODE

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

73

AA

REV

97

of

A01

1

8 7

6 5

4 3

2

1

D

FBA_CMD<30..0>

69<>

69<>

69<>
69<>

74<> 73<>

74<

73<

BI

22
4
20
9
6

17
3
26

1
5

19

10
7
29

18

13

12

14
30

27

16

11
24
8
21

FBA_DQS_DP<5>
FBA_DQS_DP<7>

FBA_DQM<5>

FBA_DQM<7>

FBA_DQS_DN<5>
FBA_DQS_DN<7>

69>74< 73<

FBA_CMD<28>

FBA_VREF1

FBA_CMD<22>
FBA_CMD<4>
FBA_CMD<20>
FBA_CMD<9>
FBA_CMD<6>
FBA_CMD<17>
FBA_CMD<3>
FBA_CMD<26>
FBA_CMD<1>
FBA_CMD<5>
FBA_CMD<19>
FBA_CMD<10>
FBA_CMD<7>
FBA_CMD<29>
FBA_CMD<18>
FBA_CMD<13>

FBA_CMD<12>
FBA_CMD<14>
FBA_CMD<30>

FBA_CMD<27>
FBA_CMD<16>

FBA_CMD<11>
FBA_CMD<24>
FBA_CMD<8>
FBA_CMD<21>

BI

BI
BI

BI

BI
BI

IN

69>74<

FBA_CLK1_DP

69>74<

FBA_CLK1_DN

IN

R5522

243_1%_2

U5503

E3

H1

74< 73<

FBA_CMD<30..0>

U5502

H1

VREFDQ

M8

VREFCA

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10_AP

R7

A11

N7

A12_BC#

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7
K7
K9

K1
L2
J3
K3
L3

F3
C7

E7
D3

G3
B7

T2
L8

J1
L1
J9
L9

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#

ZQ

NC#J1
NC#L1
NC#J9
NC#L9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

IN
IN

1

2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

E3

FBA_D<44>

F7

FBA_D<43>

F2

FBA_D<46>

F8

FBA_D<45>

H3

FBA_D<41>

H8

FBA_D<42>

G2

FBA_D<47>

H7

FBA_D<40>

D7

FBA_D<58>

C3

FBA_D<59>

C8

FBA_D<56>

C2

FBA_D<62>

A7

FBA_D<57>

A2

FBA_D<60>

B8

FBA_D<61>

A3

FBA_D<63>

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

44
43
46
45
41
42
47
40

58
59
56
62
57
60
61
63

P1V5_GPUS

P1V5_GPUS

74< 69>

74< 69>

74<>

BI

FBA_D<40..47>

BI

FBA_D<56..63>

1.5A

74<

73<

FBA_CLK1_DP

FBA_CLK1_DN

69>

73<>74<>

73<>

69>

69<>
69<>

69<>
69<>

74<>

73<>

FBA_CMD<0>

FBA_CMD<16>

BI

69<>

69<>

FBA_DQS_DP<4>
FBA_DQS_DP<6>

FBA_DQM<4>
FBA_DQM<6>

FBA_DQS_DN<4>
FBA_DQS_DN<6>

69>

FBA_CMD<28>

IN

IN

1

2

IN

IN

FBA_CMD<22>

22

FBA_CMD<4>

4

FBA_CMD<20>

20

FBA_CMD<9>

9

FBA_CMD<6>

6

FBA_CMD<17>

17

FBA_CMD<3>

3

FBA_CMD<26>

26

FBA_CMD<1>

1

FBA_CMD<5>

5

FBA_CMD<19>

19

FBA_CMD<10>

10

FBA_CMD<7>

7

FBA_CMD<29>

29

FBA_CMD<18>

18

FBA_CMD<13>

13

FBA_CMD<12>

12

FBA_CMD<14>

14

FBA_CMD<30>

30

FBA_CMD<27>

27

FBA_CMD<16>

16

FBA_CMD<11>

11

FBA_CMD<24>

24

FBA_CMD<8>

8

FBA_CMD<21>

21

R5519

160_1%_2

R5521

1

10K_5%_2

R5520

1

10K_5%_2

FBA_VREF1

69>74<

BI
BI

BI
BI

BI
BI

IN

2

2

IN

FBA_CLK1_DP

FBA_CLK1_DN

R5523

243_1%_2

IN
IN

1

2

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

M8

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M2
N8
M3

J7
K7
K9

K1
L2
J3
K3
L3

F3
C7

E7
D3

G3
B7

T2
L8

J1
L1
J9
L9

VREFDQ
VREFCA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12_BC#
A13
A14
A15

BA0
BA1
BA2

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#

ZQ

NC#J1
NC#L1
NC#J9
NC#L9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

FBA_D<35>

F7

FBA_D<36>

F2

FBA_D<32>

F8

FBA_D<38>

H3

FBA_D<33>

H8

FBA_D<39>

G2

FBA_D<34>

H7

FBA_D<37>

D7

FBA_D<51>

C3

FBA_D<52>

C8

FBA_D<48>

C2

FBA_D<54>

A7

FBA_D<50>

A2

FBA_D<55>

B8

FBA_D<49>

A3

FBA_D<53>

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

35
36
32
38
33
39
34
37

51
52
48
54
50
55
49
53

FBA_D<32..39>

BI

BI

FBA_D<48..55>

P1V5_GPUS

1.5A

P1V5_GPUS

69<>

69<>

D

CC

BB

C5545

0.1UF_16V_2

8

P1V5_GPUS

1

2

0.1UF_16V_2

C5544

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

1

2

0.1UF_16V_2

C5543

1

2

0.1UF_16V_2

C5542

7 6

1

2

0.1UF_16V_2

C5541

1

2

1uF_6.3V_2

C5540

1

C5539

2

1uF_6.3V_2

P1V5_GPUS

1

2

C5538

0.1UF_16V_2 0.1UF_16V_2

1

5 4

C5537

2

1

0.1UF_16V_2

2

C5536

1

2

0.1UF_16V_2

C5535

1

2

0.1UF_16V_2

C5534

1

1uF_6.3V_2

2

C5533

1

2

1uF_6.3V_2

C5532

1

AA

2

INVENTEC

TITLE

EVEREST-M
VRAM

CODE

SIZE

C

CHANGE by

Frank Hu

3

Fri Dec 31 10:16:53 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

74

of

1

REV

97

A01

8 7

6 5

4 3

2

1

U5505

H1

75<

FBC_VREF0

FBC_CMD<30..0>

U5504

H1

75<

FBC_VREF0

FBC_CMD<30..0>

D

76<>

75<76<

75<>

69>

FBC_CMD<28>

BI

7
20
4
14
17
6
26
3
1
10
21
5
22
18
29
30

12
9
13

0
25

2
24
8
19

FBC_DQS_DP<0>

FBC_DQS(3)

FBC_DQM<0>
FBC_DQM<3>

FBC_DQS_DN<0>
FBC_DQS_DN<3>

IN

FBC_CMD<7>
FBC_CMD<20>
FBC_CMD<4>
FBC_CMD<14>
FBC_CMD<17>
FBC_CMD<6>
FBC_CMD<26>
FBC_CMD<3>
FBC_CMD<1>
FBC_CMD<10>
FBC_CMD<21>
FBC_CMD<5>
FBC_CMD<22>
FBC_CMD<18>
FBC_CMD<29>
FBC_CMD<30>

FBC_CMD<12>
FBC_CMD<9>
FBC_CMD<13>

75< 69>
75< 69>

FBC_CMD<0>
FBC_CMD<25>

FBC_CMD<2>
FBC_CMD<24>
FBC_CMD<8>
FBC_CMD<19>

BI

BI
BI

BI

BI
BI

1

R5515

IN

FBC_CLK0_DP
FBC_CLK0_DN

R5517

IN
IN

1

10K_5%_2 243_1%_2

2

2

M8

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M2
N8
M3

J7
K7
K9

K1
L2
J3
K3
L3

F3
C7

E7
D3

G3
B7

T2
L8

J1
L1
J9
L9

VREFDQ
VREFCA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12_BC#
A13
A14
A15

BA0
BA1
BA2

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#

ZQ

NC#J1
NC#L1
NC#J9
NC#L9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

FBC_D<3>
FBC_D<6>
FBC_D<0>
FBC_D<7>
FBC_D<1>
FBC_D<4>
FBC_D<2>
FBC_D<5>

FBC_D<24>
FBC_D<27>
FBC_D<31>
FBC_D<28>
FBC_D<29>
FBC_D<26>
FBC_D<30>
FBC_D<25>

3
6
0
7
1
4
2
5

24
27
31
28
29
26
30
25

BI

BI

P1V5_GPUS

P1V5_GPUS

69>

FBC_CLK0_DP

75<

69>

75<

FBC_CLK0_DN

76<>

FBC_D<0..7>

FBC_D<24..31>

1.5A

69>

75<>

FBC_CMD<25>

BI

69<>

69<>

FBC_DQS(2)
FBC_DQS(1)

FBC_DQM(2)
FBC_DQM(1)

FBC_DQSN(2)
FBC_DQSN(1)

FBC_CMD<28>

IN

IN

IN

FBC_CMD<7>

7

FBC_CMD<20>

20

FBC_CMD<4>

4

FBC_CMD<14>

14

FBC_CMD<17>

17

FBC_CMD<6>

6

FBC_CMD<26>

26

FBC_CMD<3>

3

FBC_CMD<1>

1

FBC_CMD<10>

10

FBC_CMD<21>

21

FBC_CMD<5>

5

FBC_CMD<22>

22

FBC_CMD<18>

18

FBC_CMD<29>

29

FBC_CMD<30>

30

FBC_CMD<12>

12

FBC_CMD<9>

9

FBC_CMD<13>

13

75<
75<

FBC_CMD<0>

0

FBC_CMD<25>

25

FBC_CMD<2>

2

FBC_CMD<24>

24

FBC_CMD<8>

8

FBC_CMD<19>

19

1

R5514

160_1%_2

2

R5516

1

10K_5%_2

69>
69>

BI

BI
BI

BI

BI
BI

IN

2

FBC_CLK0_DP
FBC_CLK0_DN

IN

R5518

243_1%_2

IN
IN

1

2

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

M8

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M2
N8
M3

J7
K7
K9

K1
L2
J3
K3
L3

F3
C7

E7
D3

G3
B7

T2
L8

J1
L1
J9
L9

VREFDQ
VREFCA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12_BC#
A13
A14
A15

BA0
BA1
BA2

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#

ZQ

NC#J1
NC#L1
NC#J9
NC#L9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

E3

FBC_D<18>

F7

FBC_D<16>

F2

FBC_D<20>

F8

FBC_D<17>

H3

FBC_D<23>

H8

FBC_D<19>

G2

FBC_D<22>

H7

FBC_D<21>

D7

FBC_D<13>

C3

FBC_D<11>

C8

FBC_D<14>

C2

FBC_D<8>

A7

FBC_D<12>

A2

FBC_D<10>

B8

FBC_D<15>

A3

FBC_D<9>

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

18
16

20

17

23

19
22
21

13

11

14

8
12
10
15

9

BI

FBC_D<16..23>

BI

FBC_D<8..15>

P1V5_GPUS

1.5A

P1V5_GPUS

69<>

69<>

D

CC

BB

C5531

0.1UF_16V_2

8

P1V5_GPUS

1

C5530

0.1UF_16V_2 0.1UF_16V_2

2

FBC_VREF0

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

1

C5529

2

1

C5528

2

0.1UF_16V_2 0.1UF_16V_2

IN

R5502

1.1K_1%_2

7 6

1

2

1.1K_1%_2

1

0.01UF_50V_2

2

C5527

P1V5_GPUS

R5503

C5500

1

C5526

1uF_6.3V_2 1uF_6.3V_2

2

1

2

1

2

P1V5_GPUS

1

C5525

2

1

C5524

2

0.1UF_16V_2

1

0.1UF_16V_2

2

C5523

1

0.1UF_16V_2

2

C5522

1

C5521

2

0.1UF_16V_2

1

2

0.1UF_16V_2

C5520

1

C5519

1uF_6.3V_2 1uF_6.3V_2

2

1

2

C5518

1

2

AA

P1V5_GPUS

1

R5506

76<

FBC_VREF1

IN

R5507

1.1K_1%_2

1.1K_1%_2

1

0.01UF_50V_2

2

C5502

2

1

2

INVENTEC

TITLE

EVEREST-M

VRAM

REV

97

A01

5 4

CODE

SIZE

C

CHANGE by

Frank Hu

3

Fri Dec 31 10:16:54 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

75

of

1

78

56

4

23

1

FUSE6000

65W-75W 8A(6036A0003401)

90W 10A(6036A0002901)

120W 12A(6036A0006001)

CN6000

G1

G1

G2

G2

1

1

2

2

3

3

4

4

ACES_91302_0047L_1_4P

1

C6035

2

1000PF_50V_2

FUSE6000

1

8A_125V

2

1

C6033

2

10PF_50V_2

D

R6000

1

4.7K_5%_3

1

20.5K_1%_2

RSC_0603_DY

8
7
6

1

2200pF_50V_2

PVADPTR

1

C6025

CSC0805_DY

2

1

R6002

C C

1

R6003

RSC_1206_DY

2

2

RSC_1206_DY

1

R6012

2

WS

ACPRES#

R6005

Q6003

D

NMOS_4D3S

AM4410NC

C6010

P3V3_AL

OUT

2

2

Q6002

1

S

2
3
45

G

1

S

2
3
4 5

G

NMOS_4D3S

8

D

7
6

AM4410NC

2

C6007

2

1

0.1UF_25V_3

R6023

1

2

1M_5%_3

2

R6006

4.02K_1%_3

1

2

2

R6007

4.02K_1%_3

1

1

D6000

3

2

DIODES_BAV99

R6008

10K_5%_3

1

Active Low

TI_BQ24725RGRR_QFN_20P

HW_I_ADC

B B

1

1

R6013

C6028

2

3.3K_1%_3

2

CSC0603_DY

OUT

EC_SMB2_DATA

EC_SMB2_CLK

C6026

OUT

OUT

10

1

2

1

1

C6008

C6029

2

CSC0402_DY

2

CSC0402_DY

100pF_50V_2

1

C6027

2

CSC0402_DY

P3V3_AL

1

P3V3_AL

2

A A

WS

CHG_EN

IN

Active High

R6021

1

10K_5%_3_DY

1

SSM3K7002FU_DY

Q6004

G

3

DS

2

R6014

2

110K_1%_2

2

R6011

1

1

C6011

2

30.1K_1%_2

L6001

NFE31PT222Z1E9L

1

4

6

ACDET

7

IOUT

8

SDA

9

SCL
ILIM

0.1UF_16V_2

3

R6020

0.01_1%_6

1

1

C6013

2

C6012

2

0.1UF_16V_2

5

3

CMSRC

ACOK

ACDRV

BATDRV

SRP

SRN

13

12

11

214

ACP

GND

2

0.1UF_25V_3

0.1UF_25V_3

ACN

PHASE
HIDRV

LODRV

151814

PVADPTR

2
43

1

C6014

2

1

TML

VCC

BTST
REGN

PVADPTR

U6000

21
20

19
17

16

1

C6017

2

D6001

1

A1

C6015

2

1UF_25V_3

1

1UF_10V_2

R6009

1

10_1%_2

R6010

1

6.98_1%_2

R6016

2

D6002

C

BAT54C_30V_0.2A

3

1

R6015

10_5%_5

2

1

VRCHARGER_HG
VRCHARGER_PH

2

0.047uF_16V_2

3

A1

C

BAT54C_30V_0.2A

VRCHARGER_LG

2

2

1

A2

C6006

A2

PVBAT

1

R6017

2

R6019

HW_V_ADC

OUT

1

1

33K_5%_2_DY

2

C6003

2

0.1uF_16V_2_DY

PVBAT

Q6005

8

D

7

1

+

C6018

68UF_25V

2

2

678

Q6000

AON7410

1

D

NMOS_4D3S

G

S

1

324 5

1

C6002

2

1

C6005

2

470pF_50V_2

1

C6001

2

4.7UF_25V_5

L6000

1

PCMC063T_4R7MN

678

5

2

AON7410

NMOS_4D3S

Q6001

D

G

S

3

214

D6003

1

2

2

R6004

1

2.2_5%_3

1

SBR3U40P1_DY

C6009

2

0.0015uF_50V_2

1

1

PAD6000

POWERPAD_2_0610

2

2

1

C6000

2

4.7UF_25V_5

2

CSC0805_DY

R6001

1

0.01_1%_6

C6022

2

0.1UF_16V_2

1

C6020

2

0.1UF_25V_3

6

NMOS_4D3S

TPCA8065_H

2
43

1

1

C6021

2

0.1UF_25V_3

RSC_0603_DY

2

R6018

1

RSC_0603_DY

PVPACK

1

S

2
3
45

G

1

C6016

2

1

C6019

2

4.7UF_25V_5

C6024

1

0.1uF_25V_3

1

C6023

2

4.7UF_25V_5

2

1

C6004

CSC0805_DY

2

4.7UF_25V_5

4.02K_1%_3

D

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CS

DOC.NUMBER

1310xxxxx-0-0

SHEET

of

9776

1

CODE

SIZE

CHANGE by

8

67

45

XXX

3 2

DATE

21-OCT-2002

C

REV

X01

78

56

4

23

1

PVPACK

FUSE6100

LITTLEFUSE_R451015_15A_65V

1

2

1

D

P5V_AL

C6106

2

2

R6108

360K_1%_2

EZJZ0V500AA

1

2

2

R6100

1

1K_5%_2

D6101

1

1

2

D6106

2

R6109R6110

2

EZJZ0V500AA

1

D6100

1 1

102K_1%_3

EC_SMB1_DATA

EC_SMB1_CLK

BATT_IN

BI

OUT

BI

33_5%_2

1
1

33_5%_2

R6101

R6102

2
2

1

715K_1%_2

2

C C

1000PF_50V_2

2

1

1

2

D6104

2

PHP_PESD5V0S1BB_SOD523_2P

1

1

2

D6103

2

PHP_PESD5V0S1BB_SOD523_2P

PHP_PESD5V0S1BB_SOD523_2P

CN6100

1

BATT+

2

BATT+

3

ID

4

B-I

5

TS

6

SMD

7

SMC

8

GND

9

GND

SYN_200045GR009G15JZR_9P

G
G
G
G

G1
G2
G3
G4

REMOVE ?

D

P3V3_AL

P5V_AL

2

B B

A2

PVRTC

3

D6105

BAT54C_30V_0.2A

CN6101

2

-

LOTES_AAA_BAT_059_P03_2P

1

+

C

+V5AUXON

A1

1

1

OUT

C6107

R6106

1K_5%_2

2

U6100

1

RESET

2

GND
VCCMRVSEN

1

GMT_G686LT11U_SOT23_5P

2

0.1uF_16V_2

P5V_AL

1

R6105

10K_5%_2

2

5
43

PVBAT

1

R6104

510K_1%_2

THRM_SHUTDWN#

IN

2
1

2

D6102

R6103

100K_1%_2

2

1

EZJZ0V120JA_DY

A A

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CS

DOC.NUMBER

1310xxxxx-0-0

SHEET

77 97

of

1

CODE

SIZE

CHANGE by

8

67

45

XXX

3 2

DATE

21-OCT-2002

C

REV

X01

78

56

4

23

1

P5V_AL

P3V3_AL

P15V_A
10K_5%_2

1

R6200

1

R4

CHECK

2

100K_5%_2_DY

R1

D

EC_PW_ON#

+V5AUXON

IN

IN

1

0_5%_2_DY

1

10K_5%_2

CHECK

D1

EC_PW_ON

OUT

3

DIODE-BAT54-TAP-PHP

2

R2

2

1

2

NC

1

R3

2

20K_5%_2_DY

1

SSM3K7002FU

3

Q6203

1

SSM3K7002FU

DS

G

2

2

2

R6201

1

100K_5%_2

WS

1

3

Q1

DS

G

G

3

DS

Q6202

SSM3K7002FU

2

2

120K_1%_2

1

R6210

1

C6218

2

2

0.047uF_16V_2

P3V3_AL

R5

1

0_5%_2

Q6200

8

D

7
6
5

NMOS_4D3S

FDMC8884

2

1

S

2
3
4

G

PAD6205

1

1

POWERPAD_2_0610

2

2

1

C6211

2

2200pF_50V_2

SSM3K7002FU

Q6201

1

P3V3_A

200_5%_2

G

1

R6202

2

32

DS

C C

D

PVBAT

1

1

2

2

PAD6202

POWERPAD_2_0610

PVBAT

1

1

2

2

PAD6203

POWERPAD_2_0610

+V5AUXON

D6201

BAT54C_30V_0.2A

A1

1

IN

A2

2

130K_1%_3

C

3

1

R6209

2

P2V

1

4A

8

7

6

D

Q6204

SS

1

8

D

Q6205

1

54

NMOS_4D3S

G

3

2

6

7

5

G

234

10UF_6.3V_3

AON7410

AON7702L

C6207

+V3LDO

P5V_AL

1

PAD6204

1

2

1

2 2

POWERPAD1X1M

+V5AUXON

C6212

0.1UF_25V_3

2

P5V_A

67

1

V3LA_HG
V3LA_SW
V3LA_LG

1

C6206

2

7
8

9
10
11
12

R6215

RSC_0402_DY

1

R6212

1

10K_5%_2

RSC_0402_DY

1UF_6.3V_2

IN

6

412

5163

25

TML

VO2 VO1
VREG3
VBST2
DRVH2
LL2
DRVL2

2

2

R6204

1

VFB2

ENTRIP2

U6200

SKIPSEL

EN0

13

14

2

1

R6211

TONSEL

VREF

GND

VIN

15

17

1

C6208

2.2uF_25V_5

2

2

VFB1

VREG5

0_5%_3

B B

1

C6205

4.7UF_25V_5

2

C6204

4.7UF_25V_5

1

2

10A

P3V3_AL

PAD6201

1

1

2

POWERPAD_2_0610

1

R6207

6.8K_1%_2

22
1

R6208

A A

10K_1%_2

1

+

C6202

2

330UF_6.3V

8

L6201

22

1

PCMC063T_3R3MN

C6209

2

TRIP1

PGOOD
VBST1
DRVH1

LL1

DRVL1

ENC

TI_TPS51123RGER_QFN_24P

0.22UF_6.3V_2

1

V5A_HG
V5A_SW

V5A_LG

C6213

0.1UF_25V_3

24
23
22
21
20
19

18

AON7410

NMOS_4D3S

2

AON7702L

1

R6213

0_5%_3

2

3.8A

876

54

G

5

G

4

Q6206

D

S

1

2

3

876

Q6207

D

S

1

2

3

1

C6203

2

1

PCMC063T_3R3MN

R6216C6220

1

2

2

4.7UF_25V_5

1

1

C6201

2

L6200

2200pF_50V_24.7_5%_3

45

4.7UF_25V_5

2

CHANGE by

1

C6214

2

4.7UF_25V_5

15.4K_1%_2

1

R6205

1

+

C6200

2

330UF_6.3V

2
1

R6206

10K_1%_2

2

D6202

DIODES_BAV99

2

3
1

C6215

2

0.1uF_16V_2

XXX

3 2

PAD6200

1

1

POWERPAD_2_0610

2

1

1

C6223

2

0.1uF_16V_2

DATE

7A

P5V_A

2

2

D6203

DIODES_BAV99

1

3

C6222

2

21-OCT-2002

C6224

0.1UF_25V_2

P15V_A

1

1

INVENTEC

TITLE

1UF_25V_3

2

SIZE

MODEL,PROJECT,FUNCTION

Block Diagram

CS

DOC.NUMBER

1310xxxxx-0-0

SHEET

CODE

C

of

78 97

1

REV

X01

78

56

4

23

1

PVBAT

1

P5V_A

P0V75_S

3.7A

1

C6300

D

CHECK

R6303

1

10K_1%_2

0_5%_2

1

2

0_5%_2

1

2

2

IN

IN

1

C C

52.3K_1%_2

R6302

2

R6300

R6301

1

0.01uF_50V_2

C6301

2

2.2uF_6.3V_3

2

1

0.1uF_10V_2

C6302

2

U6300

12 15

17

S3

16

S5

6

VREF

8

REFIN

7

GND

19

MODE

18

2

1

R6305

TRIP

VBSTV5IN

DRVH

DRVL

PGND

PGOOD

VDDQSNS

VLDOIN

VTT

VTTSNS

VTTGND

VTTREF

TML

14
13

SW

11

10
20
9
2
3

1

4
5
21

2

PAD6310

2

1

POWERPAD_2_0610

1

R6306

1

2.2_5%_3

VR15_HG
VR15_PH

VR15_LG

P0V75_VREF_M

1

1

2

C6305

1

0.1UF_25V_3

TPCA8065_H

2

TPCA8A02_H

PAD6300

1

POWERPAD_2_0610

2

2

876

54

3.7A

Q6300

D

NMOS_4D3S

G

S S

1

2

3

876

5

Q6301

D

G

1

2

4

3

1

R6307

4.7_5%_3

1

2

C6306

2200pF_50V_2

2

1

C6307

4.7UF_25V_5

2

1

C6308

4.7UF_25V_5

2

L6300

1

3 4

PCMC104T_1R0MN

2

1

C6309

4.7UF_25V_5

2

1

C6310

+

560UF_2.5V

2

PAD6301

1

1

2

POWERPAD_2_0610

PAD6302

1

1

2

POWERPAD_2_0610

2

2

22A

P1V5

D

VOUT=(1.8*R2)/(R1+R2)

R6304

75K_1%_2

1

100K_5%_2

2

TI_TPS51216RUKR_QFN_20P

C6303

2

C6304

2

10uF_6.3V_3

0.22uF_6.3V_2

PVBAT

B B

+V1.05S_VCCP_EN

IN

1

876

54

Q6350

D

NMOS_4D3S

P5V_A

G

R6350

0_5%_2

2

A A

CSC0402_DY

C6350

1

R6351

2

1

2

110K_1%_2

1
2
3
4
5

1

R6352

200K_1%_2

2

U6350

VBST

PGOOD

DRVH

TRIP
EN
VFB
RF

TI_TPS51218DSCR_SON_10P

SW
V5IN
DRVL

GND

11

R6353

2.2_5%_3

1

10
9
8

VRVCCP_HG

7

VRVCCP_PH

6

VRVCCP_LG

1

C6351

1uF_10V_2

2

C6352

0.1UF_25V_3

2

1

2

8

S S

AON7410

1

2

3

5

876

Q6351

D

G

AON7702L

1

2

3

4

67

1

1

2

2
1

C6354

2

1

R6354

4.7_5%_3

1

2

C6353

2200pF_50V_2

2

PAD6350
POWERPAD_2_0610

1

2

L6350

5.1K_1%_2

10K_1%_2

C6356

4.7UF_25V_5

2

R6356

C6355

4.7UF_25V_5

1

PCMC063T_3R3MN

R6355

2

1

1

2

C6340

10K_5%_2

P3V3_S

1

2

CSC0402_DY

CHANGE by

GMT_G5694F11U_SOP_8P

U6340

8

10UF_6.3V_3

VIN

1

VCC

5

EN

PGND

9

TML

VR18_PH

LX

PAN_ELL5PR2R2N

4

FB

2

REF

GND

376

1

C6342

L6340

1

2

0.1UF_16V_2

DATE

XXX

21-OCT-2002

3 2

R6342

R6343

P1V8_S

1

1

C6344

22UF_6.3V_5

2

PAD6340

1

2

2

POWERPAD_2_0610

2

2

1

13K_1%_2

2

1

1

C6343

2

CSC0402_DY

10K_1%_2

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

SIZE

CS

DOC.NUMBER

1310xxxxx-0-0

SHEET

of

9779

CODE

C

1

REV

X01

P5V_A

2

R6341

1

2

4.7UF_25V_5

1

POWERPAD_2_0610

P1V05_VCCPS

PAD6351

1

2

2

C6341

R6340

10_5%_3

1

1

C6345

2

R1

2

0.1UF_16V_2

1

1

C6357

+

R2

330UF_6.3V

2

VOUT=(1+R1/R2)*0.7

2

1

45

78

56

4

23

1

R6400

R6401

2

2

C6400

100PF_50V_2_DY

VTT_PG

P3V3_A

IN
IN

IN

1

2

OUT

R6404

1

10K_5%_2

R6405

1

0_5%_2_DY

P3V3_S

2

R6402

10K_5%_2

1

2

2

2

R6403

1K_5%_2

1

C6402

2

0.01UF_50V_2

1
2

4

1

U6400

VREF

REFIN

GSNS

VSNS

2

R6406

86.6K_1%_2

1

2

2

0.1UF_25V_3

C6404

7

5

6

1

8

Q6400

D

NMOS_4D3S

G

S

TPCA8065_H

1

4

3

2

678

Q6401

D

R6407

1

15

16

17

PWPD

PGOOD

13

14

EN

BST

MODE

0_5%_3

TI_TPS51219RTER_QFN_16P

12

SW

DH

DL

V5

VRVCCIO_PH

11

VRVCCIO_HG

10

VRVCCIO_LG

9

P5V_A

PGND

TRIP

GND

COMP

G

3

4 5

S

TPCA8A02_H

1

2

6

5

837

1

C6403
1UF_10V_2

2

1.5S_CPU_PG

SLP_S3#_5R

IN

IN

1

0_5%_2

1

100K_5%_2_DY

D

1

C6401

2.2UF_10V_3

VSS_SENSE_VCCIO

VCCIO_SENSE

2

VCCIO_SEL

C C

PVBAT

1

PAD6400

1

2

POWERPAD_2_0610

2
1

C6405

4.7UF_25V_5

2

1

C6406

4.7UF_25V_5

2

2

R6408

RSC_0603_DY

1

1

C6408

CSC0402_DY

2

1

C6407

4.7UF_25V_5

2

L6400

1

ETQP4LR36AFM

NEW

PVCCIO

PAD6401

2
43

1

1

POWERPAD_2_0610

PAD6402

1

1

POWERPAD_2_0610

1

C6409

22UF_6.3V_5

2

2

2

2

2

1

C6410

+

560UF_2.5V

2

D

1

C6433

1

3300PF_50V_2

B B

0.22UF_6.3V_2

2

C6435

P5V_A

1

C6430

10UF_10V_5

2

1

C6431

10UF_10V_5

2

A A

1

C6432

0.1UF_16V_2

2

1UF_10V_2

C6436

1

POWERPAD1X1M

1

PAD6430

2

5.11K_1%_2

1

2

1

2

R6430

1

25

TML

24
23

VIN

22

VIN
PGND

20

PGND

19

PGND

2

C6437

1UF_10V_2

2

1

3

4

2

GND

VREF

SLEW

COMP

U6430

PGOOD

VID1

V5FILT

V5DRV

1816151413

17
1

2

C6434

0.01UF_50V_2

2

6

5

RSC_0402_DY

VOUT

MODE

SWVIN
SW
SW
SW
SW

BST

VID0

EN

R6434

1

1

0_5%_2

R6435

0_5%_2_DY

2

R6431

7
8
9

1021
11

1

12

1

C6438

CSC0402_DY

2

2

2

R6432

0_5%_3

R6433

1

0_5%_2

1

TI_TPS51461RGER_QFN_24P

IN

VRVCCSA_PH

2

2

IN

VCCSA_VID1

IN

VCCSA_VID0

VCCSA_SENSE

C6439

2

0.1UF_25V_3

VTT_PG

IN

WS

WS

P0V85_S

L6430

1

PCMC063T_R33MN

1

1

R6437

RSC_0603_DY

2

1

C6440

CSC0402_DY

2
43

1

C6441

22UF_6.3V_5

2

1

C6442
22UF_6.3V_5

2

1

C6443

22UF_6.3V_5

2

1

C6444
22UF_6.3V_5_DY

2

PAD6431

1

1

2

POWERPAD_2_0610

2

2

P3V3_S

1

R6436
10K_5%_2

2

8

67

OUT

VCCSA_PG

CHANGE by

45

XXX

3 2

DATE

21-OCT-2002

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CS

DOC.NUMBER

1310xxxxx-0-0

SHEET

80 97

of

1

SIZE

CODE

C

REV

X01

78

56

4

23

1

VREF

75K_1%_2

CPU_CSP3

CPU_CSN3

IN

IN

7

CCSP3

CCSN3

GOCP_R

GCSN2

30

29

0_5%_2

2

1

R6522

IN

GPU_CSN2

2

1

R6511

2
1 1

R6512

2

100K_1%_NTC

CPU_CSN1

CPU_CSN2

CPU_CSP2

IN

IN

IN

4

586

CCSP2

CCSN2

CCSN1

GTHERM

GSKIP#

GPWM2

32

31

33

OUT

GPWM1

1

R6530

30K_5%_2

2

1

C6508

0.1UF_16V_2_DY

2

PVBAT

C6505

1

2

R6513

CPU_CSP1

IN

2

3

COCR-1

CCSP1

GPWM1

CPWM3

0.1UF_16V_2_DY

1

2

1

15.4K_1%_2

1

CTHERM

GND

V5

CDH1

CBST1

CSW1

CDL1

V5DRV

N_C

PGND

CDL2

CSW2

CBST2

CDH2

VBAT

R6514

2.2UF_10V_3

49
48
47
46
45
44
43
42
41
40
39

2 2

38

2.2_5%_3

37

VREF

P5V_CPU

2

R6532

2

2.2_5%_3

P5V_A

R6533

R6534

1

10_5%_3

1

C6506

2

P5V_CPU

1

1

0.1UF_25V_2

P5V_A

2

1

C6507

4.7UF_10V_3
TPCA8065_H

2

VRCPU_HG1

C6509

1

0.1UF_25V_2

2

VRCPU_PH1
VRCPU_LG1

C6510

1

PVBAT

R6531

36

35

34

OUT

GPWM2

1

10K_5%_2

OUT

CPWM3

OUT

2

GSKIP

VRCPU_LG2

VRCPU_PH2

VRCPU_HG2

1

PAD6500

1

POWERPAD_2_0610

2

2

6

5

7

8

Q6500

D

NMOS_4D3S

G

S

1

4

3

2

5

678

Q6501

D

NMOS_4D3S

G

S

TPCA8057_H

1

432

PVBAT

1

PAD6501

1

POWERPAD_2_0610

2

5

627

8

Q6502

D

NMOS_4D3S

G

S

1

432

TPCA8065_H

567

8

Q6503

D

NMOS_4D3S

G

S

TPCA8057_H

1

432

CPU_CSN1

CPU_CSP1

1

1

1

C6513

C6512

2

C6511

2

4.7UF_25V_5

2

4.7UF_25V_5

1

R6535

RSC_0603_DY

1

2

C6515

CSC0402_DY

OUT

C6516

0.033UF_16V_2

R6539

1

3

1

1

1

162K_1%_2

L6500

OUT

1

C6514

2

4.7UF_25V_5

1

17.8K_1%_3

4.7UF_25V_5

R6538

2

100K_1%_NTC

PAN_ETQP4LR36ZFC_4P

R6537

2

28.7K_1%_2

2

1

4
2

2

R6540

C6531

470UF_2V

2

PVCORE

1

C6532

+

2

1

470UF_2V

+

3

2

3

2

CPU_CSN2

CPU_CSP2

1

1

1

C6518

C6517

2

4.7UF_25V_5

C6519

2

2

4.7UF_25V_5

1

R6536

RSC_0603_DY

1

C6521

CSC0402_DY

OUT

C6522

OUT

1

C6520

2

4.7UF_25V_5

R6542

1 1

17.8K_1%_3

4.7UF_25V_5

2

100K_1%_NTC

PAN_ETQP4LR36ZFC_4P

1

0.033UF_16V_2

1

162K_1%_2

R6543

3

1

L6501

R6541

2

28.7K_1%_2

2

2

R6544

1

4
2

560UF_2.5V

2

C6533

PVCORE

1

+

2

1

C6534

470UF_2V

+

2

3

2 2

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CS

DOC.NUMBER

1310xxxxx-0-0

SHEET

81

of

97

1

CODE

SIZE

CHANGE by

45

XXX

3 2

DATE

21-OCT-2002

C

REV

X01

PVTT

1

R6500

D

VR_SVID_CLK

VR_SVID_DATA

IN
BI

2

54.9_1%_2

VREF

C6501

P3V3_A

1

1

2.2UF_6.3V_3

2

2

C6502

C C

2.2UF_6.3V_3

VREF

R6504

R6505

30K_1%_2

1

1

VAXG_SENSE

VSSAXG_SENSE

2

200K_1%_2

B B

2

VREF

MAIN_PWRGD

IN

A A

R6526

20K_5%_2

VR_ON

OUT

1 1

R6527

8.66K_1%_2

2 2

8

1

C6500

1

0.1UF_16V_2_DY

R6501

2

130_1%_2

2

VR_SVID_CLK

VR_SVID_ALRT#

VR_SVID_DATA

H_PROCHOT#

+VGFX_PWRGD

IN

IN

1

33PF_50V_2

1

4.12K_1%_2

VREF

VREF

2

42.2K_1%_2

VR_ON

VR_PWRGD

R6506

1

R6507

1

C6503

2

R6515

2

VREF

1

R6524

100K_1%_2

2

1

R6525

56K_1%_2

2

R6502

IN
OUT

IN
IN

BI

OUT

OUT

0_5%_2

0_5%_2

R6508

0_5%_2_DY

33PF_50V_2

1

8.45K_1%_2

1

1

R6503

24K_1%_2

2

2

2

1

2

P3V3_A

C6504

1

R6510

1

R6509

0_5%_2_DY

2

2

R6519

2

R6521

2

R6517

2

R6523

2

2

13
14
15
16
17
18

19
20
21
22
23
24

0_5%_2_DY

0_5%_2_DY

0_5%_2_DY

0_5%_2_DY

1
1
1

1

67

VREF

V3R3

VR_ON

CPGOOD

VCLK

ALERT#

VDIO

VR_HOT

GPGOOD

GF_IMAX

GVFB

GGFB

VREF

VSSSENSE

IN

12

11

CGFB

CF-IMAX

GCSN1

GCOMP

26

25

2

1

IN

GPU_CSN1

1

15.4K_1%_2

100K_1%_NTC

100K_1%_2

VCCSENSE

IN

10

9

CVFB

CCOMP

U6500

TI_TPS51650RSLR_QFN_48P

GCSP2

GCSP1

28

27

0_5%_2

0_5%_2

0_5%_2

2

2

1

1

R6516

R6520

R6518

IN

IN

GPU_CSP1

GPU_CSP2

R6528

2

R6529

D

78

56

4

23

1

PVBAT

1

PAD6503

1

2

POWERPAD_2_0610

D

P5V_CPU

CPWM3

R6545

1

2.2_5%_3

TI_TPS51601DRBR_SON_8P

U6501

1

BST
SKIP#

3

IN

PWM

4 5

GND

2

1

0.1UF_25V_2

PAD

DRVH

SW

VDD

DRVL

C6523

9
8

72
6

2

VRCPU_HG3
VRCPU_PH3

VRCPU_LG3

P5V_A

1

C6524

1UF_10V_2

2

2

678

TPCA8065_H

NMOS_4D3S

D

Q6505

1

C6525

4.7UF_25V_5

2

G

S

1

4 5

3

2

678

TPCA8057_H

NMOS_4D3S

Q6506

D

G

S

1

4 5

3

2

1

R6546

RSC_0603_DY

1

2

C6529

CSC0402_DY

2

1

C6526

4.7UF_25V_5

2

1

C6527

4.7UF_25V_5

2

CPU_CSN3

CPU_CSP3

1

C6528

4.7UF_25V_5

2

OUT

OUT

1

17.8K_1%_3

R6548

PAN_ETQP4LR36ZFC_4P

R6549

1

2

100K_1%_NTC

1

L6502

C6530

1

0.033UF_16V_2
R6547

1

162K_1%_2

2

1

28.7K_1%_2

43
2

2

2

R6550

D

2

PVCORE

C C

R6600

1

2.2_5%_3

TI_TPS51601DRBR_SON_8P

U6600

1

BST

GSKIP#

GPWM1

IN
IN

SKIP#

3

PWM

4 5

GND

B B

C6600

2

1

0.1UF_25V_2 4.7UF_25V_5

PAD

DRVH

SW

VDD

DRVL

2

9
8

72
6

VRAXG_HG1
VRAXG_PH1

VRAXG_LG1

P5V_A

1

C6601

1UF_10V_2

2

PVBAT

1

PAD6600

1

2

POWERPAD_2_0610

2

678

TPCA8065_H

NMOS_4D3S

G

4 5

3

2

5

678

TPCA8057_H

NMOS_4D3S

G

4

3

2

D

S

1

D

S

1

Q6600

Q6601

1

C6602

4.7UF_25V_5

2

1

C6606
CSC0402_DY

1
2

R6601

RSC_0603_DY

2

1

C6603

4.7UF_25V_5

2

1

C6604

2

GPU_CSN1

GPU_CSP1

1

C6605

4.7UF_25V_5

2

OUT

OUT

1

17.8K_1%_3

R6603

PAN_ETQP4LR36ZFC_4P

2

1

100K_1%_NTC

1

1

0.033UF_16V_2

1

162K_1%_2

R6604

2

43
2

L6600

C6607

R6602

28.7K_1%_2

1

2

2

R6605

2

PVAXG

PVBAT

1

PAD6601

1

2

POWERPAD_2_0610

2

678

R6606

1

2.2_5%_3

A A

GSKIP#

GPWM2

IN
IN

TI_TPS51601DRBR_SON_8P

U6601

1
3

4 5

BST
SKIP#
PWM
GND

2

C6608

1

0.1UF_25V_2

9

PAD

8

DRVH

72

SW

6

VDD

DRVL

2

VRAXG_HG2
VRAXG_PH2

VRAXG_LG2

P5V_A

TPCA8065_H

NMOS_4D3S

TPCA8057_H

NMOS_4D3S

G

4 5

3

2

678

D

S

1

D

Q6602

Q6603

1

C6609

1UF_10V_2

2

8

G

S

3

214 5

67

1

C6610

4.7UF_25V_5

2

1

C6614
CSC0402_DY

1

2

R6607

RSC_0603_DY

2

1

C6611

4.7UF_25V_5

2

1

C6612

4.7UF_25V_5

2

GPU_CSN2

GPU_CSP2

1

C6613

4.7UF_25V_5

2

OUT

OUT

45

R6609

1

17.8K_1%_3

C6615

1

0.033UF_16V_2
R6608

1

162K_1%_2

2

PAN_ETQP4LR36ZFC_4P

R6610

1

100K_1%_NTC

1

L6601

2

43
2

CHANGE by

2

2

R6611

XXX

2

DATE

1

28.7K_1%_2

3 2

PVAXG

21-OCT-2002

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CS

DOC.NUMBER

1310xxxxx-0-0

SHEET

82 97

of

1

SIZE

CODE

C

REV

X01

Original Sch

P5V_A

R6707

10K_5%_2

1

2

R6705

2

SLP_S3#_3R

IN

1

0_5%_2

1

C6702

CSC0402_DY

2

78

56

4

23

1

PVBAT

11

PAD6702

1

D

WS

P3V3_S

2

P5V_A

3.5A

6

8

7

5

Q6700

D

TPCA8065_H

NMOS_4D3S

CHECK

R6801

10K_5%_2

2

R6703

75K_1%_2

1

1

WS

EC_DGPU_PWR_EN

C C

IN

VDDC_GPU_PG

R6802

1

2

10K_5%_2

1

C6801

1UF_6.3V_2

2

I80

OUT

U6700

TI_TPS51217DSCR_SON_10P

1
2
3
4
5

1

R6704

1K_1%_2

PGOOD

TRIP

EN

VFB

TRAN

VBST

DRVH

SW

V5IN

DRVL

GND

11

2

10
9
8
7
6

R6700

2.2_5%_3

1

VRGPU_HG
VRGPU_SW

1

C6701

1uF_10V_2

2

VRGPU_LG

1

2

C6700

0.1UF_25V_3

G

2

TSB_TPCA8057_H_8P

S

3

214

TSB_TPCA8057_H_8P

876

876

54

Q6701

876

5

D S

G

1

2

4

3

1

3

2

54

Q6702

876

5

D S

G

1

2

4

3

1

3

2

2

POWERPAD_2_0610

2

C6704

4.7UF_25V_5

2

1

SBR3U40P1

2

D6700

1

C6705

4.7UF_25V_5

2

L6700

1

PAN_ETQP4LR36WFC_4P

C6708

1

4.7UF_25V_5

2

2
43

1

C6706

+

470UF_2V

2

PAD6700

1

1

POWERPAD_2_0610

PAD6701

1

1

POWERPAD_2_0610

2

2

30A

PVCORE_GPU

2

2

1

C6707

+

470UF_2V

2

D

1

1

C6709

47pF_50V_2

2

C6703

2

B B

P3V3_S

1

CHECK

WS

POW_SW0

A A

CHECK

WS

POW_SW1

8

IN

IN

R6708

10K_5%_2

2

P3V3_S

1

R6

10K_5%_2

2

SSM3K7002FU

67

2

R6701

68K_1%_2

1

3

Q2

DS

1

G

2

1

C1

100PF_50V_2

2

SSM3K7002FU

R7

40.2K_1%_2

1

Q3

DS

1

G

2 3 2

WS

VID1

POW_SW1

VID0

POW_SW0
0
0

1

VID1

POW_SW1

VID0

POW_SW0
0

1

45

+VDDC_GPU
PCORE_GPU

0

1

0

1.05V

1.00V

0.90V

+VDDC_GPU
PCORE_GPU

1

0

CHANGE by

1.00V

0.90V

XXX

3 2

1

R6702

10.2K_1%_2

2

CSC0402_DY

1

R6706

20K_1%_2

2

For XT

For PRO

DATE

21-OCT-2002

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

C

CS

1310xxxxx-0-0

SHEET

83 97

of

1

REV

X01

78

56

4

23

1

CONFIGURATION STRAPS:

STRAPS

TX_PWRS_ENB

TX_DEEMPH_EN

D

RESERVED

PIN

GPIO_0

GPIO_1

GPIO_2

DESCRIPTION OF DEFAULT SETTINGS

Full Tx output swing=1 (Default)

50% Tx output swing=0

Tx De-emphasis enabled=1 (Default)
Tx De-emphasis disabled=0

Advertises the PCIe device as 2.5 GT/s capable at power on=0
Advertises the PCIe device as 5.0 GT/s capable at power on=1

Pin-Based Straps

GPU

Whistler

(ASIC Internal pull down, and PCB Default is 0)

RESERVED
RESERVED

GPIO_8

GPIO_21

Must be low during reset
PCB default is left unconnected
Must be low during reset

(PCB default is 0)

Voltage control signal for the memory-voltage regulator.

BIF_VGA DIS

BIOS_ROM_EN
CONFIG[2]

CONFIG[1]
CONFIG[0]

C C

AUD[0]
AUD[1]

GPIO_9

GPIO_22
GPIO_13

GPIO_12
GPIO_11

HSYNC
VSYNC

VGA controller capacity enabled=0 (Default)
VGA controller capacity disabled=1

Disable the external BIOS ROM device=0 (Default)

Enable the external BIOS ROM device=1

If GPIO_22 = 0, then CONFIG [2:0] defines the primary

memory-aperture size. Default is 0 0 1

AUD [1:0]:

0 0 = No audio function
0 1 = Audio for DisplayPort only

1 0 = Audio for DisplayPort and HDMI, if dongle is detected
1 1 = Audio for both DisplayPort and HDMI. (Default is 1 1)

RESERVED

GENLK_CLK

Must be low during reset
PCB default is left unconnected

D

(2.012A)

P1V8_SP3V3_A

1

B B

C5104

2

68pF_50V_2

VDDC_GPU_PG

A A

IN

PX_MODE

IN

1

R5106

2

100K_5%_2

3

DS

1

G

Q5105

SSM3K7002FU

2

1

C5107

2

1
2
5

2.2uF_6.3V_3

P3V3_A

1

C5108

2

1

P1V8_GPUS

Q5110

D

NMOS_4D1S

AM3402N FDMC7692

R5111

68pF_50V_2

3

G

2

4

S

36

G

1

2

100K_5%_2

DS

Q5109

SSM3K7002FU

R5114

1

G

R5115

1

G

P15V_A

1

560K_1%_2

2

3

DS

Q5112

2

P15V_A

1

560K_1%_2

2

3

DS

Q5113

2

SSM3K7002FU

SSM3K7002FU

R5516

1

0_5%_2_DY

R5517

1

0_5%_2

2

2

BACO MODE

8

67

(7A)

P1V5_GPUS

1

C5116

0.01uF_50V_2

2

Q5117

1

S

2
3
4 5

G

NMOS_4D3S

45

D

P1V5

1

8
7
6

C5118

2.2uF_6.3V_3

2

DGPU_PWR_EN#

CHANGE by

P3V3_S

2

SD

1

1

C5120

2

R5119

IN

3 2

1

10K_5%_2

XXX

2

0.1uF_16V_2

DATE

21-OCT-2002

G

3

Q5121

AM2321P

P3V3_GPUS

1

G

200_5%_2

2

3

DS

Q5122

SSM3K7002FU

2

R5123

1

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CS

DOC.NUMBER

1310xxxxx-0-0

SHEET

84 97

of

SIZE

CODE

C

REV

X01

1

78

56

4

23

1

WHISTLER XT
WHISTLER PRO

PEG_TX0_DP
PEG_TX0_DN

PEG_TX1_DP

D

C C

PEG_TX1_DN
PEG_TX2_DP

PEG_TX2_DN
PEG_TX3_DP

PEG_TX3_DN
PEG_TX4_DP

PEG_TX4_DN
PEG_TX5_DP

PEG_TX5_DN
PEG_TX6_DP

PEG_TX6_DN
PEG_TX7_DP

PEG_TX7_DN
PEG_TX8_DP

PEG_TX8_DN
PEG_TX9_DP

PEG_TX9_DN

TDP: 30~35 W
TDP: 20~25 W

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

AA38

Y37

W36

W38
V37

V35
U36

U38
T37

T35
R36

R38
P37

P35
N36

N38
M37

M35
L36

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

PCIE_RX8P
PCIE_RX8N

PCIE_RX9P
PCIE_RX9N

U5124

PCI EXPRESS INTERFACE

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

Y33
Y32

W33Y35
W32

U33
U32

U30
U29

T33
T32

T30
T29

P33
P32

P30
P29

N33
N32

N30
N29

PEG_RX0_C_DP
PEG_RX0_C_DN

PEG_RX1_C_DP
PEG_RX1_C_DN

PEG_RX2_C_DP
PEG_RX2_C_DN

PEG_RX3_C_DP
PEG_RX3_C_DN

PEG_RX4_C_DP
PEG_RX4_C_DN

PEG_RX5_C_DP
PEG_RX5_C_DN

PEG_RX6_C_DP
PEG_RX6_C_DN

PEG_RX7_C_DP
PEG_RX7_C_DN

PEG_RX8_C_DP
PEG_RX8_C_DN

PEG_RX9_C_DP
PEG_RX9_C_DN

CLOSE TO GPU

C5128
C5129

C5130
C5131

C5132
C5133

C5134
C5135

C5136
C5137

C5138
C5139

C5140
C5141

C5142
C5143

C5144
C5145

C5146
C5147

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

PEG_RX0_DP

BI

PEG_RX0_DN

BI

PEG_RX1_DP

BI

PEG_RX1_DN

BI

PEG_RX2_DP

BI

PEG_RX2_DN

BI

PEG_RX3_DP

BI

PEG_RX3_DN

BI

PEG_RX4_DP

BI

PEG_RX4_DN

BI

PEG_RX5_DP

BI

PEG_RX5_DN

BI

PEG_RX6_DP

BI

PEG_RX6_DN

BI

PEG_RX7_DP

BI

PEG_RX7_DN

BI

PEG_RX8_DP

BI

PEG_RX8_DN

BI

PEG_RX9_DP

BI

PEG_RX9_DN

BI

D

PEG_TX10_DP
PEG_TX10_DN

PEG_TX11_DP
PEG_TX11_DN

PEG_TX12_DP
PEG_TX12_DN

B B

CLK_PEG_GPU_REF_DP
CLK_PEG_GPU_REF_DN

A A

PEG_TX13_DP
PEG_TX13_DN

PEG_TX14_DP
PEG_TX14_DN

PEG_TX15_DP
PEG_TX15_DN

C5000

1

2

0.1UF_16V_2

P3V3_S

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

R5003

2

10K_5%_2

L38
K37

K35
J36

J38
H37

H35
G36

G38
F37

F35
E37

AB35
AA36

1

AH16

AA30

PCIE_RX10P
PCIE_RX10N

PCIE_RX11P
PCIE_RX11N

PCIE_RX12P
PCIE_RX12N

PCIE_RX13P
PCIE_RX13N

PCIE_RX14P
PCIE_RX14N

PCIE_RX15P
PCIE_RX15N

CLOCK

PCIE_REFCLKP
PCIE_REFCLKN

PERSTB

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

CALIBRATION

PCIE_CALRP

PCIE_CALRNPWRGOOD

L33
L32

L30
L29

K33
K32

J33
J32

K30
K29

H33
H32

Y30
Y29

PEG_RX10_C_DP
PEG_RX10_C_DN

PEG_RX11_C_DP
PEG_RX11_C_DN

PEG_RX12_C_DP
PEG_RX12_C_DN

PEG_RX13_C_DP
PEG_RX13_C_DN

PEG_RX14_C_DP
PEG_RX14_C_DN

PEG_RX15_C_DP
PEG_RX15_C_DN

R5126

1.27K_1%_2

1

1

2K_1%_2

2

2

R5127

P1V0_GPU

C5148
C5149

C5150
C5151

C5004
C5005

C5152
C5153

C5154
C5155

C5156
C5157

1
1

1
1

1
1

1
1

1
1

1
1

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

2

0.1UF_16V_2

PEG_RX10_DP

BI

PEG_RX10_DN

BI

PEG_RX11_DP

BI

PEG_RX11_DN

BI

PEG_RX12_DP

BI

PEG_RX12_DN

BI

PEG_RX13_DP

BI

PEG_RX13_DN

BI

PEG_RX14_DP

BI

PEG_RX14_DN

BI

PEG_RX15_DP

BI

PEG_RX15_DN

BI

AMD_216_0810_001_FCBGA_962P

5

U5001

+

DGPU_HOLD_RST#

PLT_RST#

8

IN
IN

1

2

-

TC7SZ08FU

3

R5002

1

0_5%_2_DY

4

2

PEG_PLT_RST#

R5125

1

100K_5%_2

2

67

GEN2:

PCI EXPRESS BUS:TRANSMITTED/RECEIVER
UP TO 5.0-GT/S BIT RATE.

CHANGE by

45

XXX

3 2

DATE

21-OCT-2002

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CS

DOC.NUMBER

1310xxxxx-0-0

SHEET

85 97

of

1

SIZE

CODE

C

REV

X01

8

IF GPU_GPIO22 = 0, THEN GPIO[13:11]
DEFINES THE PRIMARY MEMORY APERTURE SIZE

GPU_
GPIO13 GPIO12

GPU_

0

0
0

VID1

POW_SW1

POW_SW0
0
0
1

VID1

POW_SW1

POW_SW0 PCORE_GPU
0
1

0
0

1
1

VID0

0
1
0

VID0

1
0

GPU_
GPIO11

1
00

0
1

+VDDC_GPU
PCORE_GPU

1.05V

1.00V

0.90V

+VDDC_GPU

1.00V

0.90V

MEMORY APERTURE
SIZE

256 MB

(DEFAULT)

128 MB

64 MB
32 MB

For XT

For PRO

E

R5158

1

10K_5%_2

R5159

1

10K_5%_2

R5161

1
10K_5%_2

R5163

1

10K_5%_2

2

2

2

2

GPU_GPIO19

IN

GPU_LCM_BKLTEN

IN

IN

POW_SW0

IN

POW_SW1

D

P3V3_GPUS

C

C5006

SWING: 1.8V
CLK_GPU_27M

FBM_11_160808_121T

2

1

L5007

1

2

1

C5161

2

10UF_6.3V_3

0.1UF_16V_2

IN

C5163

1

0_5%_2_DY

1

2

0.1UF_16V_2

R5009

2

3.3V,0.05A

1

0_5%_2

R5010

2

1

C5011

2

15PF_50V_2

1

0_5%_2

R5012

2

1

4

27MHZ_12PF

XTAL_4PIN

1

1M_5%_2

U5017

1

X1_ICLK

4

VDD_100M

8

VDD_27M

7

S0

3

S1

6

GND_PLL

2

GND_27M

IDT_6V40088_DFN_10P

32 KHZ SPREAD SPECTRUM MODULATION

P3V3_GPUS

TP5165

2

R5160R5008

1

B

10K_5%_2_DY

1

10K_5%_2

2

A

THRM_GPU_DP
THRM_GPU_DN

THRM_SHUTDWN#

2

2

R5164

R5162

1

1

10K_5%_2_DY

TP24

1

GPU_JTAG_TDO

10K_5%_2_DY

OUT

GPU_JTAG_TDI

OUT

GPU_JTAG_TRSTB

OUT

GPU_JTAG_TMS

OUT
OUT

GPU_JTAG_TCK

JTAG MODE

P3V3_GPUS

C5013

1

2

0.1UF_16V_2
C5014

2

1

2200PF_50V_3

IN
IN
OUT

8

7 6 5 4 3 2

X5015

3
2

R5016

2

X2

100M

27M

TML

1

VCC

2

DXP

3 6

DXN

4 5

THERM#

GMT_G784_MSOP_8P

P3V3_GPUS

1

10K_5%_2

1

10K_5%_2

1

10K_5%_2_DY

1

10K_5%_2

1

10K_5%_2_DY

1

10K_5%_2

1

10K_5%_2_DY

1

10K_5%_2_DY

1

10K_5%_2_DY

1

10K_5%_2_DY

1

10K_5%_2_DY

1

10K_5%_2

1

10K_5%_2

1

10K_5%_2_DY

1

C5166

2

10

5

GPU_XOIN2_100M

9

GPU_XOIN_27M

11

SWING: 3.3V

U5018

SMBCLK

SMBDATA

ALERT#

GND

15PF_50V_2

R5167

R5168

R5019

R5169

R5170

R5171

R5172

R5173

R5174

R5175

R5176

R5177

R5178

R5179

8
7

2

2

2

2

2

2

2

2

2

2

2

2

2

2

R5022

1

33_5%_2

R5023

1

33_5%_2

R5020

1

0_5%_2_DY

R5021

1

0_5%_2_DY

GPU_GPIO0

OUT

GPU_GPIO1

OUT

GPU_GPIO2

OUT

GPU_THERM_INT#

IN

GPU_GPIO22

OUT

GPU_GPIO11

OUT

GPU_GPIO12

OUT

GPU_GPIO13

OUT

OUT

GPU_GPIO23

GPU_GPIO9

OUT

GPU_GPIO5

OUT

OUT

GPU_CRT_HSYNC

OUT

GPU_CRT_VSYNC

GPU_GPIO21

OUT

2

OUT

2

OUT

P1V8_GPUS

P1V0_GPU

FBM_11_160808_121T

P1V8_GPUS

1

R5024

22

1

R5025

10K_5%_2_DY 10K_5%_2_DY

2

GPU_THM_CLK

BI

2

GPU_THM_DAT

BI

EC_SMB2_CLK

BI

EC_SMB2_DATA

BI

MEM_ID3 MEM_ID2

0
0 0

[ALERT]

HDMI&DP Audio

GPU_XOIN2_100M_R

P1V8_GPUS

GPU_XOIN_27M_R

FBM_11_160808_121T

L5180

2

1

GPU_TS_FDO

IN

1

L5181

C5026

2

I=0.125A

1

2

10UF_6.3V_3

C5183

C5182

I=0.075A

1

2

1

1UF_6.3V_2

2

1

C5184

1UF_6.3V_2

2

10UF_6.3V_3

1

C5027

2

0.1UF_16V_2

MLPS option for future ASIC

P1V8_GPUS

MEM_ID1

0

0

2

R5030

R5029

1

10K_5%_2_DY

GPU_LCM_BKLTEN

GPU_THERM_INT#

GPU_JTAG_TRSTB

2

R5185

1

499_1%_2

1

C5028

DPLL_PVDD

2

0.1UF_16V_2

DPLL_VDDC

TP5031
TP5032

GPU_XOIN_27M_R
GPU_XOIN2_100M_R

L5186

2

1

FBM_11_160808_121T

MEM_ID0

11
1

P1V8_GPUS

2

1

10K_5%_2_DY

GPU_THM_DAT
GPU_THM_CLK

2

2

R5191

R5187

1

1

10K_5%_2

TP24

TP5189
TP5190

TP24

GPU_GPIO0
GPU_GPIO1
GPU_GPIO2

GPU_GPIO5

1
1

GPU_GPIO9

GPU_GPIO11
GPU_GPIO12
GPU_GPIO13

GPU_EDP_HPD

POW_SW0

GPU_GPIO19

POW_SW1
GPU_GPIO21
GPU_GPIO22
GPU_GPIO23

GPU_JTAG_TDI
GPU_JTAG_TCK
GPU_JTAG_TMS
GPU_JTAG_TDO

TP5035
TP5036

1

TP24

1

TP24

GPU_HDMI_HPD1

C5033

2

1

0.1UF_16V_2
R5034

2

1

249_1%_2

TP24

1
1

TP24

THRM_GPU_DP
THRM_GPU_DN

GPU_TS_FDO

I=0.005A

1

1

C5192

C5188

2

2

10UF_6.3V_3

TSVDD

(GDDR5)

Vendor
HYNIX

(1GB)

OUT
OUT
OUT

BI
BI

IN
OUT

IN
IN

IN
IN
IN
OUT

OUT
OUT

OUT
IN
IN
IN
IN
IN
IN
IN
IN

(1GB)

AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9

AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

AJ21
AK21

AK26
AJ26

AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

AK24

IN

SAMSUNG

10K_5%_2

MEM_ID0
MEM_ID1
MEM_ID2
MEM_ID3

AH13

CLOSE TO GPU

AM32
AN32

AN31

AV33
AU34

AW34

IN

AW35

IN

AF29

OUT

AG29

OUT

AK32

OUT

AL31

AJ32
AJ33

1

C5193

2

1UF_6.3V_2

0.1UF_16V_2

U5124

TXCAP_DPA3P
TXCAM_DPA3N

MUTI GFX

DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2

DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

SWAPLOCKA
SWAPLOCKB

I2C

SCL
SDA

GENERAL PURPOSE I/O

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

HPD1

VREFG

DPLL_PVDD
DPLL_PVSS

PLL/CLOCK

DPLL_VDDC

XTALIN
XTALOUT

XO_IN

XO_IN2

DPLUS

THERMAL

DMINUS

TS_FDO

TS_A/NC

TSVDD
TSVSS

DPA

DPB

DPC

DPD

DAC1

DAC2

DDC/AUX

AMD_216_0810_001_FCBGA_962P

TX0P_DPA2P
TX0M_DPA2N

TX1P_DPA1P
TX1M_DPA1N

TX2P_DPA0P
TX2M_DPA0N

TXCBP_DPB3P
TXCBM_DPB3N

TX3P_DPB2P
TX3M_DPB2N

TX4P_DPB1P
TX4M_DPB1N

TX5P_DPB0P
TX5M_DPB0N

TXCCP_DPC3P
TXCCM_DPC3N

TX0P_DPC2P
TX0M_DPC2N

TX1P_DPC1P
TX1M_DPC1N

TX2P_DPC0P
TX2M_DPC0N

TXCDP_DPD3P
TXCDM_DPD3N

TX3P_DPD2P
TX3M_DPD2N

TX4P_DPD1P
TX4M_DPD1N

TX5P_DPD0P
TX5M_DPD0N

HSYNC
VSYNC

AVSSQ

VDD1DI
VSS1DI

R2/NC

R2B/NC

G2/NC

G2B/NC

B2/NC

B2B/NC

COMP/NC

H2SYNC/GENLK_CLK

V2SYNC/GENLK_VSYNC

VDD2DI/NC
VSS2DI/NC

A2VDD/NC

A2VDDQ/NC

A2VSSQ/TSVSSQ

R2SET/NC

DDC1CLK

DDC1DATA

AUX1P
AUX1N

DDC2CLK

DDC2DATA

AUX2P
AUX2N

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX5P

DDCDATA_AUX5N

DDC6CLK

DDC6DATA

DDCCLK_AUX7P

DDCDATA_AUX7N

RSET

AVDD

C/NC
Y/NC

R

RB

G

GB

B

BB

AU24
AV23

AT25
AR24

AU26
AV25

AT27
AR26

AR30
AT29

AV31
AU30

AR32
AT31

AT33
AU32

AU14
AV13

AT15
AR14

AU16
AV15

AT17
AR16

AU20
AT19

AT21
AR20

AU22
AV21

AT23
AR22

AD39
AD37

AE36
AD35

AF37
AE38

AC36
AC38

AB34
AD34

AE34
AC33

AC34

AC30
AC31

AD30
AD31

AF30
AF31

AC32
AD32
AF32

AD29
AC29

AG31
AG32

AG33
AD33
AF33

AA29

AM26
AN26

AM27
AL27

AM19
AL19

AN20
AM20

AL30
AM30

AL29
AM29

AN21
AM21

AJ30
AJ31

AK30
AK29

GPU_HDMI_TXC_DP

BI

GPU_HDMI_TXC_DN

BI

GPU_HDMI_TX0_DP

BI

GPU_HDMI_TX0_DN

BI

GPU_HDMI_TX1_DP

BI

GPU_HDMI_TX1_DN

BI

GPU_HDMI_TX2_DP

BI

GPU_HDMI_TX2_DN

BI

GPU_EDP_TX1_DP

BI

GPU_EDP_TX1_DN

BI

GPU_EDP_TX0_DP

BI

GPU_EDP_TX0_DN

BI

CLOSE TO GPU

2

2

R5194

R5196

1

150_1%_2

GPU_CRT_HSYNC

OUT

GPU_CRT_VSYNC

OUT

R5195

499_1%_2

2

1

GPU_PS1

OUT

R5037

2

1

0_5%_2_DY

R5038

2

1

0_5%_2_DY

1.8V,0.1A

R5039

2

1

0_5%_2_DY

R5040

2

1

0_5%_3_DY

R5041

2

1

715_1%_2_DY

Away from noisy GND area.

GPU_HDMI_DDCCLK

BI

GPU_HDMI_DDCDATA

BI

BI
BI

BI
BI

R5197

1

150_1%_2

OUT

GPU_PS2

P3V3_GPUS

3.3V,0.13A

GPU_PS3

OUT

GPU_EDP_AUX_DP
GPU_EDP_AUX_DN

GPU_CRT_DDCCLK
GPU_CRT_DDCDATA

CHANGE by

2

1

150_1%_2

Away from noisy GND area.

7 6 5 4 3

OUT

OUT

OUT

BEN LEE

XXX

GPU_CRT_R
GPU_CRT_G
GPU_CRT_B

AVDD

1

C5198

10UF_6.3V_3

2

VDD1D1

1

C5199

10UF_6.3V_3

2

DATE

1

HDMI

EDP

DUAL CHANNEL FOR 3D FUNCTION

CRT

I=0.07A

1

C5200

0.1UF_16V_2

2

I=0.045A

1

C5201

0.1UF_16V_2 1UF_6.3V_2

2

L5042

1

FBM_11_160808_121T

1

C5204

1UF_6.3V_2

2

Away from noisy GND area.

L5207

1

1

FBM_11_160808_121T

C5205

2

P1V8_GPUS

GPU_PS1
GPU_PS2
GPU_PS3

1

R5202

2

10K_5%_2_DY
IN
IN
IN

1

C5206

R5203

2

10K_5%_2_DY

1

R5208

2

1

1

R5209

2

2

0.1UF_16V_2_DY

FUTURE ASIC

GPU Multi Level Pin Straps feature

INVENTEC

TITLE

Everest Main Board

MODEL,PROJECT,FUNCTION

Block Diagram

SIZE

CODE

C

February 22, 2010

21-OCT-2002

2

CS

SHEET

P1V8_GPUS

2

P1V8_GPUS

2

0_5%_3_DY

1

C5210

2

10K_5%_2_DY

0.1UF_16V_2_DY

DOC.NUMBER

CS_1310AXXXXXX-MTR

1310xxxxx-0-0

1

1

FF

E

D

C

1

R5211

10K_5%_2_DY

2

1

1

C5213

R5212

2

2

10K_5%_2_DY

0.1UF_16V_2_DY

B

A

REV

A01

X01

1

9786

of

78

CHANNEL A

56

4

23

1

U5124

DDR2
GDDR3/GDDR5

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10

K10

L18
L20

L27
N12

AG12

M12
M27

AH12

G8
K9

G9
A8
C8
E8
A6
C6
E6
A5

2

2

2

2

VM_A0_ADA<0>
VM_A0_ADA<1>
VM_A0_ADA<2>
VM_A0_ADA<3>
VM_A0_ADA<4>
VM_A0_ADA<5>
VM_A0_ADA<6>
VM_A0_ADA<7>
VM_A0_ADA<8>
VM_A0_ADA<9>
VM_A0_ADA<10>
VM_A0_ADA<11>
VM_A0_ADA<12>
VM_A0_ADA<13>
VM_A0_ADA<14>
VM_A0_ADA<15>
VM_A0_ADA<16>
VM_A0_ADA<17>
VM_A0_ADA<18>
VM_A0_ADA<19>
VM_A0_ADA<20>
VM_A0_ADA<21>
VM_A0_ADA<22>
VM_A0_ADA<23>
VM_A0_ADA<24>
VM_A0_ADA<25>
VM_A0_ADA<26>
VM_A0_ADA<27>
VM_A0_ADA<28>
VM_A0_ADA<29>
VM_A0_ADA<30>
VM_A0_ADA<31>
VM_A1_ADA<0>
VM_A1_ADA<1>
VM_A1_ADA<2>
VM_A1_ADA<3>
VM_A1_ADA<4>
VM_A1_ADA<5>
VM_A1_ADA<6>
VM_A1_ADA<7>
VM_A1_ADA<8>
VM_A1_ADA<9>
VM_A1_ADA<10>
VM_A1_ADA<11>
VM_A1_ADA<12>
VM_A1_ADA<13>
VM_A1_ADA<14>
VM_A1_ADA<15>
VM_A1_ADA<16>
VM_A1_ADA<17>
VM_A1_ADA<18>
VM_A1_ADA<19>
VM_A1_ADA<20>
VM_A1_ADA<21>
VM_A1_ADA<22>
VM_A1_ADA<23>
VM_A1_ADA<24>
VM_A1_ADA<25>
VM_A1_ADA<26>
VM_A1_ADA<27>
VM_A1_ADA<28>
VM_A1_ADA<29>
VM_A1_ADA<30>
VM_A1_ADA<31>

R5045

1

243_1%_2

R5218

1

243_1%_2

R5219

1

243_1%_2

R5220

1

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

VM_A0_ADA<31..0>

BI

D

C C

P1V5_GPUS

1

R5043

2

1

R5214

2

40.2_1%_2

100_1%_2

C5216

MVREFDA_GPU

1

0.1UF_16V_2

2

VM_A1_ADA<31..0>

BI

R & CAPS CLOSE TO GPU

B B

P1V5_GPUS

1

R5044

R5215

40.2_1%_2

2

1

100_1%_2

2

C5217

MVREFSA_GPU

1

0.1UF_16V_2

2

P1V5_GPUS

R & CAPS CLOSE TO GPU

A A

DDR3

DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63

MVREFDA
MVREFSA

MEM_CALRN0
MEM_CALRN1
MEM_CALRN2

MEM_CALRP1
MEM_CALRP0
MEM_CALRP2

MAA1_5/MAA_13_BA2

MEMORY INTERFACE A

MAA1_6/MAA_14_BA0

MAA1_7/MAA_A15_BA1

GDDR5/DDR2/GDDR3

EDCA0_0/QSA_0/RDQSA_0
EDCA0_1/QSA_1/RDQSA_1
EDCA0_2/QSA_2/RDQSA_2
EDCA0_3/QSA_3/RDQSA_3
EDCA1_0/QSA_4/RDQSA_4
EDCA1_1/QSA_5/RDQSA_5
EDCA1_2/QSA_6/RDQSA_6
EDCA1_3/QSA_7/RDQSA_7

DDBIA0_0/QSA_0B/WDQSA_0
DDBIA0_1/QSA_1B/WDQSA_1
DDBIA0_2/QSA_2B/WDQSA_2
DDBIA0_3/QSA_3B/WDQSA_3
DDBIA1_0/QSA_4B/WDQSA_4
DDBIA1_1/QSA_5B/WDQSA_5
DDBIA1_2/QSA_6B/WDQSA_6
DDBIA1_3/QSA_7B/WDQSA_7

DDR2

GDDR5/GDDR3

DDR3

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8

MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12

WCKA0_0/DQMA_0

WCKA0B_0/DQMA_1

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

ADBIA0/ODTA0

ADBIA1/ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B
RASA1B

CASA0B
CASA1B

CSA0B_0
CSA0B_1

CSA1B_0
CSA1B_1

CKEA0
CKEA1

WEA0B
WEA1B

MAA0_8
MAA1_8

GDDR5

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

A32
C32
D23
E22
C14
A14
E10
D9

C34
D29
D25
E20
E16
E12
J10
D7

A34
E30
E26
C20
C16
C12
J11
F8

J21
G19

H27
G27

J14
H14

K23
K19

K20
K17

K24
K27

M13
K16

K21
J20

K26
L15

H23
J19

VM_A0_AA<0>
VM_A0_AA<1>
VM_A0_AA<2>
VM_A0_AA<3>
VM_A0_AA<4>
VM_A0_AA<5>
VM_A0_AA<6>
VM_A0_AA<7>
VM_A1_AA<0>
VM_A1_AA<1>
VM_A1_AA<2>
VM_A1_AA<3>
VM_A1_AA<4>
VM_A1_AA<5>
VM_A1_AA<6>
VM_A1_AA<7>

0

1
2
3
4
5
6
7
0

1
2
3
4
5
6
7

BI

BI

VM_WCKA0_0_DP

BI

VM_WCKA0_0_DN

BI

VM_WCKA0_1_DP

BI

VM_WCKA0_1_DN

BI

VM_WCKA1_0_DP

BI

VM_WCKA1_0_DN

BI

VM_WCKA1_1_DP

BI

VM_WCKA1_1_DN

BI

BI
BI
BI
BI
BI
BI
BI
BI

BI

VM_DDBIA0_0
VM_DDBIA0_1

BI

VM_DDBIA0_2

BI

VM_DDBIA0_3

BI
BI

VM_DDBIA1_0
VM_DDBIA1_1

BI

VM_DDBIA1_2

BI

VM_DDBIA1_3

BI

BI
BI

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT

OUT
OUT

OUT
OUT

BI
BI

VM_A0_AA<7..0>

VM_A1_AA<7..0>

VM_EDCA0_0
VM_EDCA0_1
VM_EDCA0_2
VM_EDCA0_3
VM_EDCA1_0
VM_EDCA1_1
VM_EDCA1_2
VM_EDCA1_3

VM_ADBIA0
VM_ADBIA1

DDR_A_CLKA0_DP
DDR_A_CLKA0_DN

DDR_A_CLKA1_DP
DDR_A_CLKA1_DN

DDR_A_RASA0#
DDR_A_RASA1#

DDR_A_CASA0#
DDR_A_CASA1#

DDR_A_CSA0#_0
DDR_A_CSA1#_0

DDR_A_CKEA0
DDR_A_CKEA1

DDR_A_WEA0#
DDR_A_WEA1#

VM_A0_AA<8>
VM_A1_AA<8>

243_1%_2

R5221

R5222

67

2

AMD_216_0810_001_FCBGA_962P

2

INVENTEC

TITLE

Everest Main Board

MODEL,PROJECT,FUNCTION

Block Diagram

CODE

SIZE

C

CHANGE by

45

XXX

3 2

BEN LEE

DATE

February 22, 2010

21-OCT-2002

CS

DOC.NUMBER

1310xxxxx-0-0

CS_1310AXXXXXX-MTR

SHEET

of

87 97

1 1

1

REV

X01

A01

1

243_1%_2

1

243_1%_2

8

D

78

56

4

23

1

CHANNEL B

U5124

DDR2
GDDR3/GDDR5
DDR3

DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63

MVREFDB
MVREFSB

MEMORY INTERFACE B

GDDR5/DDR2/GDDR3

EDCB0_0/QSB_0/RDQSB_0
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7

DDBIB0_0/QSB_0B/WDQSB_0
DDBIB0_1/QSB_1B/WDQSB_1
DDBIB0_2/QSB_2B/WDQSB_2
DDBIB0_3/QSB_3B/WDQSB_3
DDBIB1_0/QSB_4B/WDQSB_4
DDBIB1_1/QSB_5B/WDQSB_5
DDBIB1_2/QSB_6B/WDQSB_6
DDBIB1_3/QSB_7B/WDQSB_7

AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

Y12

AA12

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5

VM_B0_ADA<0>

VM_B0_ADA<31..0>

BI

D

C C

P1V5_GPUS

1

R5046

R5223

40.2_1%_2

2

1

2

100_1%_2

C5225

1

0.1UF_16V_2

2

VM_B1_ADA<31..0>

MVREFDB_GPU

BI

R & CAPS CLOSE TO GPU

B B

P1V5_GPUS

1

R5047

40.2_1%_2

2

MVREFSB_GPU

R5224

1

100_1%_2

2

C5226

1

0.1UF_16V_2

2

0

1
2
3
4
5
6
7
8
9

10

11

12

13

14

15

16

17

18

19
20
21
22
23
24
25
26
27
28
29
30
31
0

1
2
3
4
5
6
7
8
9

10

11

12

13

14

15

16

17

18

19
20
21
22
23
24
25
26
27
28
29
30
31

VM_B0_ADA<1>
VM_B0_ADA<2>
VM_B0_ADA<3>
VM_B0_ADA<4>
VM_B0_ADA<5>
VM_B0_ADA<6>
VM_B0_ADA<7>
VM_B0_ADA<8>
VM_B0_ADA<9>
VM_B0_ADA<10>
VM_B0_ADA<11>
VM_B0_ADA<12>
VM_B0_ADA<13>
VM_B0_ADA<14>
VM_B0_ADA<15>
VM_B0_ADA<16>
VM_B0_ADA<17>
VM_B0_ADA<18>
VM_B0_ADA<19>
VM_B0_ADA<20>
VM_B0_ADA<21>
VM_B0_ADA<22>
VM_B0_ADA<23>
VM_B0_ADA<24>
VM_B0_ADA<25>
VM_B0_ADA<26>
VM_B0_ADA<27>
VM_B0_ADA<28>
VM_B0_ADA<29>
VM_B0_ADA<30>
VM_B0_ADA<31>
VM_B1_ADA<0>
VM_B1_ADA<1>
VM_B1_ADA<2>
VM_B1_ADA<3>
VM_B1_ADA<4>
VM_B1_ADA<5>
VM_B1_ADA<6>
VM_B1_ADA<7>
VM_B1_ADA<8>
VM_B1_ADA<9>
VM_B1_ADA<10>
VM_B1_ADA<11>
VM_B1_ADA<12>
VM_B1_ADA<13>
VM_B1_ADA<14>
VM_B1_ADA<15>
VM_B1_ADA<16>
VM_B1_ADA<17>
VM_B1_ADA<18>
VM_B1_ADA<19>
VM_B1_ADA<20>
VM_B1_ADA<21>
VM_B1_ADA<22>
VM_B1_ADA<23>
VM_B1_ADA<24>
VM_B1_ADA<25>
VM_B1_ADA<26>
VM_B1_ADA<27>
VM_B1_ADA<28>
VM_B1_ADA<29>
VM_B1_ADA<30>
VM_B1_ADA<31>

R & CAPS CLOSE TO GPU

GPU_TESTEN

P3V3_GPUS

A A

JTAG SIGNAL STUFF OPTION

SIGNALS

GPU_TESTEN

8

NORMAL
MODE

0

JTAG
MODE

1

R5048

R5049

1

10K_5%_2_DY

2

1

5.11K_1%_2

2

1

C5227

2
1

R5050

2

DEBUG ONLY

1

C5228

R5051

0.1UF_16V_2_DY0.1UF_16V_2_DY

2
1

51_1%_2_DY51_1%_2_DY

2

67

AD28
AK10

AL10

TESTEN

CLKTESTA
CLKTESTB

AMD_216_0810_001_FCBGA_962P

PLACE ALL THESE COMPONENTS VERY CLOSE TO GPU (WITHIN

25MM) AND KEEP ALL COMPONENT CLOSE TO EACH OTHER.
(WITHIN 5MM) EXCEPT RSER2

45

DDR2

GDDR5/GDDR3

DDR3

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8

MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12

MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

WCKB0_0/DQMB_0

WCKB0B_0/DQMB_1

WCKB0_1/DQMB_2

WCKB0B_1/DQMB_3

WCKB1_0/DQMB_4

WCKB1B_0/DQMB_5

WCKB1_1/DQMB_6

WCKB1B_1/DQMB_7

ADBIB0/ODTB0

ADBIB1/ODTB1

CLKB0

CLKB0B

CLKB1

CLKB1B

RASB0B
RASB1B

CASB0B
CASB1B

CSB0B_0
CSB0B_1

CSB1B_0
CSB1B_1

CKEB0
CKEB1

WEB0B
WEB1B

MAB0_8
MAB1_8

GDDR5

DRAM_RST

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

H3
H1
T3
T5
AE4
AF5
AK6
AK5

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

T7
W7

L9
L8

AD8
AD7

T10
Y10

W10
AA10

P10
L10

AD10
AC10

U10
AA11

N10
AB11

T8
W8

AH11

CHANGE by

VM_B0_AA<0>
VM_B0_AA<1>
VM_B0_AA<2>
VM_B0_AA<3>
VM_B0_AA<4>
VM_B0_AA<5>
VM_B0_AA<6>
VM_B0_AA<7>
VM_B1_AA<0>
VM_B1_AA<1>
VM_B1_AA<2>
VM_B1_AA<3>
VM_B1_AA<4>
VM_B1_AA<5>
VM_B1_AA<6>
VM_B1_AA<7>

0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7

BI

BI

VM_WCKB0_0_DP

BI

VM_WCKB0_0_DN

BI

VM_WCKB0_1_DP

BI

VM_WCKB0_1_DN

BI

VM_WCKB1_0_DP

BI

VM_WCKB1_0_DN

BI

VM_WCKB1_1_DP

BI

VM_WCKB1_1_DN

BI

BI
BI
BI
BI
BI
BI
BI
BI

VM_DDBIB0_0

BI

VM_DDBIB0_1

BI

VM_DDBIB0_2

BI

VM_DDBIB0_3

BI

VM_DDBIB1_0

BI

VM_DDBIB1_1

BI

VM_DDBIB1_2

BI

VM_DDBIB1_3

BI

BI
BI

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT

OUT
OUT

OUT
OUT

BI
BI

XXX

1

R5052

2

BEN LEE

R5053

1

10_1%_2

5K_1%_2

VM_RESET_R2VM_RESET_R1

2

C5054

DATE

February 22, 2010

21-OCT-2002

3 2

VM_B0_AA<7..0>

VM_B1_AA<7..0>

VM_EDCB0_0
VM_EDCB0_1
VM_EDCB0_2
VM_EDCB0_3
VM_EDCB1_0
VM_EDCB1_1
VM_EDCB1_2
VM_EDCB1_3

VM_ADBIB0
VM_ADBIB1

DDR_B_CLKB0_DP
DDR_B_CLKB0_DN

DDR_B_CLKB1_DP
DDR_B_CLKB1_DN

DDR_B_RASB0#
DDR_B_RASB1#

DDR_B_CASB0#
DDR_B_CASB1#

DDR_B_CSB0#_0
DDR_B_CSB1#_0
DDR_B_CKEB0

DDR_B_CKEB1
DDR_B_WEB0#

DDR_B_WEB1#
VM_B0_AA<8>

VM_B1_AA<8>

R5055

1

1

51_1%_2

2

120PF_50V_2

2

INVENTEC

TITLE

CODE

SIZE

CS

C

VM_RESET

OUT

Everest Main Board

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

1310xxxxx-0-0

CS_1310AXXXXXX-MTR

SHEET

of

88 97

11

1

REV

X01

A01

D

8

7 6 5 4 3 2

1

P1V5_GPUS

GDDR5 900MHZ,1.5V,2.3A(PEAK)

1

1

1

C5234

C5237

2

1UF_6.3V_2

1

1

1

C5236

C5232

C5229

2

0.1UF_16V_2

STITCHING CAPS OPTION FOR MEM SIGNALS
THAT HAVE A CHANGE OF REFERENCE PLANE
VOLTAGE.ADD STITCHING CAPS WHEN REQUIRED,
ONE CAP PER THREE SIGNALS

2

2

0.1UF_16V_2

0.1UF_16V_2

C5240

2

2

1UF_6.3V_2

1

1

C5241

C5239

2

2

0.1UF_16V_2

E

P1V8_GPUS

1

L5230

2

PCIE_PVDD

FBM_11_160808_121T

1.8V,0.04A

1UF_6.3V_2

1

C5056

2

0.1UF_16V_2

1.8V,0.05A

1

C5238

C5242

2

10UF_6.3V_3

P1V0_GPU

1

2

FBM_11_160808_121T

D

C5231

P1V8_GPUS

FBM_11_160808_121T

C

B

1

2

1

C5235

2

10UF_6.3V_3

L5233

2

1

1UF_6.3V_2

0.1UF_16V_2

1UF_6.3V_2

1

C5246

C5244

C5245

L5243

1

2

1

2

1

2

1UF_6.3V_2

0.1UF_16V_2

P1V8_GPUS

P3V3_GPUS

P1V8_GPUS

P1V8_GPUS

0.1UF_16V_2

2

1UF_6.3V_2

10UF_6.3V_3

1

1

L5249

L5250

1

1

C5251

2

1UF_6.3V_2

1

C5252

2

10UF_6.3V_3

2

2

2

1

C5247

2

1

C5248

2

FBM_11_160808_121T

FBM_11_160808_121T

Follow GDDR3 ORB

FBM_11_160808_121T

L5057

1.0V,0.1A

1

C5253

2

1UF_6.3V_2

1

C5254

2

10UF_6.3V_3

1.8V,0.017A

1

C5255

2

10UF_6.3V_3

3.3V,0.06A

1

C5256

2

10UF_6.3V_3

1.8V,0.17A

1.8V,0.15A

1

C5257

2

10UF_6.3V_3

1

C5258

2

1

C5259

2

1

C5265

2

1UF_6.3V_2

1

C5266

2

10UF_6.3V_3

1

C5270

2

1UF_6.3V_2

1

C5271

2

10UF_6.3V_3

VDD_CT

1

C5261

2

1

C5262

2

1

C5059

1UF_6.3V_2

C5272

2

0.1UF_16V_2

1

C5273

C5268

2

1UF_6.3V_2

1UF_6.3V_2

VDDR4

1

C5263

2

1

C5269

C5274

2

10UF_6.3V_3

1UF_6.3V_2

MVP18

1

C5058

C5264

2

1UF_6.3V_2

1

1

C5060

2

2

1UF_6.3V_2

0.1UF_16V_2

SPV18
SPV10

1

C5260

2

1

C5267

2

10UF_6.3V_3

1UF_6.3V_2

VOLTAGE SENESE
WAITING POWER DESIGN

GPU POWER

U5124

MEM I/O

AC7
AF7
AJ7

AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10

K11
K13

L12
L16
L21
L23
L26

M11
N11

R11
U11

Y11

M20
M21

V12
U12

AN9

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15

J7

VDDR1#16

J9

VDDR1#17
VDDR1#18
VDDR1#19

K8

VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25

L7

VDDR1#26
VDDR1#27
VDDR1#28

P7

VDDR1#29
VDDR1#30
VDDR1#31

U7

VDDR1#32
VDDR1#33

Y7

VDDR1#34

LEVEL
TRANSLATION

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

I/O

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8

VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6

NC_VDDRHA
NC_VSSRHA

NC_VDDRHB
NC_VSSRHB

PLL

H7

MPV18#1

H8

MPV18#2

SPV18

SPV10

SPVSS

VOLTAGE
SENESE

FB_VDDC

FB_VDDCI

FB_GND

AD11

1UF_6.3V_2

AG10

10UF_6.3V_3

1

AF26
AF27

2

1

2

1

2

C5276

1

C5275

2

AG26
AG27

1UF_6.3V_2

AF23
AF24
AG23
AG24

AF13

1UF_6.3V_2

AF15
AG13
AG15

AD12
AF11
AF12
AG11

1UF_6.3V_2

1

2

0.1UF_16V_2

AM10

AN10

0.1UF_16V_2

AF28

AG28

AH29

PCIE

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8

PCIE_VDDR/PCIE_PVDD

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8

PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

CORE

VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19

POWER

VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32

VDDC/BIF_VDDC#33

VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41

VDDC/BIF_VDDC#42

VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8

VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
VDDCI#15
VDDCI#16

ISOLATED

CORE I/O

VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9

AA31
AA32
AA33
AA34
V28
W29
W30
Y31
AB37

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

1.8V,0.04A

C5063

PCIE_PVDD

C5062

1

C5282

2

1

C5283

2

1

C5284

2

1

C5061

2

1

C5281

2

1

2

1

1

C5064

2

1UF_6.3V_2

2

1

C5288

2

1UF_6.3V_2

1UF_6.3V_2

1

C5289

1UF_6.3V_2

1UF_6.3V_2

2

1

C5290

1UF_6.3V_210UF_6.3V_3

1UF_6.3V_2

2

1

C5291

2

10UF_6.3V_3

BIF_VDDC

1

C5287

2

1UF_6.3V_2

1UF_6.3V_2

1.8V,0.44A

C5297

1

0.1UF_16V_2

2

1

C5065

2

1.0V,1.1A

1

C5298

2

1UF_6.3V_2

1UF_6.3V_2

C5304

1

2

1UF_6.3V_2

VDDC+VDDCI=43.3A(PEAK)

1

C5293

2

1

C5294

2

1

C5295

2

1

C5296

2

BIF_VDDC IS SEPARATE CORE
POWER FOR THE PCIE BUS LOGIC.

1

C5300

2

1UF_6.3V_2

1

C5301

1UF_6.3V_2

2

1

C5302

1UF_6.3V_2

2

1

C5303

2

10UF_6.3V_3

1

C5305

2

1UF_6.3V_2

1

C5306

1UF_6.3V_2

2

1

C5307

1UF_6.3V_2

2

1

C5308

2

10UF_6.3V_3

C5310

1UF_6.3V_2

1UF_6.3V_2

10UF_6.3V_3 1UF_6.3V_2

PCIE_VDDR

1

C5316

1UF_6.3V_2

2

1

2

1UF_6.3V_2

1

C5312

2

1UF_6.3V_2

1

C5313

2

1

C5314

2

1

C5315

2

C5318

1UF_6.3V_2

1UF_6.3V_2

10UF_6.3V_3

1

C5066

1UF_6.3V_21UF_6.3V_20.1UF_16V_2

2

1UF_6.3V_2

1UF_6.3V_2

10UF_6.3V_3

C5328

C5324

1

2

1UF_6.3V_2

1

2

1UF_6.3V_2

1

C5325

1UF_6.3V_2

2

1

C5326

1UF_6.3V_2

2

1

C5327

2

10UF_6.3V_3

1

2

1UF_6.3V_2

1

C5319

2

1UF_6.3V_2

1

C5320

2

1

C5321

2

1

C5322

2

1

C5334

2

1

C5335

2

1

C5330

2

1

C5331

2

1

C5332

2

1

C5333

2

PVCORE_GPU

P1V8_GPUS

L5336

2

1

BLM18PG600SN1D

10UF_6.3V_3

P1V0_GPU

10UF_6.3V_3

PVCORE_GPU

1

C5338

2

1UF_6.3V_2

1

C5339

1UF_6.3V_2

2

1

C5337

1UF_6.3V_2

2

1

C5340

2

10UF_6.3V_3

FF

1UF_6.3V_2

E

1UF_6.3V_2

1UF_6.3V_2

D

10UF_6.3V_3

C

VDDC+VDDCI=43.3A(PEAK)

AMD_216_0810_001_FCBGA_962P

1

C5277

2

1

C5279

2

1UF_6.3V_2

1

C5285

2

1UF_6.3V_2

1

C5292

2

1UF_6.3V_2

1

C5299

2

1UF_6.3V_2

1UF_6.3V_2

1

C5309

2

1

C5311

2

1UF_6.3V_2

1

C5317

2

1UF_6.3V_2

1

C5323

2

1UF_6.3V_2

1

B

C5329

2

1UF_6.3V_2

1UF_6.3V_2

1

C5278

2

A

1

C5280

2

10UF_6.3V_3

1

C5286

2

10UF_6.3V_3

10UF_6.3V_3

A

INVENTEC

TITLE

Everest Main Board

MODEL,PROJECT,FUNCTION

Block Diagram

SIZE

CODE

February 22, 2010

8

7 6 5 4 3

CHANGE by

BEN LEE

XXX

DATE

21-OCT-2002

2

C

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

1310xxxxx-0-0

1

1

REV

A01

X01

1

9789

of

8

7 6 5 4 3 2

1

U5124

FF

AB39

E

D

C

B

E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33

J27

K14
L11

L17
L22

L24
M17

M22
M24
N16
N18

N21
N23
N26

R15
R17

R20
R22
R24
R27

T11
T13
T16
T18
T21
T23
T26
U15
U17

U20
U22
U24
U27

V11
V16
V18
V21
V23
V26

Y15
Y17
Y20
Y22
Y24
Y27
U13
V13

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35

GND

GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109

F7

GND#110

F9

GND#111

G2

GND#112

G6

GND#113

H9

GND#114

J2

GND#115
GND#116

J6

GND#117

J8

GND#118
GND#119

K7

GND#120
GND#121
GND#122

L2

GND#123
GND#124
GND#125

L6

GND#126
GND#127
GND#128
GND#129
GND#130
GND#131

N2

GND#132
GND#133
GND#134
GND#135

N6

GND#136
GND#137
GND#138

R2

GND#139
GND#140
GND#141
GND#142
GND#143

R6

GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154

U2

GND#155
GND#156
GND#157
GND#158
GND#159

U6

GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167

W2

GND#168

W6

GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162

GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60

GND/PX_EN#61

GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

AMD_216_0810_001_FCBGA_962P

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

A39
AW1
AW39

BACO

P3V3_S

1

10K_5%_2

IN

IN

IN

C5345

P3V3_GPUS

1

G

2

1

10K_5%_2

R5344

2

3

DS

Q5343

SSM3K7002BFU

2

R5342

Q5341

PX_EN

1

G

SSM3K7002BFU

DGPU_PWR_EN#

VPCIE_ON

VDDC_ON

1

2

3

DS

2

0.1UF_16V_2

PX_EN#

ALPHA_AO3416_SOT23_3P

1
2

PVCORE_GPU

P3V3_S

5

U5067

+

-

TC7SZ08FU

3

R5068

1

0_5%_2_DY

Q5070

AM2302N

Q5069

G

DGPU_PWROK

VDDC_GPU_PG

4

2

P1V0_GPU

2

1

G

D S

3

D

D

G

G

S D

S

S

C5346

C5347

2

4.7UF_6.3V_3

1

1

4.7UF_6.3V_3

2

P3V3_S

1

C5348

0.1UF_16V_2

2

OUT

R5071

0_5%_2

1

IN

2

PX_MODE

OUT

PX_MODE

PX_MODE=0, FOR BACO MODE
PX_MODE=1, FOR NORMAL MODE

1
2

5

U5349

+

-

TC7SZ08FU

3

4

BIF_VDDC

R5350

1

2

0_5%_3_DY

R5352

1

G

1

1K_5%_2

2

3

DS

Q5351

SSM3K7002BFU

2

PVCORE_GPU

P5V_S

R5353

1

G

1

1K_5%_2

2

3

DS

Q5072

SSM3K7002BFU

2

OUT

VDDC_ON

OUT

VPCIE_ON

E

D

C

B

A

A

INVENTEC

TITLE

Everest Main Board

MODEL,PROJECT,FUNCTION

Block Diagram

SIZE

CODE

February 22, 2010

8

7 6 5 4 3

CHANGE by

BEN LEE

XXX

DATE

21-OCT-2002

2

C

DOC.NUMBER

CS

CS_1310AXXXXXX-MTR1A01

SHEET

1310xxxxx-0-0

1

REV

X01

1

9790

of

78

56

4

23

1

U5124

LVDS CONTROL

D

LVTMDP

C C

VARY_BL

DIGON

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

TXOUT_U3P
TXOUT_U3N

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

TXOUT_L3P
TXOUT_L3N

AK27
AJ27

AK35
AL36

AJ38
AK37

AH35
AJ36

AG38
AH37

AF35
AG36

AP34
AR34

AW37
AU35

AR37
AU39

AP35
AR35

AN36
AP37

DPCD_VDD10 DPCD_VDD18

DPCD_VDD10

DPCD_VDD18

DPEF_VDD10 DPEF_VDD18

DP C/D POWER

AP20
AP21

AP13
AT13

AN17
AP16
AP17
AW14
AW16

AP22
AP23

AP14
AP15

AN19
AP18
AP19
AW20
AW22

R5382

1

150_1%_2 150_1%_2

2

AW18

AH34
AJ34

DPCD/DPC_VDD18#1
DPCD/DPC_VDD18#2

DPCD/DPC_VDD10#1
DPCD/DPC_VDD10#2

DP/DPC_VSSR#1
DP/DPC_VSSR#2
DP/DPC_VSSR#3
DP/DPC_VSSR#4
DP/DPC_VSSR#5

DPCD/DPD_VDD18#1
DPCD/DPD_VDD18#2

DPCD/DPD_VDD10#1
DPCD/DPD_VDD10#2

DP/DPD_VSSR#1
DP/DPD_VSSR#2
DP/DPD_VSSR#3
DP/DPD_VSSR#4
DP/DPD_VSSR#5

DPCD_CALR

DP E/F POWER

DPEF/DPE_VDD18#1
DPEF/DPE_VDD18#2

U5124

DP A/B POWER

DPAB/DPA_VDD18#1
DPAB/DPA_VDD18#2

DPAB/DPA_VDD10#1
DPAB/DPA_VDD10#2

DP/DPA_VSSR#1
DP/DPA_VSSR#2
DP/DPA_VSSR#3
DP/DPA_VSSR#4
DP/DPA_VSSR#5

DPAB/DPB_VDD18#1
DPAB/DPB_VDD18#2

DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2

DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
DP/DPB_VSSR#4
DP/DPB_VSSR#5

DPAB_CALR

DP PLL POWER

DPAB_VDD18/DPA_PVDD

DP_VSSR/DPA_PVSS

AN24
AP24

AP31
AP32

AN27
AP27
AP28
AW24
AW26

AP25
AP26

AN33
AP33

AN29
AP29
AP30
AW30
AW32

AW28

AU28
AV27

1

R5384

DPAB_VDD18

DPAB_VDD10

DPAB_VDD18

DPAB_VDD10

2

DPAB_VDD18

DPAB_VDD18

D

AMD_216_0810_001_FCBGA_962P

1

2

10UF_6.3V_3

1

2

10UF_6.3V_3

1

2

10UF_6.3V_3

DPCD_VDD10

1.0V,0.33A

1

C5376

2

1UF_6.3V_2

DPAB_VDD10DPCD_VDD18

1.0V,0.33A

1

C5377

2

1UF_6.3V_2

DPEF_VDD10

1.0V,0.22A

1

C5378

2

1UF_6.3V_2

1

DPEF_VDD10

DPEF_VDD18

C5379

2

0.1UF_16V_20.1UF_16V_2

R5073

2

0_5%_2

1

1

R5383

2

150_1%_2

C5380

2

0.1UF_16V_2

1

C5381

2

45

P1V8_GPUS

DPAB_VDD18

P1V0_GPU

1.8V,0.33A

1

B B

2

2

2

C5359

2

10UF_6.3V_3

L5355

L5354

1

BLM18PG181SN1D

L5357

1

1

BLM18PG181SN1D_DY

BLM18PG181SN1D_DY

1

C5362

2

1UF_6.3V_2

1

C5365

2

2

2

C5373

2

0.1UF_16V_20.1UF_16V_2
L5369

L5368

1

BLM18PG181SN1D

L5371

1

1

BLM18PG181SN1D_DY

BLM18PG181SN1D_DY

1.8V,0.33A

1

C5360

A A

2

R5356

1

2

R5358

0_1%_3

0_1%_3

1

2

10UF_6.3V_3

1

C5363

2

1UF_6.3V_2

DPEF_VDD18

1

C5366

2

2

2

C5374

0.1UF_16V_2
R5370

1

R5372

0_1%_3

0_1%_3

1

1.8V,0.33A

40MILL 40MILL

1

C5361

2

10UF_6.3V_3

8

1

C5364

2

1UF_6.3V_2

1

C5367

C5375

2

67

AL33
AM33

AN34
AP39
AR39
AU37

AF34
AG34

AK33
AK34

AF39
AH39
AK39
AL34
AM34

1

AM39

P1V8_GPUS

1

R5074

2
1

R5075

2

DPEF/DPE_VDD10#1
DPEF/DPE_VDD10#2

DP/DPE_VSSR#1
DP/DPE_VSSR#2
DP/DPE_VSSR#3
DP/DPE_VSSR#4

DPEF/DPF_VDD18#1
DPEF/DPF_VDD18#2

DPEF/DPF_VDD10#1
DPEF/DPF_VDD10#2

DP/DPF_VSSR#1
DP/DPF_VSSR#2
DP/DPF_VSSR#3
DP/DPF_VSSR#4
DP/DPF_VSSR#5

DPEF_CALR

DPAB_VDD18/DPB_PVDD

DPCD_VDD18/DPC_PVDD

DPCD_VDD18/DPD_PVDD

DPEF_VDD18/DPE_PVDD

DPEF_VDD18/DPF_PVDD

AMD_216_0810_001_FCBGA_962P

FUTURE ASIC

10K_5%_2_DY

1

10K_5%_2_DY

CHANGE by

C5076

XXX

3 2

0.1UF_16V_2_DY

2

BEN LEE

DP_VSSR/DPB_PVSS

DP_VSSR/DPC_PVSS

DP_VSSR/DPD_PVSS

DP_VSSR/DPE_PVSS

DP_VSSR/DPF_PVSS

DATE

February 22, 2010

21-OCT-2002

AV29
AR28

AU18
AV17

AV19
AR18

AM37
AN38

AL38
AM35

DPCD_VDD18

DPCD_VDD18

DPEF_VDD18

DPEF_VDD18

PS_0: BALL AM34

ADD THESE BOM OPTIONS TO
SUPPORT FUTURE GPU MULTI
LEVEL PIN STRAPS FEATURE.

INVENTEC

TITLE

Everest Main Board

MODEL,PROJECT,FUNCTION

Block Diagram

SIZE

CODE

C

CS

DOC.NUMBER

1310xxxxx-0-0

CS_1310AXXXXXX-MTR

SHEET

91

1 1

of

1

97

REV

X01

A01

E

D

DDR_A_CLK0_DN
DDR_A_CLK0_DP

P1V5_GPUS

C

1

2

R5079

1

R5080

2

8

VM_A0_ADA<31..0>

VM_A0_AA<8>
VM_A0_AA<7..0>

P1V5_GPUS

1

1

R5456

R5455

60.4_1%_2

2

2

P1V5_GPUS

R5083

1

1

C5081

2

2

R5457

1UF_6.3V_2_DY

2.37K_1%_25.49K_1%_2

1

1

C5082

R5458

2

2

1UF_6.3V_2

7 6 5 4 3 2

DQ31|DQ7
DQ30|DQ6
DQ29|DQ5
DQ28|DQ4
DQ27|DQ3
DQ26|DQ2
DQ25|DQ1
DQ24|DQ0
DQ23|DQ15
DQ22|DQ14
DQ21|DQ13
DQ20|DQ12
DQ19|DQ11
DQ18|DQ10
DQ17|DQ9
DQ16|DQ8
DQ15|DQ23
DQ14|DQ22
DQ13|DQ21
DQ12|DQ20
DQ11|DQ19
DQ10|DQ18
DQ9|DQ17
DQ8|DQ16
DQ7|DQ31
DQ6|DQ30
DQ5|DQ29
DQ4|DQ28
DQ3|DQ27
DQ2|DQ26
DQ1|DQ25
DQ0|DQ24

RFU/A12/NC
A7/A8|A0/A10
A6/A11|A1/A9
A5/BA1|A3/BA3
A4/BA2|A2/BA0
A3/BA3|A5/BA1
A2/BA0|A4/BA2
A1/A9|A6/A11
A0/A10|A7/A8

WCK01|WCK23
WCK01#|WCK23#

WCK23|WCK01
WCK23#|WCK01#

EDC3|EDC0
EDC2|EDC1
EDC1|EDC2
EDC0|EDC3

DBI3#|DBI0#
DBI2#|DBI1#
DBI1#|DBI2#
DBI0#|DBI3#

RAS#|CAS#
CAS#|RAS#

CKE#
CK#
CK

CS#|WE#
WE#|CS#

ZQ
SEN

RESET#
MF

Vpp,NC
Vpp,NC1

VREFD1
VREFD2

VREFC

ABI#

U5089

VDDQ-B1

VDDQ-B3
VDDQ-B12
VDDQ-B14

VDDQ-D1

VDDQ-D3
VDDQ-D12
VDDQ-D14

VDDQ-E5
VDDQ-E10

VDDQ-F1

VDDQ-F3
VDDQ-F12
VDDQ-F14

VDDQ-G2
VDDQ-G13

VDDQ-H3
VDDQ-H12

VDDQ-K3
VDDQ-K12

VDDQ-L2
VDDQ-L13

VDDQ-M1

VDDQ-M3
VDDQ-M12
VDDQ-M14

VDDQ-N5
VDDQ-N10

VDDQ-P1

VDDQ-P3
VDDQ-P12
VDDQ-P14

VDDQ-T1

VDDQ-T3
VDDQ-T12
VDDQ-T14

VDD-C5
VDD-C10
VDD-D11

VDD-G1

VDD-G4
VDD-G11
VDD-G14

VDD-L1

VDD-L4
VDD-L11
VDD-L14
VDD-P11

VDD-R5
VDD-R10

VSSQ-A1
VSSQ-A3

VSSQ-A12
VSSQ-A14

VSSQ-C1
VSSQ-C3
VSSQ-C4

VSSQ-C11
VSSQ-C12
VSSQ-C14

VSSQ-E1
VSSQ-E3

VSSQ-E12
VSSQ-E14

VSSQ-F5

VSSQ-F10

VSSQ-H2

VSSQ-H13

VSSQ-K2

VSSQ-K13

VSSQ-M5

VSSQ-M10

VSSQ-N1
VSSQ-N3

VSSQ-N12
VSSQ-N14

VSSQ-R1
VSSQ-R3
VSSQ-R4

VSSQ-R11
VSSQ-R12
VSSQ-R14

VSSQ-V1
VSSQ-V3

VSSQ-V12
VSSQ-V14

VSS-B5
VSS-B10
VSS-D10

VSS-G5
VSS-G10

VSS-H1
VSS-H14

VSS-K1
VSS-K14

VSS-L5
VSS-L10
VSS-P10

VSS-T5
VSS-T10

VM_A0_ADA<30>

BI

BI
BI

60.4_1%_2

BI
BI

0_5%_2_DY

2

1

30

VM_A0_ADA<26>

26

VM_A0_ADA<29>

29

VM_A0_ADA<27>

27

VM_A0_ADA<31>

31

VM_A0_ADA<25>

25

VM_A0_ADA<28>

28

VM_A0_ADA<24>

24

VM_A0_ADA<16>

16

VM_A0_ADA<20>

20

VM_A0_ADA<17>

17

VM_A0_ADA<21>

21

VM_A0_ADA<18>

18

VM_A0_ADA<22>

22

VM_A0_ADA<19>

19

VM_A0_ADA<23>

23

VM_A0_ADA<5>

5

VM_A0_ADA<6>

6

VM_A0_ADA<3>

3

VM_A0_ADA<7>

7

VM_A0_ADA<4>

4

VM_A0_ADA<2>

2

VM_A0_ADA<1>

1

VM_A0_ADA<0>

0

VM_A0_ADA<11>

11

VM_A0_ADA<10>

10

VM_A0_ADA<8>

8

VM_A0_ADA<9>

9

VM_A0_ADA<12>

12

VM_A0_ADA<14>

14

VM_A0_ADA<13>

13

VM_A0_ADA<15>

15

VM_A0_AA<7>

7

VM_A0_AA<6>

6

VM_A0_AA<5>

5

VM_A0_AA<4>

4

VM_A0_AA<3>

3

VM_A0_AA<2>

2

VM_A0_AA<1>

1

VM_A0_AA<0>

0

VM_WCKA0_0_DP
VM_WCKA0_0_DN

VM_WCKA0_1_DP
VM_WCKA0_1_DN

VM_EDCA0_3
VM_EDCA0_2
VM_EDCA0_0
VM_EDCA0_1

VM_DDBIA0_3
VM_DDBIA0_2
VM_DDBIA0_0
VM_DDBIA0_1

DDR_A_RASA0#
DDR_A_CASA0#

DDR_A_CKEA0

DDR_A_CSA0#_0
DDR_A_WEA0#

R5087

2

R5088

2

VM_RESET

BI
BI

BI
BI

BI
BI
BI
BI

BI
BI
BI
BI

BI
BI

BI

BI
BI

120_1%_2

1

0_5%_2

1

BI

P1V5_GPUSP1V5_GPUS

1

C5460

2

R5084

1UF_6.3V_2_DY

1

C5461

R5085

2

1UF_6.3V_2

5.49K_1%_2 2.37K_1%_2

1

1

C5464

2

2

1

1UF_6.3V_2_DY

1

VM_REFD1_A0
VM_REFD2_A0
VM_REFDC_A0

VM_ADBIA0

C5086

2

2

1UF_6.3V_2

5.49K_1%_2 2.37K_1%_2

M2
M4
N2
N4
T2
T4
V2

V4
M13
M11
N13
N11
T13
T11
V13
V11
F13
F11
E13
E11
B13
B11
A13
A11

F2

F4

E2

E4

B2

B4

A2

A4

J5

K4

K5
K10
K11
H10
H11

H5

H4

D4

D5

P4

P5

R2
R13
C13

C2

P2
P13
D13

D2

G3

L3

J3
J11
J12

G12
L12

J13
J10

J2

J1

A5

V5
A10

V10

J14

J4

BI

HYNIX_H5GQ2H24MFR_T2C_BGA_170P

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

P1V5_GPUS

VM_A1_ADA<31..0>

GDDR5
CHANNEL A MEMORY

VM_A1_AA<8>
VM_A1_AA<7..0>

P1V5_GPUS

1

1

R5485

R5489

2

2

60.4_1%_2

60.4_1%_2

DDR_A_CLK1_DN
DDR_A_CLK1_DP

BI
BI

P1V5_GPUS

1

2

R5090

2.37K_1%_2

1

R5481

2

5.49K_1%_2

C5483

C5484

P1V5_GPUS

R5091

2

P1V5_GPUS P1V5_GPUS

1

1

C5491

2

2

R5487

1UF_6.3V_2_DY

2.37K_1%_25.49K_1%_2

1

1

C5492

R5488

2

2

1UF_6.3V_2

BI

BI
BI

VM_WCKA1_1_DP
VM_WCKA1_1_DN

VM_WCKA1_0_DP
VM_WCKA1_0_DN

DDR_A_WEA1#
DDR_A_CSA1#_0

0_5%_2_DY

1

1

2

R5494

1UF_6.3V_2_DY

1

R5495

2

1UF_6.3V_2

VM_A1_ADA<5>

5

VM_A1_ADA<6>

6

VM_A1_ADA<4>

4

VM_A1_ADA<7>

7

VM_A1_ADA<3>

3

VM_A1_ADA<2>

2

VM_A1_ADA<1>

1

VM_A1_ADA<0>

0

VM_A1_ADA<11>

11

VM_A1_ADA<10>

10

VM_A1_ADA<8>

8

VM_A1_ADA<9>

9

VM_A1_ADA<12>

12

VM_A1_ADA<14>

14

VM_A1_ADA<13>

13

VM_A1_ADA<15>

15

VM_A1_ADA<31>

31

VM_A1_ADA<24>

24

VM_A1_ADA<30>

30

VM_A1_ADA<26>

26

VM_A1_ADA<29>

29

VM_A1_ADA<25>

25

VM_A1_ADA<28>

28

VM_A1_ADA<27>

27

VM_A1_ADA<18>

18

VM_A1_ADA<21>

21

VM_A1_ADA<17>

17

VM_A1_ADA<22>

22

VM_A1_ADA<19>

19

VM_A1_ADA<23>

23

VM_A1_ADA<16>

16

VM_A1_ADA<20>

20

VM_A1_AA<0>

0

VM_A1_AA<1>

1

VM_A1_AA<3>

3

VM_A1_AA<2>

2

VM_A1_AA<5>

5

VM_A1_AA<4>

4

VM_A1_AA<6>

6

VM_A1_AA<7>

7

VM_EDCA1_0
VM_EDCA1_1
VM_EDCA1_3
VM_EDCA1_2

VM_DDBIA1_0
VM_DDBIA1_1
VM_DDBIA1_3
VM_DDBIA1_2

DDR_A_CASA1#
DDR_A_RASA1#

DDR_A_CKEA1

R5092
R5093

VM_RESET

1

1

1UF_6.3V_2_DY

C5496

2

2

2.37K_1%_2

1

2

5.49K_1%_2

1

C5497

2

VM_REFD1_A1
VM_REFD2_A1
VM_REFDC_A1

VM_ADBIA1

1UF_6.3V_2

M2
M4
N2
N4
T2
T4
V2

V4
M13
M11
N13
N11
T13
T11
V13
V11
F13
F11
E13
E11
B13
B11
A13
A11

F2

F4

E2

E4

B2

B4

A2

A4

J5

K4

K5
K10
K11
H10
H11

H5

H4

BI
BI

BI
BI

BI
BI
BI
BI

BI
BI
BI
BI

BI
BI

BI

BI
BI

120_1%_2

2

0_5%_2

2

BI

D4

D5

P4

P5

R2
R13
C13

C2

P2
P13
D13

D2

G3

L3

J3
J11
J12

G12
L12

1

J13
J10

1

J2

J1

A5

V5
A10

V10

J14

J4

BI

HYNIX_H5GQ2H24MFR_T2C_BGA_170P

DQ31|DQ7
DQ30|DQ6
DQ29|DQ5
DQ28|DQ4
DQ27|DQ3
DQ26|DQ2
DQ25|DQ1
DQ24|DQ0
DQ23|DQ15
DQ22|DQ14
DQ21|DQ13
DQ20|DQ12
DQ19|DQ11
DQ18|DQ10
DQ17|DQ9
DQ16|DQ8
DQ15|DQ23
DQ14|DQ22
DQ13|DQ21
DQ12|DQ20
DQ11|DQ19
DQ10|DQ18
DQ9|DQ17
DQ8|DQ16
DQ7|DQ31
DQ6|DQ30
DQ5|DQ29
DQ4|DQ28
DQ3|DQ27
DQ2|DQ26
DQ1|DQ25
DQ0|DQ24

RFU/A12/NC
A7/A8|A0/A10
A6/A11|A1/A9
A5/BA1|A3/BA3
A4/BA2|A2/BA0
A3/BA3|A5/BA1
A2/BA0|A4/BA2
A1/A9|A6/A11
A0/A10|A7/A8

WCK01|WCK23
WCK01#|WCK23#

WCK23|WCK01
WCK23#|WCK01#

EDC3|EDC0
EDC2|EDC1
EDC1|EDC2
EDC0|EDC3

DBI3#|DBI0#
DBI2#|DBI1#
DBI1#|DBI2#
DBI0#|DBI3#

RAS#|CAS#
CAS#|RAS#

CKE#
CK#
CK

CS#|WE#
WE#|CS#

ZQ
SEN

RESET#
MF

Vpp,NC
Vpp,NC1

VREFD1
VREFD2

VREFC

ABI#

U5094

VDDQ-B1

VDDQ-B3
VDDQ-B12
VDDQ-B14

VDDQ-D1

VDDQ-D3
VDDQ-D12
VDDQ-D14

VDDQ-E5
VDDQ-E10

VDDQ-F1

VDDQ-F3
VDDQ-F12
VDDQ-F14

VDDQ-G2
VDDQ-G13

VDDQ-H3
VDDQ-H12

VDDQ-K3
VDDQ-K12

VDDQ-L2
VDDQ-L13

VDDQ-M1

VDDQ-M3
VDDQ-M12
VDDQ-M14

VDDQ-N5
VDDQ-N10

VDDQ-P1

VDDQ-P3
VDDQ-P12
VDDQ-P14

VDDQ-T1

VDDQ-T3
VDDQ-T12
VDDQ-T14

VDD-C5
VDD-C10
VDD-D11

VDD-G1

VDD-G4
VDD-G11
VDD-G14

VDD-L1

VDD-L4
VDD-L11
VDD-L14
VDD-P11

VDD-R5
VDD-R10

VSSQ-A1
VSSQ-A3

VSSQ-A12
VSSQ-A14

VSSQ-C1
VSSQ-C3
VSSQ-C4

VSSQ-C11
VSSQ-C12
VSSQ-C14

VSSQ-E1
VSSQ-E3

VSSQ-E12
VSSQ-E14

VSSQ-F5

VSSQ-F10

VSSQ-H2

VSSQ-H13

VSSQ-K2

VSSQ-K13

VSSQ-M5

VSSQ-M10

VSSQ-N1
VSSQ-N3

VSSQ-N12
VSSQ-N14

VSSQ-R1
VSSQ-R3
VSSQ-R4

VSSQ-R11
VSSQ-R12
VSSQ-R14

VSSQ-V1
VSSQ-V3

VSSQ-V12
VSSQ-V14

VSS-B5
VSS-B10
VSS-D10

VSS-G5
VSS-G10

VSS-H1
VSS-H14

VSS-K1
VSS-K14

VSS-L5
VSS-L10
VSS-P10

VSS-T5
VSS-T10

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

1

P1V5_GPUS

FF

E

D

C

B

1

1

C5453

C5454

2

2

10UF_6.3V_3

1

1

C5459

1UF_6.3V_2

C5462

2

2

1UF_6.3V_2

1

1

C5463

C5465

2

1UF_6.3V_2

2

1UF_6.3V_2

1

C5466

2

1UF_6.3V_2

1

C5467

2

1UF_6.3V_2

1UF_6.3V_2

P1V5_GPUS

1

1

C5468

2

1

C5471

C5470

C5469

2

1UF_6.3V_2

0.1UF_16V_2

2

2

0.1UF_16V_2

1

1

1

C5473

C5472

0.1UF_16V_2

2

2

0.1UF_16V_2

1

C5474

2

0.1UF_16V_2

1

C5475

2

0.1UF_16V_2

1

C5476

2

0.1UF_16V_2

1

1

1

1

C5477

C5478

C5479

2

2

1UF_6.3V_2

0.1UF_16V_2

10UF_6.3V_3

C5480

2

2

1UF_6.3V_2

1

1

C5482

1UF_6.3V_2

C5486

2

2

1UF_6.3V_2

1

C5490

2

1UF_6.3V_2

1

C5493

2

1UF_6.3V_2

1UF_6.3V_2

A

C5498

1

2

P1V5_GPUS

1UF_6.3V_2

B

1

1

C5499

C5500

2

0.1UF_16V_2

1

1

C5501

2

2

0.1UF_16V_2

1

C5503

C5502

0.1UF_16V_2

2

2

0.1UF_16V_2

1

C5504

2

0.1UF_16V_2

1

C5505

2

0.1UF_16V_2

1

C5506

2

0.1UF_16V_2

0.1UF_16V_2

A

INVENTEC

TITLE

Everest Main Board

MODEL,PROJECT,FUNCTION

Block Diagram

SIZE

CODE

February 22, 2010

8

7 6 5 4 3

CHANGE by

BEN LEE

XXX

DATE

21-OCT-2002

2

C

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

1310xxxxx-0-0

1

1

REV

A01

X01

1

9792

of

VM_B0_ADA<31..0>

E

D

VM_B0_AA<8>
VM_B0_AA<7..0>

P1V5_GPUS

2

R5391

1

DDR_B_CLK0_DN
DDR_B_CLK0_DP

P1V5_GPUS P1V5_GPUS

C

1

1

C5388

2

2

R5386

2.37K_1%_2

1

1

C5389

2

2

R5387

5.49K_1%_2

8

2

R5392

60.4_1%_2

1

P1V5_GPUS

1

2

R5393

1UF_6.3V_2_DY

1

R5394

2

7 6 5 4 3 2

P1V5_GPUS

VM_B0_ADA<30>

BI

BI
BI

60.4_1%_2

BI
BI

R5398

0_5%_2_DY

2

30
31
29
28
24
26
27
25

17

22

16

23

18

21

19
20
5
6
4
7
3
2

1
0

11

10
8
9

12

14

13

15

7
6
5
4
3
2

1
0

VM_WCKB0_0_DP
VM_WCKB0_0_DN

VM_WCKB0_1_DP
VM_WCKB0_1_DN

VM_EDCB0_3
VM_EDCB0_2
VM_EDCB0_0
VM_EDCB0_1

VM_DDBIB0_3
VM_DDBIB0_2
VM_DDBIB0_0
VM_DDBIB0_1

DDR_B_RASB0#
DDR_B_CASB0#

DDR_A_CKEB0

DDR_B_CSB0#_0
DDR_B_WEB0#

1

VM_RESET

VM_B0_ADA<31>
VM_B0_ADA<29>
VM_B0_ADA<28>
VM_B0_ADA<24>
VM_B0_ADA<26>
VM_B0_ADA<27>
VM_B0_ADA<25>
VM_B0_ADA<17>
VM_B0_ADA<22>
VM_B0_ADA<16>
VM_B0_ADA<23>
VM_B0_ADA<18>
VM_B0_ADA<21>
VM_B0_ADA<19>
VM_B0_ADA<20>
VM_B0_ADA<5>
VM_B0_ADA<6>
VM_B0_ADA<4>
VM_B0_ADA<7>
VM_B0_ADA<3>
VM_B0_ADA<2>
VM_B0_ADA<1>
VM_B0_ADA<0>
VM_B0_ADA<11>
VM_B0_ADA<10>
VM_B0_ADA<8>
VM_B0_ADA<9>
VM_B0_ADA<12>
VM_B0_ADA<14>
VM_B0_ADA<13>
VM_B0_ADA<15>

VM_B0_AA<7>
VM_B0_AA<6>
VM_B0_AA<5>
VM_B0_AA<4>
VM_B0_AA<3>
VM_B0_AA<2>
VM_B0_AA<1>
VM_B0_AA<0>

R5406

120_1%_2

2

1

R5407

0_5%_2

2

1

BI
BI

BI
BI

BI
BI
BI
BI

BI
BI
BI
BI

BI
BI

BI

BI
BI

BI

P1V5_GPUS

1

C5396

2

1UF_6.3V_2_DY

1

C5397

2

1UF_6.3V_2

5.49K_1%_2 2.37K_1%_2

1

1

C5403

2

2

R5400

1

1UF_6.3V_2_DY

1

VM_REFD1_B0
VM_REFD2_B0
VM_REFDC_B0

VM_ADBIB0

C5404

2

2

R5401

1UF_6.3V_2

5.49K_1%_2 2.37K_1%_2

M2
M4
N2
N4
T2
T4
V2

V4
M13
M11
N13
N11
T13
T11
V13
V11
F13
F11
E13
E11
B13
B11
A13
A11

F2

F4

E2

E4

B2

B4

A2

A4

J5

K4

K5
K10
K11
H10
H11

H5

H4

D4

D5

P4

P5

R2
R13
C13

C2

P2
P13
D13

D2

G3

L3

J3
J11
J12

G12
L12

J13
J10

J2

J1

A5

V5
A10

V10

J14

J4

BI

HYNIX_H5GQ2H24MFR_T2C_BGA_170P

U5077

DQ31|DQ7
DQ30|DQ6
DQ29|DQ5
DQ28|DQ4
DQ27|DQ3
DQ26|DQ2
DQ25|DQ1
DQ24|DQ0
DQ23|DQ15
DQ22|DQ14
DQ21|DQ13
DQ20|DQ12
DQ19|DQ11
DQ18|DQ10
DQ17|DQ9
DQ16|DQ8
DQ15|DQ23
DQ14|DQ22
DQ13|DQ21
DQ12|DQ20
DQ11|DQ19
DQ10|DQ18
DQ9|DQ17
DQ8|DQ16
DQ7|DQ31
DQ6|DQ30
DQ5|DQ29
DQ4|DQ28
DQ3|DQ27
DQ2|DQ26
DQ1|DQ25
DQ0|DQ24

RFU/A12/NC
A7/A8|A0/A10
A6/A11|A1/A9
A5/BA1|A3/BA3
A4/BA2|A2/BA0
A3/BA3|A5/BA1
A2/BA0|A4/BA2
A1/A9|A6/A11
A0/A10|A7/A8

WCK01|WCK23
WCK01#|WCK23#

WCK23|WCK01
WCK23#|WCK01#

EDC3|EDC0
EDC2|EDC1
EDC1|EDC2
EDC0|EDC3

DBI3#|DBI0#
DBI2#|DBI1#
DBI1#|DBI2#
DBI0#|DBI3#

RAS#|CAS#
CAS#|RAS#

CKE#
CK#
CK

CS#|WE#
WE#|CS#

ZQ
SEN

RESET#
MF

Vpp,NC
Vpp,NC1

VREFD1
VREFD2

VREFC

ABI#

VDDQ-B1

VDDQ-B3
VDDQ-B12
VDDQ-B14

VDDQ-D1

VDDQ-D3
VDDQ-D12
VDDQ-D14

VDDQ-E5
VDDQ-E10

VDDQ-F1

VDDQ-F3
VDDQ-F12
VDDQ-F14

VDDQ-G2
VDDQ-G13

VDDQ-H3
VDDQ-H12

VDDQ-K3
VDDQ-K12

VDDQ-L2
VDDQ-L13

VDDQ-M1

VDDQ-M3
VDDQ-M12
VDDQ-M14

VDDQ-N5
VDDQ-N10

VDDQ-P1

VDDQ-P3
VDDQ-P12
VDDQ-P14

VDDQ-T1

VDDQ-T3
VDDQ-T12
VDDQ-T14

VDD-C5
VDD-C10
VDD-D11

VDD-G1

VDD-G4
VDD-G11
VDD-G14

VDD-L1

VDD-L4
VDD-L11
VDD-L14
VDD-P11

VDD-R5
VDD-R10

VSSQ-A1
VSSQ-A3

VSSQ-A12
VSSQ-A14

VSSQ-C1
VSSQ-C3
VSSQ-C4

VSSQ-C11
VSSQ-C12
VSSQ-C14

VSSQ-E1
VSSQ-E3

VSSQ-E12
VSSQ-E14

VSSQ-F5

VSSQ-F10

VSSQ-H2

VSSQ-H13

VSSQ-K2

VSSQ-K13

VSSQ-M5

VSSQ-M10

VSSQ-N1
VSSQ-N3

VSSQ-N12
VSSQ-N14

VSSQ-R1
VSSQ-R3
VSSQ-R4

VSSQ-R11
VSSQ-R12
VSSQ-R14

VSSQ-V1
VSSQ-V3

VSSQ-V12
VSSQ-V14

VSS-B5
VSS-B10
VSS-D10

VSS-G5
VSS-G10

VSS-H1
VSS-H14

VSS-K1
VSS-K14

VSS-L5
VSS-L10
VSS-P10

VSS-T5
VSS-T10

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

VM_B1_ADA<31..0>

GDDR5

CHANNEL B MEMORY

VM_B1_AA<8>
VM_B1_AA<7..0>

P1V5_GPUS

2

2

R5432

R5428

60.4_1%_2

60.4_1%_2

1

1

DDR_B_CLK1_DN
DDR_B_CLK1_DP

BI
BI

P1V5_GPUS

R5436

2

P1V5_GPUS P1V5_GPUS P1V5_GPUS

1

1

C5426

2

R5423

2.37K_1%_2

1

C5427

2

R5424

5.49K_1%_2

1

C5434

2

2

R5430

1UF_6.3V_2_DY

2.37K_1%_2

1

1

C5435

2

2

R5431

1UF_6.3V_2

5.49K_1%_2

BI

BI
BI

VM_WCKB1_1_DP
VM_WCKB1_1_DN

VM_WCKB1_0_DP
VM_WCKB1_0_DN

DDR_B_WEB1#
DDR_B_CSB1#_0

0_5%_2_DY

1

1

2

R5438

1UF_6.3V_2_DY

1

2

R5439

1UF_6.3V_2

DDR_B_CASB1#
DDR_B_RASB1#

DDR_B_CKEB1

1

2

1

2

VM_B1_ADA<5>

5

VM_B1_ADA<6>

6

VM_B1_ADA<4>

4

VM_B1_ADA<7>

7

VM_B1_ADA<3>

3

VM_B1_ADA<2>

2

VM_B1_ADA<1>

1

VM_B1_ADA<0>

0

VM_B1_ADA<11>

11

VM_B1_ADA<10>

10

VM_B1_ADA<8>

8

VM_B1_ADA<9>

9

VM_B1_ADA<12>

12

VM_B1_ADA<14>

14

VM_B1_ADA<13>

13

VM_B1_ADA<15>

15

VM_B1_ADA<31>

31

VM_B1_ADA<24>

24

VM_B1_ADA<29>

29

VM_B1_ADA<27>

27

VM_B1_ADA<28>

28

VM_B1_ADA<25>

25

VM_B1_ADA<30>

30

VM_B1_ADA<26>

26

VM_B1_ADA<17>

17

VM_B1_ADA<23>

23

VM_B1_ADA<16>

16

VM_B1_ADA<21>

21

VM_B1_ADA<18>

18

VM_B1_ADA<22>

22

VM_B1_ADA<19>

19

VM_B1_ADA<20>

20

VM_B1_AA<0>

0

VM_B1_AA<1>

1

VM_B1_AA<3>

3

VM_B1_AA<2>

2

VM_B1_AA<5>

5

VM_B1_AA<4>

4

VM_B1_AA<6>

6

VM_B1_AA<7>

7

VM_EDCB1_0
VM_EDCB1_1
VM_EDCB1_3
VM_EDCB1_2

VM_DDBIB1_0
VM_DDBIB1_1
VM_DDBIB1_3
VM_DDBIB1_2

VM_RESET

1

1UF_6.3V_2_DY

C5440

2

2.37K_1%_2

1

VM_REFD1_B1
VM_REFD2_B1
VM_REFDC_B1

VM_ADBIB1

C5441

2

1UF_6.3V_2

5.49K_1%_2

R5444

2

R5445

2

BI
BI

BI
BI

BI
BI
BI
BI

BI
BI
BI
BI

BI
BI

BI

BI
BI

120_1%_2

BI

M2
M4
N2
N4
T2
T4
V2

V4
M13
M11
N13
N11
T13
T11
V13
V11
F13
F11
E13
E11
B13
B11
A13
A11

F2

F4

E2

E4

B2

B4

A2

A4

J5

K4

K5
K10
K11
H10
H11

H5

H4

D4

D5

P4

P5

R2
R13
C13

C2

P2
P13
D13

D2

G3

L3

J3
J11
J12

G12
L12

1

J13

0_5%_2

J10

1

J2

J1

A5

V5
A10

V10

J14

J4

BI

HYNIX_H5GQ2H24MFR_T2C_BGA_170P

U5078

DQ31|DQ7
DQ30|DQ6
DQ29|DQ5
DQ28|DQ4
DQ27|DQ3
DQ26|DQ2
DQ25|DQ1
DQ24|DQ0
DQ23|DQ15
DQ22|DQ14
DQ21|DQ13
DQ20|DQ12
DQ19|DQ11
DQ18|DQ10
DQ17|DQ9
DQ16|DQ8
DQ15|DQ23
DQ14|DQ22
DQ13|DQ21
DQ12|DQ20
DQ11|DQ19
DQ10|DQ18
DQ9|DQ17
DQ8|DQ16
DQ7|DQ31
DQ6|DQ30
DQ5|DQ29
DQ4|DQ28
DQ3|DQ27
DQ2|DQ26
DQ1|DQ25
DQ0|DQ24

RFU/A12/NC
A7/A8|A0/A10
A6/A11|A1/A9
A5/BA1|A3/BA3
A4/BA2|A2/BA0
A3/BA3|A5/BA1
A2/BA0|A4/BA2
A1/A9|A6/A11
A0/A10|A7/A8

WCK01|WCK23
WCK01#|WCK23#

WCK23|WCK01
WCK23#|WCK01#

EDC3|EDC0
EDC2|EDC1
EDC1|EDC2
EDC0|EDC3

DBI3#|DBI0#
DBI2#|DBI1#
DBI1#|DBI2#
DBI0#|DBI3#

RAS#|CAS#
CAS#|RAS#

CKE#
CK#
CK

CS#|WE#
WE#|CS#

ZQ
SEN

RESET#
MF

Vpp,NC
Vpp,NC1

VREFD1
VREFD2

VREFC

ABI#

VDDQ-B1

VDDQ-B3
VDDQ-B12
VDDQ-B14

VDDQ-D1

VDDQ-D3
VDDQ-D12
VDDQ-D14

VDDQ-E5
VDDQ-E10

VDDQ-F1

VDDQ-F3
VDDQ-F12
VDDQ-F14

VDDQ-G2
VDDQ-G13

VDDQ-H3
VDDQ-H12

VDDQ-K3
VDDQ-K12

VDDQ-L2
VDDQ-L13

VDDQ-M1

VDDQ-M3
VDDQ-M12
VDDQ-M14

VDDQ-N5
VDDQ-N10

VDDQ-P1

VDDQ-P3
VDDQ-P12
VDDQ-P14

VDDQ-T1

VDDQ-T3
VDDQ-T12
VDDQ-T14

VDD-C5
VDD-C10
VDD-D11

VDD-G1

VDD-G4
VDD-G11
VDD-G14

VDD-L1

VDD-L4
VDD-L11
VDD-L14
VDD-P11

VDD-R5
VDD-R10

VSSQ-A1
VSSQ-A3

VSSQ-A12
VSSQ-A14

VSSQ-C1
VSSQ-C3
VSSQ-C4

VSSQ-C11
VSSQ-C12
VSSQ-C14

VSSQ-E1
VSSQ-E3

VSSQ-E12
VSSQ-E14

VSSQ-F5

VSSQ-F10

VSSQ-H2

VSSQ-H13

VSSQ-K2

VSSQ-K13

VSSQ-M5

VSSQ-M10

VSSQ-N1
VSSQ-N3

VSSQ-N12
VSSQ-N14

VSSQ-R1
VSSQ-R3
VSSQ-R4

VSSQ-R11
VSSQ-R12
VSSQ-R14

VSSQ-V1
VSSQ-V3

VSSQ-V12
VSSQ-V14

VSS-B5
VSS-B10
VSS-D10

VSS-G5
VSS-G10

VSS-H1
VSS-H14

VSS-K1
VSS-K14

VSS-L5
VSS-L10
VSS-P10

VSS-T5
VSS-T10

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

1

P1V5_GPUS

FF

E

D

C

C5442

1

2

P1V5_GPUS

1UF_6.3V_2

B

1

C5443

2

1

1

C5446

0.1UF_16V_2

C5447

2

2

0.1UF_16V_2

1

1

C5448

C5449

2

2

0.1UF_16V_2

0.1UF_16V_2

1

C5450

2

0.1UF_16V_2

1

C5451

2

0.1UF_16V_2

1

C5452

2

0.1UF_16V_2

0.1UF_16V_2

A

B

1

1

1

1

C5390

C5385

2

2

10UF_6.3V_3

1

C5395

1UF_6.3V_2 1UF_6.3V_2

C5399

2

2

1UF_6.3V_2

1

C5405

C5402

1UF_6.3V_2

2

2

1UF_6.3V_2

1

C5408

2

1UF_6.3V_2

1

C5409

2

1UF_6.3V_2

1UF_6.3V_2

P1V5_GPUS

1

1

C5410

2

1

C5413

C5412

C5411

2

1UF_6.3V_2

0.1UF_16V_2

2

2

0.1UF_16V_2

1

1

1

C5415

C5414

0.1UF_16V_2

2

2

0.1UF_16V_2

1

C5416

2

0.1UF_16V_2

1

C5417

2

0.1UF_16V_2

1

C5418

2

0.1UF_16V_2

C5419

0.1UF_16V_2

1

1

C5421

C5420

2

2

1UF_6.3V_2

10UF_6.3V_3

1

1

C5425

C5422

2

2

1UF_6.3V_2

1UF_6.3V_2

1

1

C5429

2

2

1UF_6.3V_2

1

C5433

2

1UF_6.3V_2

1

C5437

2

1UF_6.3V_2

1UF_6.3V_2

A

INVENTEC

TITLE

Everest Main Board

MODEL,PROJECT,FUNCTION

Block Diagram

SIZE

CODE

February 22, 2010

8

7 6 5 4 3

CHANGE by

BEN LEE

XXX

DATE

21-OCT-2002

2

C

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

1310xxxxx-0-0

1

1

REV

A01

X01

1

9793

of

78

56

EDP_MUX_IC_SEL

BI

CPU_EDP_TX0_DP

BI

CPU_EDP_TX0_DN

BI

4

23

1

U5101

1

10
11

2

4
5
6
7
8
9

D0+
D0­VDD
D1+
D1­AUX+
AUX­HPD
VDD
SEL
HPD_SEL

D

P3V3_S

0.12A

1

C5507

2

0.1UF_16V_2

1

C5508

2

0.1UF_16V_2

EDP_TX0_DP
EDP_TX0_DN

EDP_TX1_DP
EDP_TX1_DN
EDP_AUX_DP
EDP_AUX_DN

EDP_MUX_IC_SEL

BI
BI

BI
BI
BI
BI

BI

P3V3_S

1

R5509

C C

NEED A GPIO PIN

Q5098

EC_EDP_MUX_IC_SEL

IN

10K_5%_2

2

3

DS

1

G

SSM3K7002BFU

2

33 32

31328

GND

AUX_SEL

VDD

29

30

VDD

GND

27

D1+A

D0-A

D0+A

HPD_B

AUX-B

AUX+B

13

14

15

26

D1-A

25

D0+B

24

D0-B

23

D1+B

22

D1-B

21

GND

20

VDD

19

AUX+A

18

AUX-A

17

HPD_A

VDD

1612

PER_PI3VEDP212ZLEX_TQFN_32P

CPU_EDP_TX1_DP

BI

CPU_EDP_TX1_DN

BI

GPU_EDP_TX0_DP

BI

GPU_EDP_TX0_DN

BI

GPU_EDP_TX1_DP

BI

GPU_EDP_TX1_DN

BI

CPU_EDP_AUX_DP

BI

CPU_EDP_AUX_DN

BI

GPU_EDP_AUX_DP

BI

GPU_EDP_AUX_DN

BI

P3V3_S

0.12A

1

0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2

C5102

2

1

C5513

2

1

C5515

2

TRUTH TABLE (SEL CONTROL)
FUNCTION
PORT A IS ACTIVE
PORT B IS ACTIVE

SEL /HPD_SEL/AUX_SEL

L
H

(CPU)
(GPU)

D

B B

Plug Cable
Unplug Cable

A A

Plug Cable
Unplug Cable

PCH-COUGARPOINT: Pin H36 (TACH2/GPIO6)

DGPU_HPD_INTR#_R

DGPU_HPD_INTR#_R

OUT

P3V3_GPUS

L

GPU_EDP_HPD

GPU_EDP_HPD

H

L

H

OUT

R5095

2

0_5%_2

MMBT3904

1

R5096

Q5097

3

CE

B

2

1

10K_5%_2

2

1

Q5100

R5099

1

150K_5%_2

3

DS

2

2

SSM3K7002BFU

G

1

IN

Plug Cable
Unplug Cable

EDP_HPD#_CN

H

L

Plug Cable
Unplug Cable

Plug Cable
Unplug Cable

PCH-COUGARPOINT: Pin H36 (TACH2/GPIO6)

DGPU_HPD_INTR#_R

DGPU_HPD_INTR#_R

OUT

P3V3_GPUS

L

GPU_HDMI_HPD1

GPU_HDMI_HPD1

H

OUT

R5510

2

0_5%_2

MMBT3904

1

R5511

3

Q5512

CE

1

B

2

1

10K_5%_2

H

L

2

Q5103

R5514

1

150K_5%_2

Plug Cable
Unplug Cable

G

1

2

SSM3K7002BFU

GPU_HDMI_HPDETEDP_HPD#_CN

IN

3

DS

2

GPU_HDMI_HPDET

H

L

INVENTEC

TITLE

Everest Main Board

MODEL,PROJECT,FUNCTION

Block Diagram

CODE

SIZE

CS

CHANGE by

8

67

45

XXX

3 2

BEN LEE

DATE

February 22, 2010

21-OCT-2002

C

DOC.NUMBER

1310xxxxx-0-0

CS_1310AXXXXXX-MTR

SHEET

of

94 97

11

1

REV

X01

A01

78

56

4

23

1

HP_R

OUT
OUT

HP_L

MIC1_VREFO_L

OUT

MIC1_VREFO_R MIC1_VREFO_R

OUT

10UF_6.3V_3

D

C510

+PWR_AUD

POWER

1

1

dgnd

+PVDD1

POWER

CLOSE TO CODEC

C506

2

0.1UF_16V_2
C507

2

10UF_6.3V_3

SPK_OUT_L+

SPK_OUT_L-

OUT

OUT

C C

+PVDD2

POWER

SPK_OUT_R­SPK_OUT_R+

OUT
OUT

U500

37
38
39
40
41
42
43
44
45
46
47
48

AVSS2

AVDD2

PVDD1

SPK-L+

SPK-L-

PVSS1

PVSS2

SPK-R-

SPK-R+

PVDD2

EAPD

SPDIFO

1

1

C511

2

2

2.2UF_10V_3

36

2.2UF_10V_3

35

34

CBP

CBN

CPVEE

31

33

32

HP-OUT-R

HP-OUT-L

MIC1-VREFO-L

REA_ALC269Q_VB6_GR_QFN_48P

1

C512

2

10UF_6.3V_3

26

AVSS1

2.2UF_10V_3

25

AVDD1

LINE1-R

LINE1-L

MIC1-R

MIC1-L

MONO-OUT

JDREF

SENSE-B

MIC2-R

MIC2-L

LINE2-R

LINE2-L

SENSE-A

GND

27

28

29

30

VREF

LDO-CAP

MIC2-VREFO

MIC1-VREFO-R

+PWR_AUD

POWER

C514

C515

24
23
22
21
20
19
18
17
16
15
14
13
49

C517

C518

11

C513

0.1UF_16V_2

22

CLOSE TO CODEC

1

1

2

1

20K_1%_2

CLOSE TO CODEC PIN19

R512
R513

C516

0.1UF_16V_2

2

CLOSE TO CODEC

4.7UF_6.3V_3
2

1

4.7UF_6.3V_3

1

2

R511

2

CLOSE TO CODEC

1
1

MIC1_VREFO_L

20K_1%_2

2

39.2K_1%_2

2

R501

R502

1

1

IN
IN

R503

2.2K_1%_2

1K_1%_2
2

1K_1%_2

2

IN

1

1

R504

2.2K_1%_2

2

2

IN

MIC_R

IN

MIC_L

MICS

HPS

IN

BAT54_30V_0.2A

P5V_S

FBMA_11_160808_151A20T

1

1

C501

C500

2

2

10UF_6.3V_3

0.1UF_16V_2

dgnd

FBMA_11_160808_151A20T

P5V_S

3

D501

L501

L503

2

L502

1

1

CLOSE TO CODEC PIN39

CLOSE TO CODEC PIN46

FBMA_11_160808_151A20T

2

NC

dgnd

DVDD1

P3V3_S

R510

0_5%_2

2

1

1

1

B B

1

4

3

2

7

5

6

8

9

12

10

11

dgnd

C519

0.1UF_16V_2

1

2

0.01UF_50V_2

C520

1

dgnd

R514

47K_5%_2

1

1

R515

4.7K_5%_2

22

CLOSE TO CODEC PIN12

2

IN

PCSPKR_PCH_3

PCBEEP

RESET#

SYNC

DVDD-IO

SDATA-IN

DVSS2

BIT-CLK

SDATA-OUT

PD#

GPIO1-DMIC-CLK

GIO0-DMIC-DATA

1

dgnd

+PVDD1

1

C502

2

10UF_6.3V_3

+PVDD2

1

C504

2

10UF_6.3V_3

2

10UF_6.3V_3

POWER

1

C503

2

0.1UF_16V_2

dgnd

POWER

1

C505

2

0.1UF_16V_2

dgnd

+PWR_AUD

POWER

1

C523

2

P3V3_S

C508

C509

2

2

10UF_6.3V_3

0.1UF_16V_2

22_5%_2

R509

2

1

22_5%_2

1

2

dgnd

C520

22PF_50V_2

R505

1

2

IN

HDA_3S_RST#

IN

HDA_3S_SYNC

OUT

HDA_3S_SDIN0

IN

HDA_3S_BITCLK

R508

1

1

1

C521

C522

2

2

10UF_6.3V_3

0.1UF_16V_2

CLOSE TO CODEC

2

0_5%_2

dgnd

dgnd

IN

A A

R506

2

EC_MUTE#

HDA_3S_RST#

IN

1

1K_5%_2

R507

2

IN

1

0_5%_2

2

D505

NC

3

BAT54_30V_0.2A

2

D504

NC

3

BAT54_30V_0.2A

1

OUT

AMP_PD#

1

1

D503D502

VARISTOR_DY

1

2

VARISTOR_DY

2

dgnd

8

67

HDA_3S_SDOUT

IN

AMP_PD#

IN

MIC_IN_CLK
MIC_IN_DATA

IN

INVENTEC

TITLE

Everest Main Board

MODEL,PROJECT,FUNCTION

Block Diagram

CODE

SIZE

C

CHANGE by

45

XXX

3 2

BEN LEE

DATE

February 22, 2010

21-OCT-2002

CS

DOC.NUMBER

1310xxxxx-0-0

CS_1310AXXXXXX-MTR

SHEET

of

95 97

11

1

REV

X01

A01

D

78

L601

MIC_L

D

MIC_R
MICS

OUT
OUT

OUT

1

L602

1

600OHM_25%

2

600OHM_25%

2

56

1

1

1

4

JACK600
G2
G1

1
2
6
3
4
5

1

SINGA_2SJ_T351_019_6P

23

1

D

D601

C C

HP_L
HP_R

HPS

IN
IN

OUT

R603

1

R604

1

2
2

75_5%_2
75_5%_2

1

1

L603

L604

600OHM_25%

2

600OHM_25%

2

1

D603

2

1

D604

VARISTOR_DY

D605

2

VARISTOR_DY

D602

2

2

VARISTOR_DY

1

C605

2

VARISTOR_DY

C603

VARISTOR_DY

1

1

C606

2

2

100PF_50V_2

C604

2

2

100PF_50V_2

100PF_50V_2

PHP_PESD5V2S2UT_SOT23_3P

JACK601

G2
G1

1
2
6
3
4
5

SINGA_2SJ_T351_019_6P

D600

3

2
1

1

C607

100PF_50V_2

2

100PF_50V_2_DY

B B

CN600

SPK_OUT_L+
SPK_OUT_L-

SPK_OUT_R­SPK_OUT_R+

IN
IN
IN
IN

R605
R606

R607
R608

A A

0_5%_3
0_5%_3
0_5%_3
0_5%_3

SPK_OUT_L+_R
SPK_OUT_L-_R
SPK_OUT_R-_R
SPK_OUT_R+_R

1

C608

2

1

1

2

2

3

3

4

4

1

1

C610

C609

2

1000PF_50V_2_DY

1000PF_50V_2_DY

1

ACES_50224_0040N_001_4P

C611

2

2

1000PF_50V_2_DY

1000PF_50V_2_DY

G1

G1

G2

G2

INVENTEC

TITLE

Everest Main Board

MODEL,PROJECT,FUNCTION

Block Diagram

CODE

SIZE

C

CHANGE by

8

67

45

XXX

3 2

BEN LEE

DATE

February 22, 2010

21-OCT-2002

CS

DOC.NUMBER

1310xxxxx-0-0

CS_1310AXXXXXX-MTR

SHEET

of

96 97

1 1

1

REV

X01

A01

8 7

6 5

4 3

2

1

D

FBC_CMD<30..0>

76<

75<

76< 75<

BI

22
4
20
9
6

17
3
26

1
5

19

10
7
29

18

13

12

14
30

27

16

11
24
8
21

FBC_DQS_DP<7>
FBC_DQS_DP<5>

FBC_DQM<7>
FBC_DQM<5>

FBC_DQS_DN<7>

FBC_DQS_DN<5>

69>

75<>76<>

FBC_CMD<28>

FBC_VREF1

FBC_CMD<22>
FBC_CMD<4>
FBC_CMD<20>
FBC_CMD<9>

FBC_CMD<6>
FBC_CMD<17>
FBC_CMD<3>
FBC_CMD<26>
FBC_CMD<1>
FBC_CMD<5>
FBC_CMD<19>
FBC_CMD<10>

FBC_CMD<7>
FBC_CMD<29>
FBC_CMD<18>
FBC_CMD<13>

FBC_CMD<12>
FBC_CMD<14>
FBC_CMD<30>

76<

76<

FBC_CMD<27>
FBC_CMD<16>

FBC_CMD<11>
FBC_CMD<24>
FBC_CMD<8>
FBC_CMD<21>

BI

BI
BI

BI

BI
BI

69>

69>

IN

IN

FBC_CLK1_DP
FBC_CLK1_DN

R5513

243_1%_2

U5506

H1

VREFDQ

M8

VREFCA

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10_AP

R7

A11

N7

A12_BC#

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

IN
IN

1

K7
K9

K1
L2
J3
K3
L3

F3
C7

E7
D3

G3
B7

T2
L8

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#

ZQ

2

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

E3

FBC_D<63>

F7

FBC_D<56>

F2

FBC_D<61>

F8

FBC_D<57>

H3

FBC_D<62>

H8

FBC_D<59>

G2

FBC_D<60>

H7

FBC_D<58>

D7

FBC_D<46>

C3

FBC_D(43)

C8

FBC_D<40>

C2

FBC_D<45>

A7

FBC_D<44>

A2

FBC_D<41>

B8

FBC_D<42>

A3

FBC_D<47>

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

U5507

H1

76< 75<

FBC_CMD<30..0>

FBC_D<56..63>

63
56
61
57
62
59
60
58

46
43
40
45
44
41
42
47

BI

BI

FBC_D<40..47>

P1V5_GPUS

BI

69<>

69<>

1.5A

FBC_VREF1

FBC_CMD<22>

22

FBC_CMD<4>

4

FBC_CMD<20>

20

FBC_CMD<9>

9

FBC_CMD<6>

6

FBC_CMD<17>

17

FBC_CMD<3>

3

FBC_CMD<26>

26

FBC_CMD<1>

1

FBC_CMD<5>

5

FBC_CMD<19>

19

FBC_CMD<10>

10

FBC_CMD<7>

7

FBC_CMD<29>

29

FBC_CMD<18>

18

FBC_CMD<13>

13

FBC_CMD<12>

12

FBC_CMD<14>

14

FBC_CMD<30>

30

FBC_CMD<27>

27

FBC_CMD<16>

16

FBC_CMD<11>

11

FBC_CMD<24>

24

FBC_CMD<8>

8

FBC_CMD<21>

21

76< 69>
76<

69>

IN

FBC_CLK1_DP
FBC_CLK1_DN

IN
IN

P1V5_GPUS

69>
69>

69<
69<

BI

BI
BI

BI

BI
BI

IN

FBC_DQS_DP<4>
FBC_DQS_DP<6>

FBC_DQM<4>
FBC_DQM<6>

FBC_DQS_DN<4>
FBC_DQS_DN<6>

FBC_CMD<28>

1

M8

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M2
N8
M3

J7
K7
K9

K1
L2
J3
K3
L3

F3
C7

E7
D3

G3
B7

T2
L8

VREFDQ
VREFCA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12_BC#
A13
A14
A15

BA0
BA1
BA2

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#

ZQ

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

E3

FBC_D<35>

F7

FBC_D<39>

F2

FBC_D<34>

F8

FBC_D<38>

H3

FBC_D<32>

H8

FBC_D<37>

G2

FBC_D<33>

H7

FBC_D<36>

D7

FBC_D<49>

C3

FBC_D<53>

C8

FBC_D<50>

C2

FBC_D<54>

A7

FBC_D<51>

A2

FBC_D<55>

B8

FBC_D<48>

A3

FBC_D<52>

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

35
39
34
38
32
37
33
36

49
53
50
54
51
55
48
52

BI

FBC_D<32..39>

BI

FBC_D<48..55>

P1V5_GPUS

1.5A

P1V5_GPUS

69<>

69<>

D

CC

R5512

B1
B9
D1
D8
E2
E8
F9
G1
G9

BB

69>76<

FBC_CLK1_DP

69>76<

FBC_CLK1_DN

76<> 75<>

76<>

75<>

69>

75<>76<>

69>

FBC_CMD<27>

69>

FBC_CMD<0>

FBC_CMD<16>

VSSQ#B1

IN

IN

IN

IN

IN

1

R5511

160_1%_2

2

1

10K_5%_2

1

10K_5%_2

1

10K_5%_2

R5508

R5509

R5510

2

2

2

2

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

HYNIX_H5TQ1G63DFR_11C_FBGA_96P

243_1%_2

VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

C5504

0.1UF_16V_2

P1V5_GPUS

1

2

0.1UF_16V_2

C5505

1
2

0.1UF_16V_2

C5506

1

2

0.1UF_16V_2

C5507

1

2

0.1UF_16V_2

C5508

1

C5509

2

1uF_6.3V_2 1uF_6.3V_2

1

C5510

2

1

2

0.1UF_16V_2 0.1UF_16V_2

P1V5_GPUS

C5511

1

C5512

2

1

2

0.1UF_16V_2

C5513

1

C5514

2

0.1UF_16V_2 0.1UF_16V_2

1

2

C5515

1

C5516

1uF_6.3V_2

2

1

2

1uF_6.3V_2

C5517

1

2

AA

INVENTEC

TITLE

EVEREST-M

VRAM

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:55 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

97

of

1

REV

97

A01