Inventec Everest-M 6050A2447101 Schematic

8 7

6 5

4 3

2

1

D

D

CC

EVEREST-M

WS BULID

BB

2010.01.04

AA

INVENTEC

TITLE

EVEREST-M

COVER PAGE

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Tue Jan 04 11:08:28 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

1

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

D

TABLE OF CONTENTS

PAGE

1. COVER PAGE

2. INDEX

3. BLOCK DIAGRAM

4. SMB DIAGRAM

5. POWER SEQUENCE BLOCK

6. POWER FLOW

7. PCB SCREW

8. POWER CHARGER

9. POWER BATTERY

10. POWER +3A/+5A

11. POWER +V1.5/+V0.75S

12. POWER VCCP/+V1.05_LAN_M

13. POWER +V0.85S/+V1.8S

14. POWER VCORE

15. POWER VCORE

16. POWER GPU NVVDD

17. POWER +V3S/+V5S/+V1.5S

18. POWER SEQ

19. POWER SEQ

20. CPU 1

21. CPU 2

22. CPU 3 DRAM

23. CPU 4 POWER

24. CPU 5 POWER

25. CPU 6 GND

26. DDR3 DIMM0

27. DDR3 DIMM1

PAGE

28. PCH 1

29. PCH 2

30. PCH 3

31. PCH 4 AXG

32. PCH 5 USB

33. PCH 6 MISC

34. PCH 7 POWER

35. PCH 8 POWER

36. PCH 9 GND

37. EC

38. FAN & THERMAL

39. LAN

40. RJ45 & TRANSFORMER

41. AUDIO CODEC

42. AUDIO AMP

43. TPM

44. LCM CONN

45. CRT CONN

46. HDMI CONN

47. DP CONN

48. eDP CONN

49. DB CONN USB & CARDREADER

50. SATA HDD/SSD & ODD CONN

51. E-SATA CONN

52. USB CONN

53. K/B & TP/B CONN

54. BLUETOOTH CONN

PAGE

55. MINI1 WLAN/Debug Card

56. MINI2 3G

57. HALL SENSOR

58. LED

59. CLOCK GENERATOR

60. XDP

61. ME JTAG

62. PICK BUTTON BOARD

63. TOUCH PAD SW BOARD

64. POWER BUTTON BOARD

65. CARDREADER & USB BOARD

66. EMI

67. GPU SW/POWER

68. GPU-1

69. GPU-2

70. GPU-3

71. GPU-4

72. GPU-5

73. VRAM

74. VRAM

75. VRAM

76. VRAM

CC

BB

AA

INVENTEC

TITLE

EVEREST-M
INDEX

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Mon Dec 27 16:49:48 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

2

of

1

REV

97

A01

EDP

3D PANEL

15.6 WXGA LED

78

56

34

2

1

IVY BRIDGE

DDR3@1.5/0.75V

(1600MHZ)

204-PIN SODIMM X2
MAX MEMORY 8GB X2

MUX

PERICOM

eDP

eDP

QC 45W OR DC 35W

VT & TXT

SOCKET-RPGA989

37.5 X 37.5 X 5 mm

DUAL CHANNEL

D

VRAM*4(64Mb*32)

TOTAL:1GB GDDR5

HDR

HDMI 1.4

HDMI

AMD

ATI WHISTLER XT

35W

PEGX16

FDI

DMI 2.0

JTAG

JTAG

60-PIN CPU XDP

(TEST ONLY)

60-PIN PCH XDP

(TEST ONLY)

29MM X 29MM

HDR
VGA

C C

HDR(DONGLE)

HDMI 1.4

RJ45

B B

SIM CARD

CONNECTOR

RGB

R

RGB

R

HDR

DISPLAYPORT 1.1

(TEST ONLY)

HDR

LVDS

(TEST ONLY)

Gbe Phy

(100/1000)

LEWISVILLE

INTEL 82579LM_BAM271

PCIE_3: WIFI
PCIE_4: 3G/mSATA

DP

LVDS

PCIE_6

PCIE

PCH

COUGAR POINT

TDP 3.9W

25 X 25 X 2.3 mm

JTAG

HDA

SPI

USB 2.0

LS

AUDIO CODEC

REALTEK

ALC269Q_VC

SPI FLASH 8MB

WINB_W25Q64BVSSIG

RJ-11ME JTAG

INTERNAL MIC IN

EXT MIC IN
HEADPHONE/LINEOUT

USB_0 RESERVE FOR USB3.0
USB_2 RESERVE FOR USB3.0
USB_1 eSATA PORT
USB_5 Minicard WLAN
USB_10 Webcam

USB_12 Bluetooth
USB_13 Minicard 3G

HDR

(TEST ONLY)

D

USB 3.0

TI_TUSB7320

PCIE_1

SATA

USB3.0

LPC

CONN A

A A

CONN B

CARD READER

RTS5209

PCIE_2

SPI

EC WINDBOND

BATTERY CHARGER &

NPCE791LA0DX

TPM V1.2

SLB9635TT1.2_FW3.17

SPI Flash 1MB

WINB_W25Q80BVSSIG

SATA3_0: SSD
SATA3_1: HDD
SATA2_2: ZERO POWER ODD
SATA2_3: eSATA
SATA2_4: mSATA

DC/DC & IMVP 7
LI-ION BATTERY

6-Cell

8

TOUCH PADKEYBOARD

CHANGE by

67

45

3

Frank Hu

Mon Dec 27 16:50:03 2010

DATE

2

INVENTEC

TITLE

EVEREST-M

BLOCK DIAGRAM

SIZE

C

CODE

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

3

of

1

REV

97

A01

8 7

6 5

4 3

2

1

+V3A

+V5S

RES 2.2K

D

SMB_CLK

SMB_DATA

RES 2.2K

SMB_CLK
SMB_DATA

RES 2.2K

SSM3K7002

SSM3K7002

+V3S

RES 2.2K

SMB_CLK_S2

SMB_DATA_S2

CK505

SO-DIMM 0 SO-DIMM 1

PCIE

1

USB3.0_TUSB7320

2

CardReader_RTS5209

WLAN

3

MINICARD3G

4

NC

5

LAN

6
7

NC

8

NC

SATA

01SSD

HDD

2

ODD
eSATA

3
4

mSATA

NC

5

D

XDP

PCH

SML0CLK
SML0DATA

SML0_CLK

SML0_DATA

RES 2.2K

+V3A

RES 2.2K

LEWISVILLE

LAN PHY

SMB_CLK_S3
SMB_DATA_S3

SMB_CLK_A1
SMB_DATA_A1

PEG

MINICARD

WIFI

MINICAR

3G

SCL1

SDA1

RES 3.3K RES 3.3K

EC_SMB1_CLK

EC_SMB1_DATA

+V3LA

0

1
2
3

4

5
6

7
8

9

10

11

12

13

BATTERY

USB

Reserve for USB3.0
eSATA

Reserve for USB3.0

NC
NC
MINICARD WLAN

NC

NC
NC
NC
WEBCAM
NC

BLUE TOOTH

MINICARD 3G

CC

BB

SML1CLK

SML1DATA

8

SML1_CLK

SML1_DATA

RES 2.2K

7 6

+V3A

RES 2.2K

+V3A

SSM3K7002

SSM3K7002

RES 2.2K

+V3LA

RES 2.2K

EC_SMB3_CLK

EC_SMB3_DATA

5 4

EC

SCL2

SDA2

RES 1.8K

EC_SMB2_CLK

EC_SMB2_DATA

+V3LA

3

RES 1.8K

CHANGE by

Frank Hu

Mon Dec 27 16:50:16 2010

DATE

2

CHARGE IC

THERMAL IC

GPU THERMAL

INVENTEC

TITLE

EVEREST-M
SMB DIAGRAM

CODE

SIZE

CS

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

4

of

1

AA

REV

97

A01

8 7

6 5

4 3

2

1

+V3LA

SLP_S3#_5R

+V3S

PC6014

AM4825P

D

ADAPTER

PMOS

0.01 OHM
AM4825P

ADP_PRES

KBC_PW_ON

5/3.3V

(TPS51125)

PMOS

+VPACK

VO

BATT_CLK

BATT_DATA

CHARGER

SCL
SDA

ACOK

0.01 OHM

ACIN#

TPS51218

EN_PSV

+V5A

+V1.5

+V1.05S

PC6014

G2997

PC6014

SLP_S3#_5R

SLP_S3#_5R

SLP_S5#_5R

+V5S

D

+V0.75S

+V1.5S

CC

+GFX_VDD

+V0.85S

GFX_VDD_PG

VCCSA_PG

PGOOD

TPS51217

D0

EN_PSV

EN

VCCDRE_EN

VR_SVID_DATA

VR_SVID_CLK

VR_SVID_ALRT#

VTT_SELECT

VR_ON
VDIO
VCLK
ALERT#

TPS51218

EN_PSV

TPS51218

D0

EN_PSV

MAX17039

VO

VO

VR_HOT#

VOUT

VO

+V1.05_VCCP

H_PROCHOT#

VR_PWRGD
+GFX_PWRGD

+VCC_CORE

+VGFX

BB

AA

INVENTEC

TITLE

EVEREST-M

POWER SEQUENCE BLOCK

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Mon Dec 27 16:50:27 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

5

of

1

REV

97

A01

8 7

6 5

EVEREST PWROWSEQUENCE

4 3

2

1

VADPTR (-7START)

D

V5LA

VCC

MAX_MAX17435ETG

ACIN
ACOK#

ACPRES

ACPRES

NMOS

EN

EC_PW_ON

(-2)

V3A(-1)

AM3423E

(0)

PWR_SWIN#_3

EC_PCH_PWROK

8

VPACK

VBAT (-6)

NMOS

GPIO03

GPIO75

GPIO01

GPO84_XORTR#

(15)

VBAT

VSEN

VCC

GMT_G686LT11U

RESET#

LRESET#

GPIO36

GPIO50_TD0

GPIO43_TMS

GPIO32_D_PWM

PSDAT2_GPIO27

DAO_GPIO94

DA2_GPIO96

GPIO02

99ms

EC

GPO82_TEEST#

EC_DGPU_PWR_EN#

(13)

V5A

VIN

SEMTECH

SC475A

EN

7 6

VBAT

VCC

V5LA (-5)

(-4)

+V5AUXON

PLT_RST# (21)

EC_PWRSW# (2)

(1)

RSMRST#

SLP_S5#_3R

SLP_S4#_3R (3)

SLP_LAN#_3R (4)

SLP_A_3R (5)

SLP_S3#_3R (6)

(12)

MAIN_PWRGD

SLP_A_3R

INVERTER

SLP_S3_5R

INVERTER

V5A

VIN

AM3423P

EN

V1.5

VIN

AO4406

EN

(14)

GPU_VDD

V1.5

VIN

EN

PLERST#

SLP_LAN#_3R (4)

SLP_S3#_5R

(8)

V1.5_CPU

AM4430N

PWRBTN#

RSMRST#

SLP_S5#

SLP_S4#

SLP_LAN#

SLP_A#

SLP_S3#

V5A

VIN

TPS51218DSCR

EN

VIN

G5694F11U

EN

(7)

V5S

SLP_A_3R (5M)

(14)

GPU_1.5S

VBAT

EN2

TI_TPS51125

EN1

XDPLAN

RST#RST#

V02

V01

VREG5

VGA

RST#

PCH

VBAT

VCC

PGD

V3A

VCC

PGD

V3LA

VIN

AM3423P

EN

V1.5

VIN

AO4406

EN

(3A)

V1.5

V5A

V1.5_PG

V1.05_LAN_M (4A)

V1.05S_VCCP

(7)

V3S

(8)

V1.5S V3.3M (4A)

PGD

V1.05S

VIN

EN

AM4430N

GPU_1.5S

5 4

V3LA (-3)

V5A (-1)

V5LA (-5)

BUFFER

VIN

GMT_G2997F6U

EN

VIN

EN

VIN

AO4406

EN

V1.05_LAN_VR_PWRGD

AND GATE

V3S

(14)

VIN

EN

BUF_PLT_RST#

DRAMPWROK

PROCPWRGD

SYS_PWROK

VCC

AM3423P

PWROK

APWROK

(3B)

(5A)

(11)

MINICARD X2

RST#

PM_DRAM_PWRGD (20)

H_CPUPWRGD (16)

EC_PCH_PWROK (15)

VCORE

PM_APWROK (5B)

M_VREF

V0.75S

V3A

V1.05M

(7)

V1.05S

(5A)

EN

(14)

GPU_V3S

VIN

AM3423PAO4406

EN

VIN

GMT

G5694F11U

AND GATE

CHANGE by

3

ALLSYS_PWROK (19)

IMVP7

(4A)

V3.3M

VDDR_PWRGD

(7)
V1.8S

PM_APWROK (5B)

Frank Hu

RSTIN#

SM_DRAMPWROK

SM_DRAMPWROK

VCORE_PWRGOOD (18)

SVID

EN

PWRGD

AND GATE

AND GATE

Mon Dec 27 16:50:39 2010

DATE

2

TPM

RST#

CPU

CLK

EN

V0.85S

V1.05S_VCCP

(9)

SLP_S3#3R

INVENTEC

TITLE

EVEREST-M
POWER FLOW

CODE

SIZE

C

CS

SHEET

VCORE

SVID

SVID

AND

GATE

PGD

TI

TPS51218DSCR

TI

TPS51218DSCR

+V1.05S_VCCP_EN

AND GATE

DOC.NUMBER

CS_1310AXXXXXX-MTR

6

of

1

(17)

EN

(11)

PGD
EN

97

(10)

REV

A01

D

CC

BB

AA

8 7

6 5

4 3

2

1

FIX1

1

FIX_MASK

D

1

1

1

FIX2

1

FIX_MASK FIX_MASK

S1

SCREW330_600_800_1P

S24

SCREW300_700_1P

S3

SCREW300_1000_1P

S14

FIX3

1

FIX4

1

FIX_MASK FIX_MASK

S10

SCREW330_600_800_1P

1

S4

SCREW300_1000_1P

1

S12

SCREW300_1000_1P

1

FIX5

1

FIX6

1

FIX_MASK

S18

SCREW330_600_800_1P

1

S20

SCREW300_1000_1P

1

FIX_MASK

FIX7

1

FIX8

1

FIX_MASK

1

S22

SCREW330_600_800_1P

S23
SCREW300_1000_1P

1

CPU

S25

SCREW500_1000_1P

1

S26

SCREW300_1000_1P

1

D

MB

CC

SCREW120_500_0_1P

1

S7

SCREW120_0_500_1P

1

S17

SCREW120_0_500_1P

1

S9

SCREW320_500_400_1P

1

MINI CARD

S16

SCREW120_0_500_1P

1

S27

SCREW120_0_500_1P

1

S11
SCREW320_500_400_1P

1

FAN

PCH

S19
SCREW320_500_400_1P

1

S33
SCREW320_500_400_1P

1

BB

GPU

AA

INVENTEC

TITLE

EVEREST-M

PCB SCREW

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:56 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

7

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

NFE31PT222Z1E9L

1

L6001

4

3

(OVP MAX : 24.67V)

(OVP MIN : 23.106V)

45.3K_1%_2

(1.68V)

4.3K_1%_3

2

D6004

1

R6012

2

1

R6013

12.6V : 3140H

1

2

2

C6028

0.1UF_25V_3

0X15

8.4V : 40D0H

16.8V : 41A0H

1

R6017
RSC_0603_DY

2

1

R6018
RSC_0603_DY

2

D

G1

G2

ACES_91302_0047L_1_4P

8A_125V

CN6000

G1

G2

1

1

2

2

3

3

4

4

FUSE6000

1

1000PF_50V_2

2

1

C6035

2

1
2

C6033

10PF_50V_2

C6003

CSC0402_DY

1

2

R6019

1

RSC_0402_DY

2

NEAR EC

3A

R6005

4.7K_5%_3

2

1

Q6003

1

S

1

R6042

2

1 1

DIODES_SMAJ20A_13_F_2P

0_5%_2_DY

2
3
4 5

2

R6008

10K_5%_2

G

NMOS_4D3S

AM4410NC

0_5%_2

1

2

R6043

8

D

7
6

2

3

8>

0X14

512MA : 0200H_512MA

1.5A : 0600H_1.54A
3A : 0C00H_3.07A

1

D6001
BAT54C_30V_0.2A

17435_LDO

A1

OUT

10_5%_2

C

R6014

TP6002

8

D

7
6

NMOS_4D3S

1

R6036

150_5%_3

2

3

Q6004

DS

SSM3K7002BFU

2

A2

1

1UF_10V_2

2

Q6002

S

G

AM4410NC

NEAR IC

R6016

1

10_5%_5

1

G

2

1

1

C6025

2

1
2
3
45

2

IN

R6007

10K_5%_2

1

2

C6022

1UF_10V_2

1

0.1UF_25V_2

2

2

C6021

1UF_10V_2

C6811

P_GATE

3

1
2

R6020

0.01_1%_6

C6029

1

1UF_25V_3

1

4.7_5%_3

CHG_HG
CHG_SW
CHG_LG

0.01UF_50V_2

1

2

2
43

CHG_VBAT_SEN_N

1

2

2

R6000

2

C6007

1

C6008

0.1UF_16V_2

2

R6010
1K_1%_2

0.1UF_25V_3

1

2

C6006

1

2

FDMC8884

2

1

C6813

0.1UF_25V_2_DY

C6026

0.1UF_16V_2

Q6000

1

C6814

CSC0402_DY

2

1

2

2

2

PAD6000

1

POWERPAD_2_0610

1

2A

5 6 7 8

NMOS_4D3S

G

3 214

5 6 7 8

NMOS_4D3S

G

3 214

NEAR EC

D

S

D

S

1

2

Q6001
FDMC8884

D6003

SBR3U40P1

C6002

0.1UF_25V_3

1

2

R6044

1
1

0_5%_2_DY

1

C6005

4.7UF_25V_5

2

1

2

1

C6009

2

R6045

R6004

4.7_5%_3

2200PF_50V_2

RSC_0402_DY

0_5%_2

2
2

1

C6001

2

PCMC063T_3R3MN

1

1

1

C6030

1

0.1UF_25V_2

2

1

C6023

2

1UF_25V_3

2

D6000

BAV99

C6812

0.01UF_25V_2_DY

2

14

16

15

3

CHG_VBAT_SEN_P

1

DCIN

PDSL

CSSP

CSSN

19

ACIN

10

ACOK

4

LDO

21

VAA

23

GND

22

VCC

1

SCL

2

SDA

U6000
MAX_MAX17435ETG+_TQFN_24P

24

P3V3_AL

1

R6003

10K_5%_2

2

PGND-PAD

ADAPTLIM

EN

BST
DHI

LX

DLO

CSIP
CSIN
BATT

CC

IINP

ITHR

R6002

10K_5%_2

7
9
8
5
25

12
11
13
17

18

6
20

L6000

2

R6046

1

1

C6000

4.7UF_25V_5_DY4.7UF_25V_5

2

2

CHG_CHG_SEN_P

2
3
4

1

R6006

RSC_0603_DY

2

R6001

1

0.02_1%_6

CHG_CHG_SEN_N

Q6005

1

S

G

PMOS_4D3S

TPC8121

8

D

7
6
5

CC

2
43

C6016

1

4.7UF_25V_5

2

1

C6817

4.7UF_25V_5

2

BB

AA

1

17435_LDO

OUT

1

TP6000

8

7 6

5 4

8>

INVENTEC

TITLE

EVEREST-M
POWER CHARGER

CODE

SIZE

CS

CHANGE by

Frank Hu

3

Mon Jan 03 10:52:57 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

8

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

FUSE6100
LITTLEFUSE_R451015_15A_65V

R6101
R6102

1

1

C6106

1000PF_50V_2

2

R6110

1

715K_1%_2

2

1

33_5%_2

2

1

33_5%_2

2

1

D6100
EZJZ0V500AA

2

R6109

1

102K_1%_3

R6108

2

1

2

360K_1%_2

2

1

1K_5%_2

1

D6099
EZJZ0V500AA_DY

2

1

D6101
EZJZ0V500AA

2

R6100

2

CN6100
SYN_200045GR009G15JZR_9P

1

BATT+

2

BATT+

3

ID

4

B-I

5

TS

6

SMD

7

SMC

8

GND

9

GND

G1

G

G2

G

G3

G

G4

G

D

CC

BB

1

2

D6102

NC

1

BAT54_30V_0.2A_DY

3

U6100

1

RESET

2

GND

3

VCCMRVSEN

GMT_G686LT11U_SOT23_5P

1

C6107

0.1UF_16V_2

2

R6105
10K_5%_2

2

R6039

1

2

5
4

0_5%_2

1

R6104
510K_1%_2

2

1

R6103
100K_1%_2

2

AA

INVENTEC

TITLE

EVEREST-M
POWER BATTERY

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Mon Jan 03 10:53:36 2011

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

9

of

1

REV

97

A01

8 7

6 5

4 3

2

1

Q6200

8

D

1

Q6203

G

7
6

NMOS_4D3S

AON7410

3

DS

2

R6201

R6212

100K_5%_2

D

1

2

SSM3K7002BFU

100K_5%_2

Q6202

1

G

10<

3

DS

2

EC_PW_ON#

37>

1

2

1

C6211

2200PF_50V_2

2

R6200

1

0_5%_2

2

1

C6215

2

CSC0402_DY

IN

SSM3K7002BFU

1

A1

3

C

D6201
BAT54C_30V_0.2A

S

G

1

R6210

120K_1%_2

2

1
2
3
45

37>

10<

EC_PW_ON#

PAD6205

1

1

POWERPAD_2_0610

2

2

Q6805

IN

1

SSM3K7002BFU

1

R6202
200_5%_2

2

3

G

2

10>

DS

VCLK

IN

P5V_A

C6219

0.1UF_25V_2

C6216

0.1UF_25V_2

2

1

2

1

2

D6202

3

BAV99

C6218

0.1UF_25V_2

0.1UF_25V_2

1

C6217

1

D

2

D6203

3

BAV99

2

1

2

1

C6220

1UF_25V_3

1

2

CC

10A

PAD6200

1

1

POWERPAD_2_0610

2

R6207

6.8K_1%_2

R6208

10K_1%_2

8

1

1

PAD6203

2

POWERPAD_2_0610

2

A2

2

1

R6209

130K_1%_2

2

1

1

PAD6202
POWERPAD_2_0610

2

2

SKIPSEL

TONSEL

>>VRE3 OR VRE5=OOA

>>VREF=ASKIP
>>GND=PWM

>>VRE5=365/460
>>VRE3=300/375
>>VREF=245/305

REV

A01

BB

AA

>>GND=200/250

1

1

VO1
PGOOD
VBST1
DRVH1

LL1
DRVL1

18

VCLK

OUT

C6209

0.22UF_6.3V_2

2

24
23
22

VR5A_HG

20

VR5A_PH

19

VR5A_LG

C6213

1

1

2

2

1

10UF_6.3V_3

2

C6207

0.1UF_25V_3

2

1

10<

PAD6204

POWERPAD1X1M

3.8A

Q6206

AON7410

5 6 7

NMOS_4D3S

G

3 214

5 6 7 8

G

3 214

8

D

S

D

S

4.7UF_25V_5

Q6207

TPC8A05_H

C6203

1

2

C6201

1

2

4.7UF_25V_5

L6200

1

PCMC063T_3R3MN

3

4.7UF_25V_5

2

330UF_6.3V

C6214

1
2

C6200

CHANGE by

1

+

2

Frank Hu

1

POWERPAD_2_0610

1

R6205

15.4K_1%_2

2

1

R6206
10K_1%_2

2

DATE

7A

PAD6201

1

2

2

Mon Jan 03 10:54:36 2011

2

INVENTEC

TITLE

EVEREST-M
POWER +3A/+5A

SIZE

C

CODE

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

10

of

1

97

1

C6205

4.7UF_25V_5

2

1

C6204

4.7UF_25V_5

2

1

2

1

2

1

C6202

1

2

2

+

330UF_6.3V

L6201

2

1

PCMC063T_3R3MN

Q6205

TPC8A05_H

7 6

4A

56

78

D

S

D

S

32

3214

4

5678

NMOS_4D3S

G

G

Q6204

AON7410

C6212

2

0.1UF_25V_3

1

TI_TPS51125_QFN_24P

1

2

VR3AL_HG
VR3AL_PH
VR3AL_LG

C6206

1UF_6.3V_2

U6200

RSC_0603_DY

1

2

25

TML

7

VO2

8

VREG3
VBST2

10 21

DRVH2

11

LL2

12

DRVL2

R6037

2

1

CSC0805_DY
C6210

R6204

RSC_0402_DY

5 4

35294

6

ENTRIP2

VFB2

TONSEL

VREF

VFB1

ENTRIP1

SKIPSEL

VREG5

13

GND

VIN

14

15

1

2

VCLK

17

16

C6208

2.2UF_25V_5

EN0

1

2

8 7

6 5

4 3

2

1

1

1

PAD6301

2

D

POWERPAD_2_0610

2

22A

D

3.7A

8765

D

NMOS_4D3S

G

S

2

1

4 3

8765

D

G

S

TPCA8A02_H

1

23

4

Q6301

1

C6303

4.7uF_25V_5

2

2

R6047

PCMC104T_1R0MN

4.7_5%_3

1

1

C6815

2200PF_50V_2

2

1

C6300

4.7uF_25V_5

2

L6300

1

3

1

2

2
4

R6304

11.5K_1%_2

C6309

4.7uF_25V_5

1

2

1

+

C6304

560uF_2.5V

PAD6303

1

1

2

POWERPAD_2_0610

PAD6302

1

1

2

POWERPAD_2_0610

2

2

CC

2

37<

11<

30>

SLP_S4#

3.7A

P3V3_S

1

R6314

RSC_0402_DY

2

18<

V1.5_PG

1

IN

R6302

0_5%_2

2

OUT

TI_TPS51218DSCR_SON_10P

U6302

1

PGOOD

2

TRIP

3

EN

4

VFB

5

RF

10

VBST

VR15_HG

9

DRVH

8

VR15_PH

SW

7

V5IN

6

VR15_LG

DRVL

GND

R6301

2.2_5%_3

1

2

C6305

0.1uF_25V_3

1

1

C6301

CSC0402_DY

2

1

R6311

95.3K_1%_2

2

1 1

R6310

200K_1%_2

2

11

C6302

2.2uF_6.3V_3

2

Q6300

TPCA8065_H

2

30>

17<18<37<

SLP_S3#

+V1.5S_CPUDDR_PG

IN

37<

IN

11<

30>

R6307

1

0_5%_2_DY

R6306

1

0_5%_2

SLP_S4#

2

2

20/20 mil

IN

C6312

1000PF_50V_2_DY

1

0.1UF_16V_2

2

C6311

P3V3_A

1

1

2

2

C6308

1uF_10V_2

U6300

11

TML

10

VIN

9

S5

8 4

GND

7

S3

6

VTTREF

GMT_G2997F6U_MSOP10_10P

VDDQSNS

VLDOIN

VTT

PGND

VTTSNS

R6303

10K_1%_2

1

2

BB

P1V5

1
2
3

5

1.5A

1

C6307

22uF_6.3V_5

2

1

C6306

2

22uF_6.3V_5

PAD6300

1

1

2

POWERPAD_2_0610

2

1.5A

AA

INVENTEC

TITLE

EVEREST-M
POWER +V1.5/+V0.75S

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Mon Jan 03 17:25:55 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

11

of

1

REV

97

A01

8 7

6 5

4 3

1

1

PAD6403

2

POWERPAD_2_0610

2

1

P3V3_S

5 6 7 8

D

10K_5%_2

13<

1

0_5%_2

VTT_PG

R6402

2

C6413

CSC0402_DY

OUT

1

1

R6405

44.2K_1%_2

2

2

R6400

1

2

TI_TPS51218DSCR_SON_10P

U6400

1

PGOOD

2

TRIP

3

EN

4

VFB

5

RF

1

R6411

470K_1%_2

2

R6403

10

VBST

9

VRVCCP_HG

DRVH

VRVCCP_PH

8

SW

7

V5IN

VRVCCP_LG

6

DRVL

GND

1

2.2_5%_3

2

C6410

0.22UF_25V_3

1

2

11

C6411

1

2.2UF_6.3V_3

2

3.3A

23>

VSS_SENSE_VTT

NMOS_4D3S

G

3 214

5 6 8

NMOS_4D3S

G

3 214

D

Q6401

TPCA8065_H

S

7

D

Q6400
TPCA8057_H

S

2

1

C6403

4.7UF_25V_5

2

1000PF_50V_2_DY

IN

C6406

1

4.7UF_25V_5

2

1
3

PAN_ETQP4LR36WFC_4P

C6414

1

1

2

L6403

1

R6410

RSC_0402_DY

2

1

2

R6415

0_5%_2

C6401

4.7UF_25V_5

2
4

2

1

C6415

0.1UF_10V_2_DY

2

1

R6413

9.53K_1%_2

2

1

R6414
20K_1%_2

2

1

R6416

R6417

1

200_1%_2

PAD6402

1

1

POWERPAD_2_0610

PAD6401

1

1

POWERPAD_2_0610

2

2

2

2

28A

D

1

C6407

+

560UF_2.5V

2

CC

2

IN

VCC_SENSE_VTT

23>

100_5%_2

2

BB

P3V3_A

0.5A

+V1.05_LAN_M

1

37< 19<

30>

SLP_LAN#

C6452

1

R6452

10_5%_3

2

R6454

2

IN

1

0_5%_2

1

C6453

0.1UF_16V_2

2

10UF_6.3V_3

2

U6401
GMT_G5694F11U_SOP_8P

8

VIN

1

VCC

5

EN

PGND

673

9

TML

LX

4

FB

2

REF

GND

C6454

1

0.1UF_16V_2

2

L6450

1

LTF5022T_2R2N3R2_LC

2

1

R6450

3.09K_1%_2

2

1

R6451
10K_1%_2

2

1

C6451

CSC0402_DY

2

1

C6450

22UF_6.3V_5

2

PAD6400

1

1

POWERPAD_2_0610

2

1.5A

2

AA

INVENTEC

TITLE

EVEREST-M

POWER VCCP/+V1.05_LAN_M

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Mon Jan 03 17:26:41 2011

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

12

of

1

REV

97

A01

8 7

6 5

4 3

PVBAT

1

1

PAD6500

2

POWERPAD_2_0610

2

1

P3V3_A

5

6 7 8

D

10K_5%_2

R6502

2

1

0_5%_2

1

1

C6505

CSC0402_DY

R6508

78.7K_1%_2

2

2

R6501

1

2

1

2

1

C6510

47PF_50V_2

2

TI_TPS51217DSCR_SON_10P

1
2
3
4
5

R6509
1K_1%_2

PGOOD

TRIP

EN

VFB

TRAN

U6500

11

R6500

10

VBST

9

DRVH

8

SW

7

V5IN

6

DRVL

GND

VR85_HG

VR85_PH

VR85_LG

C6504

1

2.2UF_6.3V_3

2

1

0_5%_3

2

C6503

0.22UF_25V_3

1

2

Q6500

AON7410

NMOS_4D3S

G

3 2

4

5 7 8

6

G

3 2

4

D

S

1

D

Q6501

TPC8A05_H

S

1

P5V_A

2

1

C6501

4.7UF_25V_5

2

C6506

1000PF_50V_2_DY

1

C6502

4.7UF_25V_5

2

1

C6500

4.7UF_25V_5

2

L6500

2

1

PCMC063T_3R3MN

1

R6503
RSC_0402_DY

2

1

1

C6507

0.1UF_10V_2_DY

2

1

200_1%_2

1

R6504

6.49K_1%_2

2

R6506

D

6A

PAD6503

1

1

POWERPAD_2_0610

1

C6508

+

330UF_2V_9MR_PANA_-35%

2

2

2

2

CC

2

R6510

20K_1%_2

1

2

1

2

R6507

40.2K_1%_2

1

R6505
20K_1%_2

2

24>

VCCSA_SEL

IN

LOW - 0.9V
HIGH - 0.8V

R6511

2

200_1%_2

1

B

LMBT3904LT1G

C E

Q6502

1

2 3

3

DS

G

Q6503

SSM3K7002BFU

2

BB

1

1.6A

1

C6514

1

R6517
10_5%_3

2

1

C6515

2

0.1UF_16V_2

1

R6516
10K_5%_2

2

10UF_6.3V_3

2

U6502
GMT_G5694F11U_SOP_8P

8

VIN

1

VCC

5

EN

PGND

673

9

TML

LX

4

FB

2

REF

GND

1

C6511

0.1UF_16V_2

2

L6502

1

LTF5022T_2R2N3R2_LC

2

1

R6514
13K_1%_2

2

1

R6515
10K_1%_2

2

1

C6513

CSC0402_DY

2

1
2

C6512

22UF_6.3V_5

PAD6501

1

1

POWERPAD_2_0610

2

3A

2

AA

INVENTEC

TITLE

EVEREST-M

POWER +V0.85S/+V1.8S

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Mon Jan 03 17:27:17 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

13

of

1

REV

97

A01

8 7

6 5

4 3

2

1

D

+VBAT_CPU

1

R6622

178K_1%_2

2

P3V3_A

1

R6620
0_5%_2

2

8

FOLLOW BERLIN 10RG

1

R6621

20.5K_1%_2

2

C6615

1

470PF_50V_2

2

IN

VSSSENSE

23>

+VBAT_CPU

1

R6617

178K_1%_2

2

7 6

1

R6619
0_5%_2 115K_1%_2

2

1

R6618

2

14<

FOLLOW BERLIN 10RG

P3V3_A

1

R6608
0_5%_2

2

1

R6609

20.5K_1%_2

2

P5V_A

1

C6612

470PF_50V_2

2

IN

VSSAXG_SENSE

1

R6624

4.87K_1%_2

2

1

R6626

100K_5%_2

2

P5V_A

TONA
IMAXA
IMONA
CCVA
VBOOTA

14<

SRA
THERMA

14<

14<

14<
14<

14<

14<

R6611

2K_5%_2

IN
IN
IN
IN
IN
IN
IN

P5V_A

1

R6623

P5V_A

1

R6625

4.87K_1%_2

2

24>

1

R6606

2

14<

1

R6607
0_5%_2 115K_1%_2 100K_5%_2

2

1

R6627

2

14<

14<

PH3_SKIP#

PH3_PWM

IN
IN

1

C6619

1UF_6.3V_2

2

P3V3_S

1

1

R6610
2K_5%_2

2 2

2

10K_5%_2

R6038

15<

14<

1

IN
IN
IN
IN
IN
IN
IN

VRCPU_PH2

14<

2

TONB
IMAXB
IMONB

CCVB
VBOOTB
SRB
THERMB

IMAXA
IMAXB

0_5%_2

14<

14<

14<

14<
14<

14<

14<

IN

IN
IN

5 4

U6602

MAX_MAX8791GTA+_TQFN_8P

2

PWM

6

SKIP

5

VDD

BST

GND

PAD

9

1

C6618

2.2UF_6.3V_2

2

43

LXA2

44

VRA_READY

45

VRB_READY

46

CSPA1

47

CSNA1

48

CSNA2

49

CSPA2

50

CSPA3

51

CSNA3

52

IMAXA

53

IMAXB

54

TMAX

55

VR_HOT#

56

AGND

P5V_A

2.2UF_6.3V_2

8

DH

1
7

LX

4

DL

3

P5V_A

15<

15<

15<

15<

VRCPU_HG2

CPU_BST2

VRCPU_LG2

IN

IN

IN

404142

38

39

DLA2

DHA2

VDDA

DLA1

BSTA2

MAX_MAX17039GTN+_TQFN_56P

ALERT#

VDIO

VCLK

VCC

TONA

1

564

3

2

14<

1

C6616

2

PVBAT

15<

VRCPU_LG1

CPU_BST1

INININ

37

BSTA1

U6600

TONB

IN

TONA

TONB

14<

IN

15<

36

DHA1

CSPB

7

VRCPU_HG1

15<

IN

35

LXA1

CSNB

8

10A

IN
IN
IN
IN

14<

PH3_PWM

VRCPU_PH1

IN

IN

34

333132

PWM_OUT

VR_ENABLE

9

10

1

TP6601

TP24

1

POWERPAD_2_0610

VRCPU_HG3
CPU_BST3
VRCPU_PH3
VRCPU_LG3

14<

14<

14<

14<

14<

14<

IMONA

PH3_SKIP#

CCVA

GNDSA

IN

IN

IN

30

CCVA

IMONA

GNDSA

DRSKIP

DLG

VDDB

DLB

BSTB

12

13

11

INININ

GPU_BST1

VRAXG_LG1

15<

15<

1

C6617

2.2UF_6.3V_2

2

PAD6600

1

FBB

GNDSB

14<

FBA

IN

29

FBA

VBOOTB
VBOOTA

CCI2
CCI1

THERMA
THERMB

N.C.

GNDSB
IMONB

CCVB

DHB

14

VRAXG_HG1

15<

SRA
SRB

FBB

LXB
GND

15<

15<
15<

2

15<

OUT
OUT

28
27
26
25
24
23
22
21
20
19
18
17
16
15
57

2

2

4.7UF_25V_5

P5V_A

3

1

C6601

4.7UF_25V_5 4.7UF_25V_5

R6605

1

9.53K_1%_2

IN
IN

IN
IN
IN
IN

IN
IN
IN
IN
IN

14<

FBA

14<

GNDSA

CHANGE by

1

C6600

2

1000PF_50V_2

2

1000PF_50V_2

VBOOTB
VBOOTA

SRA
SRB
THERMA
THERMB

FBB
GNDSB

IMONB

CCVB
VRAXG_PH1

IN
IN

C6609

C6608

14<
14<

14<
14<

14>

14>
14<

14<

Frank Hu

1
2

14<

C6602

2

1

1

2

470PF_50V_2

470PF_50V_2

15<

R6616

5.1K_1%_2

1

+VBAT_CPU

1

C6603

2

4.7UF_25V_5 4.7UF_25V_5 4.7UF_25V_5 4.7UF_25V_5

1

C6604

2

1

C6605

2

PVAXG

22

R6604

R6603

10_1%_2

1

1

R6601

10_1%_2

2

2

100_1%_2

1

CATCH R

CATCH R

R6602

100_1%_2

1

C6610

R6614

10_1%_2

1

1

R6612

10_1%_2

23>

2

2

1

1

C6611

2

2

1000PF_50V_2

2

1000PF_50V_2

VCCSENSE

IN

1

TP6600

2

C6614

1

1

C6613

2

INVENTEC

TITLE

CODE

SIZE

CS

Mon Jan 03 17:28:44 2011

DATE

2

C

SHEET

1

14<

C6606

1
2

2

4.7UF_25V_5

C6607

EVEREST-M
POWER VCORE

DOC.NUMBER

CS_1310AXXXXXX-MTR

14

of

1

D

CC

BB

AA

REV

97

A01

8 7

6 5

4 3

2

1

PVCORE

Q6705

+VBAT_CPU

NMOS_4D3S

G

4123

NMOS_4D3S

G

4123

8765

D

TPCA8065_H

S

8765

D

S

Q6704

1

2
1

2

R6711

4.7_5%_3

C6709

3300PF_50V_2

1

2

+

C6701

1500UF_2V

3

L6702

1

2

1

10K_5%_NTC

1

3 4

PAN_ETQP4LR36ZFC_4P

R6712

2

2.37K_1%_2

1

C6704

+

2

3

R6713

2

R6715

1

RSC_0402_DY

C6710

1

0.47UF_6.3V_2

470UF_2V

R6714

1

3.6K_1%_2

2

2

D

2

CC

+VBAT_CPU

14<

CPU_BST1

D

14<

VRCPU_HG1

14<

VRCPU_PH1

14<

VRCPU_LG1

IN

IN
IN

IN

1

2.2_5%_3

0.22UF_25V_3

2

C6707

Q6703

TPCA8057_H

2

1

R6710

8765

D

NMOS_4D3S

Q6702

G

TPCA8065_H

S

60A

4123

L6701

1

2

R6706

3 4

PAN_ETQP4LR36ZFC_4P

8765

D

NMOS_4D3S

G

S

4123

1

R6705

4.7_5%_3

2
1

C6706

3300PF_50V_2

2

2.37K_1%_2 10K_5%_NTC

2

2

R6709

C6708

R6708

1

3.6K_1%_2

2

2

2

1

R6707

1

1

RSC_0402_DY

1

0.47UF_6.3V_2

14<

14<
14<

14<

CPU_BST2

VRCPU_HG2
VRCPU_PH2

VRCPU_LG2

IN

IN
IN

IN

R6716

1

2.2_5%_3

2

2

C6711

0.22UF_25V_3

1

TPCA8057_H

14<

14<
14<

14<

CPU_BST3

VRCPU_HG3
VRCPU_PH3

VRCPU_LG3

IN

IN
IN

IN

R6717

1

2.2_5%_3
C6712

0.22UF_25V_3

2

2

1

Q6701

TPCA8057_H

+VBAT_CPU

NMOS_4D3S

G

23

4

NMOS_4D3S

G

4123

8765

D

TPCA8065_H

S

1

8765

D

S

Q6700

1

R6700

4.7_5%_3

2

1

C6700

3300PF_50V_2

2

L6700

1

2

1

10K_5%_NTC

1

3 4

PAN_ETQP4LR36ZFC_4P

R6701

2

2.37K_1%_2

R6702

2

R6704

1

RSC_0402_DY

C6703

1

0.47UF_6.3V_2

R6703

1

3.6K_1%_2

2

2

+VBAT_CPU

8765

14<

14<

GPU_BST1

VRAXG_HG1
VRAXG_PH1

VRAXG_LG1

1

IN

2.2_5%_3

IN
IN

IN

2

2

C6714

0.22UF_25V_3

1

TPCA8057_H

Q6707

R6723

2

D

NMOS_4D3S

Q6706

4 23

4123

TPCA8065_H

S

1

8765

D

S

1

R6718

4.7_5%_3

2
1

C6713

3300PF_50V_2

2

14<

GPU_CSP1

14<

GPU_CSN1

1

3 4

PAN_ETQP4LR36ZFC_4P

R6719

2

2.37K_1%_2

IN

IN

L6703

1

2

R6720

1

10K_5%_NTC

1

RSC_0402_DY

1

0.47UF_6.3V_2

2

R6722

C6715

R6721

1

3.6K_1%_2

2

2

G

NMOS_4D3S

G

33A

BB

2

AA

INVENTEC

TITLE

EVEREST-M

POWER VCORE

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Mon Jan 03 17:29:38 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

15

of

1

REV

97

A01

8 7

6 5

4 3

1

1

2

PAD6801

POWERPAD_2_0610

2

2

1

3.5A

D

U6800

1

R6805

86.6K_1%_2

2

TI_TPS51217DSCR_SON_10P

1

PGOOD

2

TRIP

3

EN

4 7

VFB

5

TRAN

1

R6806

1K_1%_2

2

1

C6809

2

47PF_50V_2

1

2

R6804

1

0_5%_3

C6800

2.2UF_6.3V_3

10

VBST

VRGPU_HG

9

DRVH

8

VRGPU_PH

SW

V5IN

6

VRGPU_LG

DRVL

GND

11

2

0.1UF_25V_2

C6804

1

2

5 6 7 8

NMOS_4D3S

G

G

3 214

678

3

214 5

D

TPCA8065_H

S

D

S

Q6800

Q6801

TPCA8A02_H

G

678

3

214 5

D

S

Q6802

TPCA8A02_H

1

C6803

2

4.7UF_25V_5

1

2

1

1

R6807

40.2K_1%_2

2

C6816

100PF_50V_2

2

1

C6805

2

4.7UF_25V_5

1

PAN_ETQP4LR36WFC_4P

D6800

SBR3U40P1_DY

C6802

CSC0402_DY

L6800

1

C6807

4.7UF_25V_5

2

2
43

1

R6810

100_5%_2

2

1
2

1

R6809

10.2K_1%_2

2

1

R6808

28.7K_1%_2

2

CONNECT TO GPU

1

C6808

470UF_2V

2

R6803

1

0_5%_2

+

PAD6800

1

POWERPAD_2_0610

1

POWERPAD_2_0610

2

1

PAD6803

1

2

2

OUT

30A

2

2

68>

1

C6810

+

470UF_2V470UF_2V

2

1

C6806

+

2

FOR OPTIMUS SHUTDOWN SOLUTION

+GPU_NVVDD_L

D

CC

BB

3

Q6803

R6040

0_5%_2

2

SSM3K7002BFU

1

DS

1

G

2

NVVDD

2

R6048

33.2K_1%_2

VID0

VID1

VOLTAGE LEVEL

1

0.825V

AA

1V

0.975V

R6041

1

0_5%_2

0

0

3

Q6804

2

1

SSM3K7002BFU

DS

G

0

1

1

0

2

INVENTEC

TITLE

EVEREST-M
POWER GPU NVVDD

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Tue Jan 04 00:17:23 2011

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

16

of

1

REV

97

A01

8 7

6 5

4 3

2

1

P15V_A

WS

D

P5V_AL

100K_5%_2

1

R7035

10K_5%_2

2

SLP_S3_5R

37<

SLP_S3#

18<
30>
11<

OUT

IN

Q7088

1

SSM3K7002BFU

3

DS

G

SSM3K7002BFU

2

R7036

Q7090

1

1

2

R7039

1

0_5%_2

3

DS

G

2

OUT

SLP_S3#_15R

P3V3_AL

2

Q7005

1

D

2
5

AO6402AL

C7030

CSC0402_DY

NMOS_4D1S

1

2

19<18<17<

24<

POWERPAD_2_0610

1

2

1

1

2

2

C7026

22UF_6.3V_5

PAD7001

2

R7033

200_5%_3

1

Q7001

3

DS

1

2

SSM3K7002BFU

G

OUT

SLP_S3_5R

17> 17< 19<

D

4

S

36

G

1

C7029

22UF_6.3V_5

2

CC

P3V3_S

SLP_S3#_15R

P5V_A

IN

1
2
5

Q7004

D

NMOS_4D1S

AO6402AL

R7034

1

0_5%_2

P1V5

P5V_S

1

1

2

PAD7002

POWERPAD_2_0610

2

4

S

36

G

24<

19< 18<

17<

17>

SLP_S3#_15R

11.5A

IN

8
7
6

Q7002

D

NMOS_4D3S

AON7410

R7037

1

750K_1%_2

17>19<

S

G

2

SLP_S3_5R

1
2
3
45

IN

P0V75_S

1

R7032
22_5%_2

2

1

C7028

680PF_50V_2

2

PAD7000

1

1

POWERPAD_2_0610

2

3

1

C7027

CSC0402_DY

19< 17< 17>

SLP_S3_5R

OUT

DS

Q7000

1

G

SSM3K7002BFU

2

2

2

Q7003

1

G

SSM3K7002BFU

P1V5_S

1

R7038
200_5%_2

2

3

DS

2

BB

2

AA

INVENTEC

TITLE

EVEREST-M

POWER +V3S/+V5S/+V1.5S

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:26 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

17

of

1

REV

97

A01

8 7

18>

+V1.05_LAN_PG

P3V3_A

5

U7000

+

1

2

-

3

TC7SZ08FU

4

C7025

10K_5%_2

2

1

2

37<

19<

18<

30>

SLP_A#

R7028

IN

1

D

+V3M

R7005

1

100K_5%_2

2

1UF_6.3V_2

6 5

37< 30>

18<19<

SLP_A#

IN

P3V3_A

1

C7009

0.1UF_16V_2

2

5

U7001

+

1
2

-

3

TC7SZ08FU

4 3

2

D7001

R7029

1

IN

2

0_5%_2

BAT54_30V_0.2A

NC

3

1

OUT

PM_APWROK

30<

P3V3_A

2

P3V3_A

1

1

C7010

0.1UF_16V_2

1

C7011

0.1UF_16V_2

2

C7012

1

0.1UF_16V_2

2

D

2

5

R7001

4

1

2

3.3K_5%_2

1

C7000

0.1UF_16V_2

2

U7002

+

1

4

2

-

3

TC7SZ08FU

R7004

1

0_5%_2

2

1

C7001

0.1UF_10V_2_DY

2

5

U7003

+

1

4

2

-

3

TC7SZ08FU

OUT

+V1.05S_VCCP_EN

12<

P3V3_A

VCCSA_PG

R7002

1

10K_5%_2_DY

2

+V1.5S_CPUDDR_PG

20<

11>

37<

V1.5_PG

59<

R7006

IN

1

10K_5%_2

2

OUT

MAIN_PWRGD

60>

14<

1

C7002

0.1UF_16V_2

2

+V1.05_LAN_M

R7009

1

110K_1%_2

2

1

C7004

0.1UF_10V_2_DY

2

IN
IN

309K_1%_2

1

2

R7000

1

1M_1%_2

R7007

C7005

1000PF_50V_2

1

R7003

0_5%_2

2

1

2

1

R7008
100K_1%_2

2

2

P3V3_A

C7003

1
2

0.1UF_16V_2

U7005

+

5

1

+

4

OUT

3

-

-

2

AZV331KTR_E1

P3V3_A

1

R7010
10K_1%_2

2

37<

17< 11<

OUT

30>

SLP_S3#

38<

14>

VR_PWRGD

37>30<

EC_PCH_PWROK

+V1.05_LAN_PG

P3V3_A

18<

IN

IN
IN

P3V3_A

1

2

5

U7004

+

-

TC7SZ08FU

3

CC

1

C7013

0.1UF_16V_2

2

4

OUT

ALLSYS_PWROK

BB

WS

OUT

DRAMRST_CNTRL_CPU

P1V5

19<
17>

SLP_S3#_15R

17<
24<

P1V5_CPUDDRS

8

1

R7015

P3V3_SP3V3_A

R7016

2

1

R7024
10K_5%_2

2

D7000

2

BAT54_30V_0.2A

IN

3

R7023

1

330_5%_2

NC

1

Q7064

2

LMBT3904LT1G

SSM3K7002BFU

C E

1

B

2 3

7 6

1

R7025
10K_5%_2

2

Q7065

3

DS

1

G

2

R7030

0_5%_2

2

1

2

OUT

C7006

1000PF_50V_2

+V1.5S_CPUDDR_PG

11<

20<

18<

1

5 4

DRAMRST_CNTRL_EC

DRAMRST_CNTRL_PCH

IN

IN

1

0_5%_2_DY

R7026

1

0_5%_2

C7008

470PF_50V_2

1K_5%_2

2

3

Q7053

2

1

BSH111

1

2

CHANGE by

G

Frank Hu

2

DS

1

R7014

4.99K_1%_2

2

3

1

R7013
1K_5%_2

2

R7027

1

1K_5%_2

R7031

1

0_5%_2

Fri Dec 31 10:16:27 2010

DATE

2

2

OUT

DDR3_DRAMRST#

26>
27>

AA

2

OUT

CPU_DRAMRST#

20>

INVENTEC

TITLE

EVEREST-M

POWER SEQ

SIZE

C

CODE

CS

CS_1310AXXXXXX-MTR

SHEET

DOC.NUMBER

18

of

1

REV

97

A01

8 7

6 5

4 3

2

1

P3V3_A

P5V_A

+V1.05_LAN_M

P5V_A

+V1.05M

D

37<

18< 30>

SLP_A#

Q7062

8

D

R7022

10K_1%_2

1

2

2

220K_5%_2

R7020

1

7
6

NMOS_4D3S

AON7410

3

DS

Q7061

G

1

3

DS

IN

1

G

Q7063

SSM3K7002BFU

2

SSM3K7002BFU

2

1

2

C7016

680PF_50V_2

S

G

1
2
3
45

C7024

1

0.1UF_10V_2_DY

1

C7018

10UF_6.3V_3

2

2

1

R7021
200_5%_2

2

3

DS

G

Q7060

SSM3K7002BFU

2

1

P1V05_VCCPS

PAD7003

1

1

POWERPAD_2_0610

+V1.05S

2

2

1

C7019

10UF_6.3V_3

2

12<

30>37<

SLP_LAN#

IN

2

R7019

47K_5%_2

1

R7018

1

100K_5%_2

3

DS

G

Q7059

SSM3K7002BFU

2

1

2

P3V3_A

1

C7014

2

0.01UF_50V_2

S

G

PMOS_4D1S

AM3423P

C7015

2

1

330PF_50V_2_DY

Q7006

D

1

4

3 6

G

1
2
5

+V3M

1

2

2

R7017
200_5%_3

1

3

DS

Q7058

SSM3K7002BFU

2

D

C7017

10UF_6.3V_3

CC

P1V5_CPUDDRS

BB

AA

24<

17<

18< 17>

SLP_S3#_15R

P1V5

IN

17>17<

Q7052

8

D

7
6

AON7410

SLP_S3_5R

NMOS_4D3S

R7011

1

0_5%_2

1

S

2
3
45

G

1

R7012

200_5%_2

1

C7007

470PF_50V_2

2

2

IN

SSM3K7002BFU

2

Q7051

3

DS

1

G

2

C7023

1
2

0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2

C7022

1
2

C7021

1
2

C7020

1

2

0.1UF_16V_2

P1V5_CPUDDRS

P1V5

INVENTEC

TITLE

EVEREST-M
POWER SEQ

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:27 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

19

of

1

REV

97

A01

8 7

6 5

4 3

2

1

REMOVE CLKOUT_DMI_CLKGEN_DP

CN4500

D

C26

AN34

AL33

AN33

AL32

AN32

AM34

AP33

V8

AR33

PROC_SELECT#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

CLOCKS

DPLL_REF_CLK

DPLL_REF_CLK#

THERMAL MISC

MISCDDR3

PWR MANAGEMENT

JTAG & BPM

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

20>

H_SNB_IVB#

DMI&FDI TerminationVoltage

Set toVss when LOW

NV_CLE

Set toVcc when HIGH

18>

30>

PM_DRAM_PWRGD

+V1.5S_CPUDDR_PG

18<

P1V8_S

1

2

OUT

100K_5%_2_DY

IN
IN

R4537

2.2K_5%_2

Place close to CPT and NVRAM connector

R4538

1

4.7K_5%_2

(Default)

P3V3_A

1

R4512

2

NXP_74AHC1G09GV_SOT753_5P

2

1

R4511

200_5%_2

2

U4502

1

2
3

OUT

NV_CLE

14>

H_PROCHOT#

P3V3_A

5

VCC

B
A

GND

4

Y

32>

47PF_50V_2

C4570

1

0.1UF_16V_2

2

P1V05_VCCPS

R4510

62_5%_2

OUT

C4504

P1V5_CPUDDRS

R4532

200_5%_2

R4513

39_5%_2

1

37<>

2

1

2

33<

PM_THRMTRIP#

1

60>
33>

2

1

2

20>

H_SNB_IVB#

1

33>

H_PECI

LOW IN C6/C7

30<>

H_PM_SYNC

H_CPUPWRGD

R4500

1

130_1%_2

20>

BUF_PLT_RST#_CPU

R4517

0_5%_2_DY

OUT

OUT

2

2

BI

IN

OUT

TP4500

H_CATERR#_R

R4516

1

43_5%_2

1

56_5%_2

R4535

1

0_5%_2

R4536

1

1

0_5%_2

2

2

2

R4534

0_5%_2

R4533

PM_THRMTRIP#_R

PM_DRAM_PWRGD_R

1

H_PECI_R

H_PROCHOT#_R

H_PM_SYNC_R

2

H_CPUPWRGD_R

2

IN

3

SLP_S3_5R

Q4500

IN

SSM3K7002BFU

1

DS

G

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

2

CLKOUT_DMI_PCH_R_DP

A28

BCLK

A27

BCLK#

CLKOUT_DMI_PCH_R_DN

CLK_DP_PCH_CPU_R_DP

A16
A15

CLK_DP_PCH_CPU_R_DN

R8

AK1
A5
A4

AP29

PRDY#

AP27

PREQ#

AR26

TCK

AR27

TMS

AP30

TRST#

AR28

TDI

AP26

TDO

AL35

DBR#

AT28

BPM#[0]

AR29

BPM#[1]

AR30

BPM#[2]

AT30

BPM#[3]

AP32

BPM#[4]

AR31

BPM#[5]

AT31

BPM#[6]

AR32

BPM#[7]

CLKOUT_DMI_CLKGEN_DN

2

R4542
R4541

R4531
R4530

1
1

1
1

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

SYS_RESET#_R

OUT

IN
IN

IN
IN

IN

OUT

2

2
2

R4507
R4506
R4505

R4529

1

0_5%_2

0_5%_2

0_5%_2
0_5%_2

1
1
1

H_PRDY#
H_PREQ#

H_TCK
H_TMS
H_TRST#
H_TDI
H_TDO

0_5%_2

2

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

WS

CLK_DMI_PCH_DP

IN
IN

CLK_DMI_PCH_DN

CLK_DP_PCH_CPU_DP

IN
IN

CLK_DP_PCH_CPU_DN

OUT

CPU_DRAMRST#

140_1%_2

2

2

25.5_1%_2

2

200_1%_2

60<

20<60>

60> 20<

20<60>

60<

OUT

20<60>
20<60>

SYS_RESET#

P1V05_VCCPS

60<>

60<>

60<>

H_BPM0_XDP#
H_BPM1_XDP#
H_BPM2_XDP#
H_BPM3_XDP#
H_BPM4_XDP#
H_BPM5_XDP#
H_BPM6_XDP#
H_BPM7_XDP#

60<
60<
60<
60<
60<
60<
60<
60<

18>

60> 30<

29>

D

29>

29>
29>

CC

BB

P3V3_S

H_CPUPWRGD_R

R4556

60<>

1

C4559

0.1UF_16V_2

2

IN

U4501

1

10K_5%_2

2

R4557

BUF_PLT_RST#

56< 55<

32<>
43<

1

IN

2
3

TSB_TC7SZ07FU_SSOP_5P

NC

IN-A

GND

VCC

OUT-Y

P1V05_VCCPS

5

4

1

R4558

75_5%_2

2

R4509

1

43_5%_2

2

1

R4508
0_5%_2_DY

BUF_PLT_RST#_CPU

OUT

20<

60>20<

20< 60>

20< 60>

20< 60>

2

60>20<

H_PREQ#

60<>

H_TMS
H_TDI

H_TCK

H_TRST#

TITLE

1

IN
IN
IN

IN
IN

R4555

1

R4552

1

R4554

1
1

R4553

INVENTEC

EVEREST-M

51_5%_2

2

51_5%_2

2

51_5%_2_DY

2

51_5%_2

2
2

51_5%_2

AA

CPU 1

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:28 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

20

of

1

REV

97

A01

8 7

6 5

P1V05_VCCPS

4 3

2

1

DMI_TX_DN<3..0>

D

DMI_TX_DP<3..0>

DMI_RX_DN<3..0>

DMI_RX_DP<3..0>

FDI_TX_DN<7..0>

FDI_TX_DP<7..0>

P1V05_VCCPS

R4544

24.9_1%_2

IN

IN

0

1

2

3

OUT

OUT

0

1
2
3

0

1
2
3

OUT

0

1

2
3
4
5
6
7

OUT

30>

FDI_FSYNC0

30>

FDI_FSYNC1

30>

FDI_INT

30>

FDI_LSYNC0

30>

1

2

48>

FDI_LSYNC1

+V1.05S_VCCP_eDP_COMPIO

48>

EDP_HPD#

48<>

EDP_AUX_DP

48<>

EDP_AUX_DN

48>

EDP_TX0_DP

EDP_TX0_DN

0

1

2
3
4
5
6
7

OUT

DMI_TX_DN<0>

0

DMI_TX_DN<1>

1

DMI_TX_DN<2>

2

DMI_TX_DN<3>

3

DMI_TX_DP<0>
DMI_TX_DP<1>
DMI_TX_DP<2>
DMI_TX_DP<3>

DMI_RX_DN<0>
DMI_RX_DN<1>
DMI_RX_DN<2>
DMI_RX_DN<3>

DMI_RX_DP<0>
DMI_RX_DP<1>

DMI_RX_DP<2>
DMI_RX_DP<3>

FDI_TX_DN<0>

FDI_TX_DN<1>

FDI_TX_DN<2>
FDI_TX_DN<3>

FDI_TX_DN<4>
FDI_TX_DN<5>

FDI_TX_DN<6>
FDI_TX_DN<7>

FDI_TX_DP<0>
FDI_TX_DP<1>
FDI_TX_DP<2>
FDI_TX_DP<3>
FDI_TX_DP<4>
FDI_TX_DP<5>
FDI_TX_DP<6>
FDI_TX_DP<7>

IN
IN

IN
IN

IN

IN

BI
BI

OUT

B27
B25
A25
B24

B28
B26
A24
B23

G21
E22
F21
D21

G22
D22
F20
C21

A21
H19
E19
F18
B21
C20
D18
E17

A22
G19
E20
G18
B20
C19
D19
F17

J18
J17

H20
J19

H17

A18
A17
B16

C15
D15

C17
F16
C16
G15

C18
E16
D16
F15

CN4500

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

FDI0_FSYNC
FDI1_FSYNC

FDI_INT

FDI0_LSYNC
FDI1_LSYNC

eDP_COMPIO
eDP_ICOMPO
eDP_HDP#

eDP_AUX
eDP_AUX#

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

DMI

Intel(R) FDI

eDP

PCI EXPRESS* - GRAPHICS

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

+V1.05S_VCCP_PEG_ICOMPI

IN

PEG_RX15_DN

IN

PEG_RX14_DN

IN

PEG_RX13_DN

IN

PEG_RX12_DN

IN

PEG_RX11_DN

IN

PEG_RX10_DN

IN

PEG_RX9_DN

IN

PEG_RX8_DN

IN

PEG_RX7_DN

IN

PEG_RX6_DN

IN

PEG_RX5_DN

IN

PEG_RX4_DN

IN

PEG_RX3_DN

IN

PEG_RX2_DN

IN

PEG_RX1_DN

IN

PEG_RX0_DN
PEG_RX15_DP

IN
IN

PEG_RX14_DP

IN

PEG_RX13_DP

IN

PEG_RX12_DP

IN

PEG_RX11_DP

IN

PEG_RX10_DP

IN

PEG_RX9_DP

IN

PEG_RX8_DP

IN

PEG_RX7_DP

IN

PEG_RX6_DP

IN

PEG_RX5_DP

IN

PEG_RX4_DP

IN

PEG_RX3_DP

IN

PEG_RX2_DP

IN

PEG_RX1_DP

IN

PEG_RX0_DP
PEG_TX15_C_DN

OUT
OUT

PEG_TX14_C_DN

OUT

PEG_TX13_C_DN

OUT

PEG_TX12_C_DN

OUT

PEG_TX11_C_DN

OUT

PEG_TX10_C_DN

OUT

PEG_TX9_C_DN

OUT

PEG_TX8_C_DN

OUT

PEG_TX7_C_DN

OUT

PEG_TX6_C_DN

OUT

PEG_TX5_C_DN

OUT

PEG_TX4_C_DN

OUT

PEG_TX3_C_DN

OUT

PEG_TX2_C_DN

OUT

PEG_TX1_C_DN

OUT

PEG_TX0_C_DN
PEG_TX15_C_DP

OUT
OUT

PEG_TX14_C_DP

OUT

PEG_TX13_C_DP

OUT

PEG_TX12_C_DP

OUT

PEG_TX11_C_DP

OUT

PEG_TX10_C_DP

OUT

PEG_TX9_C_DP

OUT

PEG_TX8_C_DP

OUT

PEG_TX7_C_DP

OUT

PEG_TX6_C_DP

OUT

PEG_TX5_C_DP

OUT

PEG_TX4_C_DP

OUT

PEG_TX3_C_DP

OUT

PEG_TX2_C_DP

OUT

PEG_TX1_C_DP

OUT

PEG_TX0_C_DP

1

2

R4545

24.9_1%_2

68>
68>
68>
68>
68>
68>

68>
68>
68>
68>
68>
68>
68>
68>
68>
68>

68>
68>
68>
68>
68>
68>

68>
68>
68>
68>
68>
68>
68>
68>
68>
68>

21<
21<
21<
21<
21<
21<
21<
21<
21<

21<
21<
21<
21<
21<
21<
21<
21<
21<

21<

21<

21<
21<
21<
21<
21<
21<

21<
21<
21<
21<
21<
21<

PEG_TX15_C_DN
PEG_TX14_C_DN
PEG_TX13_C_DN

PEG_TX12_C_DN
PEG_TX11_C_DN

PEG_TX10_C_DN

PEG_TX9_C_DN

PEG_TX8_C_DN
PEG_TX7_C_DN
PEG_TX6_C_DN

PEG_TX5_C_DN
PEG_TX4_C_DN
PEG_TX3_C_DN
PEG_TX2_C_DN
PEG_TX1_C_DN

PEG_TX0_C_DN

PEG_TX15_C_DP
PEG_TX14_C_DP
PEG_TX13_C_DP
PEG_TX12_C_DP
PEG_TX11_C_DP
PEG_TX10_C_DP

PEG_TX9_C_DP
PEG_TX8_C_DP
PEG_TX7_C_DP
PEG_TX6_C_DP
PEG_TX5_C_DP
PEG_TX4_C_DP
PEG_TX3_C_DP
PEG_TX2_C_DP
PEG_TX1_C_DP
PEG_TX0_C_DP

CLOSE to CPU

C4546

IN

C4545

IN

C4544

IN

C4543

IN

C4542

IN

C4541

IN

C4540

IN

C4539

IN

C4538

IN

C4537

IN

C4536

IN

C4535

IN

C4534

IN

C4533

IN

C4532

IN

C4531

IN

C4530

IN

C4529

IN

C4528

IN

C4527

IN

C4526

IN

C4525

IN

C4524

IN

C4523

IN

C4522

IN

C4521

IN

C4520

IN

C4519

IN

C4518

IN

C4517

IN

C4516

IN

C4515

IN

1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2

2
2
2
2

2
2
2
2
2
2
2
2
2
2
2
2

2
2
2
2

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

OUT

PEG_TX15_DN

OUT

PEG_TX14_DN

OUT

PEG_TX13_DN

OUT

PEG_TX12_DN

OUT

PEG_TX11_DN

OUT

PEG_TX10_DN

OUT

PEG_TX9_DN

OUT

PEG_TX8_DN

OUT

PEG_TX7_DN

OUT

PEG_TX6_DN

OUT

PEG_TX5_DN

OUT

PEG_TX4_DN
PEG_TX3_DN

OUT
OUT

PEG_TX2_DN

OUT

PEG_TX1_DN

OUT

PEG_TX0_DN

OUT

PEG_TX15_DP

OUT

PEG_TX14_DP

OUT

PEG_TX13_DP

OUT

PEG_TX12_DP

OUT

PEG_TX11_DP

OUT

PEG_TX10_DP

OUT

PEG_TX9_DP

OUT

PEG_TX8_DP

OUT

PEG_TX7_DP

OUT

PEG_TX6_DP

OUT

PEG_TX5_DP

OUT

PEG_TX4_DP

OUT

PEG_TX3_DP

OUT

PEG_TX2_DP

OUT

PEG_TX1_DP

OUT

PEG_TX0_DP

68<
68<
68<
68<
68<
68<

68<
68<
68<
68<

68<
68<
68<
68<
68<
68<

68<
68<
68<
68<

68<
68<
68<
68<
68<
68<

68<
68<
68<
68<
68<
68<

D

CC

BB

AA

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

INVENTEC

TITLE

EVEREST-M

CPU 2

CODE

SIZE

C

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:57 2010

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

21

of

1

REV

97

A01

8 7

6 5

4 3

2

1

M_A_DQ<63..0>

D

BI

26<

M_A_BS0

26<

M_A_BS1

26<

M_A_BS2

26<

M_A_CAS#

26<

M_A_RAS#

26<

M_A_WE#

M_A_DQ<0>

0

M_A_DQ<1>

1

M_A_DQ<2>

2

M_A_DQ<3>

3

M_A_DQ<4>

4

M_A_DQ<5>

5

M_A_DQ<6>

6

M_A_DQ<7>

7

M_A_DQ<8>

8

M_A_DQ<9>

9

M_A_DQ<10>

10

M_A_DQ<11>

11

M_A_DQ<12>

12

M_A_DQ<13>

13

M_A_DQ<14>

14

M_A_DQ<15>

15

M_A_DQ<16>

16

M_A_DQ<17>

17

M_A_DQ<18>

18

M_A_DQ<19>

19

M_A_DQ<20>

20

M_A_DQ<21>

21

M_A_DQ<22>

22

M_A_DQ<23>

23

M_A_DQ<24>

24

M_A_DQ<25>

25

M_A_DQ<26>

26

M_A_DQ<27>

27

M_A_DQ<28>

28

M_A_DQ<29>

29

M_A_DQ<30>

30

M_A_DQ<31>

31

M_A_DQ<32>

32

M_A_DQ<33>

33

M_A_DQ<34>

34

M_A_DQ<35>

35

M_A_DQ<36>

36

M_A_DQ<37>

37

M_A_DQ<38>

38

M_A_DQ<39>

39

M_A_DQ<40>

40

M_A_DQ<41>

41

M_A_DQ<42>

42

M_A_DQ<43>

43

M_A_DQ<44>

44

M_A_DQ<45>

45

M_A_DQ<46>

46

M_A_DQ<47>

47

M_A_DQ<48>

48

M_A_DQ<49>

49

M_A_DQ<50>

50

M_A_DQ<51>

51

M_A_DQ<52>

52

M_A_DQ<53>

53

M_A_DQ<54>

54

M_A_DQ<55>

55

M_A_DQ<56>

56

M_A_DQ<57>

57

M_A_DQ<58>

58

M_A_DQ<59>

59

M_A_DQ<60>

60

M_A_DQ<61>

61

M_A_DQ<62>

62

M_A_DQ<63>

63

OUT
OUT
OUT

OUT
OUT
OUT

SOCKET,CPU,989P,TIN,3.0MM,STR,SMD,TR

CN4500

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15

AE10
AF10

AE8
AD9
AF9

F10
G10

N10

M10

AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8

V6

C5
D5
D3
D2
D6
C6
C2
C3

F8
G9

F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8

N8
N7

M9
N9
M7

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

SA_CS#[0]

SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

SA_ODT[0]

SA_ODT[1]
RSVD_TP[9]

RSVD_TP[10]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4]

SA_DQS[5]

SA_DQS[6]

SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

M_A_DQS_DN<0>
M_A_DQS_DN<1>
M_A_DQS_DN<2>
M_A_DQS_DN<3>
M_A_DQS_DN<4>
M_A_DQS_DN<5>

M_A_DQS_DN<6>
M_A_DQS_DN<7>

M_A_DQS_DP<0>
M_A_DQS_DP<1>
M_A_DQS_DP<2>
M_A_DQS_DP<3>
M_A_DQS_DP<4>
M_A_DQS_DP<5>
M_A_DQS_DP<6>
M_A_DQS_DP<7>

M_A_A<0>
M_A_A<1>
M_A_A<2>
M_A_A<3>
M_A_A<4>
M_A_A<5>
M_A_A<6>
M_A_A<7>
M_A_A<8>
M_A_A<9>
M_A_A<10>
M_A_A<11>
M_A_A<12>
M_A_A<13>
M_A_A<14>
M_A_A<15>

27<>

M_B_DQ<63..0>

M_CLK_DDR0_DP

OUT
OUT

M_CLK_DDR0_DN

OUT

M_CKE0

M_CLK_DDR1_DP

OUT
OUT

M_CLK_DDR1_DN

OUT

M_CKE1

M_CS#0

OUT
OUT

M_CS#1

OUT

M_ODT0

OUT

M_ODT1

BI

0

1
2
3
4
5
6
7

BI

0

1
2
3
4
5
6
7

OUT

0

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15

26<
26<

26<
26<

M_A_DQS_DN<7..0>

M_A_DQS_DP<7..0>

M_A_A<15..0>

27<
27<
27<

27<
27<
27<

BI

26<

26<
26<

26<
26<
26<

26<>

M_B_BS0
M_B_BS1
M_B_BS2

M_B_CAS#
M_B_RAS#
M_B_WE#

0

M_B_DQ<0>

1

M_B_DQ<1>

2

M_B_DQ<2>

3

M_B_DQ<3>

4

M_B_DQ<4>

5

M_B_DQ<5>

6

M_B_DQ<6>

7

M_B_DQ<7>

8

M_B_DQ<8>
M_B_DQ<9>

9

M_B_DQ<10>

10

M_B_DQ<11>

11

M_B_DQ<12>

12

M_B_DQ<13>

13

M_B_DQ<14>

14

M_B_DQ<15>

15

M_B_DQ<16>

16

M_B_DQ<17>

17

M_B_DQ<18>

18

M_B_DQ<19>

19

M_B_DQ<20>

20

M_B_DQ<21>

21

M_B_DQ<22>

22

M_B_DQ<23>

23

M_B_DQ<24>

24

M_B_DQ<25>

25

M_B_DQ<26>

26

M_B_DQ<27>

27

M_B_DQ<28>

28

M_B_DQ<29>

29

M_B_DQ<30>

30

M_B_DQ<31>

31

M_B_DQ<32>

32

M_B_DQ<33>

33

M_B_DQ<34>

34

M_B_DQ<35>

35

M_B_DQ<36>

36

M_B_DQ<37>

37

M_B_DQ<38>

38

M_B_DQ<39>

39

M_B_DQ<40>

40

M_B_DQ<41>

41

M_B_DQ<42>

42

M_B_DQ<43>

43

M_B_DQ<44>

44

M_B_DQ<45>

45

M_B_DQ<46>

46

M_B_DQ<47>

47

M_B_DQ<48>

48

M_B_DQ<49>

49

M_B_DQ<50>

50

M_B_DQ<51>

51

M_B_DQ<52>

52

M_B_DQ<53>

53

M_B_DQ<54>

54

M_B_DQ<55>

55

M_B_DQ<56>

56

M_B_DQ<57>

57

M_B_DQ<58>

58

M_B_DQ<59>

59

M_B_DQ<60>

60

M_B_DQ<61>

61

M_B_DQ<62>

62

M_B_DQ<63>

63

OUT
OUT
OUT

OUT
OUT
OUT

CN4500

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]

AM5

SB_DQ[32]

AM6

SB_DQ[33]

AR3

SB_DQ[34]

AP3

SB_DQ[35]

AN3

SB_DQ[36]

AN2

SB_DQ[37]

AN1

SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]

AN9

SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]

AN8

SB_DQ[45]

AR6

SB_DQ[46]

AR5

SB_DQ[47]

AR9

SB_DQ[48]

AJ11

SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]

AH11

SB_DQ[52]

AR8

SB_DQ[53]

AJ12

SB_DQ[54]

AH12

SB_DQ[55]

AT11

SB_DQ[56]

AN14

SB_DQ[57]

AR14

SB_DQ[58]

AT14

SB_DQ[59]

AT12

SB_DQ[60]

AN15

SB_DQ[61]

AR15

SB_DQ[62]

AT15

SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

AA10

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

DDR SYSTEM MEMORY B

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

SB_CS#[0]

SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

SB_ODT[0]

SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AE2
AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

M_B_DQS_DN<0>
M_B_DQS_DN<1>
M_B_DQS_DN<2>
M_B_DQS_DN<3>
M_B_DQS_DN<4>
M_B_DQS_DN<5>
M_B_DQS_DN<6>
M_B_DQS_DN<7>

M_B_DQS_DP<0>
M_B_DQS_DP<1>
M_B_DQS_DP<2>
M_B_DQS_DP<3>
M_B_DQS_DP<4>
M_B_DQS_DP<5>
M_B_DQS_DP<6>
M_B_DQS_DP<7>

M_B_A<0>
M_B_A<1>
M_B_A<2>
M_B_A<3>
M_B_A<4>
M_B_A<5>
M_B_A<6>
M_B_A<7>
M_B_A<8>
M_B_A<9>
M_B_A<10>
M_B_A<11>
M_B_A<12>
M_B_A<13>
M_B_A<14>
M_B_A<15>

M_CLK_DDR2_DP

OUT

M_CLK_DDR2_DN

OUT
OUT

M_CKE2

M_CLK_DDR3_DP

OUT
OUT

M_CLK_DDR3_DN

OUT

M_CKE3

OUT

M_CS#2

OUT

M_CS#3

27<

27<
27<

27<

27<

27<

27<

D

27<

CC

OUT

M_ODT2

OUT

M_ODT3

BI

0
1
2
3
4
5
6
7

BI

0
1
2
3
4
5
6
7

M_B_A<15..0>

OUT

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15

27<
27<

M_B_DQS_DN<7..0>

M_B_DQS_DP<7..0>

27<>

BB

AA

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

INVENTEC

TITLE

EVEREST-M

CPU 3 DRAM

CODE

SIZE

CS

CHANGE by

8

7 6

5 4

3

Frank Hu

Fri Dec 31 10:16:57 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

22

of

1

REV

97

A01

8 7

6 5

4 3

2

1

PVCORE

1

C4580

10uF_6.3V_3 10uF_6.3V_3

1

C4579

2

2

D

1

C4584

2

10uF_6.3V_3 10uF_6.3V_3

1

C4586

2

10uF_6.3V_3

1

C4578

2

1

2

1

C4587

2

10uF_6.3V_3

1

2

C4583

C4577

22uF_6.3V_5 22uF_6.3V_5

1

C4591

2

1

C4590

2

22uF_6.3V_5 22uF_6.3V_5

1

C4574

2

1

C4573

2

22uF_6.3V_5 22uF_6.3V_5

1

C4564

2

22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5

1

C4565

2

1

C4582

2

1

C4594

2

10uF_6.3V_3 10uF_6.3V_3

1

C4593

2

22uF_6.3V_5

1

C4589

2

22uF_6.3V_5 22uF_6.3V_5

1

C4572

2

22uF_6.3V_5

1

C4576

2

8

1

C4581

2

10uF_6.3V_310uF_6.3V_3

1

C4585

2

1

C4592

2

22uF_6.3V_5

1

C4588

2

1

C4571

2

22uF_6.3V_5

1

C4575

2

7 6

CN4500

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

POWER

PEG AND DDR

CORE SUPPLY

SVID

SENSE LINES

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

5 4

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

AJ29
AJ30
AJ28

AJ35
AJ34

B10
A10

1

C4569

+

2

3

1

2

470UF_2V

+V1.05S_VCCP_VCCIO40

20mil

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

VCCSENSE_R
VSSSENSE_R

C4599

1

C4596

2

1

C4598

2

1

C4597

2

1

C4557

2

1

2

22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5

1

C4563

22uF_6.3V_5 22uF_6.3V_5

2

22uF_6.3V_5

C4560

1

C4562

2

1

2

C4561

22uF_6.3V_5

1

2

P1V05_VCCPS

1

R4528

2

0_5%_2

P1V05_VCCPS

CLOSE TO POWER IC

1

R4546

130_1%_2

2

OUT
OUT
OUT

14<
14<

VCC_SENSE_VTT
VSS_SENSE_VTT

Fri Dec 31 10:16:58 2010

DATE

2

R4527

R4526

1

2

1

1

R4525

130_1%_2

R4551
R4549
R4550

2

2

1
1

1

PVCORE

0_5%_2

0_5%_2

R4548

54.9_1%_2

2

43_1%_2

2

0_5%_2

2

0_5%_2

1

R4504

100_1%_2

2

1

R4503

100_1%_2

2

P1V05_VCCPS

R4502

10_1%_2

10_1%_2

1

2

1

R4501

2

3

1

2

OUT
OUT

WS

CHANGE by

1

R4547

75_1%_2

2

VCCSENSE
VSSSENSE

OUT
OUT

Frank Hu

P1V05_VCCPS

C4503

1

2

22uF_6.3V_5

C4566

22uF_6.3V_5

VR_SVID_ALRT#
VR_SVID_CLK
VR_SVID_DATA

INVENTEC

TITLE

CODE

SIZE

C

C4558

1

2

14<

14<>

EVEREST-M

CPU 4 POWER

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

23

of

D

CC

BB

AA

REV

97

A01

1

8 7

6 5

4 3

2

1

WS

Function

xxVccSA_Select[1]
[[ CPU PIN# C24

VID0 of VR ]]
SNB HIGH
IVB HIGH

SNB LOW

D

IVB LOW

0
0

1
1

xxVccSA_Select[0]

[[ CPU PIN# C22
VID1 of VR ]]

0
1

0

1

VCCSA VR Vout

0.90V

0.725V

0.80V

0.675V

SLP_S3#_15R

PVAXG

CN4500

SM_VREF

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

AK35
AK34

AL1

B4
D1

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

M27
M26
L26
J26
J25
J24
H26
H25

1

1

C4509

2

C4600

1

2

22uF_6.3V_5 22uF_6.3V_5 22uF_6.3V_5

1

2

C4510

2

C4601

1
2

C4604

22uF_6.3V_5_DY

1

+

32

C4506
470UF_2V

1

C4511

2

C4602

1

2

1

22uF_6.3V_5_DY

2

1

+

C4605

32

C4505
470UF_2V

1

C4512

2

22uF_6.3V_522uF_6.3V_5 22uF_6.3V_522uF_6.3V_5

C4603

1
2

22uF_6.3V_5

WS

1

C4513

2

22uF_6.3V_5

1

C4507

2

22uF_6.3V_5

1

C4514

2

22uF_6.3V_5

1

C4508

2

22uF_6.3V_5

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

POWER

LINES

GRAPHICS

VAXG_SENSE

VSSAXG_SENSE

SENSE

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

DDR3 -1.5V RAILS

P0V75_VREF_M

20/20 mil

IN

VAXG_SENSE

OUT
OUT

VSSAXG_SENSE

P0V75_VREF_M_H

6A

1

C4554

2

10uF_6.3V_3

R4524

1

0_5%_2

14<

14<

20/20 mil

CPU_CHA_VREFDQ

1

C4556

2

10uF_6.3V_3

Q4501

1
2
5

2

1

2

10uF_6.3V_3

D

NMOS_4D1S

AO6402AL

C4555

4

S

36

G

20/20 mil

1

2

CPU_CHB_VREFDQ

1

C4553

2

10uF_6.3V_3

1

C4502

2

10uF_6.3V_3

C4595

470pF_50V_2

1

C4552

2

10uF_6.3V_3

1

C4501

2

10uF_6.3V_3

WS

P1V8_S

P0V75_VREF_M_H

1

2

P1V5_CPUDDRS

1

C4551

2

10uF_6.3V_3

1

C4500

2

10uF_6.3V_3

R4523

100K_5%_2

1

C4568

2

P0V85_S

C4567

D

CC

+

220UF_2.5V

BB

1

+

2

220UF_2.5V

L4500

2

FBM_11_160808_181A15T

1

8

1

C4547

2

22uF_6.3V_5

1.1A

1

C4549

2

1uF_6.3V_2 1uF_6.3V_2

7 6

1

C4548

2

1

2

10uF_6.3V_3

VCCPLL

C4550

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

1.8V RAIL
MISC VREFSA RAIL

5 4

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

VCCIO_SEL

H23

C22
C24
A19

1

R4559

0_5%_2_DY

AA

OUT

VCCSA_SENSE

R4543

OUT

2

VCCSA_SEL

13<

1

WS

10K_5%_2

2

WS

INVENTEC

TITLE

EVEREST-M

CPU 5 POWER

CODE

SIZE

C

CHANGE by

Frank Hu

3

Mon Jan 03 17:28:06 2011

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

24

of

1

REV

97

A01

8 7

CN4500

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

D

AR19

AR16
AR13
AR10

AR7
AR4

AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10

AP7

AP4

AP1

AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AN7

AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10

AM7

AM4

AM3

AM2

AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AL7

AL4

AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AK7

AK4
AJ25

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96

VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28

AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2

W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26

N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27

K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10

G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

6 5

CN4500

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

4 3

60<

60<

60<
60<
60<
60<

60<
25<
60<
25<
25<
25<
25<
60<
60<
60<
60<

60<
60<

CFG<0>
CFG<1>
CFG<2>
CFG<3>
CFG<4>
CFG<5>
CFG<6>
CFG<7>
CFG<8>
CFG<9>
CFG<10>
CFG<11>
CFG<12>
CFG<13>
CFG<14>
CFG<15>
CFG<16>
CFG<17>

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

PEG Static Lane Reversal

CFG(2)

LOW eDP ENABLE

CFG(4)

1: (Default) Normal operation
0: Lane Reversed

1: (Default) eDP Disabled

0: eDP Enabled

PEG Defer Training

CN4500

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29

AJ31
AH31
AJ33
AH33

AJ26

CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

RSVD5

VCC_DIE_SENSE
VSS_DIE_SENSE

RESERVED

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER

RSVD28
RSVD29
RSVD30
RSVD31
RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9

RSVD_NCTF10

RSVD51
RSVD52

BCLK_ITP

BCLK_ITP#

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

KEY

L7
AG7
AE7
AK2
W8

AT26
AM33
AJ27

AH27
AH26

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AN35
AM35

AT2
AT1
AR1

B1

2

1

D

CC

IN

CLK_XDP_CLKGEN_DP

IN

CLK_XDP_CLKGEN_DN

BB

AA

PEG Static Lan Reversal

LOW eDP ENABLE

PCIE Port Bifurcation

PEG Defer Training

STRAP PIN

8

R4522

R4521

R4520

R4519

R4518

25>60<

CFG<2>

CFG<4>
CFG<5>

CFG<6>
CFG<7>

IN
IN
IN

IN
IN

7 6

1K_1%_2

1

1

1
1

1

2

1K_1%_2

2

2

1K_1%_2_DY

2

1K_1%_2_DY

2

1K_1%_2_DY

CFG(7)

1: (Default) PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

PCIE Port Bifurcation Straps

CFG[6:5]

5 4

11: (Default) x16 - Device 1 function 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled
00: x8, x4, x4 - Device 1 function 1 and 2 enabled

INVENTEC

TITLE

EVEREST-M

CPU 6 GND

CODE

SIZE

CS

CHANGE by

Frank Hu

3

Fri Dec 31 10:16:59 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

25

of

1

REV

97

A01

8 7

6 5

CHA

4 3

2

1

22>

M_A_A<15..0>

D

22>
22>
22>

22>

26<
26<

SA0_DIM0
SA1_DIM0

60< 27<

22<>

22<>

OUT
OUT

59<> 29<>

M_A_DQS_DP<7..0>

M_A_DQS_DN<7..0>

BI

22>

M_A_BS0

22>

M_A_BS1

22>

M_A_BS2

22>

M_CS#0

22>

M_CLK_DDR0_DP

M_CLK_DDR0_DN

M_CLK_DDR1_DP
M_CLK_DDR1_DN

M_CS#1

M_CKE0

22>

M_CKE1

22>

22>

M_A_CAS#

22>

M_A_RAS#

22>

M_A_WE#

PCH_3S_SMCLK

PCH_3S_SMDATA

22>

M_ODT0

22>

M_ODT1

IN

IN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15

M_A_DQS_DP<0>

0

M_A_DQS_DP<1>

1

M_A_DQS_DP<2>

2

M_A_DQS_DP<3>

3

M_A_DQS_DP<4>

4

M_A_DQS_DP<5>

5

M_A_DQS_DP<6>

6

M_A_DQS_DP<7>

7

M_A_DQS_DN<0>

0

M_A_DQS_DN<1>

1

M_A_DQS_DN<2>

2

M_A_DQS_DN<3>

3

M_A_DQS_DN<4>

4
5

M_A_DQS_DN<5>
M_A_DQS_DN<6>

6

M_A_DQS_DN<7>

7

M_A_A<0>
M_A_A<1>
M_A_A<2>
M_A_A<3>
M_A_A<4>
M_A_A<5>

M_A_A<6>
M_A_A<7>

M_A_A<8>
M_A_A<9>
M_A_A<10>
M_A_A<11>
M_A_A<12>
M_A_A<13>

M_A_A<14>
M_A_A<15>

107

119

109
108

114
121
101
103
102
104

115
110
113

197
201
202
200

116

120

136

153

170

187

137

154

171

188

135

152

169

186

98
97
96
95
92
91
90
86
89
85

84
83

80
78

79

73
74

11
28
46
63

12
29
47
64

10
27
45
62

CN4101

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

BELLW_80001_6021_204P

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

5
7

15

17
4
6

16

18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70

129

131

141

143

130

132

140

142

147

149

157

159

146

148

158

160

163

165

175

177

164

166

174

176

181

183

191

193

180

182

192

194

M_A_DQ<0>

M_A_DQ<1>

M_A_DQ<2>

M_A_DQ<3>
M_A_DQ<4>
M_A_DQ<5>
M_A_DQ<6>
M_A_DQ<7>
M_A_DQ<8>
M_A_DQ<9>
M_A_DQ<10>
M_A_DQ<11>
M_A_DQ<12>
M_A_DQ<13>
M_A_DQ<14>
M_A_DQ<15>
M_A_DQ<16>
M_A_DQ<17>
M_A_DQ<18>
M_A_DQ<19>
M_A_DQ<20>
M_A_DQ<21>
M_A_DQ<22>
M_A_DQ<23>
M_A_DQ<24>
M_A_DQ<25>
M_A_DQ<26>
M_A_DQ<27>
M_A_DQ<28>
M_A_DQ<29>
M_A_DQ<30>
M_A_DQ<31>
M_A_DQ<32>
M_A_DQ<33>
M_A_DQ<34>
M_A_DQ<35>
M_A_DQ<36>
M_A_DQ<37>
M_A_DQ<38>
M_A_DQ<39>
M_A_DQ<40>
M_A_DQ<41>
M_A_DQ<42>
M_A_DQ<43>
M_A_DQ<44>
M_A_DQ<45>
M_A_DQ<46>
M_A_DQ<47>
M_A_DQ<48>
M_A_DQ<49>
M_A_DQ<50>
M_A_DQ<51>
M_A_DQ<52>
M_A_DQ<53>
M_A_DQ<54>
M_A_DQ<55>
M_A_DQ<56>
M_A_DQ<57>
M_A_DQ<58>
M_A_DQ<59>
M_A_DQ<60>
M_A_DQ<61>
M_A_DQ<62>
M_A_DQ<63>

C4126

1

2

2.2UF_6.3V_2

22<>

C4122

1

2

1UF_6.3V_2

P3V3_S

1

2

P1V5

C4125

1
2

C4127

0.1UF_16V_2

DIMM0_VREF_DQ

1
2

C4119

1
2

0.1UF_16V_2

C4124

LAYOUT NOTE: PLACE
THESE CAPS NEAR
SO-DIMM0 POWER PIN

C4123

1
2

1UF_6.3V_21UF_6.3V_21UF_6.3V_2

C4140

1
2

1

C4137

2

26< 27>

18>
27>

DIMM0_VREF_CA

C4120

1
2

2.2UF_6.3V_2 0.1UF_16V_2

C4139

1
2

10UF_6.3V_310UF_6.3V_3

1

C4136

10UF_6.3V_310UF_6.3V_3

2

PM_EXTTS#1_R

DDR3_DRAMRST#

C4121

1
2

PLACE THESE CAPS
CLOSE TO VTT1 AND
VTT2

C4138

1
2

10UF_6.3V_3

1

C4135

10UF_6.3V_3

2

OUT
OUT

20/20 MIL

20/20 MIL

75
76
81
82
87
88
93
94

99
100
105
106
111
112
117
118
123
124

199

77
122
125

198

30

1

126

2
3
8

9
13
14
19

20
25
26
31
32
37
38
43

BELLW_80001_6021_204P

CN4101

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

VDDSPD

NC1
NC2
NCTEST

EVENT#
RESET#

VREF_DQ
VREF_CA

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

VTT1
VTT2

44
48
49
54
55
60
61
65
66
71
72

127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

1.5A

203
204

G1

G1

G2

G2

NOTE:PLACE C4100
ON COMMON PATH

FOR BOTH DIMM'S

C4110

1
2

C4100

1
2

1UF_6.3V_21UF_6.3V_2

1

2

C4109

1UF_6.3V_2

P0V75_S

C4128

1
2

1UF_6.3V_2

D

CC

BB

M_A_DQ<63..0>

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

21
22
23
24

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

BI

NOTE:

IF SA0_DIM0=0 , SA1_DIM0=0
SO-DIMMA SPD ADDRESS IS 0XA0
SO-DIMMA TS ADDRESS IS 0X30

IF SA0_DIM0=1 , SA1_DIM0=0
SO-DIMMA SPD ADDRESS IS 0XA2
SO-DIMMA TS ADDRESS IS 0X32

8

7 6

P3V3_S

1

1

R4102

10K_5%_2_DY

R4100

10K_5%_2 10K_5%_2

2

2

1

1

2

2

R4125

10K_5%_2_DY

R4101

IN

IN

SA0_DIM0

SA1_DIM0

26>

26>

26>27>

PM_EXTTS#1_R

IN

5 4

1

0_5%_2

R4127

2

P3V3_S

1

R4126

10K_5%_2

2

OUT

PM_EXTTS#1

WS

REMOVE 1UF CAP 1PCS

AA

INVENTEC

TITLE

EVEREST-M
DDR3 DIMM0

CODE

SIZE

CS

CHANGE by

Frank Hu

3

Fri Dec 31 10:17:00 2010

DATE

2

C

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

26

of

1

REV

97

A01

8 7

6 5

4 3

2

1

CHB

22>

M_B_A<15..0>

D

22>

22>

22>

22>

27<
27<

SA0_DIM1
SA1_DIM1

60<

22<>

22<>

OUT
OUT

29<>

59<>

26<

M_B_DQS_DP<7..0>

M_B_DQS_DN<7..0>

BI

22>

M_B_BS0

22>

M_B_BS1

22>

M_B_BS2

22>

M_CS#2

22>

M_CLK_DDR2_DP

M_CLK_DDR2_DN

M_CLK_DDR3_DP

M_CLK_DDR3_DN

PCH_3S_SMDATA

M_CS#3

22>

M_CKE2

22>

M_CKE3

22>

M_B_CAS#

22>

M_B_RAS#

22>

M_B_WE#

PCH_3S_SMCLK

22>

M_ODT2

22>

M_ODT3

IN

IN

107

119

109
108

114
121
101
103
102
104

115
110
113

197
201
202
200

116

120

136

153

170

187

137

154

171

188

135

152

169

186

98
97
96
95
92
91
90
86
89
85

84
83

80
78

79

73
74

11
28
46
63

12
29
47
64

10
27
45
62

CN4100

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

BELLW_80001_2021_204P

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

M_B_DQ<0>
M_B_DQ<1>

M_B_DQ<2>
M_B_DQ<3>

M_B_DQ<4>
M_B_DQ<5>
M_B_DQ<6>
M_B_DQ<7>
M_B_DQ<8>
M_B_DQ<9>
M_B_DQ<10>

M_B_DQ<11>
M_B_DQ<12>
M_B_DQ<13>

M_B_DQ<14>
M_B_DQ<15>
M_B_DQ<16>
M_B_DQ<17>

M_B_DQ<18>
M_B_DQ<19>
M_B_DQ<20>
M_B_DQ<21>
M_B_DQ<22>
M_B_DQ<23>
M_B_DQ<24>
M_B_DQ<25>
M_B_DQ<26>
M_B_DQ<27>
M_B_DQ<28>
M_B_DQ<29>
M_B_DQ<30>
M_B_DQ<31>
M_B_DQ<32>
M_B_DQ<33>
M_B_DQ<34>
M_B_DQ<35>
M_B_DQ<36>
M_B_DQ<37>
M_B_DQ<38>
M_B_DQ<39>
M_B_DQ<40>
M_B_DQ<41>
M_B_DQ<42>
M_B_DQ<43>
M_B_DQ<44>
M_B_DQ<45>

M_B_DQ<46>
M_B_DQ<47>
M_B_DQ<48>
M_B_DQ<49>
M_B_DQ<50>
M_B_DQ<51>

M_B_DQ<52>
M_B_DQ<53>

M_B_DQ<54>
M_B_DQ<55>

M_B_DQ<56>
M_B_DQ<57>

M_B_DQ<58>
M_B_DQ<59>

M_B_DQ<60>
M_B_DQ<61>

M_B_DQ<62>
M_B_DQ<63>

0

1

2
3
4
5

6

7

8

9
10
11
12
13
14
15
16

17
18
19

20

21

22
23

24

25

26
27
28
29

30
31
32
33
34

35
36
37
38
39
40
41
42

43
44

45
46
47
48
49

50

51
52
53
54
55
56
57
58
59
60
61
62
63

M_B_A<0>

0

1

M_B_A<1>
M_B_A<2>

2

M_B_A<3>

3

M_B_A<4>

4

M_B_A<5>

5

M_B_A<6>

6

M_B_A<7>

7

M_B_A<8>

8

M_B_A<9>

9

M_B_A<10>

10

M_B_A<11>

11

M_B_A<12>

12

M_B_A<13>

13

M_B_A<14>

14
15

M_B_A<15>

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

M_B_DQS_DP<0>

0

M_B_DQS_DP<1>

1

M_B_DQS_DP<2>

2

M_B_DQS_DP<3>

3

M_B_DQS_DP<4>

4

M_B_DQS_DP<5>

5

M_B_DQS_DP<6>

6

M_B_DQS_DP<7>

7

M_B_DQS_DN<0>

0

M_B_DQS_DN<1>

1

M_B_DQS_DN<2>

2

M_B_DQS_DN<3>

3

M_B_DQS_DN<4>

4
5

M_B_DQS_DN<5>
M_B_DQS_DN<6>

6

M_B_DQS_DN<7>

7

M_B_DQ<63..0>

BI

WS

REMOVE CPU_CHB_VREFDQ

NOTE:

SO-DIMMB SPD ADDRESS IS 0XA4

SO-DIMMB TS ADDRESS IS 0X34

SA1_DIM1

27>

IN

R4104

10K_5%_2

R4123

10K_5%_2_DY

22<>

C4112

1
2

1UF_6.3V_2

DIMM1_VREF_DQ

P3V3_S

1

1

R4124
10K_5%_2_DY

2

2

1

1

R4103
10K_5%_2

2

2

P1V5

1
2

IN

C4115

1UF_6.3V_2

1
2

SA0_DIM1

C4116

27>

C4114

1

2

1UF_6.3V_2

C4113

1

2

1UF_6.3V_2

P3V3_S

C4117

1
2

0.1UF_16V_22.2UF_6.3V_2

0.1UF_16V_2

LAYOUT NOTE: PLACE

THESE CAPS NEAR

SO-DIMM0 POWER PIN

C4134

1
2

10UF_6.3V_3

C4131

1
2

10UF_6.3V_3

PM_EXTTS#1_R

DDR3_DRAMRST#

1

C4104

DIMM1_VREF_CA

2

C4133

1
2

10UF_6.3V_3

C4130

1
2

10UF_6.3V_3 10UF_6.3V_3

C4105

1
2

2.2UF_6.3V_2

C4132

1
2

10UF_6.3V_3

C4129

1
2

1
2

PLACE THESE CAPS
CLOSE TO VTT1 AND
VTT2

OUT
OUT

20/20 MIL

20/20 MIL

C4106

0.1UF_16V_2

CN4100

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

BELLW_80001_2021_204P

C4108

1

2

1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2

20/20 MIL

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

VTT1
VTT2

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

1.5A

203
204

G1

G1

G2

G2

C4107

1
2

PLACE THESE CAPS
CLOSE TO VTT1 AND
VTT2

P0V75_S

C4102

1

2

C4101

1
2

D

CC

BB

CPU_CHA_VREFDQ

R4128

1K_5%_2_DY

DRAMRST_CNTRL_CPU

8

P0V75_VREF_M

P1V5_CPUDDRS

R4130

C4103

P1V5

1

2

1

2

DIMM1_VREF_DQ

1

R4122

1K_1%_2

2

1

R4121

1K_1%_2

2

R4143

2

1

0_5%_2_DY

1

R4119

0_5%_2

CPU_CHB_VREFDQ

R4120

2

1

0_5%_2_DY

2

1

R4110

1

0_5%_2

R4141
0_5%_2_DY

2

Q4101

1

D

2
5

NMOS_4D1S

AO6402AL

4

S

36

G

2

IN

5 4

1

2

P1V5

DIMM0_VREF_DQ

R4114

2

1

0_5%_2_DY

Q4100

4

S

1

2

3 6

G

NMOS_4D1S

AO6402AL

R4115

1

1

D

2

0_5%_2

5

IN

R4111

1

2

0_5%_2

R4142

1

0_5%_2_DY

R4144

1

0_5%_2_DY

R4118

1K_1%_2

2

R4117

1K_1%_2

1

2

2

1

1

2

2

2

2

R4129

1K_5%_2_DY

C4118

0.1UF_16V_2

1K_5%_2_DY

0.1UF_16V_2

1

7 6

DIMM0_VREF_CA

1K_5%_2_DY

R4131

1K_5%_2_DY

DRAMRST_CNTRL_CPU

1K_5%_2_DY

P1V5

R4132

R4133

1

R4136
0_5%_2

2

1

1

R4137

0_5%_2

2

2

1

2

1

2

R4138

1

C4141

0.1UF_16V_2

0_5%_2_DY

R4105

2

1

2

3

DIMM1_VREF_CA

R4139

2

1

0_5%_20_5%_2

1

2

CHANGE by

R4140

1

0_5%_2

R4116
0_5%_2_DY

2

1

0_5%_2_DY

Frank Hu

R4112

P1V5

1

R4134

1K_5%_2_DY

2

2

1

R4135

1K_5%_2_DY

2

Fri Dec 31 10:16:30 2010

DATE

2

1

C4142

0.1UF_16V_2_DY

2

INVENTEC

TITLE

CODE

SIZE

C

WS

EVEREST-M

DDR3 DIMM1

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

27

AA

REV

97

of

A01

1

8 7

P3V3_AL

1

2

NC

3

1

RTC BATTERY

2

D

U4703

1

+

2

-

MAXELL_ML1220_T10_2P

H-VCC VRM=1.5V
L- (Default) VCC VRM=1.8V

HDA_3S_SYNC

PCSPKR_PCH_3

No Reboot
1: No Reboot enabled

0: (Default) No Reboot disabled

HDA_3S_SDOUT

STRAP
Flash Override

Disable - (Default)Internal pull-down

Enable - pull-up

HDA_3S_SYNC_R

PCH_SPI_SI

FLASH DESCRIPTOR SECURITY OVERIDE

HDA_3S_SDOUT_R

FLASH_OVERRIDE

28<>
28<>

28<>

PCH_SPI_CS0#

28<>

PCH_SPI_SO

1

2

SIG442

1K_5%_2_DY

BI

OUT

OUT

OUT

BI

R4893

1

0_5%_2

IN

Q4705

AM2321P_DY

PCH_SPI_CS0#

PCH_SPI_SO

8

D4704

BAT54_30V_0.2A

+V_RTC

R4777

150_1%_3

R4778

1.2K_1%_3

P3V3_S

1

R4782

2

R4851

2

10K_5%_2_DY

R4783

2

1K_5%_2

P3V3_S

1

R4785

10K_5%_2_DY

2

HIGH:ENABLE
LOW:DISABLE

2

OUT

3

1

G

S D

2

BI
BI

+V3M_SPI

2

R4764

3.3K_5%_2

1

BI
BI

+V_RTC

C4762

1uF_6.3V_2

WS

P5V_S

1

Q4703

G

3

2

DS

SSM3K7002FU

P3V3_A

1

1

WS

STRAP PIN
HIGH - ENABLE ANTITHEFT
LOW - Internal

WS

HDA_3S_SDOUT_R

P3V3_A

R4892

1

2

1K_5%_2_DY

WINB_W25Q64BVSSIG_SOIC_8P

CN4701

1
2
3
4

ACES_91960_0084L_8P

2

10K_5%_2

1

1
2
3
4

CE#
SO
WP#
VSS

R4765

U4702

/CS
DO_IO1
/WP_IO2
GND

VDD

HOLD#

SCK

SI

/HOLD_IO3

DIO_ID0

7 6

R4762

1

20K_1%_2

R4760

1

1

R4761

1M_5%_2

20K_1%_2

1

2

2

STRAP

HDA_3S_BITCLK

HDA_3S_RST#

HDA_3S_SDIN0

HDA_3S_SDOUT

37>

EC_SMI

28<>

PCH_SPI_CLK

28<>

PCH_SPI_CS0#

PCH_SPI_CS1#

+V3M_SPI

VCC

CLK

28<>

28<>

8
7

6

5

BI
BI

8

R4766

7
6

BI

5

BI

2

1

1uF_6.3V_2

2

2

1

1uF_6.3V_2

2

R4813

BI

OUT

IN

OUT

IN

R4773

1

60>

60<>

PCH_TCK

61>

PCH_SPI_SI

PCH_SPI_SO

PCH_SPI_CLK
PCH_SPI_SI

3.3K_5%_2

1

2

PCH_SPI_CLK
PCH_SPI_SI

6 5

+V_RTC

C4763

330K_5%_3

C4761

R4759

1

2

+V_RTC_RTCRST#

+V_RTC_SRTCRST#

+V_RTC_INTRUDER#

R4767

R4770

R4769

WS

2

60<>

60<>

BI
BI

0_5%_2_DY

2

1

C4779

1

12pF_50V_2

51_5%_2

OUT

R4812

R4755

1

1

60>

60>

Q4704

2

SSM3K7002FU

2

1

28>

28>

1
1

33_1%_2

2

33_1%_2

2

33_1%_2

2

P5V_S

1

G

3

DS

dgnd

TP4713

PCH_TMS
PCH_TDI
PCH_TDO

33_5%_2

2

0_5%_2

2

HDA_3S_BITCLK_R

HDA_3S_SYNC_R

HDA_3S_RST#_R

1

33_1%_2

1

61>

61<

OUT

33_5%_2

1

BI
BI

28<>
28<>

+V3M_SPI

28<>

28<>

R4756

R4754

37<

37<

37<

1

C4764

0.1UF_16V_2

2

1

2

33_5%_2

2

37>

EC_SPI_CLK

EC_SPI_CS0#

37>

EC_SPI_SI

37>

EC_SPI_SO

1

R4772

10M_5%_2

2

RTCX1
RTCX2

R4768

2

HDA_3S_SDOUT_R

OUT
OUT
OUT

PCH_SPI_CLK_R

PCH_SPI_CS0#_R

PCH_SPI_MOSI_R

OUT

OUT

OUT

CLOSED TO EC

4

X4701

32.768KHZ

1

2 3

U4700

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN#/GPIO33

N32

HDA_DOCK_RST#/GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

ITL_PANTHERPOINT_FCBGA_989P

R4800

1

33_5%_2_DY

33_5%_2_DY

33_5%_2_DY

1

0_5%_2_DY

R4799

1

R4798

1

R4797

2

2

2

1

0_5%_2_DY

1

0_5%_2_DY

1

0_5%_2_DY

1

0_5%_2_DY

CLOSED TO PCH

5 4

4 3

+V3M

C4766

2

18pF_50V_2

C4765

2

18pF_50V_2

JTAG

R4804

R4803

R4802

R4801

1

1

RTC

IHDA

SPI

2

22

2

2

INTVRMEN-

high- Enable Internal VRs
low-Enable External VRs

LPC

SATA 6G

SATA

BI

PCH_SPI_CLK

BI

PCH_SPI_CS0#

BI

PCH_SPI_SI

BIIN

PCH_SPI_SO

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

R4786

1

0_5%_3

1.05V VRM Enable

C38
A38
B37
C37

D36
E36

K36
V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11
Y10

AB12
AB13

AH1

P3
V14
P1

+V3M_SPI

2

BI
BI
BI
BI

OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

+V1.05S_SATAICOMPO

+V1.05S_SATA3RCOMPO

PCH_XDPFN10
PCH_XDPFN11

R4850

1K_5%_2_DY

28<>

STRAP PIN

28<>

PCH_SPI_CS1#

28<>

28<>

CHANGE by

3

2

P3V3_A

+V1.05S

60> 28>

61>

60<>

PCH_TDI

60>

28>

PCH_TMS

61>

60<>
60>

28>

PCH_TDO

61<

60<>

LPC_3S_AD<0>
LPC_3S_AD<1>
LPC_3S_AD<2>
LPC_3S_AD<3>

R4707

1

0_5%_2

R4708

1

RSC_0402_DY

LPC_3S_FRAME#

R4758

1

10K_5%_2

BI

PCI_3S_SERIRQ

SATA_SSD_RX_DN
SATA_SSD_RX_DP
SATA_SSD_TX_DN
SATA_SSD_TX_DP

SATA_HDD_RX_DN
SATA_HDD_RX_DP
SATA_HDD_TX_DN

SATA_HDD_TX_DP
SATA_ODD_RX_DN

SATA_ODD_RX_DP
SATA_ODD_TX_DN
SATA_ODD_TX_DP

SATA_ESATA_RX_DN
SATA_ESATA_RX_DP

SATA_ESATA_TX_DN
SATA_ESATA_TX_DP

SATA_mSATA_RX_DN
SATA_mSATA_RX_DP

SATA_mSATA_TX_DN
SATA_mSATA_TX_DP

R4890

1

750_1%_2

1
2

OUT

Frank Hu

2

2

OUT

PCH_XDPFN11

R4763

1

RSC_0402_DY

DATE

Sun Jan 02 19:22:09 2011

2

2

OUT
OUT
OUT

37<>
37<>
37<>

55<
37<>
43<

WS

R4757

1

37.4_1%_2

R4891

1

49.9_1%_2

R4852

10K_5%_2

2

2

Placememt note

1

R4706

210_1%_2

2

1

R4705

100_1%_2

2

55<

43<

55<43<

43< 55<

P3V3_S

37<>

55<

43<

SATA SSD

SATA HDD

SATA ODD

eSATA

mSATA

+V1.05S

2

+V1.05S

2

P3V3_S

121

2

28>

1

R4823

0_5%_2_DY

2

INVENTEC

TITLE

SIZE

C

1

R4704

210_1%_2

2

1

R4703

100_1%_2

2

R4771

10K_5%_2

OUT

LED_3S_SATA#

OUT

PCH_XDPFN10

EVEREST-M
PCH 1

CODE

CS

CS_1310AXXXXXX-MTR

SHEET

2

1

2

DOC.NUMBER

28

1

1

R4702

210_1%_2

R4701

100_1%_2

of

1

D

CC

Distance between the PCH and

cap on the "P" signal should be
identical distance between the
PCH and cap on the "N" signal

for same pair

BB

58<

28>

AA

REV

A01

97

8 7

6 5

4 3

2

1

WS

CLKREQ_USB3#

CLKREQ_CR#

D

CLKREQ_WLAN#

27<
59<>
26<
60<

PCH_3S_SMCLK

29<>

PCH_3A_SMCLK

PCH_3A_SMDATA

55<>

PCH_3S_SMDATA

IN

IN

IN

CLKREQ_LAN#

IN

STUFF FOR INTEGRATED CLK

CLKIN_DMI_PCH_DN

CLKIN_DMI_PCH_DP

CLKIN_BUF_DOT96_DN

CLKIN_BUF_DOT96_DP

CLKIN_PCH14

CLKIN_SATA1_DP
CLKIN_SATA1_DN

R4745

2.2K_5%_2

BI

BI

BI

BI

8

10K_5%_2_DY

10K_5%_2_DY

P3V3_S

1

1

2

2

R4894

1

10K_5%_2

R4895

1

10K_5%_2

R4731

1

10K_5%_2

R4730

1

R4748

1

R4744

2.2K_5%_2

R4743

2.2K_5%_2

P3V3_S

2

2

P3V3_A

2

2

2

R4796

IN

R4795

IN

R4794

IN

R4793

IN

R4792

IN

R4788

IN

R4787

IN

P3V3_A

1

1

2

2

USB3.0

CARD READER

WLAN

2

1

1

2

1

2

1

2

1

2

1

2

1

2

P5V_S

R4742

2.2K_5%_2

2

1

G

DS

Q4703

3

SSM3K7002BFU

3

DS

1

G

Q4702

2

SSM3K7002BFU

60<

CLK_XDP_DN
CLK_XDP_DP

60<

7 6

3G

LAN

10K_5%_2

10K_5%_2

10K_5%_2

10K_5%_2

10K_5%_2

10K_5%_2

10K_5%_2

PCIE_USB3_RX_DN
PCIE_USB3_RX_DP
PCIE_USB3_TX_DN
PCIE_USB3_TX_DP

PCIE_CR_RX_DN
PCIE_CR_RX_DP
PCIE_CR_TX_DN
PCIE_CR_TX_DP

PCIE_WLAN_RX_DN
PCIE_WLAN_RX_DP

PCIE_WLAN_TX_DN
PCIE_WLAN_TX_DP

PCIE_3G_RX_DN
PCIE_3G_RX_DP
PCIE_3G_TX_DN
PCIE_3G_TX_DP

WS

PCIE_LAN_RX_DN
PCIE_LAN_RX_DP
PCIE_LAN_TX_DN
PCIE_LAN_TX_DP

P3V3_A

CLK_PCIE_LAN_DN

CLK_PCIE_LAN_DP

CLKREQ_LAN#

OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

C4780
C4781

C4782
C4783

C4758
C4757

C4784
C4785

C4760
C4759

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

P3V3_A

WS

1

CLK_PCIE_USB3_DN
CLK_PCIE_USB3_DP

CLKREQ_USB3#

CLK_PCIE_CR_DN
CLK_PCIE_CR_DP

CLKREQ_CR#

CLK_PCIE_WLAN_DN

CLK_PCIE_WLAN_DP

CLKREQ_WLAN#

WS

CLK_PCIE_3G_DN
CLK_PCIE_3G_DP

CLKREQ_3G#

R4814

R4774

OUT
OUT

1

1

R4816
R4815

2

2

1
1

10K_5%_2

10K_5%_2

2
2

IN

1

10K_5%_2

2

1
1

0_5%_2

2

0_5%_2

2

REMOVE CLK_XDP_CLKGEN_DN

REMOVE CLK_XDP_CLKGEN_DP

WS

R4889
R4859

R4858

PCIE_USB3_TX_C_DN

2

1

PCIE_USB3_TX_C_DP

2

1

1

2

2

1

PCIE_WLAN_TX_C_DN

211

PCIE_WLAN_TX_C_DP

2

PCIE_3G_TX_C_DN

1

2

PCIE_3G_TX_C_DP

1

2

PCIE_LAN_TX_C_DN

1

2

PCIE_LAN_TX_C_DP

1

2

TP4711

R4740

TP4703

0_5%_2
0_5%_2

TP4705

CLKOUT_ITPXDP_DN
CLKOUT_ITPXDP_DP

PCIE_CR_TX_C_DN
PCIE_CR_TX_C_DP

TP4712

1

1

10K_5%_2

2

OUT
OUT

IN

OUT
OUT

IN

OUT
OUT

IN

OUT
OUT

IN

TP4704

CLK_PCIE_LAN_R_DN
CLK_PCIE_LAN_R_DP

1

TP4706

1

1

1

U4700

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40
Y39

J2

PCIECLKRQ0#/GPIO73

AB49
AB47

M1

PCIECLKRQ1#/GPIO18

AA48

AA47

V10

PCIECLKRQ2#/GPIO20

Y37
Y36

A8

PCIECLKRQ3#/GPIO25

Y43
Y45

L12

PCIECLKRQ4#/GPIO26

V45
V46

L14

PCIECLKRQ5#/GPIO44

AB42
AB40

E6

PEG_B_CLKRQ#/GPIO56

V40

V42

T13

PCIECLKRQ6#/GPIO45

V38
V37

K12

PCIECLKRQ7#/GPIO46

AK14
AK13

CLKOUT_PCIE0N
CLKOUT_PCIE0P

CLKOUT_PCIE1N
CLKOUT_PCIE1P

CLKOUT_PCIE2N
CLKOUT_PCIE2P

CLKOUT_PCIE3N
CLKOUT_PCIE3P

CLKOUT_PCIE4N
CLKOUT_PCIE4P

CLKOUT_PCIE5N
CLKOUT_PCIE5P

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

PCI-E*

ITL_PANTHERPOINT_FCBGA_989P

5 4

CLOCKS

P3V3_A

2

PCH_3A_SMCLK

29<>

PCH_3A_SMDATA

DRAMRST_CNTRL_PCH
SML0_CLK

39<>

39<>

SML0_DATA

SML1ALERT#
SML1_CLK
SML1_DATA

CL_CLK
CL_DATA
CL_RST#

29<

29<>

29<>

55>

55>

55>

29<>

29<

29<

55<>

55<>

SML1ALERT#

39<>

37<>

EC_SMB3_CLK

29>

SML1_DATA

37<>

EC_SMB3_DATA

29>

39<>

SML0_CLK

29>

SML0_DATA

29>

SML1_CLK

P3V3_A

R4741

IN

1

10K_5%_2

1

2.2K_5%_2

1

2.2K_5%_2

IN

IN

BI

BI

BI

BI

1

2.2K_5%_2

1

2.2K_5%_2

2

SSM3K7002BFU

DS

3

2

SSM3K7002BFU

DS

3

R4752

R4751

R4750

R4749

G

Q4701

Q4700

2

2

2

2

2

D

P3V3_A

1

1

G

SMBUS

SML1ALERT#/PCHHOT#/GPIO74

Link

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

10K_5%_2

E12
H14
C9

A12
C8
G12

C13
E14
M16

M7

T11

P10

R4753

1

BI
BI

IN
OUT
OUT

IN
OUT
OUT

OUT

OUT

OUT

Controller

CC

BB

AA

FLEX CLOCKS

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

M10

AB37
AB38

AV22
AU22

AM12
AM13

BF18
BE18

BJ30
BG30

G24
E24

AK7
AK5

K45

H45

V47
V49

IN

OUT
OUT

OUT
OUT

OUT
OUT

IN

IN

IN
IN

IN
IN

IN

IN

OUT
OUT

Y47

K43
F47

CLK_GPU_27M_SS_R

H47
K49

OUT

CLKREQ_GPU_PEG#
CLK_PEG_GPU_REF_DN

CLK_PEG_GPU_REF_DP
CLK_DMI_PCH_DN

CLK_DMI_PCH_DP
CLK_DP_PCH_CPU_DN

CLK_DP_PCH_CPU_DP
CLKIN_DMI_PCH_DN

CLKIN_DMI_PCH_DP

CLKIN_BUF_DOT96_DN
CLKIN_BUF_DOT96_DP

CLKIN_SATA1_DN
CLKIN_SATA1_DP

CLKIN_PCH14

59> 29<

29<59>

CLKIN_PCI_FB
XTAL25_IN

XTAL25_OUT

R4747

1

90.9_1%_2

1

22_5%_2

DGPU_PRSNT#

29>

2

CLOSE TO PCH

R4700

2

29>

OUT

67<

20<

18pF_50V_2

1

R4854

10K_5%_2

2

+V1.05S

CLK_GPU_27M

C4777

1

R4855

10K_5%_2

2

OUT

1

R4849

X4700

1

25MHz

1

2

CLKIN_BUF_CPYCLK_DN

IN
IN

CLKIN_BUF_CPYCLK_DP

2

2

1

C4776

18pF_50V_2

2

1M_5%_2

OUT

XTAL25_OUT

29>

29>

XTAL25_IN

INVENTEC

TITLE

EVEREST-M
PCH 2

CODE

SIZE

C

CHANGE by

Frank Hu

3

Sun Jan 02 15:32:31 2011

DATE

2

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

29

of

1

REV

97

A01

8 7

6 5

4 3

2

1

DSWVRMEN- Deep S4/S5 Well On-Die Voltage Regulator Enable

high-Enabled(Default)

low-Disabled

U4700

BC24

21>

DMI_RX_DN<0>

21>

DMI_RX_DN<1>

21>

DMI_RX_DN<2>

21>

DMI_RX_DN<3>

D

+V1.05S

1

R4739

49.9_1%_2

2

21>

DMI_RX_DP<0>

21>

DMI_RX_DP<1>

21>

DMI_RX_DP<2>

21>

DMI_RX_DP<3>

21<

DMI_TX_DN<0>

21<

DMI_TX_DN<1>

21<

DMI_TX_DN<2>

21<

DMI_TX_DN<3>

21<

DMI_TX_DP<0>

21<

DMI_TX_DP<1>

21<

DMI_TX_DP<2>

21<

DMI_TX_DP<3>

IN
IN
IN
IN

IN
IN
IN
IN

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

1

750_1%_2

R4888

2

BE20
BG18
BG20

BE24
BC20
BJ18
BJ20

AW24
AW20
BB18
AV18

AY24
AY20
AY18
AU18

BJ24
BG25
BH21

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

DMI

FDI

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

P3V3_S

60>

20>

SYS_RESET#

1

R4734

10K_5%_2

2

EC

SUSACK#_EC

IN

IN

R4887

1

0_5%_2_DY

2

SUSACK#_R

C12

K3

SUSACK#

SYS_RESET#

CLOSE TO IC

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT/GPIO31

E10

BATLOW#/GPIO72

A10

RI#

ITL_PANTHERPOINT_FCBGA_989P

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

System Power Management

SLP_LAN#/GPIO29

SUS_PWR_ACK_R

37>

EC_PWRSW#

60>

XDP_PWRSW#

IN

IN

BAT54_30V_0.2A

IN

LOW_BAT#_3

D4702

3

R4847

1

0_5%_2

2

NC

IN

2

1

OUT

SUSACK#_R

P3V3_A

1

R4738

10K_5%_2

2

R4846

1

0_5%_2

2

D4703

3

BAT54_30V_0.2A

ALLSYS_PWROK
EC_PCH_PWROK

18>

PM_APWROK

PM_DRAM_PWRGD

37>

SUS_PWR_ACK

2

NC

1

RSMRST#

37<

30<

ACPRESENT

30<

IN

IN

IN

OUT

IN

OUT

PM_RI#

2

C4778

0.1UF_10V_2_DY

2

C4769

0.1UF_10V_2_DY

0.1UF_10V_2_DY

1

1

C4768

R4886

0_5%_2

R4848

0_5%_2

2

2

2

IN

IN

1

1

1

RSMRST#_R

SUS_PWR_ACK_R

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

DSWVRMEN

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16
AV12
BC10
AV14
BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

P3V3_A

R4883

1

0_5%_2

37<

19<

37<

21<

21<

21<

21<

55<>

30<

37>

37<

17<11< 18<

37<

20<>

21>
21>
21>
21>
21>
21>
21>
21>

21>
21>
21>
21>
21>
21>
21>
21>

2

37<>

37<

19<12<

C4767

0.1UF_10V_2_DY

30<

37<30>

IN

FDI_TX_DN<0>

IN

FDI_TX_DN<1>

IN

FDI_TX_DN<2>

IN

FDI_TX_DN<3>

IN

FDI_TX_DN<4>

IN

FDI_TX_DN<5>

IN

FDI_TX_DN<6>

IN

FDI_TX_DN<7>

IN

FDI_TX_DP<0>

IN

FDI_TX_DP<1>

IN

FDI_TX_DP<2>

IN

FDI_TX_DP<3>

IN

FDI_TX_DP<4>

IN

FDI_TX_DP<5>

IN

FDI_TX_DP<6>

IN

FDI_TX_DP<7>

OUT

FDI_INT

OUT

FDI_FSYNC0

OUT

FDI_FSYNC1

OUT

FDI_LSYNC0

OUT

FDI_LSYNC1

2

IN

RSMRST#_R

IN

PCIE_WAKE#

BI

PCI_3S_CLKRUN#

OUT

SUS_STAT#

OUT

FM_32KHZ

OUT

SLP_S5#

OUT

SLP_S4#

OUT

SLP_S3#

OUT

SLP_A#

OUT

SLP_SUS#

BI

H_PM_SYNC

OUT

SLP_LAN#

21<

37>

11<

18<

STRAP PIN

+V_RTC

1

330K_5%_2

2

1

330K_5%_2_DY

2

CLOSE TO IC

1

43<

D

R4885

R4884

CC

BB

P3V3_A

R4732

1

8.2K_5%_2

8

7 6

2

ISOLATION

30<

55<>

19< 12<

30<37<

ACPRESENT

SUS_PWR_ACK

30<

PM_RI#

PCIE_WAKE#

30>37<

SLP_LAN#

IN
IN

IN

IN

OUT

PCI_3S_CLKRUN#

5 4

IN

R4776

R4735

R4736

R4775

R4824

R4733

2

10K_5%_2

1

2

10K_5%_2

1

2

10K_5%_2

1

2

10K_5%_2

1

10K_5%_2_DY

2

1

P3V3_S

1

8.2K_5%_2

2

CHANGE by

Frank Hu

3

Sun Jan 02 18:04:44 2011

DATE

2

INVENTEC

TITLE

EVEREST-M
PCH 3

SIZE

C

CODE

CS

SHEET

DOC.NUMBER

CS_1310AXXXXXX-MTR

30

of

1

97

REV

A01

AA