Inventec Dakar 10F 6050A2491301, Dakar FG 6050A2491301, Dakar R 6050A2491301, Dakar RG 6050A2491301 Schematic

REV

DATE CHANGE NO.

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D

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7 6 5 4 3 2 1

7 6 5 4 3

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P/N

VER:

DATEDATEEE

DESIGN

DRAWER

CHECK

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INVENTEC

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DOC.NUMBER REV

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POWER

THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT WRITTEN PERMISSION,INVENTEC CORPORATION,2009 ALL RIGHT RESERVED.

HSF Property:ROHS or Halogen-Free(5L3?)

RESPONSIBLE

SIZE=

FILE NAME:

2

DAKAR10F/FG/R/RG

2011.10.28

21-OCT-2002

XXX

MODEL,PROJECT,FUNCTION

Everest Main Board

C

CS

1310xxxxx-0-0

1 69

X01

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

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AA

4

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TABLE OF CONTENTS

PAGE

1. COVER PAGE

2. INDEX

3. BLOCK DIAGRAM

4. POWER MAP

5. POWER CHARGER

6. POWER +V3LA/+V3A/+5A

7. POWER +V1.5/+V0.75

8. POWER +V1.8S

9. POWER VCCIO

10. POWER VCCSA

11. POWER VCORE

12. POWER VGFX

13. POWER VCORE_DGPU

14. ENABLE PIN

15. LOAD SWITCH-1

16. LOAD SWITCH-2

17. PCB SCREW

18. HALL SENSOR

19. LED

20. K/B & TP/B CONN

21. EC

22. LAN

23. RJ45 & TRANSFORMER

24. AUDIO CODEC

25. SPEAKER/HP JACK/MIC JACK

PAGE

26. CARDREADER

27. MINI1 WLAN/DEBUG CARD

28. MINI2 3G/LTE

29. SATA HDD/ODD CONN

30. USB 2.0 CONN

31. USB 3.0 CONTROLLER

32. USB 3.0 CONN W/ S&C

33. USB 3.0 CONN

34. LCM CONN

35. CRT CONN

36. HDMI CONN

37. HDMI CEC

38. DDR3 DIMM0

39. DDR3 DIMM1

40. FAN & THERMAL SENSOR

41. CPU 1

42. CPU 2

43. CPU 3 DRAM

44. CPU 4 POWER

45. CPU 5 POWER

46. CPU 6 GND

47. PCH 1

48. PCH 2

49. PCH 3

50. PCH 4 AXG

PAGE

51. PCH 5 USB

52. PCH 6 MISC

53. PCH 7 POWER

54. PCH 8 POWER

55. PCH 9 GND

56. VGA 1

57. VGA 2

58. VGA 3

59. VGA 4

60. VGA 5

61. VGA 6

62. VRAM 1

63. VRAM 2

64. VRAM 3

65. VRAM 4

66. USB BOARD

67. PICK BUTTON BOARD

68. POWER BUTTON BOARD

69. EMI

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

692

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

AMD

PEG

W/ POWER EXPRESS

THAMES LE \ THAMES XT \

SEYMOUR XTX

29X 29 MM

IVY BRIDGE \

SANDY BRIDGE

DC 35W

SOCKET-RPGA989

37.5 X 37.5 X 5 mm

FDI

DMI 2.0

DDR3 INTERFACE

(1333/1600 MHZ)

204-PIN SODIMM0

DDR3@1.5/0.75V

(1333/1600 MHZ)

204-PIN SODIMM1

INTERNAL MIC IN

AUDIO CODEC

DDR3@1.5/0.75V

EXT MIC IN HEADPHONE

HDMI

HDA

REA_ALC269Q_VB6

PCH

USB_0: USB CONN

USB_2: USB CONN

USB_8: CARD READER

USB_9: MINICARD WLAN

USB_10:WEBCAM

CRT

LCM

LVDS

USB2.0

PANTHER POINT \

COUGAR POINT

25 X 25 X 2.3 mm

SLEEP & CHARGE

RJ45

PCIE_1:LAN

PCIE

USB3.0

USB_1: USB3.0 CONN

ATHEROS_AR8161/8162

CARD READER

REA_RTS5129

PCIE_2:WLAN

PCIE_3:USB3.0

PCIE

USB2.0

SATA

SPI

USB_8:

SATA0:ESATA SATA1: HDD

SATA6: ODD

ENE-P2809A

THERMAL SENSOR

EC WINDBOND

NPCE885LA0DX

SPI

SPI FLASH 8MB

MXIC_MX25L3206EM2I

BATTERY CHARGER &

DC/DC & IMVP 7

LI-ION BATTERY

6-Cell

KEYBOARD

TOUCH PAD

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

693

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

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23

INVENTEC

REV

B

ADAPTOR

FUSE

65W-75W 8A 6036A0003401 90W 10A 6036A0002901

120W 12A 6036A0006001

BQ24725RGRR

CHARGER

EC_SMB2 CHG_EN BATT_IN ACPRES

BATTERY PACK

+VCORE_+-0.5%

+VCORE1_+-0.5%

TI_TPS61640

POWER BUDGET 53A F 280K OCP 53A PEAK 53A AVG 28.822A 1880UF_1.1M£[ // 2276UF_0.203M£[

VDD_CORE

TPS51217

+VBAT

TPS51123

POWER BUDGET 12.139 A F 300K OCP 10.4A R=120K PEAK 7.283A AVG 2.363A 220UF_25M£[ // 53.92UF_1.529M£[

TPS51123

POWER BUDGET 9.429 A F 375K

OCP 10.7A R=130K PEAK 5.695A AVG1.048 A 220UF_25M£[ //10.6UF_5.924M£[

+V5A_+-5%

+V3LA_+-5%

AO6402L

POWER BUDGET 4.711A PEAK2.592A

100.82UF_0.842M£[

TSP51461

POWER BUDGET 6A F 340K OCP 6A PEAK 6A AVG 1.262A

AO6402L

POWER BUDGET 4.711A PEAK2.592A

100.82UF_0.842M£[

AO6402L

POWER BUDGET 4.711A PEAK2.592A

100.82UF_0.842M£[

INRUSH 0.9A

+V3A

INRUSH 0.9A

+V3S

INRUSH 0.9A

+V5S

+V0.85S_+-0.5%

AM2321P

POWER BUDGET 4.711A PEAK2.592A

GMT_AT1530F11U

POWER BUDGET 4.711A PEAK2.592A

+V3_LAN

INRUSH 0.9A

100.82UF_0.842M£[

+V1.8S

INRUSH 0.9A

100.82UF_0.842M£[

POWER BUDGET 20.070A F 340K OCP 29.1A R=75K PEAK 20.070A AVG 11.531A 560UF_25M£[ // 80UF_0.93M£[

TPS51216

POWER BUDGET 13.7 A F 340K OCP 10.1A R=115K PEAK 17.107A AVG4.835 A 560UF_25M£[ // 1274.8UF_0.214M£[

V1.5_+-5%

+V0.75S

TPS51216

+V1.5S

AON7410

+V1.5_CPU

AON7410

+VTT_+-5%

TPS51216

POWER BUDGET 13.7 A CHANGING POINTS~~ TPS51218 SAME AS 2009 PROJECT OCP 10.1A R=115K TPS51217 SAME AS 2010 PROJECT

+V1.8S IS NEW IC GMT_AT1530F11U CHARGE IS NEW IC BQ24725 VCC CORE IS NEW IC TPS51640 VTT IS NEW IC TPS51219 V0.85 IS NEW IC TPS 51641 V3_V5 IS NEW IC TPS51123 POWER BUDGET ~~IC SPEC (MAX CURRENT ) PEAK CURRENT ~~RATIO OF INTERNAL PREDICTION AVG CURRENT ~~TEST RESULT(MAX CURRENT) INRUSH ~~L/S TURN NO

F 340K

PEAK 17.107A AVG4.835 A

560UF_25M£[ // 1274.8UF_0.214M£[

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

694

A3

21-OCT-2002XXX

R6800

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

R6801

PVBAT

21

21 21

21D3

21D2

21E6 21E8

BATT_IN

EC_SMB1_DATA

EC_SMB1_CLK

21D3

21D2

OUT BI

BI

R6054 R6053

21 21

1M_5%_2

R6050

R6051

EZJZ0V500AA_DY

33_5%_2

21 21

33_5%_2

21

EZJZ0V500AA_DY

R6052

220K_1%_2

P3V3AL

1K_5%_2

21

PVPACK

C6050

1000PF_50V_2

2 1

21

EZJZ0V500AA_DY

FUSE6050

LITTLEFUSE_R451015_15A_65V

21

D6703D6702D6701

21

1 2 3 4 5 6 7 8 9

CN6050

BATT+ BATT+ ID B-I TS SMD SMC GND GND

SYN_200045GR009G18TZR_9P

G1

G

G2

G

G3

G

G4

G

FUSE6000 65W-75W 8A(6036A0003401) 90W 10A(6036A0002901)

120W 12A(6036A0006001)

CN6000

G1

5

G2

6

ACES_50315_0047N_002_4P

1

2

3

4

TP6003 TP6004 TP6005

1 1 1

TP30

C7601

1000PF_50V_2

2 1

TP30

FUSE6000

8A_125V

TP30

R6015

PVADPTR

4.7K_5%_3

21

PVADPTR

L7600

C7602

10PF_50V_2

2 1

NFE31PT222Z1E9L

4

2121

3

21E6 21E8

HW_V_ADC

OUT

0.1UF_16V_2_DY

C6800

NEAR EC

RSC_0603_DY

R6802

33K_5%_2_DY

RSC_0603_DY

2 1

R6014

RSC_0603_DY

8

D

7 6

DS-AM4410NCE_C

C6014

R6018

2 1 2 1

CSC0805_DY

R6019

2 1

RSC_1206_DY

21

RSC_1206_DY

21E6

R6002

20.5K_1%_2

ACPRES

21E8

OUT

21E6

OUT

2200PF_50V_2

P3V3AL

21

HW_I_ADC

C6037

21D2 37C3

21D2 21D3

100PF_50V_2

NEAR EC

BI

EC_SMB2_DATA

EC_SMB2_CLK

R6003

3.32K_1%_3

21

C6029

CSC0603_DY

2 1

56C8

21D3

56D8

37C6

NMOS_4D3S

R6013

10K_5%_3

2 1

21

S

G

1 2 3 45

0.1UF_25V_3

RSC_0603_DY

21

4.3K_5%_2

C6036

100PF_50V_2

NEAR IC

2 1

CSC0402_DY

R6016

SHORT_0402

R6017

C6031C6030

R6006

C6035

1

S

2 3 4 5

G

DS-AM4410NCE_C

2121

21

R6005R6004

4.3K_5%_2

2 1

21

Q6011Q6010

NMOS_4D3S

CSC0402_DY

D

C6034

8 7 6

2 1

3

D6002

DIODES_BAV99

0.1UF_25V_3

TI_BQ24725ARGRR_QFN_20P

P3V3AL

21

R6007

110K_5%_2

PVBAT

R6000

21 43

0.01_1%_6

C6020

21

0.1UF_16V_2

PVADPTR

D6000

21

A2A1

C6022C6021

251

ACN

PHASE HIDRV

BTST REGN

LODRV

15

14

1UF_10V_2

TML

VCC

C6028

2 1

0.1UF_25V_3

21

20 19 18 17 16

2 1

C6026

1UF_25V_3

R6020

4.7_5%_3

2 1

3

4

U6000

6

ACDET

7

IOUT

8

SDA

9

SCL

10

ILIM

ACOK

BATDRV

11

ACDRV

SRN

12

CMSRC

SRP

13

ACP

GND

C

BAT54C_30V_0.2A

3

21

R6012

10_5%_5

21

3

D6001

BAT54C_30V_0.2A

VRCHARGER_HG

VRCHARGER_PH

C6027

0.047UF_16V_2

C

A2A1

VRCHARGER_LG

21

AON7410

21

AON7410

12

PAD6000

POWERPAD_2_0610

2 1

678

NMOS_4D3S

G

321

4 5

678

NMOS_4D3S

G

321

4 5

Q6000

D

S

C6001 C6002 C6003

2 1

4.7UF_25V_5470PF_50V_2

2 1

L6000

21

4.7UF_25V_5

2 1

R6001

ETQP3W4R7WFN

2 1

0.02_1%_6

C6023

0.1UF_16V_2

0.1UF_25V_3

Q6001

D

D6700

S

2 1

21

R7600

RSC_0603_DY

C7600

SBR3U40P1_DY

CSC0402_DY

2 1

C6024

C6004

CSC0805_DY

2 1

21 43

2 1

C6010

0.1UF_25V_3

21

C6025

2 1

Q6012

8

D

7 6

NMOS_4D3S

TPCA8065_H

C6011

2 1

4.7UF_25V_5

C6012

4.7UF_25V_5

S

G

2 1

PVPACK

1 2 3

0.1UF_25V_3

45

C6013

2 1

4.7UF_25V_5

C6033

CSC0805_DY

21

SHORT_0402

R6011

R6009

21

R6008

91K_5%_2

21

C6032

0.1UF_16V_2

2 1

SHORT_0402

R6010

2 1

6.8_5%_2

4.3K_5%_2

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

695

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

IN

R6114

2.2_5%_3

C6121

14C7

EN_5V

EN_3V

2121

VRP3V3A_HG VRP3V3A_PH VRP3V3A_LG

2 1

IN

R6160

140K_1%_2

R6110

2 1 2 1

120K_1%_2

3

1

4

5

TRIP2

EN0

13

VFB2

U6100

SKIPSEL

14

2

VFB1

TONSEL

VREF

VREG5

GND

VIN

16

15618

17

TRIP1

ENC

TI_TPS51123RGER_QFN_24P

25

TML

7 24

VO2 VO1

8

VREG3

9 22

VBST2

10 21

DRVH2

11 20

LL2

12 19

DRVL2

SKIP_3V_5V

VRP5V0A_VIN

RSC_0402_DY

R6113

2 1

C6122

1UF_25V_3

2 1

PGOOD VBST1 DRVH1

DRVL1

LL1

2VREF

5V_PG

C6123

0.22UF_6.3V_2

2 1

23

2.2_5%_3

VRP5V0A_HG VRP5V0A_PH VRP5V0A_LG

EN_3V_5V

VRP5V0A_LDO

C6120

10UF_6.3V_3

2 1

OUT

C6155R6155

0.1UF_16V_2

IN

OUT

6C6 14C8

VRP5V0A_PH

2121

VRP5V0A_LG

IN

AON7410

NMOS_4D3S

G

4 5

AON7702A

G

4 5

678

321

678

321

VBATP

D

S

D

S

14D6 14C7

OUT

Q6151

OUT

6D3

4.7UF_25V_5

2 12 1

R7615

RSC_0603_DY

C7615

CSC0402_DY

2 1

6B3 14D5

C6161C6160

4.7UF_25V_5

2 1

ETQP3W3R3WFN

C6150

150UF_6.3V

+

2 1

VO=(( R6150/R6151)+1)*2

R6150

15.4K_1%_2

2 12 1

R6151

10K_1%_2

VRP5V0A

OUT

14D6 14C8 14D4

14D7

PVBAT

14C7

PAD6110

12

POWERPAD_2_0610

VBATP

2 1

C6111

4.7UF_25V_5

2 1

R7610

2 1

C7610

2 1

14D6

OUT

VRP3V3A

R6100

6.8K_1%_2

2 12 1

R6101

+

C6100

150UF_6.3V

2 1

C6110

4.7UF_25V_5

L6100 L6150

21 21

ETQP3W3R3WFN

RSC_0603_DY

CSC0402_DY

10K_1%_2

VOUT=((R6100/R6101)+1)*2

OUT

2 1

Q6101

6C3 14C8

678

D

S

321

678

D

S

321

Q6100 Q6150

NMOS_4D3S

AON7410

G

4 5

C6115

0.1UF_16V_2

14C6 14C8

VRP3V3A_LDO

OUT

AON7702A

G

4 5

1UF_6.3V_2

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

696

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

PVBAT

21

P5V0A

1 2

2 1

4.7UF_25V_5

RSC_0603_DY

CSC0402_DY

PAD6210

C6212

2 1

POWERPAD_2_0610

4.7UF_25V_5

L6200

PCMC104T_1R0MN

21 43

21

VRP1V5

OUT

1 2

PAD6220

+

C6200

POWERPAD1X1M

2 1

560UF_2.5V

1512

14

13

11

10

20

9

2

3

1

4

5

21

P0V75S

VRP1V5_HG

VRP1V5_PH

VRP1V5_LG

C6220

P0V75M_VREF

2 1

10UF_6.3V_3

2.2_5%_3

C6221

2 1

0.22UF_6.3V_2

C6215R6215

0.1UF_16V_2

678

G

321

678

321

Q6200

D

2 1

C6211

4.7UF_25V_5

212 1

R7620

C7620

C6210

S S

Q6201

D

14C2

OUT

FDMC8884

NMOS_4D3S

2121

4 5

FDMS0310AS

4 5

1V5_PG

C6216

2 1

2.2UF_6.3V_3

U6200

VBSTV5IN

DRVH

14D1 14C2

IN

14D1

IN

DDR3L_SEL

IN

R6200

21

EN_0V75

EN_1V5

10K_1%_2

21

C6217

R6201

2 1

52.3K_1%_2

0.01UF_50V_2

C6218

2 1

0.1UF_16V_2

R6203

2 1

21

R6202

100K_5%_2

75K_1%_2

17

S3

16

S5

6

VREF

8

REFIN

7

GND

19

MODE

18

TRIP

TI_TPS51216RUKR_QFN_20P

SW

DRVL

PGND

PGOOD

VDDQSNS

VLDOIN

VTT

VTTSNS

VTTGND

VTTREF

TML

VOUT=REFIN=1.8*(R6201/(R6200+R6201))

MODE=100KOHM:TRACKING DISCHARGE

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

697

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

P3V3S

P5V0A

R6970

C6972

2 1

10_5%_2

1UF_10V_2

C6971

2 1

10UF_6.3V_3

RICHTEK_RT8068AZQW_WDFN_10P

U6970

11

TML

10 1

PVIN PVIN SVIN NC FB

PGOOD

LX LX LX

EN

9 8 7 6 5

2 3 4

100K_5%_2

R6971

EN_1V8

21

PAN_ELL5PR2R2N

IN

L6970

14B1

21

R6973

2 1

C6974

2 1

20.5K_1%_2

C6970

2 1

CSC0402_DY

C6975

10UF_6.3V_3

2 1

10UF_6.3V_3

VRP1V8S

OUT

14A2

R6972

10K_1%_2

2 1

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

698

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

2 1

4.7UF_25V_5

RSC_0603_DY

CSC0402_DY

PVBAT

212 1

PAD6310

C6312

1 2

POWERPAD_2_0610

4.7UF_25V_5

L6300

CYN_PCMB063T_R68MS_4P

21

43

+

22UF_6.3V_5

C6301

2 1

C6300

2 1

560UF_2.5V

VRP1V05S

OUT

14A8

14B7

R6307

VCCP_PG

21

C6318

2 1

2.2UF_6.3V_3

10K_1%_2

46B4

44A3

IN IN IN

VCCIO_SEL

VSS_SENSE_VCCIO

VCC_SENSE_VCCIO

14A8 14B6

OUT

0_5%_2_DY

TI_TPS51219RTER_QFN_16P

C6319

2 1

0.01UF_50V_2

R6308 R6306

2 1 2 1

C6320

11.3K_1%_2

2 1

0.01UF_50V_2

EN_VCCP

IN

R6303

2 1

100K_5%_2

678

FDMC8884

NMOS_4D3S

G

321

4 5

678

FDMS0310AS

G

321

4 5

Q6300

D

2 1

C6311

4.7UF_25V_5

21

R7630

C7630

2 1

C6310

S S

Q6301

D

0.1UF_16V_2

P5V0A

C6316

2 1

C6315

2.2UF_6.3V_3

21

R6315

21

17

16815

14

7

MODE

GND

EN

PGND

13

BST

SW

DH

DL

V5

U6300

PWPD

5

COMP

6 21

R6302

PGOOD

TRIP

1

VREF

2

REFIN

3

GSNS

4

VSNS

2.2_5%_3

VRP1VO_VCCP_PH

12

VRP1VO_VCCP_HG

11

VRP1V0_VCCP_LG

10

9

52.3K_1%_2

VOUT=1.05V@REFIN=3.3V; VOUT=1.0V@REFIN=GND

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

699

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

C6522

R6520

5.11K_1%_2

21

R6521

21

RSC_0402_DY

2

5

4

VREF

U6500

V5FILT

COMP

PGOOD

16

6

VOUT

SLEW

VID1

VID0

151417

TI_TPS51461RGER_QFN_24P

MODE

7

SWVIN

8

SW

9

SW

10

SW

11

SW

12

BST

EN

VRPVSA_PH

R6524

SHORT_0402

R6525

1133

TML

VIN VIN PGND PGND PGND

GND

V5DRV

18

25 24 23 22 21 20 19

P5V0A

2 1

22UF_6.3V_5

C6511C6510

0.1UF_16V_2

2 1

C6520

3300PF_50V_2

21

2 1

C6521

0.22UF_6.3V_2

SHORT_0402

C6523

2 1

1UF_6.3V_2

C6524

2 1

1UF_6.3V_2

0.01UF_50V_2

2 1

VCCSA_SENSE

EN_SA

VCCSA_VID0

21

VCCSA_VID1

21

C6515

0.1UF_16V_2

45A2

IN

L6500

CYN_PCMB063T_R33MS_4P

21

R7650

RSC_0603_DY

14B5

IN

45A2

IN

45A2

IN

2 1

C7650

CSC0402_DY

2 1

21

43

22UF_6.3V_5

2 1

22UF_6.3V_5 22UF_6.3V_5_DY

2 1

22UF_6.3V_5

2 1

VRPVCCSA

C6503C6502C6501C6500

2 1

OUT

14A6

SA_PG

OUT

21B6 14A6

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6910

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

11B7 11D7 11D4 11A4

11A7 11C8

VREF_CPU

IN

43K_1%_2

R6622R6620

39K_1%_2

2121

PVBAT

PAD6610

POWERPAD_2_0610

1 2

21

PVBAT_CPU

OUT

11B3 11D3

24K_1%_2

R6618

100K_5%_NTC

OUT

2.2UF_10V_3

CTHERM

GND

V5

CDH1

CBST1

CSW1

CDL1

V5DRV

PGND

CDL2

CSW2

CBST2

CDH2

VBAT

CPWM3

VREF_CPU

21

GSKIP#

R6623

2121

C6631

0.1UF_16V_2_DY

2 1

V5_CPU

C6629 C6630 R6602

R6619

15.4K_1%_2

10_5%_3

R6617

VREF_CPU

21

P5V0A

21

4.7UF_10V_3

2 1

49

V5_CPU

48

47

46

45

44

43

42

41

40

39

2.2_5%_3

38

R6616

37

P5V0A

21

IN

0.1UF_16V_22.2_5%_3

0.1UF_16V_2

2 1

11D5

C6622R6601

C6624R6606

10K_5%_3

PVBAT

11A7 11B7 11D4 11D6

IN

12C8

OUT

11C8

R6621

90.9K_1%_2

47PF_50V_2

8.45K_1%_2

21

47PF_50V_2

5.6K_1%_2

IN

R6625

R6718

C6632

C6726

VREF_CPU

21

P3V3A

44B3

GOCP-R

VREF

V3R3

VR_ON

CPGOOD

VCLK

ALERT#

VDIO

VR_HOT#

SLEW

GPGOOD

GF_IMAX

P3V3A

44B3

IN

VSSSENSE

12

CGFB

GGFB

25

R6719

R6723

R6728

IN

VCCSENSE

11

CVFB

GVFB

26

21

11C3

IN

9

CCSN3

GCSN1

282729

8

CCSP3

GCSP1

CPU_CSP2

7

CCSP2

GCSP2

30

10

CCOMP

U6600

TI_TPS51650RSLR_QFN_48P

GCOMP

21

0_5%_2_DY

21

0_5%_2_DY

P3V3A

0_5%_2

2 1

R6724

R6720

GPU_CSP1

GPU_CSN1

IN

11C3

IN

CPU_CSN2

6

CCSN2

GCSN2

31

11D3

IN

CPU_CSN1

5

CCSN1

GTHERM

32

11D3

IN

CPU_CSP1

3

4

CCSP1

GSKIP#

33

34

GPWM1

RSC_0402_DY

R6730

100K_5%_2

2 1

CF-IMAX

GPWM1

OUT

12B8

11C4

2

35

2 1

1

COCP-R

GPWM2

36

R6731

21

13

14

15

16

17

18

19

20

21

22

23

24

21

2+02+1 R6626 R6627 R6711 R6712 R6714 R6716 R6719

DNP

3.3K 56K DNP

DNP

200K

DNP

30K

DNP DNP

0DNP 0 0

11B7 11D6

11D4

11A4 11A7 11C8

VREF_CPU

IN

R6626

4.7K_1%_2

R6723 DNP 0

R6627

75K_1%_2

2 1 2 1

P3V3A

VREF_CPU

R6711

200K_1%_2

2 12 1

R6712

21D3

30K_1%_2

IN

EN_PVCORE

R6628

0_5%_2_DY

2 12 1

R6629

20K_1%_2

IN

45C3

R6630

0_5%_2

R6631

RSC_0402_DY

2 1 2 1

11C8 11D4 11B7 11A4 11A7

C6633

2 1

2.2UF_6.3V_3

IN IN

VR_ON

11D6

OUT

2.2UF_6.3V_3

GFX_VSS_SENSE

GFX_VCC_SENSE

0_5%_2_DY

OUT

11D7

VREF_CPU

C6634

49B7

44C2

11C7

44C2

11A3

IN

OUT

IN OUT BI OUT

OUT

R6713

R6715

VR_ON

PVCORE_PG

VR_SVID_ALERT#

VR_SVID_DATA

CPU_PROCHOT#

PVAXG_PG

0_5%_2

VREF_CPU

IN

11A4 11B7

0_5%_2

11A7

11A4 40B4

2 1

11A3

44C2

21C3 41D6

11A4

11D7 11D6 11C8 11A4 11A7 11D4

R6716R6714

0_5%_2_DY

2 1

11D4 11C8 11D7 11D6

15.4K_1%_2

12C5

100K_5%_NTC

R6729

12D5

2 1

C6727

0.1UF_16V_2_DY

2 1

40B4

11C7 49B7

OUT

R6638

68UF_25V

IN

2121

PVCORE_PG

PVAXG_PG

C6000

+

2 1

11A4 11A7 11B7 11C8 11D6 11D7

C6610

2 1

C6611

2 1

4.7UF_25V_5

PVBAT_CPU

678

FDMS7692

FDMS0306AS

NMOS_4D3S

G

321

4 5

678

G

321

4 5

D

S

D

PVBAT_CPU

678

11D7

R6634

2 1

FDMS7692

FDMS0306AS

2K_5%_2

NMOS_4D3S

G

321

4 5

678

G

321

4 5

R6732

2 1

44C2

D

S

Q6621Q6611 Q6620Q6610

DS

S

2K_5%_2

11C7 11B7

11C7 44C2

C6612

2 1

4.7UF_25V_5

IN

BIOUT

C6613

2 1

4.7UF_25V_5

11D5

11B3 11D1

IN

R7661

RSC_0603_DY

2 12 1

C7661

CSC0402_DY

11D5

11D1

IN

R7662

RSC_0603_DY

2 12 1

C7662

CSC0402_DY

VR_SVID_CLK

VR_SVID_DATA

C6615

C6614

2 1

4.7UF_25V_5

CPU_CSN1

OUT

CPU_CSP1

OUT

CPU_CSN2VR_SVID_CLK

OUT

CPU_CSP2

OUT

11D3

R6607

17.8K_1%_2 100K_5%_NTC

P1V05SP3V3A

R6632

2 1

54.9_1%_2

C6617

C6616

2 1

4.7UF_25V_5

21

100K_5%_NTC17.8K_1%_2

PAN_ETQP4LR36ZFC_4P

21

PAN_ETQP4LR36ZFC_4P

R6633

130_1%_2

2 1

21-OCT-2002XXX

2 1

4.7UF_25V_5

C6623

21

0.033UF_16V_2

R6605

21

162K_1%_2

R6604R6603

28.7K_1%_2

43 21

L6610

560UF_2.5V

C6625

21

0.033UF_16V_2

R6610

21

162K_1%_2

28.7K_1%_2

43 21

L6620

C6635

2 1

0.1UF_16V_2

A3

2121

+

2 1

470UF_2V_DY

R6609R6608

2121

MODEL,PROJECT,FUNCTION

Block Diagram

CS

2

1

C6600C6604

+

3

1

470UF_2V

+

3

C6602

PVCORE

C6601

1

470UF_2V

+

3

2

PVCORE

1

C6603

470UF_2V

+

3

2

X011310xxxxx-0-0

6911

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

OUT

GPU_CSN1

GPU_CSP1

R6702

17.8K_1%_2

3300PF_50V_2

0.022UF_16V_2

162K_1%_2

21

PAN_ETQP4LR36WFC_4P

R6705

L6710

C6723

C6722

21

R6704R6703

2121

PVAXG

PVBAT

28.7K_1%_2100K_5%_NTC

12

PAD6710

2 12 1

C6710

POWERPAD_2_0610

C6712

C6711

2 1

4.7UF_25V_5

2 1

PVBAT_AXG

C6713

2 1

4.7UF_25V_5

OUT

12C5

43 21

1

C6700

470UF_2V

1

+

C6701

C6702

+

470UF_2V_DY 560UF_2.5V

3

2

3

2

2 1

11A4 11B5

11A6

PVBAT_AXG

678

C6720R6701

2121

2.2_5%_3

GSKIP#

IN

GPWM1

IN

3 4 5

TI_TPS51601DRBR_SON_8P

U6710

PWM GND DRVL

0.1UF_16V_2

PAD

DRVHBST

SWSKIP#

VDD

9 81

72 6

P5V0A

C6721

2 1

FDMS7692

FDMS0306AS

1UF_6.3V_2

NMOS_4D3S

G

4 5

G

4 5

321

678

321

D

S

Q6711Q6710

D

S

IN

R7671

RSC_0603_DY

2 12 1

C7671

CSC0402_DY

12B1

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6912

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

16A1 13B2

16C4

16A8

PVBAT

12

R6755

240K_5%_2

U6750

TON

9

VDDP

2

VDD

4

PGOOD

CS

13K_1%_2

EN_DEM D1

GND

21

UGATE

PHASE

LGATE

BOOT

VOUT

G0

FB

G1

D0

R6752

2.2_5%_3

13

VRPVCORE_DGPU_HG

12

VRPVCORE_DGPU_PH

11

VRPVCORE_DGPU_LG

8

PWRCNTL_0

7

3

PWRCNTL_1

14

R6753

6

R6754

1

10K_1%_2

16.5K_1%_2

21

C6753

0.1UF_16V_2

IN

56C5

IN

21

56F7 56D5

56F7

52C6 13B2

13D1

OUT

IN

P5V0A

DGPU_PWRGD

EN_DGPU

R6756

10_5%_2

21

C6757

C6754

2 1

1UF_6.3V_2

16

1UF_6.3V_2

10

R6758

15 5

2 1

17

PAD6760

2 1

678

FDMS7692

NMOS_4D3S

G

321

4 5

678

FDMS0306AS

G

321

4 5

POWERPAD_2_0610

D

S

Q6751Q6750

D

S

C6761

C6760

2 1

4.7UF_25V_5

PAN_ETQP4LR36WFC_4P

R7675

2 12 1

RSC_0603_DY

C7675

CSC0402_DY

C6762

2 1

4.7UF_25V_5

L6750

4.7UF_25V_5

21 43

R6751 R6750

2 1 2 1

2.2K_1%_210K_1%_2

2

C6750

VRPVCORE_DGPU

1

+

3

470UF_2V

1

+

2

C6752

470UF_2V

3

OUT

13C2

13C3

21D6 45D3 13A2 14A6 14B8 14D2 49A1

IN

DGPU_PWR_EN

SLP_S3#_3R

IN

VRPVCORE_DGPU

R7016

10K_5%_2

R7020

0_5%_2_DY

PAD6750

1 2

POWERPAD_2_0610

PAD6751

1 2

POWERPAD_2_0610

560UF_2.5V

P3V3S_DGPU

EN_DGPU

21

C7010

2 1

PVCORE_DGPU

21

C6751

0.1UF_16V_2

+

2 1

13C8

OUTIN

REA_RT8208BGQW_WQFN_16P

R7017

10K_5%_2

R7019

R7030

POWERPAD_2_0610

2 1

R7018

21

PAD6950

P1V5S_DGPU

1

2

EN_VPCIEDGPU_PWR_EN

C7011

2 1

1 2

OUT

1UF_6.3V_2

PVPCIE

21

OUT

13A6

IN

DGPU_PWRGD

100K_5%_2_DY

13C8

VGA TYPE¡G

G1G0

0 0 1 1

1

0 1

0

SEYMOUR XTX

VOUT

1.15

1.05 1

0.9

THAMES XT

VOUT

N/A

0.9

THAMES LE

VOUT N/A

N/AN/A

11

0.9

RESISTOR VALUE

R6750(R1)

R6751(R2)

R6754(R3)

R6753(R4)

2.2 K

16.5 K

10 K

P.S. R6750(R1)R6751(R2)R6753(R3)R6754(R4)

10 K

P1V5S_DGPU

52C6

P5V0A

16A1 16C4

13D2 16A8

49A1 21D6 14B8 13D2 14A6 14D2 45D3

IN

13A3

SLP_S3#_3R

IN

1K_5%_2

0_5%_2_DY

VRPVPCIE

13B1

C6955

2 1

22UF_6.3V_5

U6950

5

VIN

6

EN_VPCIE

IN

7 8 9

VCNTL

POK

EN

VIN

VOUT

FB

GND

4

C6952

3 2

1

2 1

R6950

2 12 1

68PF_50V_2

2.7K_1%_2

C6950

2 1

ANPEC_APL5930KAI_TRG_SOP_8P

C6954

2 1

1UF_10V_2

R6951

10K_1%_2

VRPVPCIE

C6951

2 1

22UF_6.3V_5

1UF_10V_2

OUT

13A2

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6913

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

DDR_P1V5

3V & 5V

EN_5V

3

Q7000

21C3 15D4

IN

EC_PW_ON#

SSM3K7002BFU

1

DS

G

C7000

2 1

2

0.047UF_16V_2

14D4 14D6

21F6 14C8 15D6

21F6 14D8 15D6

6B6 14C6

6C1

6C3 6C6

IN

P5VAUXON

VRP3V3A_LDO

VBATP

P5VAUXON

3

C

RSC_0402_DY

10K_5%_2

A2A1

2 1

R7000

R7001

R7002

0_5%_3

R7003

0_5%_2

D7000

BAT54C_30V_0.2A_DY

21

SKIP_3V_5VVRP5V0A

VRP5V0A_VIN

EN_3V_5V

EN_3V

OUT

6D6

6B5

6B4

14C8

6C1 14D4

6C8

6B4

6B6

IN

VRP5V0A

VRP3V3A

VRP5V0A_LDO

VRP3V3A_LDO

PAD6150

1 2

POWERPAD_2_0610

PAD6100

1 2

POWERPAD_2_0610

1 2

PAD6120

POWERPAD1X1M

1 2

PAD6121

POWERPAD1X1M

P5V0A

21

P3V3AL

21

P5V0AL

21

P3V3_LDO

21

C6151

++

330UF_6.3V_DY

2 12 1

C6101

330UF_6.3V_DY

6B3

IN

2 13

C7001

0.1UF_16V_2

2 1

DIODES_BAV99

VRP5V0A

C7002

D7002

3

21

D7001

DIODES_BAV99

21

C7004

1UF_25V_3

2 1

C7003

0.1UF_16V_2

2 1

P15V0A

6C1 14C8 14D6

IN

VRP5V0A_LG

21D6 14A6

13D2 14B8 49A1

45D3

21D3 49B3

R7010

R7012

0_5%_2

21

IN

47K_5%_2

IN

C7005

0.1UF_16V_2

2 1

C7006

CSC0402_DY

2 1

EN_0V75SLP_S3#_3R

EN_1V5SLP_S5#_3R

OUT

7C7 13A2

7C7

P3V3S

21

R7013

7B3 14C2

1V5_PG

IN

RSC_0402_DY

1V5_PG

OUT

P1V5

7C1

PAD6200

1 2

POWERPAD_2_0610

IN

VRP1V5

PAD6201

1 2

POWERPAD_2_0610

21

VCCIO

21D6 14A6 13A2 13D2 14D2 45D3

49A1

IN

SLP_S3#_3R

R7021

47K_5%_2

EN_VCCP

21

C7020

2 1

0.1UF_16V_2

OUT

9D6

VCCSA

9C6 14A8

VCCP_PG

R7040

0_5%_2

21

EN_SA

C7040

CSC0402_DY

2 1

10B4

OUTIN

DGPU

P3V3S

P1V8S

P3V3S

10K_5%_2

R7050

21

C7050

0.01UF_50V_2

2 1

EN_1V8

OUT

8B4

P3V3S

R7041

10K_5%_2

2 1

13

OUTIN

PVSA

21

P1V8S

8B2

VRP1V8S

IN

PAD6900

1 2

POWERPAD_2_0610

21

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6914

A3

21-OCT-2002XXX

14B6

9B1

21

SA_PG SA_PG

D7040

SLP_S3#_3R

IN

BAT54_30V_0.2A

2

NC

21D6

10A5 21B6

13A2

OUT

14A6

14B8 13D2 49A1 14D2

45D3

R7022

10K_5%_2

9C6 14A8

VCCP_PG

IN

VCCP_PG

P1V05S

PAD6300

1 2

POWERPAD_2_0610

VRP1V05S

IN

PAD6301

1 2

POWERPAD_2_0610

21

10C1

VRPVCCSA

IN

PAD6500

1 2

POWERPAD_2_0610

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

P3V3AL

PVBAT P3V3_LDO

R7491

510K_1%_2

2

D7490

56D6

40A8 40B1

THRM_SHUTDWN#

OUT

NC

BAT54_30V_0.2A

R7492

2 1

13

5 3

120K_1%_2

2 1

P15V0A

R7107

2 1

470K_5%_2

3

Q7104

49B1

16A7 15A4 15B4

SLP_S3_3R

IN

1

SSM3K7002BFU

DS

G

2

C7101

2 1

4

U7490

VDD

SENSE RESET#

GND

1

2200PF_50V_2

P5VAUXON

GND

TI_TPS3801_01_SC70_5P

2

OUT

21F6 14C8 14D8

P3V3AL

R7108

0_5%_2

P5V0A

R7110

0_5%_2

1 2 5

21

Q7105

D

NMOS_4D1S

AO6402AL

Q7107

D

NMOS_4D1S

AO6402AL

4

S

36

G

C7102

2 1

POWERPAD_2_0610

4

S

36

G

C7104

POWERPAD_2_0610

2 1

680PF_50V_2

PAD7102

2 1

CSC0402_DY

PAD7101

12

21C3

14D8

EC_PW_ON#

IN

P3V3S

12

C7103

2 1

22UF_6.3V_5

15B8 15A4 15B4 49B1

16A7

IN

SLP_S3_3R

SSM3K7002BFU

P5V0S

C7105

2 1

15B8

22UF_6.3V_5

15A4 15B4 49B1

16A7

IN

SLP_S3_3R

SSM3K7002BFU

R7104

100K_5%_2_DY

2 12 1

R7100

10K_5%_2

R7109R7111

Q7106

1

G

Q7108

1

G

1

SSM3K7002BFU

200_5%_2

2 12 1 3

DS

3 2

200_5%_2

DS

Q7101

3

DS

G

2

P15V0A

2 1

R7105

100K_5%_2

C7100

2200PF_50V_2

P3V3AL

1 2 5

Q7102

D

NMOS_4D1S

AO6402AL

P3V3A

4

S

36

G

PAD7100

1 2

POWERPAD_2_0610

SSM3K7002BFU

1

Q7103

21

R7106

200_5%_2

2 1

3

DS

G

2

P1V5S

21

R7113

C7107

2 1

15B4 49B1

16A7

22UF_6.3V_5

15B8

IN

SLP_S3_3R

SSM3K7002BFU

1

Q7110

3 2 2 1

DS

G

2

200_5%_2

Q7111

1

G

P0V75S

R7114

3

2 1

DS

200_5%_2

SSM3K7002BFU

2

21-OCT-2002XXX

MODEL,PROJECT,FUNCTION

CS

A3

Block Diagram

X011310xxxxx-0-0

6915

R7112

P1V5

8 7 6

21

Q7109

D

NMOS_4D3S

AM7330N

Q7112

D

NMOS_4D3S

AM7330N_DY

POWERPAD_2_0610

1

S

2 3 45

G

1

S

2 3 45

G

PAD7103

1 2

0_5%_2

C7106

2 1

CSC0402_DY

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

P1V5

Q7113

8

D

7 6

NMOS_4D3S

AM7330N

Q7114

8

D

7 6

16B7 16A5

DGPU_PWR_EN_15R

IN

NMOS_4D3S

AM7330N

R7116

220K_5%_2

21

C7108

1

S

2 3 45

G

1

S

2 3 45

G

P1V5S_DGPU

R7115

200_5%_2

2 1

POWER EXPRESS

DGPU_PWR_EN#

DGPU_PWRGD

DURING RESET

HIGH

AFTER RESET

HIGH

0 : DGPU POWER SWITCH TURNED ON 1 : POWER SWITCH TURNED OFF

0 : DGPU POWER IS NOT STABLE 1 : DGPU POWER IS STABLE

680PF_50V_2

2 1

32

Q7115

DS

G

IN

DGPU_PWR_EN_3R

16A6 16B7

1

DGPU_HOLD_RST#

LOW

SSM3K7002BFU

2

P1V8S

R7038

0_5%_6_DY

21

Q7118

1

D

2 5

NMOS_4D1S

4

S

36

G

P1V8S_DGPU

16A8 16A1 13D2 13B2

IN

DGPU_PWR_EN

R7039

0_5%_2

0 : KEEP DGPU IN RESET 1 : RESET IS RELEASED

P3V3S

R7031

Q7002

SSM3K7002BFU

1

21

G

3

2 1

DS

C7023

10K_5%_2

2 1

CSC0402_DY

DIODES_DMP2305U_SOT23_3P

R7042

Q7003

S

0_5%_2_DY

SD

G

P3V3S_DGPUP3V3S

21

D

C7024

2 1

CSC0402_DY

AO6402AL

2

CSC0402_DY

16D7

16A5

IN

DGPU_PWR_EN_15R

R7120

220K_5%_2

21

C7110

200_5%_2

2 1

R7119

C7021

2 1

680PF_50V_2

G

3

Q7119

DS

SSM3K7002BFU

P3V3S

2 1

16C7 16A6

IN

DGPU_PWR_EN_3R

1

13B2

13D2 16C4 16A1

IN

DGPU_PWR_EN

P3V3_LDO

16B7 16C7

R7033

DGPU_PWR_EN_3R

10K_5%_2

3

2 1

DS

G

IN

2

R7035

0_5%_2

Q7018

SSM3K7002BFU

21

C7022

2 1

1

CSC0402_DY

IN

SLP_S3_3R

SSM3K7002BFU

R7047

0_5%_2_DY

Q7019

R7121

10K_5%_2

2 1

G

SSM3K7002BFU

3

Q7120

DS

2

P15V0A

IN

DGPU_PWR_EN#

51B6

51C7

R7034

1M_5%_2

DGPU_PWR_EN_15R

3

2 12

1

21

DS

G

OUT

16D7

16B7

1

DGPU_PWR_EN

OUT

13B2

16C4 16A8 13D2

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6916

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 0~49(PCB SCREW)

1

FIX_MASK

1

FIX_MASK

1

FIX_MASK

FIX1

FIX2

FIX3

1

FIX_MASK

1

FIX_MASK

1

FIX_MASK

11

FIX_MASK

FIX5

FIX6

FIX7

FIX8FIX4

BOUNDARY SCAN TEST POINT

PVCORE

1

TP30

1

TP30

PVADPTR

TP1

TP2

PVBAT

PVCORE_DGPU

TP9TP8 TP10

11 1

TP30 TP30TP30

TP30

TP5

TP4TP3

1

11

TP30

PVAXG

TP6

1

TP30

TP7

1

TP30

PCB

S1

1

SCREW300_1000_1P

S2

1

SCREW300_1000_1P

S3

1

SCREW300_1000_1P

S5

1

SCREW300_1000_1P

S6

1

S7

1

S8

1

SCREW300_1000_1P

CPU WLANGPU

S10

1

S11

1

S12

1

S13

1

SCREW330_600_1P

1

S14

SCREW330_600_1P

S15

SCREW330_600_1P

STD16

1

STDPAD_1.15_6-TOP

4.2MM

3G

1

STD17

STDPAD_1.15_6-TOP

4.2MM

1

STD18

STDPAD_1.15_6-TOP

4.2MM

FAN

STD21

S18

1

SCREW220_700_1P

S20

1

SCREW540_1000_NP_1P

1

STDPAD_1.15_6.0_TOP

2MM

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6917

A3

21-OCT-2002XXX

REFERENCE 50-99(HALL SENSOR)

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

P3V3AL

R50

U50

3

MAG_MH248BESO_SOT23_3P

VDD

GND

OUT

100K_5%_2

1

2 12 1

2

C50

1000PF_50V_2

LID_SW#_3

SFI_SFI0402ML120C_LF_SMD_2P_DY

2 1

OUT

D50

21D3

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6918

A3

21-OCT-2002XXX

REFERENCE 100~199(LED)

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

SUSPEND LED

TP100

21B6

IN

PWR_OLED#

1

TP30

D154

HT_191UY

21 21

R160

150_5%_2

POWER ON LED

21D6

IN

PWR_WLED#

1

TP30

TP101

D159

21

19_217_T1D_CP1Q2QY_3T

R150

220_5%_2

21

P3V3A

P5V0S

P3V3S

WIFI/WIMAX/3G/LTE LED

21D6

D156

TP104

IN

WL_OLED#

1

TP30

HT_191UY

21 21

R155

150_5%_2

DC IN / BATTERY CHARGE LED

D152 BRIGHT:BOTH AC-ADAPTER IS PLUGGED IN AND BATTERY IS FULL CHARGED D155 BRIGHT:WHILE CHARGING BATTERY FROM AC-ADAPTER

BLINK:LOW BATTERY

P5V0A

21B6

IN

DCIN_WLED#

BAT_OLED#

1

TP30

TP102

TP103

D152

21

19_217_T1D_CP1Q2QY_3T

D155

21 21

HT_191UY

R152

220_5%_2

R154

150_5%_2

21

P3V3AL

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6919

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 200~249(POWER CONN) REFERENCE 250~299(KB/TP CONN)

R253

21

0_5%_2_DY

P3V3S

21B3

21B6 21D6 21D6

IN IN IN

21B3 20D3

CAPS_LED#_3 SCROLL_LED#_3 NUM_LED#_3

IN

R250 R251 R252

SCAN_OUT<17..0>

OUT

SCAN_IN<7..0>

21

200_5%_2

21

200_5%_2_DY

21

200_5%_2

SCAN_OUT<16>

16

SCAN_OUT<17>

17

SCAN_OUT<4>

4

SCAN_OUT<2>

2

SCAN_OUT<13>

13

SCAN_OUT<15>

15

SCAN_OUT<1>

1

SCAN_OUT<0>

0

SCAN_OUT<11>

11

SCAN_OUT<9>

9

SCAN_OUT<5>

5

SCAN_OUT<6>

6

SCAN_OUT<10>

10

SCAN_OUT<14>

14

SCAN_OUT<8>

8

SCAN_OUT<12>

12

SCAN_OUT<7>

7

SCAN_OUT<3>

3 7 2 3 4 0 5 6 1

SCAN_IN<7> SCAN_IN<2> SCAN_IN<3> SCAN_IN<4> SCAN_IN<0> SCAN_IN<5> SCAN_IN<6> SCAN_IN<1>

CN250

34

33

32

31

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

G

30

G 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

PTWO_196094_34021_3_34P

G2 G1

21B3 20C6

IN

SCAN_IN<7..0>

SCAN_IN<0>

0

SCAN_IN<1>

1

SCAN_IN<2>

2

SCAN_IN<3>

3

SCAN_IN<4>

4

SCAN_IN<5>

5

SCAN_IN<6>

6

SCAN_IN<7>

7

D250

D251

D252

D253

D254

D255

D256

D257

SFI_SFI0402ML120C_LF_SMD_2P_DY

21

SFI_SFI0402ML120C_LF_SMD_2P_DY

21

SFI_SFI0402ML120C_LF_SMD_2P_DY

21

SFI_SFI0402ML120C_LF_SMD_2P_DY

21

SFI_SFI0402ML120C_LF_SMD_2P_DY

21

SFI_SFI0402ML120C_LF_SMD_2P_DY

21

SFI_SFI0402ML120C_LF_SMD_2P_DY

21

SFI_SFI0402ML120C_LF_SMD_2P_DY

21

SFI_SFI0402ML120C_LF_SMD_2P_DY SFI_SFI0402ML120C_LF_SMD_2P_DYSFI_SFI0402ML120C_LF_SMD_2P_DY

21

KEYBOARD CONN

D260D259D258

P5V0S P3V3S

21D3

BI

21D3 38C8 39C8 48A8 38C8 39C8 48A8

BI BI BI

PHP_PESD5V2S2UT_SOT23_3P_DY

IM_CLK_5 IM_DAT_5 PCH_3S_SMCLK PCH_3S_SMDATA

D280

2

1

ACES_50503_0084N_001_8P

3

CN280

1

2

3

4

5

6

7

8

G1

21D3

OUT

G2

PWR_SWIN#_3

21

D200

SFI_SFI0402ML120C_LF_SMD_2P_DY

CN200

1

2

ACES_50224_0020N_001_2P

3

G

4

G

TOUCHPAD CONN

POWER CONN

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6920

A3

21-OCT-2002XXX

DOC.NUMBER

of

INVENTEC

TITLE

DATE

CODE

E

D

C

B

A

7 6 5 4 3 2 1

7 6 5 4 3

E

D

C

B

A

FF

8

CHANGE by

8

REV

2 1

SHEET

SIZE

REFERENCE 300~389(KBC)

0.1UF_16V_2

P3V3S

C312

2 1

CLOSE PIN4

C306

2 1

10UF_6.3V_5_DY

0.1UF_16V_2

P3V3AL

2

D300

14C8

14D8 15D6

P5VAUXON

NC

R320

100K_5%_2

2 1

13

VCC_POR#

21B6

OUTIN

R318

2.2_5%_3

FOR ESD PROTECT

P3V3AL_RP3V3AL

21

C304

C303

C302

C301

2 1

C300

2 1

4.7UF_6.3V_3

2 1

0.1UF_16V_2

2 1

0.1UF_16V_2

2 1

0.1UF_16V_2

2 1

0.1UF_16V_2

C313

BAT54_30V_0.2A

R301

0_5%_1

21

14D2

P3V3AL

2 1

100K_5%_2

47A6 47A6

47A6 21C8

47A6

0.1UF_16V_2

0.1UF_16V_2_DY

IN

LCM_BKLTEN

2 1

R303

10K_5%_2

R346

21C8 21C7

21C7

21B6

40C8

OUTIN

R345R344

10K_5%_2_DY

2 1

21

13D2 45D3

14A6 14B8

49A6 49A5

OUT OUT

IN

OUT

52C2 41D5

21E8

36B2

EC_SPI_CS0# EC_SPI_CLK

40C8 14A6

49B7

21E6

13A2

32B1

32A6

5B7 5D5 21E8 5D3

34B5

5B8

37B1

20C7

49B8 49A8 19B4 33C6 24A2 22D7

31D4

49A6 19A7 19A7

40C6 20C7 19D7

22B5

21F4

BI

21B6 10A5

49B3

IN IN IN

OUT

IN IN

OUT

IN

OUT

OUT OUT

IN

IN OUT OUT OUT OUT OUT

31A5 32A8 32A8 19C7

R342

R340

R341

IN IN

IN OUT OUT OUT

OUT OUT OUT

IN OUT

IN

H_PECI

10K_5%_2

HW_I_ADC HW_V_ADC BATT_IN

EC_BKLTEN LCM_BKLTEN ACPRES

EC_CTL3

SLP_S3#_3R HDMI_HPD_EC

SCROLL_LED#_3

NUM_LED#_3 ACPRESENT EC_PWRSW# LOW_BAT#_3 WL_OLED# USB_OC#_1 EC_MUTE# WOL_AUX_ON#

OUT OUT OUT OUT

33_5%_2

FAN_TACH1 SA_PG

USB_OC#_0 PCH_PWROK BAT_OLED# DCIN_WLED#

FAN1_PWM CAPS_LED#_3 PWR_OLED#

EC_32KHZ LAN_RST#

VCC_POR#

43_5%_2

P3V3S P3V3AL_EC

R332 R323

USB30_PWR_EN EC_ILIM_SEL EC_CTL2 PWR_WLED#

21

21 21

R339

2 1

P3V3AL_EC_VREF

TP311

TP314

TP315

TP316

TP307

TP317

TP318

EC_SPI_CLK_R

EC_SPI_SO_REC_SPI_SO EC_SPI_SI_REC_SPI_SI

TP319

TP320

TP321

TP322 TP323

EC_PECI

21

4.7K_5%_2

21

TP30

1

TP30

2 1

TP30

TP30 TP30

104

97 98 99

1

100 108

96 95 94

101

1

105 106 107

1

79

114

1

6

109

80 26

123

73 74

1

75

117 112 110

93

1

91 90 92

86 87

44

C310

1UF_6.3V_2

31

1

63 64

32

1

118

62 65 22

1

81 66 16

1

111

1

113

77 30

85

13 12

P3V3AL_R

P3V3AL_EC

P3V3S

102

AVCC

12

4

VDD

LRESET#/GPIOF7

LCLK/GPIOF5

LFRAME#/GPIOF6

LAD3/GPIOF4 LAD2/GPIOF3 LAD1/GPIOF2 LAD0/GPIOF1

SERIRQ/GPIOF0

GPIO11/CLKRUN#

GPIO65/SMI# ECSCI#/GPIO54 GPIO10/LPCPD#

GPIO85/GA20 KBRST#/GPIO86

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO26/PSCLK2 GPIO35/PSDAT1 GPIO37/PSCLK1

GPIO17/SCL1/N2TCKGPIO67/N2TMS GPIO22/SDA1/N2TMS

GPIO73/SCL2

GPIO74/SDA2

GPIO23/SCL3A GPIO31/SDA3A GPIO47/SCL4A

GPIO53/SDA4A GPIO42/SCL3B/TCK GPIO43/SDA3B/TMS GPIO44/SCL4B/TDI

GPIO75/SPI_SCK

GPIO77/SPI_DI GPIO76/SPI_DO

AGND

WINB_NPCE885LA0DX_LQFP_128P

103

115

887646

U301

VREF

GPIO90/AD0 GPIO91/AD1 GPIO92/AD2 GPIO93/AD3 GPIO05/AD4 GPIO04/AD5 GPIO03/AD6 GPIO07/AD7

GPIO94/DA0 GPIO95/DA1 GPIO96/DA2 GPIO97/DA3

GPIO02 GPIO16 GPIO24 GPIO27/PSDAT2 GPIO30/F_WP# GPIO34/CIRRXL GPIO36 GPIO41/F_WP# GPIO51/N2TCK

GPIO70 GPIO71 GPIO72

GPIO20/TA2/IOX_DIN_DIO GP(I)O84/IOX_SCLK/XORTR# GPO82/IOX_LDSH/TEST# GPIO06/IOX_DOUT

GPIO81/F_WP# F_CS0# F_SCK

F_SDI_F_SDIO1 F_SDIO_F_SDIO0

VCORF

19

VCC5

VCC4

VCC3

VCC2

VCC1

GPIO46/SDA4B/CIRRXM/TRST#

GND6

GND5

GND4

GND3

GND2

GND1

5

897845

18

116

PAD319

2 1

POWERPAD1X1M

AGND_KBC

U301

GPIO56/TA1 GPIO14/TB1 GPIO01/TB2

GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM GPIO32/D_PWM GPIO45/E_PWM GPIO66/G_PWM GPIO33/H_PWM GPIO40/F_PWM

GP(I)O83/SOUT_CR/TRIST# GPIO87/CIRRXM/SIN_CR

GPIO00/EXTCLK

GPIO55/CLKOUT/IOX_DIN_DIO

VCC_POR#

PECI VTT

KBSOUT0/GPOB0/JENK#

KBSOUT1/GPIOB1/TCK KBSOUT2/GPIOB2/TMS KBSOUT3/GPIOB3/TDI

KBSOUT4/GPOB4/JEN0#

KBSOUT5/GPIOB5/TDO

KBSOUT6/GPIOB6/RDY#

KBSOUT7/GPIOB7 KBSOUT8/GPIOC0

KBSOUT9/GPOC1/SDP_VIS# KBSOUT10_P80_CLK/GPIOC2 KBSOUT11_P80_DAT/GPIOC3

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

KBSOUT15/GPIO61/XOR_OUT

GPIO60/KBSOUT16 GPIO57/KBSOUT17

KBSIN0/GPIOA0/N2TCK KBSIN1/GPIOA1/N2TMS

KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7

7 2 3 1 128 127 126 125 8

1

9 29 124 121 122

27 25 11 10 7114 7215

70 69 67 68 119 120 24 28 17 20 21 23

82 84 83

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

54 55 56 57 58 59 60 61

BUF_PLT_RST#

CLK_KBPCI

LPC_3S_FRAME#

LPC_3S_AD<3> LPC_3S_AD<2> LPC_3S_AD<1> LPC_3S_AD<0> PCI_3S_SERIRQ

PCI_3S_CLKRUN#

TP324

RUNSCI0#_3

TP30

EC_3S_A20GATE KBRST#

2 1

10K_5%_2

TP30

EN_PVCORE USB_OC#_2 IM_DAT_5 IM_CLK_5

EC_SMB1_CLK EC_SMB1_DATA EC_SMB2_CLK EC_SMB2_DATA AOAC_ON# WLON# FLASH_OVERRIDE LID_SW#_3

TP30

TP326

TP30

TP303

TP30

TP304

TP30

TP305

EC_PW_ON# SB_USB_1 EC_CTL1

SCAN_OUT<1> SCAN_OUT<2> SCAN_OUT<3> SCAN_OUT<4> SCAN_OUT<5> SCAN_OUT<6> SCAN_OUT<7> SCAN_OUT<8> SCAN_OUT<9> SCAN_OUT<10> SCAN_OUT<11> SCAN_OUT<12> SCAN_OUT<13> SCAN_OUT<14> SCAN_OUT<15> SCAN_OUT<16> SCAN_OUT<17>

SCAN_IN<0> SCAN_IN<1> SCAN_IN<2> SCAN_IN<3> SCAN_IN<4> SCAN_IN<5> SCAN_IN<6> SCAN_IN<7>

TP30

1

R300

TP306

IN

BI BI BI BI BI BI BI

OUT OUT

TP325

P3V3AL

PWR_SWIN#_3

1

RSMRST#

1

SB_USB_0 SLP_S5#_3R

1 1

H_PROCHOT_EC

1

SB_USB_2

OUT OUT OUT

SCAN_OUT<17..0>

0 1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17

SCAN_IN<7..0>

0

1

2

3

4

5

6

7

27C3 27C7

51A7 27C3 47C3 27C3 47C3 27C3 47C3 27C3 47C3 27C3 47C3 27B7 47C2

51C7 52D6

OUT OUT OUT

OUT

14D8

15D4 33D8 32A8

28C3

49B3 49A5

IN

BI BI

BI BI BI BI BI BI

18C4

IN

OUT

IN OUT OUT

OUT

IN

57A6 51A8

20A4 21D1 49C2

49B7 11A8 30A3

20A7

5D3 21D2 56D8 56C8

27C2 21D2

21D2 27B2

47B8 47B7

20D6

21D2 5D3

32A8 32C3

49B3 14D2 21B1 30B6

20C6

20A7

20D3

P3V3S

R312

2 1

10K_5%_2

41D6 11B7

R326

2 1

10K_5%_2

37C3

OUT

OUT OUT

21D3

56D8 37C6

21D3

56C8

21D3

CPU_PROCHOT#

52C2 52C2

27C2

27B2

5D3 5D3 21D3 5A7 5A7

EC_SMB1_CLK

BI

EC_SMB1_DATA

BI

EC_SMB2_CLK

BI

EC_SMB2_DATA

BI BI BI

10K_5%_2

2 1

3

Q300

DS

G

SSM3K7002BFU

2

R333

1

AOAC_ON# WLON#

RSMRST#

H_PROCHOT_ECSCAN_OUT<0>

R324

100K_5%_2

2 1

R334 R335

R322 R321 R317 R316

OUT

2 1 2 1 2 1 2 1 2 1 2 1

21D3

IN

3.3K_5%_2

1.8K_5%_2

1.8K_5%_2 10K_5%_2 10K_5%_2

21D3

P3V3AL

49C2 49B7

56D6 21E6

P3V3AL

L300

P3V3AL_EC

21

50D7

FBM_11_160808_121T

C314

2 1

C305

2 1

10UF_6.3V_5_DY

0.1UF_16V_2

AGND_KBC

5B7 21E6

IN

5D5 21E6 32A8

21E6 5D3

IN

OUT

HW_I_ADC HW_V_ADC BATT_IN

1.BATTERY

C316

C317

2 1

0.1UF_16V_2

2 1

C315

2 1

0.1UF_16V_2

EC_SMB2EC_SMB1 EC_SMB3

1.CHARGE

VGA_LCM_BKLTEN

PCH_LCM_BKLTEN

IN

GM: 100K PM: 10K

R302

100K_5%_2

3 CELL ID

49A1

0_5%_1

2.GPU THERMAL

3.CEC

P3V3AL

R313

10K_5%_2

21

U300

21D6 47A6

47A6

21C6

21C8

47A6

P3V3AL

21C6

47A6

21C8

IN

OUT

IN

OUT

EC_SPI_CS0# EC_SPI_SO

R315

10K_5%_2_DY

EC_SPI_CS1# EC_SPI_SO

21

1

CS#

2

SO_SIO1

3

WP#_ACC

4

1 2 3 4

SI_SIO0

GND

MXIC_MX25L3206EM2I_12G_SOP_8P

U302

CS# SO_SIO1 WP#_ACC

SI_SIO0

GND

MXIC_MX25L3206EM2I_12G_SOP_8P_DY

HOLD#

SCLK

8

VCC

7 6 5

8

VCC

7 6 5

R314

R319

3.3K_5%_2

21

EC_SPI_CLK EC_SPI_SI

3.3K_5%_2_DY

21

EC_SPI_CLK EC_SPI_SI

IN IN

P3V3AL

21C7 21C6 47A6

P3V3AL

21C7 21C6

C311

680PF_50V_2

2 1

21D6

47A6 21C7

47A6

21D6 47A6

21C7

FAN_TACH1

C309

2 1

C318

2 1

P1V05S

WINB_NPCE885LA0DX_LQFP_128P

XXX 21-OCT-2002

MODEL,PROJECT,FUNCTION

Block Diagram

C CS

1310xxxxx-0-0

21 69

X01

REFERENCE 400~499(LAN)

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

Q400

P3V3A

IN

WOL_AUX_ON#

21D6

DIODES_DMP2305U_SOT23_3P

S

SD

G

C400

2 1

G

CSC0402_DY

R400

100K_5%_2

D

C401

21

2 1

0.047UF_16V_2

PAD400

1 2

POWERPAD_2_0610

P3V3A_LAN

21

C402

2 1

C403

2 1

4.7UF_6.3V_3

C404

2 1

1UF_6.3V_2

C405

2 1

0.1UF_16V_2 10UF_6.3V_5_DY

PAVDDVCO_LAN

C424

2 1

1UF_6.3V_2_DY

C425

2 12 1

0.1UF_16V_2

R402

0_5%_3

PDVDDL_LAN

C427

C426

2 1

1UF_6.3V_2

0.1UF_16V_2

48D8 48D7 48C7

P3V3S

21

R401

21B6

C413

2 1

30K_5%_2

22A5

0.1UF_16V_2

LAN_X1

LAN_X2

2121

PAVDDL_LAN

C412

2 1

1UF_6.3V_2

PVLX_LAN

LQM21PN2R2MC0D_DY

FOR SW MODE

PDVDDL_LAN

C406

2 1

C407

2 1

10UF_6.3V_3_DY

0.1UF_16V_2_DY

C408

2 1

X400

R406L400

RSC_0603_DY

1000PF_50V_2_DY

21

CLKREQ_LAN#

OUT

PAVDDH_LAN

C414

2 1

OUT OUT

49B3 49A5 27C7 31C6

22A5

C415

2 1

1UF_6.3V_2

23B7 23C6

22B5 22B5

IN

OUT

IN IN

23B7 23C6

0.1UF_16V_2

23B7 23C6

23B7 23B7 23B7 23B7

P3V3A_LAN

LAN_RST# PCIE_WAKE#

LAN_X1 LAN_X2

R405

2.37K_1%_2

BI BI BI BI BI BI BI BI

21

LAN_TRD0_DP LAN_TRD0_DN LAN_TRD1_DP LAN_TRD1_DN LAN_TRD2_DP LAN_TRD2_DN LAN_TRD3_DP LAN_TRD3_DN

PVLX_LAN

FOR LDO MODE

R403

2 1

10K_5%_2

R404

2 1

10K_5%_2_DY

34

38

LED_1

LED_0

TRXN0

AVDDL

12

13916

37

RX_N

DVDDL_REG

TRXP1

TRXN1

141115

353633

RX_P

AVDDL

AVDD33

TRXP2

17

U400

1 2 3 4 5 6 7 8

10

VDD33 PERSTN WAKEN CLKREQN ISOLATN AVDDL_REG XTLO XTLI AVDDH_REG RBIAS

LX

GND

TRXP0

402339

41

PAVDDL_LAN

C416

0.1UF_16V_2 0.1UF_16V_2

2 1

PAVDDL_LAN

PCIE_LAN_TX_DN PCIE_LAN_TX_DP CLK_PCIE_LAN_DP CLK_PCIE_LAN_DN

31

32

AVDDLTRXP3

30

TX_P

REFCLK_P

REFCLK_N

TX_N

NC

TESTMODE

SMDATA

SMCLK

PPS LED_2 AVDDH TRXN3

AVDDL

TRXN2

ATHEROS_AR8161_AL3A_R_QFN_40P

201918

1UF_6.3V_2_DY

C417

PCIE_LAN_RX_C_DP

29

PCIE_LAN_RX_C_DN

28 27 26 25 24

22 21

C418

C423

0.1UF_16V_2

2 1

PAVDDH_LAN

2 1

C419

0.1UF_16V_2

2 1

48D8

IN

48D8

IN

48C7

IN

48C7

IN

C421 C422

C420

0.1UF_16V_2

P3V3A_LAN

21

0.1UF_16V_2

21

0.1UF_16V_2

PCIE_LAN_RX_DP PCIE_LAN_RX_DN

OUT OUT

48D8 48D8

25MHZ

C409

2 1

33PF_50V_2

C410

2 1

33PF_50V_2

C417:8161 STUFF 8162 OPEN

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6922

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 400~499(LAN)

JACK470

23C3

23B3 23B3

23C3 23C3 23B3 23C2 23B3 23C2 23B3 23C3 23B3 23C2 23B3 23C2 23B3

LAN_TD_DP

IN

LAN_TD_DN

IN

LAN_RD_DP

IN

LAN_C_DP

IN

LAN_C_DN

IN

LAN_RD_DN

IN

LAN_D_DP

IN

LAN_D_DN

IN

LAN_TRD0_DN LAN_TRD0_DP

LAN_TRD1_DN LAN_TRD1_DP

C478

2 1

C479

2 1

0.1UF_16V_2

23C6 22B5 23C6 22B5

22B5 22B5

23B7 22B5 23B7 22B5

23B7 22B5

IN IN

LAN_TRD0_DN LAN_TRD0_DP

LAN_TRD1_DN LAN_TRD1_DP

LAN_TRD2_DN LAN_TRD2_DP

LAN_TRD3_DN LAN_TRD3_DP

IN IN

IN

22B5 23B7

IN

C480

2 1

C470

2 1

CSC0402_DY

C481

2 1

0.1UF_16V_2

C471

2 1

CSC0402_DY

C482

2 1

0.1UF_16V_2

CSC0402_DY

C472

2 1

C483

2 1

0.1UF_16V_2

C473

2 1

CSC0402_DY

0.1UF_16V_2

1

TX+

2

TX-

3

RX+

4

P4

5

P5

6

RX-

7

P7

8

P8

SANTA_130456_051_8P

U471

2 15

TCT TCT

3 1 7 8 6 4 5

1 3 2 4 6 5 7 9

8 10 12 11

TX-

TD-

TX+

TD+ RCT

RCT RX-

RD-

RX+

RD+ NC

NC

BOTH_TS21C_HF_SOP_16P

U470

TCT1

MCT1

TD1-

MX1-

TD1+

MX1+

TCT2

MCT2

TD2-

MX2-

TD2+

MX2+

TCT3

MCT3

TD3-

MX3-

TD3+

MX3+

TCT4

MCT4

TD4-

MX4-

TD4+

MX4+

BOTH_GST5009_RA_SOP_24P

C474

2 1

1UF_6.3V_2

G1

G

G2

G

R474

2 1

R475

75_5%_3

2 1

LAN_TD_DN LAN_TD_DP

LAN_RD_DN LAN_RD_DP

75_5%_3

OUT OUT

2 1

RSC_0603_DY

2 1

RSC_0603_DY

LAN_TD_DN LAN_TD_DP

LAN_RD_DN LAN_RD_DP

LAN_C_DN LAN_C_DP

LAN_D_DN LAN_D_DP

23B3 23B3

23B3

R476

R477

23D5 23D5

23D5 23D5 23B3

RSC_0402_DY

OUT OUT

R478

2 1

R479

2 1

23D5 23C3 23D5 23C3

23D5 23C2 23D5 23C2

LAN_C_DN

LAN_C_DP

LAN_D_DN

LAN_D_DP

OUT

23D5 23B3

14 16 10 9 11 12 13

24 22 23 21 19 20 18 16 17 15 13 14

R473

R472

R471

R470

75_5%_3

2 1

75_5%_3

2 1

C475

1000PF_2000V_6

2 1

75_5%_3

C477

C476

2 1

CSC0402_DY 75_5%_3

100PF_50V_2

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6923

A3

21-OCT-2002XXX

REFERENCE 500~549(AUDIO CODEC)

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

AGND_AUDIO

2.2UF_6.3V_3

C503

CLOSE TO PIN27

P5V0S_AUDIO_AVDDP5V0S

C513C519

C512

10UF_6.3V_3

2 1

2.2UF_6.3V_3

2 1

0.1UF_16V_2

2 1

BLM18PG121SN1(6014B0041601_0603)

R515

0_5%_3

21

P5V0S_AUDIO_AVDD

U500

AVSS2

AVDD2

PVDD1

SPK-L+

SPK-L-

PVSS1

PVSS2

SPK-R-

SPK-R+

PVDD2

EAPD

SPDIFO

0.1UF_16V_2

MIC_IN_CLK_R

21

C502

2 1

36

CBP

DVDD1

1

34

35

CBN

CPVEE

GPIO1/DMIC-CLK

GPIO0/DMIC-DATA

3

2

33

HP-OUT-R

PD#

4

31

32

HP-OUT-L

DIGITAL

SDATA-OUT

5

6

C518

2 1

30

MIC1-VREFO-L

MIC1-VREFO-R

BIT-CLK

DVSS2

7

22PF_50V_2_DY

29

28

LDO-CAP

MIC2-VREFO

ANALOG

DVDD-IO

SDATA-IN

8

9

HDA_R_SDIN0

HDA_R_BITCLK

C510

2 1

2710

263825

VREF

AVSS1

RESET#

SYNC

11

P3V3A

C522

2 1

0.1UF_16V_2

AVDD1

LINE1-R

LINE1-L

MIC1-R

MIC1-L

MONO-OUT

JDREF

Sense-B

MIC2-R

MIC2-L

LINE2-R

LINE2-L

Sense A

GND

PCBEEP

REA_ALC269Q_VB6_CGT_QFN_48P

12

C520

0.1UF_16V_2

22_5%_2

1UF_6.3V_2

P5V0S

BLM18PG121SN1(6014B0041601_0603)

R516

21

2.2UF_6.3V_3

P5V0S_PVDD

0_5%_3

C532

2 1

C506

2 1

10UF_6.3V_3_DY

0.1UF_16V_2_DY

C505

2 1

C507

2 1

4.7UF_6.3V_3

C536

0.1UF_16V_2

2 1

C500

2 1

4.7UF_6.3V_3

0.1UF_16V_2

37

AGND_AUDIO

39

C529

25B8 25C2

OUT

25B8

OUT

SPK_OUT_L_P

SPK_OUT_L_N

R512 R511

21

0_5%_3

21

0_5%_3

RESERVE FOR EMI (THERMAL PAD 4X4 VIAS)

2 1

25B8

C531

2 1

4.7UF_6.3V_3

OUT OUT

0.1UF_16V_2

SPK_OUT_R_N

SPK_OUT_R_P

R510

R509

21

0_5%_3

21

0_5%_3

40

41

42

43

44

45

46

47

48

P3V3S

C514

2 1

CSC0402_DY

C515

2 1

CSC0402_DY

C516

2 1

CSC0402_DY

C517

2 1

CSC0402_DY

AGND_AUDIO

TIED UNDER OR NEAR CODEC

PAD500

1 2

POWERPAD1X1M

21

AGND_AUDIO

34B3

BI BI

MIC_IN_DATA

MIC_IN_CLK

C523

CSC0402_DY

C508

2 1

C509

1UF_6.3V_2

100_5%_2

2 1

R505

RESERVE FOR EMI

MIC_REF_L MIC_REF_R

24

23

22

21

20

19

18

17

16

15

14

13

49

R502

R503

0_5%_2

HP_R HP_L

21

OUT OUT OUT OUT

MIC_R

MIC_L

R514

20K_1%_2

AGND_AUDIO

47K_1%_2

HDA_3S_RST# HDA_3S_SYNC

HDA_3S_SDIN0

HDA_3S_BITCLK HDA_3S_SDOUT EC_MUTE#

25B3

25A3

25D3

BI BI

21

CLOSE TO PIN13

R500

20K_1%_2

R501

39.2K_1%_2

R507

2121

P5V0S_AUDIO_AVDD

25C2

21

MICS

21

HPS

PCSPKR_PCH_3

2 1

100PF_50V_2

47C7

IN

47C7

IN

47B7

IN

47C7

IN

47B7

IN

21D6

IN

C521

R506

4.7K_1%_2

2 1

C504

2 1

0.1UF_16V_2

4.7UF_6.3V_3

C501

AGND_AUDIO

25C5

IN

25B2

IN

47C8

IN

21

AGND_AUDIO

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6924

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERCE 600~649(JACK/MIC/SPEAKER)

AUDIO JACKS

MIC_REF_L

21

MICPHONE

JACK600

SINGA_2SJ_T351_019_6P

5

TP607

4

1

3 6

1

2 111 G1 G2

TP606

TP30

TP30 TP30

MICS

TP605

TP604

OUT

2.2K_5%_2

R606

0_5%_3

24B2

0_5%_3

21

R607

RESERVE FOR EMI

C601C600

21

R604R605

2.2K_5%_2

R602

R603

21

1K_5%_2

21

1K_5%_2

MIC_REF_R

C606

C607

2.2UF_6.3V_3

24D3

IN

24D3

IN

21

MIC_R

21

MIC_L

24C2

BI

24C2

BI

AGND_AUDIO

2 1

CSC0402_DY

EMI CAPACITORS TO CLOSE TO JACK SIDE

AGND_AUDIO

D600

3

INTERNAL SPEAKERS

24C7 24C7 24C7 24C7

NOTE:SPK TRACE SHOULD 30~40 MILS WIDTH

SPK_OUT_L_P

IN

SPK_OUT_L_N

IN

SPK_OUT_R_N

IN

SPK_OUT_R_P

IN

C602

2 1

470PF_50V_2_DY

C603

2 1

C604

2 1

470PF_50V_2_DY

C605

2 1

470PF_50V_2_DY

C608

2 1

C609

470PF_50V_2_DY

2 1

470PF_50V_2_DY

CN600

4 G2

4

3

2

1

ACES_50224_0040N_001_4P

G2

G1

24D3

R601 R609

75_5%_2

HP_R

IN IN

HP_L

75_5%_2

21 21

21

R600

PHP_PESD5V2S2UT_SOT23_3P_DY

AGND_AUDIO

0_5%_3

R608

0_5%_3

24B2

21

OUT

C611

2 1

RESERVE FOR EMI

AGND_AUDIO

2

1

HPS

1

TP601

TP30

1

TP600

TP30

C610

2 1

470PF_50V_2_DY

HEADPHONE

JACK601

5

TP603

1

4

TP30

3 6 2

1

TP30

G1

TP602

G2

SINGA_2SJ_T351_019_6P

AGND_AUDIO

470PF_50V_2_DY

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6925

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERNCE 900~999(CARDREADER)

SD_CMD

SD_R_CLK SD_CLK

R901

21

26B3

BI

26B3

BI

0_5%_2

RESERVE FOR EMI

SD_CD#

17

16

15

14

SP8

3V3_IN

4

SP7

CARD_3V3

5

13

SP6

SP5

SP4

SP3

SP2SP14

SP1

XD_CD#V18

SDREG

REA_RTS5129_QFN_24P

6

C904

1UF_6.3V_2

2 1

12

11

10

922

8

724

18

U900

SP9

SP10

GPIO0

RREF

DP

DM

1

3

2

26B3

1UF_6.3V_2

BI

C901

19

SP11

SD_D3

20

SP12

SD_D2

21

SP13

23

XD_D7

25

TML

2 1

R900

21

CARD_REF

BI

SD_D0

SD_D1

SD_WP

26B3

P3V3S_CR

C905 C906

26B3

2.2UF_6.3V_3

BIBI

26B3

BI

26B3

BI

0.1UF_16V_2

2 1

CN900

26C7 26D5

26C5

26C5 26C5 26C7 26C5 26B5

SD_D3

BI

SD_CMD

BI

SD_CLK

BI

SD_D0

BI

SD_D1

BI

SD_D2

BI

SD_CD#

BI

SD_WP

BI

1

CD-DAT3

2

CMD

3

VSS1

4

VDD

5

CLK

6

VSS2

7

DAT0

8

DAT1

9

DAT2

10

CARD_DETECT

11

WRIT_PROTECT

TAI_PSDAT0_09GLBS1ZZ4H1_11P

G1

G2

6.2K_1%_2

P3V3S_CR

51B2

USB_CR_DN

BI

USB_CR_DP

BI

C902

0.1UF_16V_2

2 1

P3V3S

PAD900

1 2

21

P3V3S_CARD

POWERPAD_2_0610

4.7UF_6.3V_3

C900

2 1

C903

0.1UF_16V_2

2 1

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6926

A3

21-OCT-2002XXX

REFERENCE 1300~1349(WLAN)

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

P3V3S

P1V5S

C1302

10UF_6.3V_3

2 1

31C6

52B6

47C2

22B5

27B7 48B7 48D7 48D8

48B7 48B7

21E3 27C3 51A7

48D8 48D8

27C7

21E3

49A5 49B3

28C3

51A8 57A6

BI BI

IN IN

IN OUT

OUT

IN IN

BI

IN

PCIE_WAKE#

BTIFON# CLKREQ_WLAN#

CLK_PCIE_WLAN_DN CLK_PCIE_WLAN_DP

BUF_PLT_RST# CLK_PCI_DEBUG

PCIE_WLAN_RX_DN PCIE_WLAN_RX_DP

PCIE_WLAN_TX_DN PCIE_WLAN_TX_DP

BTIFON#

PCI_3S_SERIRQ

C1304

0.1UF_16V_2

2 1

R1300

R1301

C1303

RESERVE FOR EMI

R1302

R1303

0_5%_2

21

0_5%_2

21

0_5%_2

21

0_5%_2_DY

21

CSC0402_DY

11 13 15 17 19 21 23 25

29 31 33 35 37 39 41 43 45 47 49 51

1 3 5 7 9

CN1300

WAKE# CH_DATA CH_CLK CLKREQ# GND REFCLKREFCLK+ GND LPC_DEBUG_RST# LPC_PCI_CLK GND PERN0 PERP0

GND PETN0 PETP0 GND Reserved Reserved Reserved Reserved +V3AL PWR_LED# NUM_LED# CAPS_LED#

LPC_FRAME#

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

W_DISABLE#

PERST#

+3.3VAUX

SMB_CLK

SMB_DATA

USB_DUSB_D+

LED_WWAN# LED_WLAN# LED_WPAN#

0.1UF_16V_2

2 1

2

3.3V

4

GND

6

1.5V

8 10 12 14 16 18

GND

20 22 24 26

GND

2827

1.5VGND

30 32 34

GND

36 38 40

GND

42 44 46 48

1.5V

50

GND

52

3.3V

G2G1

GG

C1305

R1304

0_5%_5

2 1

C1301

10UF_6.3V_3

2 1

LPC_3S_FRAME#

LPC_3S_AD<3> LPC_3S_AD<2> LPC_3S_AD<1> LPC_3S_AD<0>

BUF_PLT_RST#

PCH_3A_ALERT_CLK PCH_3A_ALERT_DAT

USB_WLAN_DN USB_WLAN_DP

SUPPORT AOAC:STUFFSUPPORT AOAC:OPEN

2 1

Q1300

1

D

2 5

AM3423P_DY

C1306

CSC0402_DY

IN

21E3

IN IN IN IN

21E3

IN

57A6

BI BI

PMOS_4D1S

48D2 48D3

51B2 51B2

47C3 21E3 47C3 47C3 21E3 47C3 21E3 47C3 21E3

27C7 51A8 28C3

48D2 48D3

S

G

3

2

4

36

AOAC_ON#

Q1301

DS

G

SSM3K7002BFU

P3V3A

2 1

1

C1307

CSC0402_DY

IN

WLON#

21D2

21D3

21D2

21D3

IN

BELLW_80003_4021_52P

MINI CARD 1(WLAN)

21-OCT-2002XXX

MODEL,PROJECT,FUNCTION

CS

A3

Block Diagram

X011310xxxxx-0-0

6927

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 1400~1499(3G)

P1V5S

2 1

C1412

2 1

0.1UF_16V_2

22UF_6.3V_5

C1410

C1411

2 1

0.1UF_16V_2

P3V3S

IN

C1400C1401C1402

22UF_6.3V_5

2 1

52D6

47B3 47B3

SATA_MINICARD_RX_DP

BI

SATA_MINICARD_RX_DN

BI

SATA_MINICARD_TX_DN

BI

SATA_MINICARD_TX_DP

BI

C1405

C1407

CLOSE TO CONN SIDE

0.01UF_50V_2

21

C1406

0.01UF_50V_2

21

C1408

21

0.01UF_50V_2

21

52D6

OUT

SATA_MINICARD_C_RX_DP SATA_MINICARD_C_RX_DN

SATA_MINICARD_C_TX_DN SATA_MINICARD_C_TX_DP

MSATA_DET

TP1402

CN1400

1

WAKE#

3

CH_DATA

5

CH_CLK

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

LPC_DEBUG_RST#

19

LPC_PCI_CLK

21

GND

23

PERN0

25

PERP0

29

GND

31

PETN0

33

PETP0

35

GND

37

Reserved

39

Reserved

41

Reserved

43

Reserved

45

+V3AL

47

TP24

1

PWR_LED#

49

NUM_LED#

51

CAPS_LED#

LPC_FRAME#

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

W_DISABLE#

+3.3VAUX

SMB_CLK

SMB_DATA

LED_WWAN# LED_WLAN# LED_WPAN#

PERST#

USB_DUSB_D+

2

3.3V

4

GND

6

1.5V

8 10 12 14 16 18

GND

20 22 24 26

GND

2827

1.5VGND

30 32 34

GND

36 38 40

GND

42 44 46 48

1.5V

50

GND

52

3.3V

G2G1

GG

UIM_PWR UIM_DATA UIM_CLK UIM_RST

BUF_PLT_RST#

1

TP24

1

TP24

USB_3G_DN USB_3G_DP

TP1400 TP1401

OUT

BI BI

OUT

BI BI

28A6 28A4 28A4

IN

51B2 51B2

0.1UF_16V_2

2 1

28B6 28A4

3G_OFF#

21E3 27C3 27C7 51A8 57A6

3

Q1400

DS

SSM3K7002BFU

2

G

0.1UF_16V_2

2 1

3G_ON#

1

BELLW_80003_4021_52P

P3V3S

28A4 28D3

UIM_PWR

IN

U1400

1

VIO

3

VIO VIO

6

VIO

52

VBUSGND

4

NXP_IP4223CZ6_SOT457_6P_DY

CN1401

P5

GND

P6

28D3

UIM_DATA

BI BI

VPP

P7

I_O

G2 G1

G

P1

VCC

P2

RST

P3

CLK

G

UIM_PWR UIM_RST UIM_CLK

IN IN

28B6 28D3 28C3

28C3

TAI_PMPAT5_06GLBS7NI4H1_6P

2 1

C1404

2 1

0.1UF_16V_2

4.7UF_6.3V_3

C1403

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6928

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 1700~1749(HDD) REFERENCE 1750~1799(ODD)

SATA HDD

CN1700

1

IN IN

OUT OUT

SATA_HDD_TX_DP SATA_HDD_TX_DN

SATA_HDD_RX_DN SATA_HDD_RX_DP

47C3 47C3

C1704 C1705 C1700

C1701

0.01UF_50V_2

21

0.01UF_50V_2

21

0.01UF_50V_2

21

0.01UF_50V_2

21

SATA_HDD_TX_C_DP SATA_HDD_TX_C_DN

SATA_HDD_RX_C_DN SATA_HDD_RX_C_DP

PLACE CLOSE TO CONNECTOR(<100MILS)

P5V0S

40MIL

2 1

C1702

2 1

22UF_6.3V_5

0.1UF_16V_2

C1706

2 1

C1703

22UF_6.3V_5

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V3.3

9

V3.3

10

V3.3

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

RESERVED

19

GND

20

V12

21

V12

22

V12

G1

G2

SANTA_194911_1_22P

P5V0S

P3V3S

R1752

1M_5%_2_DY

R1750

10K_5%_2_DY

2 1

Q1750

52D2

IN

SATA_ODD_PWREN

SSM3K7002BFU_DY

1

G

47B3 47B3

3 2 1

DS

2

OUT OUT

IN IN

100K_5%_2_DY

C1754

CSC0402_DY

R1751

21

SATA_ODD_RX_DP SATA_ODD_RX_DN

SATA_ODD_TX_DN SATA_ODD_TX_DP

2 1

Q1751

TPC6111_DY

C1758

2 1

CSC0402_DY

C1750

C1753

36

G

PMOS_4D1S

521

4

S

D

C1751

C1752

R1754

C1757

21

2 1

0_5%_6

C1756

2 1

22UF_6.3V_5

0.01UF_50V_2

21

C1755

22UF_6.3V_5

51C7

0.01UF_50V_2

51B6

52B6 52D7

2 1

0.1UF_16V_2

OUT

SATA_ODD_RX_C_DP SATA_ODD_RX_C_DN

SATA_ODD_TX_C_DN SATA_ODD_TX_C_DP

SATA_ODD_DA#

SATA_ODD_PRSNT#

CN1750

P6

GND

P5

GND

P4

MD

P3

+5V

P2

+5V

P1

DP

S7

GND

S6

B+

S5

B-

S4

GND

S3

A-

S2

A+

S1

GND

SYN_127382FR013G212ZR_13P

SATA ODD

G1

G

G2

G

PLACE CLOSE TO CONNECTOR(<100MILS)

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6929

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 2000~2099(USB)

P5V0A_USB3

CN2002

1

51C2 51C2

BI BI

USB_P2_DN USB_P2_DP

2 3 4

1 2 3 4 G2

G1

G2

ACES_50224_0040N_001_4P

P5V0A

PAD2000

1 2

POWERPAD_2_0610

P5V0A_USB_PW1

21

22UF_6.3V_5_DY

C2000 C2001

1UF_6.3V_2

2 1

P5V0A_USB3

21D3

SB_USB_2

IN

C2004

CSC0402_DY

2 1

U2000

1 2 3

OUT

GND

OUT

IN

OUT

IN

OC#

EN

ROHM_BD82020FVJ_TSSOP_8P

8 7 6 54

22UF_6.3V_5

C2002

0.1UF_16V_2

2 1

C2003

2 1

R2000

RSC_0402_DY

2 1

P3V3AL

R2001

10K_5%_2

2 1

USB_OC#_2

OUT

21D3

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6930

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 2400~2499(USB3.0)

P1V05_USB3

2 1

0.1UF_16V_2

21

IN

OUT

IN

OUT

31A6 31A8 31A6

31A8

C2425

2 1

0.1UF_16V_2

21

PLT_RST# PCIE_WAKE# CLKREQ_IC_USB3#

USB3_SMI#

OUT OUT OUT

IN

X2400

24MHZ

21

PCIE_USB3_RX_C_DP PCIE_USB3_RX_C_DN

USB3_SCLK USB3_CS# USB3_SI USB3_SO

USB3_XT1 USB3_XT2

C2412C2413

15PF_50V_2

2 1

31A5

P3V3_USB3

34

12

VDD33

22

VDD33

U2400

1

PECLKP

2

PECLKN

4

PETXP

5

PETXN

7

PERXP

8

PERXN

47

PERSTB

48

PEWAKEB

10

PECREQB

46

SMIB

11

PONRSTB

15

SPISCK

14

SPICSB

16

SPISI

13

SPISO

24

XT1

23

XT2

27

IC(L)

VDD33

43

VDD33

P1V05_USB3

6

VDD10

C2417

2 1

C2418

2 1

0.01UF_50V_2

C2419

2 1

0.01UF_50V_2

C2420

2 1

0.01UF_50V_2

C2421

2 1

0.01UF_50V_2

C2422

2 1

0.01UF_50V_2

C2423

2 1

0.01UF_50V_2

C2424

0.1UF_16V_2

IN IN

PCIE_USB3_RX_DP

OUT

PCIE_USB3_RX_DN

OUT

IN IN

R2406

10K_5%_2

2

NC

CLK_PCIE_USB3_DP CLK_PCIE_USB3_DN

PCIE_USB3_TX_DP PCIE_USB3_TX_DN

49B3 49A5 27C7 22B5

21

13

1UF_6.3V_2

2 1

C2409

C2410

36B2

51A7 41C7

C2411

0.1UF_16V_2

31B6

31C7 51B6

P3V3_USB3

R4754

2 1

10K_5%_2

R4955

10K_5%_2

CLKREQ_USB3#

21

USB3_SMI#

IN

48B7 48B7

48D8 48D8

48D8

31C6 51B6

P3V3_USB3

D2400

BAT54_30V_0.2A

48B7 31B8

15PF_50V_2

2 1

31C7 48B7

OUT

CLKREQ_USB3#

R2405

0_5%_2

CLKREQ_IC_USB3#

21

31C6

IN

USB30_PWR_EN

21D6

P3V3_USB30_AVDD

9

21

30

33

39

VDD10

GND

RENESAS_UPD720202K8_BAA_A_QFN_48P

49

42

VDD10

3

AVDD33

25

AVDD33

U3TXDP2

U3TXDN2

U2DM2

U2DP2

U3RXDP2

U3RXDN2

OCI2B OCI1B

PPON2 PPON1

U3TXDP1

U3TXDN1

U2DM1

U2DP1

U3RXDP1

U3RXDN1

10K_5%_2

RREF

R2424

1

G

37

38 45

44 40

41

17 19

18 20

28

29 36

35 31

32

26

P3V3A

2 1

3

SSM3K7002BFU

2

R2427

220K_5%_2

DS

Q2402

USB3_IC_TX2_DP

USB3_IC_TX2_DN USB2_IC_TX2_DN

USB2_IC_TX2_DP USB3_IC_RX2_DP

USB3_IC_RX2_DN

C2472

S

2 1

Q2403

SD

CSC0402_DY

DIODES_DMP2305U_SOT23_3P

21

G

C2473

G

D

2 1

C2400

CSC0402_DY

BI BI

P3V3_USB3

C2401

2 1

0.1UF_16V_2

P3V3_USB3

FBM_11_160808_121T

33B5

33B5 33C5

33C5 33B5

33B5

C2402

2 1

0.1UF_16V_2

0.01UF_50V_2

P3V3_USB30_AVDD

L2400

C2403

2 1

21

C2406

C2404

2 1

0.01UF_50V_2

C2408

2 1

10UF_6.3V_3

P3V3_USB3

21

R2415 R2416

USB3_IC_TX1_DP

USB3_IC_TX1_DN USB2_IC_TX1_DN

USB2_IC_TX1_DP USB3_IC_RX1_DP

USB3_IC_RX1_DN

R2400

1.6K_1%_2

21

10K_5%_2

21

10K_5%_2

32D7

BI

32D7

BI

32D7

BI

32D7

BI

R2413

R2414

BI

21

0_5%_2

USB2_IC_TX1_DN_R

USB2_IC_TX1_DP_R

C2405

2 1

0.01UF_50V_2

C2414

2 1

0.1UF_16V_2

C2470

2 1

0.01UF_50V_2

2 1

0.1UF_16V_2

BI BI

0.01UF_50V_2

C2415

2 1

32B8

C2471

2 1

C2416

2 1

0.01UF_50V_2

10UF_6.3V_3

31B6

IN

OUT

P3V3_USB3

R2480 R2481

10K_5%_2

USB3_CS# USB3_SO

P5V0A

P1V5

VIN EN POK

VCNTL

VIN

U2403

GND

FB

VOUT

31.6K_1%_2

R2423

1

2

3

4

2 1

TRACE WIDTH>20MILS

R2422

10K_1%_2

C2433

150PF_50V_2

21

C2434

2 1

22UF_6.3V_5

9 8 7

6

5

ANPEC_APL5930KAI_TRL_SOP_8P

C2435

1UF_6.3V_2

2 1

IN

USB30_PWR_EN

47K_5%_2

P3V3_USB3

21D6 31D4

C2480

0.1UF_16V_2

2 1

U2480

1

CS#

2

SO

3

WP#

MAC_MX25L512EMI_10G_SOP_8P

HOLD#

SCLK

8

VCC

7 6 54

SIGND

2 1

USB3_SCLK USB3_SI

22UF_6.3V_5

31B6

IN

31B6

IN

C2438

2 1

P1V05_USB3

PAD2400

1 2

POWERPAD1X1M

21

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6931

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

USB3.0 FROM CONTROLLLER

31B2 31B2

USB3_IC_RX1_DN

BI

USB3_IC_RX1_DP

BI

R2430 R2431

21

0_5%_2

21

0_5%_2

USB3_SSRX1_DN USB3_SSRX1_DP

REFERENCE 2400~2499(USB3.0)

32C7

BI

32C7

BI

USB3.0 FROM PCH

USB3.0 FROM CONTROLLLER

USB3.0 FROM PCH

51C6 51C6

31B2 31B2

51C6 51C6

USB3_PCH_RX1_DN

BI

USB3_PCH_RX1_DP

BI

BI BI

R2432 R2433

USB3_IC_TX1_DN USB3_SSTX1_DN USB3_IC_TX1_DP

USB3_PCH_TX1_DN USB3_PCH_TX1_DP

C2447

C2440

C2448

C2441

P5V0A_USB2

R2448

21 21

21

P5V0A_USB1

0_5%_2 0_5%_2

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

USB3_SSTX1_DP

USB3.0

BI BI

32B7 32B7

0_5%_5_DY

USB2.0 FROM SLEEP&CHARGE IC

32A8

BI

32A8

BI

USB2.0 FROM PCH

32B8

51C2

BI

32B8

51C2

BI

31B1

BI

31B1

BI

USB_IC_DP USB_IC_DN

USB_P0_DN USB_P0_DP

USB2_IC_TX1_DN_R USB3_SSTX1_DN USB2_IC_TX1_DP_R

R2455

USB2.0 FROM CONTROLLLER

R2454

R2446

R2447

0_5%_2

21 21

0_5%_2

R2503

R2504

21

0_5%_2

21

0_5%_2

USB_P0_R_DN USB_P0_R_DP

21

0_5%_2

21

0_5%_2

L2404

WCM_2012_900T

21 34

32D5

BI

32D5

BI

32D5

BI

32D5

BI

2 1

USB_P0_L_DN USB_P0_L_DP

USB3_SSRX1_DN USB3_SSRX1_DP

USB3_SSTX1_DP

22UF_6.3V_5

CN2401

1

VBUS

2

D-

3

D+

4

PGND

5

SSRX-

6 7 8 9

LOTES_AUSB0026_P001A_9P

SSRX+ GND SSTXSSTX+

G G G G

C2427

C2426

G1 G2 G3

USB 3.0 CONNECTOR

G4

0.1UF_16V_2

2 1

C2432

1000PF_50V_2

2 1

21D3 32A8

SB_USB_0

IN

47UF_6.3V_5_DY

C2428

P5V0A

2 1

CURRENT LIMIT 2.5A

U2402

1 2 3

OUT

GND

OUT

IN

OUT

IN

OC#EN

ROHM_BD82024FVJ_TSSOP_8P_DY

P5V0A_USB1

+

C2429

100UF_6.3V_DY

8 7 6 54

2 1

P3V3AL

R2408

10K_5%_2

USB_OC#_0

2 1

OUT

21B6 32A6

0_5%_2

21

R2456 R2457

R2444 R2445

0_5%_2

5 6 7 8

DSC CTL1 CTL2 CTL3

21

0_5%_2

21

0_5%_2

21 21

4

ILIM_SEL

NC

9

3 10

DP_OUT DP_IN

2 11

1

U2401

DM_OUT DM_IN

IN

PWPD ILIM0 ILIM1

GND

FAULT#

OUT

TI_TPS2541A_QFN_16P

12

P5V0A_USB1

17 16 15 14

USB_OC#_0

13

P5V0A

2 1

C2442

0.1UF_16V_2

OUT

32B1

21B6

R2435

28K_1%_2

2 1

R2436

0_5%_2_DY

2 1

51C2

32C8

31B2

21D6

21D3

32C3 21C3 21D6 21E6

BI BI

USB2_IC_TX1_DN

BI

USB2_IC_TX1_DP

BI

IN

IN IN IN IN

USB_P0_DN USB_P0_DP

EC_ILIM_SEL

SB_USB_0 EC_CTL1 EC_CTL2 EC_CTL3

P5V0A

R2458

100K_5%_2_DY

32C8

BI BI

USB_IC_DP USB_IC_DN

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6932

A3

21-OCT-2002XXX

REFERENCE 2400~2499(USB3.0)

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

P5V0A_USB2

P5V0A

C2450

CURRENT LIMIT 2.5A

21C3

IN

SB_USB_1

47UF_6.3V_5

C2454

U2404

1

GND

2

IN

3

IN

ROHM_BD82024FVJ_TSSOP_8P

2 1

8

OUT

7

OUT

6

OUT

54

OC#EN

+

330UF_6.3V

2 1

P3V3AL

R2409

10K_5%_2

USB_OC#_1

2 1

OUT

USB2.0 FROM PCONTROLLER

USB2.0 FROM PCH

USB3.0 FROM CONTROLLLER

21D6

31C2

51C2

BI BI

USB2_IC_TX2_DN USB2_IC_TX2_DP

USB_P1_DN USB_P1_DP

USB3_IC_RX2_DN

BI

USB3_IC_RX2_DP

BI

R2453 R2452

R2450 R2451

USB 3.0 CONNECTOR

21

0_5%_2

21

0_5%_2

21 21

0_5%_2

21

0_5%_2

R2437 R2438

21

0_5%_2

21

0_5%_2

USB_P1_R_DN USB_P1_R_DP

WCM_2012_900T

USB3_SSRX2_DN USB3_SSRX2_DP

L2405

33B3 33B3

33B2 33B2

P5V0A_USB2

C2452

0.1UF_16V_2

2 1

CN2402

1

VBUS

2

D-

3

D+

4

PGND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

LOTES_AUSB0026_P001A_9P

G1

G

G2

G

G3

G

G4

G

BI BI

USB_P1_L_DN USB_P1_L_DP

USB3_SSRX2_DN USB3_SSRX2_DP

USB3_SSTX2_DN USB3_SSTX2_DP

33C3 33C3

34

C2453

1000PF_50V_2

2 1

USB3.0 FROM PCH

51C6 51C6

USB3.0 FROM CONTROLLLER

USB3.0 FROM PCH

51C6 51C6

USB3_PCH_RX2_DN

BI

USB3_PCH_RX2_DP

BI

USB3_IC_TX2_DN

BI

USB3_IC_TX2_DP

BI

USB3_PCH_TX2_DN

BI

USB3_PCH_TX2_DP

BI

R2439 R2440

C2443

C2445

C2444

C2446

21

0_5%_2

21

0_5%_2

21

0.1UF_16V_2

21

0.1UF_16V_2

21

0.1UF_16V_2

USB3_SSTX2_DN USB3_SSTX2_DP

33C3

BI

33C3

BI

USB3.0

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6933

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFFERENCE 3000~3049(LCM)

P3V3S

Q3000

S

SD

DIODES_DMP2305U_SOT23_3P

R3000

47K_5%_2

2 1

57B6

50D7

IN

VGA_LCM_VDDEN

PCH_LCM_VDDEN

R3011

R3012

0_5%_1

21

0_5%_1

21

LCM_VDDEN

1

Q3001

G

SSM3K7002BFU

57B6

50D7

21E6

50C6 50C6

PCH_LVDS_TXDL0_DN

IN

PCH_LVDS_TXDL0_DP

IN

PCH_LVDS_TXDL1_DN

IN

PCH_LVDS_TXDL1_DP

IN

PCH_LVDS_TXDL2_DN

IN

PCH_LVDS_TXDL2_DP

IN

PCH_LVDS_TXCL_DN

IN

PCH_LVDS_TXCL_DP

IN

R3019 R3020

R3021 R3022

R3023 R3024

R3025 R3026

21

0_5%_1

21

0_5%_1

21

0_5%_1

21

0_5%_1

21

0_5%_1

21

0_5%_1

21

0_5%_1

21

0_5%_1

3

DS

2

R3001

470K_5%_2

IN IN

IN

C3000

2 1

21

VGA_INV_PWM_3 PCH_INV_PWM_3

EC_BKLTEN

GM:OPEN PM: 10K

0.01UF_50V_2

PCH_LCM_VDDEN#

56D6

BI

56D6

BI

50D7

BI

50C7

BI

R3013 R3014

10K_5%_2

VGA_LVDS_DDCCLK VGA_LVDS_DDCDATA

PCH_LVDS_DDCCLK PCH_LVDS_DDCDATA

0_5%_1

21

0_5%_1

21

R3035

D

G

680PF_50V_2

100_5%_2

R3009

21 21

R3003

100_5%_2

C3006

1000PF_50V_2

2 1

PAD3003

1 2

POWERPAD_2_0610

C3003

2 1

100_5%_2

SSM3K7002BFU

R3015

R3016

R3017

R3018

2 1

R3004

Q3002

1

21

0_5%_1

21

0_5%_1

21

0_5%_1

21

0_5%_1

R3006

100K_5%_2

P3V3S_LCMP3V3S_MOS_LCM

21

C3002

2 1

C3001

10UF_6.3V_3

2 1

0.1UF_16V_2

3

DS

G

GM:2.2K

P3V3S

PM:4.7K

2

2 1

(60130B4720ZT)

LVDS_DDCCLK LVDS_DDCDATA

34A6 34A6

INV_PWM_3_R

EC_BKLTEN_R

C3007

CSC0402_DY

2 1

24A6 24A6

IN IN

51B2 51B2

BI BI

2.2K_5%_2

LVDS_TXDL0_DN LVDS_TXDL0_DP

LVDS_TXDL1_DN LVDS_TXDL1_DP

LVDS_TXDL2_DN LVDS_TXDL2_DP

LVDS_TXCL_DN LVDS_TXCL_DP

BI BI

MIC_IN_CLK MIC_IN_DATA

2.2K_5%_2

R3002

21

USB_CAM_DN USB_CAM_DP

R3010

100_5%_2

R3005

21

MIC_IN_DATA_R

21

C3004

2 1

0.1UF_16V_2

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

CN3000

1

2

3

4

5

6

7

8

9

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

ACES_50203_03001_001_30P

G1

G

G2

G

57A6 57A6

VGA_LVDS_TXDL0_DN

IN

VGA_LVDS_TXDL0_DP

IN

VGA_LVDS_TXDL1_DN

IN

VGA_LVDS_TXDL1_DP

IN

VGA_LVDS_TXDL2_DN

IN

VGA_LVDS_TXDL2_DP

IN

VGA_LVDS_TXCL_DN

IN

VGA_LVDS_TXCL_DP

IN

R3027 R3028

R3029 R3030

R3031 R3032

R3033 R3034

21

0_5%_1

21

0_5%_1

21

0_5%_1

21

0_5%_1

21

0_5%_1

21

0_5%_1

21

0_5%_1

21

0_5%_1

LVDS_TXDL0_DN LVDS_TXDL0_DP

LVDS_TXDL1_DN LVDS_TXDL1_DP

LVDS_TXDL2_DN LVDS_TXDL2_DP

LVDS_TXCL_DN LVDS_TXCL_DP

OUT OUT

34C3 34C3

34B3 34B3

PVBAT

C3009

2 1

C3010

4.7UF_25V_5

21-OCT-2002XXX

2 1

P3V3S

C3011

2 1

0.1UF_16V_2

0.1UF_25V_3

MODEL,PROJECT,FUNCTION

CS

A3

Block Diagram

X011310xxxxx-0-0

6934

REFERENCE 3050~3099(CRT)

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

P5V0S

D3050

IN IN

VGA_CRTR PCH_CRTR

VGA_CRTG PCH_CRTG

VGA_CRTB PCH_CRTB

56D3 56E2

50B7

56D3 56E2

50B7

56D3 56E2

50B7

R3064

R3065

R3066 R3067

R3068 R3069

0_5%_1

21

0_5%_1

21

0_5%_1

21 21

0_5%_1 0_5%_1

21

0_5%_1

21

CRTR

CRTG

CRTB

L3052

L3051

L3050

21

120NH,5%

CRTR_L

CRTG_L

CRTB_L

OUT

35A7

35C3

SBR3U40P1

P5V0S_CRT1

21 21

FUSE3050

SMD1812P110TF

P5V0S_CRT2

R3054

2 1

150_1%_2

R3055

2 1

150_1%_2

R3056

2 1

150_1%_2

C3050

2 1

15PF_50V_2

C3051

2 1

15PF_50V_2

C3052

2 1

35A3

15PF_50V_2

BI

GM:2.2K PM:2K

(60130B2020ZT)

CRT_DDCDATA_OUT

CRT_DDCCLK_OUT

R3050 R3051

2.2K_5%_2

P5V0S_CRTVDD

2.2K_5%_2

2 1

R3053

100_5%_2

R3052

100_5%_2

35D4 35A7 35D4 35D4 35A7

21

35A3

IN

35A3

IN

21

IN

35A7

IN IN

CRT_DDCDATA_R_OUT CRT_HSYNC_R_OUT CRT_VSYNC_R_OUT CRT_DDCCLK_R_OUT

CRTR_L CRTG_L CRTB_L

TP3050

TP3051

1

TP24

CN3051

1

2

3

4

5

6

7

8

9

10

11

12 13 14 15

G1

12

G2

13 14 15

SUYIN_070546HR015M25KZR_15P

G1 G2

C3054C3053

0.1UF_16V_2_DY

2 1

0.1UF_16V_2_DY

2 1

RESERVE CAP FOR EMI

R3070

2 1

P3V3S

R3061R3060

2.2K_5%_2

2 1

0.22UF_6.3V_2

C3056

P5V0S

2 1

GM:2.2K PM:10K

(60130B1030ZT)

2.2K_5%_2

35A4

OUT

CRT_VSYNC

CRT_HSYNC

CRT_DDCDATA

CRT_DDCCLK

R3071

R3072

R3073

R3074

R3075

R3076

R3077

P3V3S

0.22UF_6.3V_2

C3055

U3050

1 16

VCC-SYNC SYNC_OUT2

2

35C3

35D4

35C3

35D4

P5V0S_CRTVDD

2 1

C3057

35C3 35D4

CRTR_L

IN

CRTG_L

IN

CRTB_L

IN

VCC-VIDEO

3

VIDEO_1

4

VIDEO_2

5

VIDEO_3

6

GND

7

VCC-DCC

TI_TPD7S019_15DBQR_SSOP_16P

SYNC_IN2

SYNC_OUT1

SYNC_IN1 DCC_OUT2

DDC_IN2 DDC_IN1

DDC_OUT1BYP

CRT_VSYNC_OUT

15

CRT_VSYNC CRT_HSYNC_OUT

14 13

CRT_HSYNC

12 11

CRT_DDCDATA CRT_DDCCLK

10 98

IN IN IN

IN

0.22UF_6.3V_2

2 1

35B4

35A4 35A4

R3062

R3063

21

30_5%_2

21

30_5%_2

CRT_VSYNC_R_OUT

CRT_HSYNC_R_OUT

CRT_DDCDATA_OUT

CRT_DDCCLK_OUT

OUT OUT OUT

OUT

35C3

35C5

0_5%_1

21

0_5%_1

21

0_5%_1

21

0_5%_1

VGA_CRT_DDCDATA

21

0_5%_1

PCH_CRT_DDCDATA

21

0_5%_1

21

VGA_CRT_DDCCLK

0_5%_1

21

PCH_CRT_DDCCLK

VGA_CRT_VSYNC

PCH_CRT_VSYNC

VGA_CRT_HSYNC

PCH_CRT_HSYNC

56F7 56D3

IN

50A6

IN

56F7 56D3

IN

50A6

IN

56A3

IN

50A6

IN

56A3

IN

50A6

IN

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6935

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 3150~3199(HDMI)

PLACE CLOSE TO CONNECTOR

R3174

R3175

R3176

R3177

S

21

P3V3S

G

S

0_5%_1

D

DS

GM:680_5% PM:499_5%

(6013A0076801)

HDMI_DDCDATA

HDMI_DDCCLK

G

Q3150

G

SSM3K17FU

DS

R3164

680_5%_2

R3163

680_5%_2

R3162

680_5%_2

R3161

680_5%_2

R3160

680_5%_2

R3159

680_5%_2

R3158

680_5%_2

R3157

680_5%_2

HDMI_CN_DDCDATAHDMI_DDCDATA

HDMI_CN_DDCCLK

D

21

Q3152

BI BI

P3V3S

3

DS

SSM3K7002BFU

36C8

P5V0AL

2

R3152

C3151

22PF_50V_2_DY

2 1

13

NC

BAT54_30V_0.2A

2 1

TP3151

R3154

1K_5%_2

D3150

R3153

2.2K_5%_2

2 1

21

(60130B2020ZT)

TP24

1

GM: 2.2K PM:2K

CN3150

1

TMDS Data2+

2

TMDS Data2 Shield

3

TMDS Data2-

4

TMDS Data1+

5

TMDS Data1 Shield

6

TMDS Data1-

7

TMDS Data0+

8

TMDS Data0 Shield

9

TMDS Data0-

10

TMDS Clock+

11

TMDS Clock Shield

12

TMDS Clock-

13

CEC

14

Reserved

15

DDC Clock

16

DDC Data

17

DDC/CEC GND

18

+5V Power

19

Hot Plug Detect

SYN_100042GR019M26DZL_19P

G1

G2

G3

G4

36C3

R3165

37C3

37D3

36A7 36A7

36A7 36B7

36B7 36B7

36A2 36A2

IN IN

HDMI_TX2_C_DP HDMI_TX2_C_DN

HDMI_TX1_C_DP HDMI_TX1_C_DN

HDMI_TX0_C_DP HDMI_TX0_C_DN

HDMI_TXC_C_DP HDMI_TXC_C_DN

P5V0AL

40MIL

100PF_50V_2

2 1

L3151

34

HDMI_TX2_R_DP

21

HDMI_TX2_R_DN

WCM_2012_900T

L3152

34

HDMI_TX1_R_DP

21

HDMI_TX1_R_DN

WCM_2012_900T

L3153

34

HDMI_TX0_R_DP

21

HDMI_TX0_R_DN

WCM_2012_900T

L3154

34

HDMI_TXC_R_DP HDMI_TXC_R_DN

21

WCM_2012_900T

D3155

2 1 21

SBR3U40P1

C3150

P5V0AL_HDMI_VDD1

37C1

CLOSE TO CONNECTOR

37D6

36C6 37D3

37C3

36C6

FUSE3150

SMD1812P110TF

OUT

BI BI

BI

HPDET_IC

2.2K_5%_2

HDMI_CEC

HDMI_CN_DDCCLK HDMI_CN_DDCDATA

P5V0AL_HDMI_VDD2

R3150

470K_5%_2

2 1

100K_5%_2

1

G

2 1

P3V3S

2

50B3

56C5

56F3

IN

56F3

IN

56F3

IN

56F3

IN

56F3

IN

56F3

IN

56F3

IN

56F3

IN

50B3

IN OUT

50B3

IN

50B3

IN

50B3

IN

50B3

IN

50B3

IN

50B3

IN

50B3

IN

PCH_HPDET

OUT

VGA_HPDET

OUT

VGA_HDMI_TX2_DN VGA_HDMI_TX2_DP VGA_HDMI_TX1_DN VGA_HDMI_TX1_DP VGA_HDMI_TX0_DN VGA_HDMI_TX0_DP VGA_HDMI_TXC_DN VGA_HDMI_TXC_DP

PCH_HDMI_TX2_DN PCH_HDMI_TX2_DP PCH_HDMI_TX1_DN PCH_HDMI_TX1_DP PCH_HDMI_TX0_DN PCH_HDMI_TX0_DP PCH_HDMI_TXC_DN PCH_HDMI_TXC_DP

R3180

R3181

C3152

C3154

C3156

C3158

C3160

C3162

C3164

C3166

21

0_5%_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

HPDET

TC7SZ08FU

C3153

C3155

C3157

C3159

U3150

4

C3161

C3163

C3165

C3167

5

+-

1

2

3

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

HDMI_HPD_EC

PLT_RST#

IN IN

HDMI_TX2_C_DN HDMI_TX2_C_DP HDMI_TX1_C_DN HDMI_TX1_C_DP HDMI_TX0_C_DN HDMI_TX0_C_DP HDMI_TXC_C_DN HDMI_TXC_C_DP

37B1 21D6

51A7 41C7 31C6

36D5

36A7

36D5

36A7

OUT OUT OUT OUT OUT OUT OUT

21-OCT-2002XXX

36D5

36A7

36D5

36A7

36D5

36B7

36D5

36A7

36C5

36B7

36C5

36B7

MODEL,PROJECT,FUNCTION

CS

A3

Block Diagram

X011310xxxxx-0-0

6936

50B3

56B3

BI BI

PCH_HDMI_DDCDATA

PCH_HDMI_DDCCLK

VGA_HDMI_DDCDATA

VGA_HDMI_DDCCLK

P3V3S

GM: 2.2K PM:10K

(60130B1030ZT)

2.2K_5%_2

36D6

BI BI

36D6

HDMI_DDCCLK

BI BI

36A2

36C5

36A2 36C5

36A2 36D5

36A2

36D5

36A2 36D5

36D5

36A2

36A2 36D5

2 1

IN

R3179R3178

2.2K_5%_2

Q3151

2 1

SSM3K17FU

HDMI_TXC_C_DP

HDMI_TXC_C_DN

HDMI_TX0_C_DN

HDMI_TX0_C_DP

HDMI_TX1_C_DN

HDMI_TX1_C_DP

HDMI_TX2_C_DN

HDMI_TX2_C_DP

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

P3V3AL

132

P3V3AL

NC

R3204

27K_5%_2

2 1

2

3

Q3203

DS

SSM3K7002BFU

D3200

BAT54_30V_0.2A

HDMI_CEC

1

G

22K_5%_2

100K_5%_2

2 1

4.7K_5%_2

R3205

R3206

R3213

BI

CEC_OUT

21

2 1

Q3201

G

SSM3K17FU

G

DS

HDMI_CN_DDCCLK

D

BI

4.02K_1%_2

HDMI_DDCCLK_CEC

R3201

2 1

S

P3V3AL

OUT

4.02K_1%_2

BI

HDMI_DDCDATA_CEC

37B3 37B6

R3200

2 1

G

Q3200

SSM3K17FU

G

S

HDMI_CN_DDCDATA

D

DS

P3V3AL

R3210

4.7K_5%_2

2 1

5A7 21D3 21D3

56D8 56C8

21D2

37A8

37A6

37D8 37C6

EC_SMB2_CLK EC_SMB2_DATA

BI

CEC_XOUT

OUT

CEC_XIN

IN

CEC_IN

IN

CEC_OUT

OUT

U3202

1 20

P3_5-SSCK-SCL-CMP1_2 P3_4-SCS#-SDA-CMP1_1

2

P3_7-CNTR0#-SSO-TXD1

3

RESET#

4

XOUT-P4_7

5

VSS-AVSS

6

XIN-P4_6

7

VCC-AVCC

8

MODE

9

P4_5-INT0#-RXD1

10 11

P1_7-CNTR00-INT10# P1_6-CLK0-SSI01

RENESAS_R5F211B4D61SP_LSSOP_20P

P3_3-TCIN-INT3#-SSI00-CMP1_0

P1_0-KI0#-AN8-CMP0_0 P1_1-KI1#-AN9-CMP0_1

P1_2-KI2#-AN10-CMP0_2

P1_3-KI3#-AN11-TZOUT

P1_5-RXD0-CNTR01-INT11#

P4_2-VREF

P1_4-TXD0

19

HDMI_DDCDATA_CEC

18

HDMI_DDCCLK_CEC

17 16 15 14 13 12

BI

36C6 36C3 37B3

BI

36C6 36C3

P3V3AL

C3200

R3215

21

2 1

0.1UF_16V_2

0_5%_2_DY

2 1

R3208

2 1

4.7K_5%_2

37C5 37D5

R3227

21

33_5%_2

PHP_74LVC1G17_SOT753_5P

U3200

4

5

+

-

3

1

NC

2

HDMI_HPD_EC

HPDET_IC

OUT

36C4

IN

36B2

21D6

R3209

5A7

BI

21D2

BI BI

2

P3V3AL

1

5

U3203

37B6 36C3

CEC_IN

IN

R3214

4

21

68_5%_2

74LVC1G14GV

NC

+

-

3

P3V3AL

C3202

2 1

C3205

0.1UF_16V_2

2 1

1UF_6.3V_2

R3202

2 1

RSC_0402_DY

P3V3AL

R3211

47K_5%_2

37B6 37B6

CEC_XOUT CEC_XIN

2 1

R3212

2 1

47K_5%_2

INOUT

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6937

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 4100~4299(DDR)

CHA

LAYOUT NOTE: PLACE CAPS NEAR SO-DIMM0 POWER PIN

1UF_6.3V_2

2 1

P3V3S

C4114 C4115

IN

2 1

0.1UF_16V_2

2 1

2.2UF_6.3V_3

PM_EXTTS#1_R

C4102C4101 C4103 C4104

1UF_6.3V_21UF_6.3V_21UF_6.3V_2

2 1

P0V75M_VREF

ALL VREF TRACES SHOULD HAVE 10 MIL TRACE WIDTH

C4150 C4116

0.1UF_16V_2

2 1

P3V3S

R4104

10K_5%_2

2 1

C4105 C4107C4106

2 1

C4110 C4108C4109

10UF_6.3V_3

2 1

2.2UF_6.3V_3

10UF_6.3V_310UF_6.3V_310UF_6.3V_3

2 1

10UF_6.3V_310UF_6.3V_3

OUT OUT

2 1

38B5 39C3 39C3 41A5

P0V75M_VREF

C4117 C4118

0.1UF_16V_2

2 1

PM_EXTTS#1_R DDR3_DRAMRST#

1

2 3 8 9

CN4100

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VDDSPD

NC1 NC2 NCTEST

EVENT# RESET#

VREF_DQ VREF_CA

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15

BELLW_80001_1021_204P

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52

VTT1 VTT2

44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

1.5A

20325 204

G1 G2

P0V75S

75 76 81 82 87 88 93 94

99 100 105 106 111 112 117 118 123 124

199

77 122 125

198

30

126

13

14

19

20

26

31

32

37

38

43

PLACE THESE CAPS CLOSE TO VTT1 AND VTT2

BI

43A8 43A8 43A8 43C5 43C5 43D4 43D4 43D4 43D4 43D4 43D4 43A8 43A8 43A8 38A6 38A6 20A7 39C8 20A7 39C8

43C5 43C5

43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5 43B5

M_A_A<15..0>

M_A_BS0

IN

M_A_BS1

IN

M_A_BS2

IN

M_CS#0

IN

M_CS#1

IN

M_CLK_DDR0_DP

IN

M_CLK_DDR0_DN

IN

M_CLK_DDR1_DP

IN

M_CLK_DDR1_DN

IN

M_CKE0

IN

M_CKE1

IN

M_A_CAS#

IN

M_A_RAS#

IN

M_A_WE#

IN OUT OUT

IN

M_A_A<0>

0

M_A_A<1>

1

M_A_A<2>

2

M_A_A<3>

3

M_A_A<4>

4

M_A_A<5>

5

M_A_A<6>

6

M_A_A<7>

7

M_A_A<8>

8

M_A_A<9>

9

M_A_A<10>

10

M_A_A<11>

11

M_A_A<12>

12

M_A_A<13>

13

M_A_A<14>

14

M_A_A<15>

15

SA0_DIM0

SA1_DIM0 PCH_3S_SMCLK PCH_3S_SMDATA

M_ODT0

M_ODT1

M_A_DQS0_DP M_A_DQS1_DP M_A_DQS2_DP M_A_DQS3_DP M_A_DQS4_DP M_A_DQS5_DP M_A_DQS6_DP M_A_DQS7_DP M_A_DQS0_DN M_A_DQS1_DN M_A_DQS2_DN M_A_DQS3_DN M_A_DQS4_DN M_A_DQS5_DN M_A_DQS6_DN M_A_DQS7_DN

98 97 96 95 92 91 90 86 89 85

107

84 83

119

80 78

109 108

79 114 121 101 103 102 104

73

74 115 110 113 197 201 202 200

116 120

11

28

46

63 136 153 170 187

12

29

47

64 137 154 171 188

10

27

45

62 135 152 169 186

CN4100

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15

BA0 BA1 BA2 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA

ODT0 ODT1

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

BELLW_80001_1021_204P

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

M_A_DQ<0>

5

M_A_DQ<1>

7

M_A_DQ<2>

15

M_A_DQ<3>

17

M_A_DQ<4>

4

M_A_DQ<5>

6

M_A_DQ<6>

16

M_A_DQ<7>

18

M_A_DQ<8>

21

M_A_DQ<9>

23

M_A_DQ<10>

33

M_A_DQ<11>

35

M_A_DQ<12>

22

M_A_DQ<13>

24

M_A_DQ<14>

34

M_A_DQ<15>

36

M_A_DQ<16>

39

M_A_DQ<17>

41

M_A_DQ<18>

51 53

M_A_DQ<19>

40

M_A_DQ<20>

42

M_A_DQ<21>

50

M_A_DQ<22>

52

M_A_DQ<23>

57

M_A_DQ<24>

59

M_A_DQ<25>

67

M_A_DQ<26>

69

M_A_DQ<27>

56

M_A_DQ<28>

58

M_A_DQ<29>

68

M_A_DQ<30>

70

M_A_DQ<31>

129

M_A_DQ<32>

131

M_A_DQ<33>

141

M_A_DQ<34>

143

M_A_DQ<35>

130

M_A_DQ<36>

132

M_A_DQ<37>

140

M_A_DQ<38>

142

M_A_DQ<39>

147

M_A_DQ<40>

149

M_A_DQ<41>

157

M_A_DQ<42>

159

M_A_DQ<43>

146

M_A_DQ<44>

148

M_A_DQ<45>

158

M_A_DQ<46>

160

M_A_DQ<47>

163

M_A_DQ<48>

165

M_A_DQ<49>

175

M_A_DQ<50>

177

M_A_DQ<51>

164

M_A_DQ<52>

166

M_A_DQ<53>

174

M_A_DQ<54>

176

M_A_DQ<55>

181

M_A_DQ<56>

183

M_A_DQ<57>

191

M_A_DQ<58>

193

M_A_DQ<59>

180

M_A_DQ<60>

182

M_A_DQ<61> M_A_DQ<62>

192

M_A_DQ<63>

194

M_A_DQ<63..0>

0 1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

P1V5

C4100

+

330UF_2.5V_DY

2 1

43D8

BI

NOTE:PLACE C4100 ON COMMON PATH FOR BOTH DIMM'S

2.2UF_6.3V_3

38C3 39C3

43A4

48A8 48A8

NOTE: IF SA0_DIM0=1 , SA1_DIM0=0

SO-DIMMA SPD ADDRESS IS 0XA2 SO-DIMMA TS ADDRESS IS 0X32

10K_5%_2_DY

R4100

P3V3S

R4101

10K_5%_2_DY

SA0_DIM0

SA1_DIM0

38C8

IN

38C8

IN

C4119 C4120 C4121 C4122

1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2

2 1

IF SA0_DIM0=0 , SA1_DIM0=0 SO-DIMMA SPD ADDRESS IS 0XA0 SO-DIMMA TS ADDRESS IS 0X30

10K_5%_2

R4102

R4103

10K_5%_2

2 1 2 1

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6938

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 4100~4299(DDR)

CHB

P1V5

C4124

1UF_6.3V_2

2 1

P3V3S

C4138

2 1

LAYOUT NOTE: PLACE CAPS NEAR SO-DIMM0 POWER PIN

C4127C4126C4125

1UF_6.3V_2 1UF_6.3V_2

2 1

1UF_6.3V_2

2 1

C4137

0.1UF_16V_2

2 1

P0V75M_VREF

ALL VREF TRACES SHOULD HAVE 10 MIL TRACE WIDTH

C4139C4151

2.2UF_6.3V_3

2 1

0.1UF_16V_2

2 1

C4128

10UF_6.3V_3

2 12 1

C4133

10UF_6.3V_3

2.2UF_6.3V_3

C4129

10UF_6.3V_3

2 12 1

C4132

10UF_6.3V_3

38C3 38B5 41A5 38C3

C4130

10UF_6.3V_3

2 12 1

C4131

10UF_6.3V_3

OUT OUT

P0V75M_VREF

C4141C4140

0.1UF_16V_2

2 1

PM_EXTTS#1_R DDR3_DRAMRST#

CN4101

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

BELLW_80001_5021_204P

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52

VTT1 VTT2

44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

203 204

G1

G2

1.5A

P0V75S

BI

43A4 43A4 43A4 43C1 43C1 43D1 43D1 43D1 43D1 43D1 43D1 43A4 43A4

43C1 43C1

43B1 43B1 43B1 43B1 43B1 43B1 43B1 43B1 43B1 43B1 43B1 43B1 43B1 43B1 43B1 43B1

M_B_A<15..0>

M_B_BS0

IN

M_B_BS1

IN

M_B_BS2

IN

M_CS#2

IN

M_CS#3

IN

M_CLK_DDR2_DP

IN

M_CLK_DDR2_DN

IN

M_CLK_DDR3_DP

IN

M_CLK_DDR3_DN

IN

M_CKE2

IN

M_CKE3

IN

M_B_CAS#

IN

M_B_RAS#

IN

M_B_WE#

IN

IN IN

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

M_B_A<0>

0

M_B_A<1>

1

M_B_A<2>

2

M_B_A<3>

3

M_B_A<4>

4

M_B_A<5>

5

M_B_A<6>

6

M_B_A<7>

7

M_B_A<8>

8

M_B_A<9>

9

M_B_A<10>

10

M_B_A<11>

11

M_B_A<12>

12

M_B_A<13>

13

M_B_A<14>

14

M_B_A<15>

15

PCH_3S_SMCLK PCH_3S_SMDATA

M_ODT2 M_ODT3

M_B_DQS0_DP M_B_DQS1_DP M_B_DQS2_DP M_B_DQS3_DP M_B_DQS4_DP M_B_DQS5_DP M_B_DQS6_DP M_B_DQS7_DP M_B_DQS0_DN M_B_DQS1_DN M_B_DQS2_DN M_B_DQS3_DN M_B_DQS4_DN M_B_DQS5_DN M_B_DQS6_DN M_B_DQS7_DN

CN4101

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10_AP

84

A11

83

A12

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS#0

27

DQS#1

45

DQS#2

62

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

BELLW_80001_5021_204P

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

M_B_DQ<63..0>

M_B_DQ<0>

5

DQ0

M_B_DQ<1>

7

DQ1

M_B_DQ<2>

15

DQ2

M_B_DQ<3>

17

DQ3

M_B_DQ<4>

4

DQ4

M_B_DQ<5>

6

DQ5

M_B_DQ<6>

16

DQ6

M_B_DQ<7>

18

DQ7

M_B_DQ<8>

21

DQ8

M_B_DQ<9>

23

DQ9

M_B_DQ<10>

33

M_B_DQ<11>

35

M_B_DQ<12>

22

M_B_DQ<13>

24

M_B_DQ<14>

34

M_B_DQ<15>

36

M_B_DQ<16>

39

M_B_DQ<17>

41

M_B_DQ<18>

51

M_B_DQ<19>

53

M_B_DQ<20>

40

M_B_DQ<21>

42

M_B_DQ<22>

50

M_B_DQ<23>

52

M_B_DQ<24>

57

M_B_DQ<25>

59

M_B_DQ<26>

67

M_B_DQ<27>

69

M_B_DQ<28>

56

M_B_DQ<29>

58

M_B_DQ<30>

68

M_B_DQ<31>

70

M_B_DQ<32>

129

M_B_DQ<33>

131

M_B_DQ<34>

141

M_B_DQ<35>

143

M_B_DQ<36>

130

M_B_DQ<37>

132

M_B_DQ<38>

140

M_B_DQ<39>

142

M_B_DQ<40>

147

M_B_DQ<41>

149

M_B_DQ<42>

157

M_B_DQ<43>

159

M_B_DQ<44>

146

M_B_DQ<45>

148

M_B_DQ<46>

158

M_B_DQ<47>

160

M_B_DQ<48>

163

M_B_DQ<49>

165

M_B_DQ<50>

175

M_B_DQ<51>

177

M_B_DQ<52>

164

M_B_DQ<53>

166

M_B_DQ<54>

174

M_B_DQ<55>

176

M_B_DQ<56>

181

M_B_DQ<57>

183

M_B_DQ<58>

191

M_B_DQ<59>

193

M_B_DQ<60>

180

M_B_DQ<61>

182

M_B_DQ<62>

192

M_B_DQ<63>

194

0 1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

BI

43D4

2.2UF_6.3V_3

43A1

43A4 39A7 39A6

OUT OUT

SA0_DIM1 SA1_DIM1

48A8

38C8 20A7 48A8

38C8 20A7

PLACE THESE CAPS CLOSE TO VTT1 AND VTT2

NOTE: SO-DIMMB SPD ADDRESS IS 0XA4 SO-DIMMB TS ADDRESS IS 0X34

P3V3S

C4145C4144C4143C4142

1UF_6.3V_2

R4106R4105

2 1

1UF_6.3V_2 1UF_6.3V_2

2 1

1UF_6.3V_2

2 1

10K_5%_210K_5%_2_DY

2 12 1

IN

R4107

10K_5%_2

SA1_DIM1SA0_DIM1

R4108

10K_5%_2_DY

39C8 39C8

IN

2 1 2 1

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6939

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 4300~4349(FAN) REFERENCE 4411~4449(THERMAL )

P5V0S

POWERPAD_2_0610

KC_FBM_11_160808_101_T_2P_DY

PAD4300

1 2

L4300

P5V0S_FAN

21

C4307

P3V3S

2 1

R4300

10K_5%_2

2 1

21B6

IN

FAN_TACH1

1

TP4300

TP30

C4301

2 1

22UF_6.3V_5_DY

C4302

4.7UF_6.3V_3

2 1

0.1UF_16V_2

CN4300

1

2

3

4

ACES_50273_0047N_001_4P

G1

G

G2

G

P3V3S

C4300

2 1

220pF_50V_2

C4305

2 1

CSC0402_DY

R4306

10K_5%_2

21B6

IN

FAN1_PWM

1

TP30

TP4301

2 1

C4306

2 1

CSC0402_DY

FAN CN

P5V0AL

56D6

40B1 15D8

OUT

100K_5%_2

THRM_SHUTDWN#

P5V0AL

C4441

2 1

0.1UF_16V_2

1

2

3

4

U4441

VCC

TMSNS1

GND

RHYST1

TMSNS2

OT1

RHYST2

OT2

ENE_P2809A2_SOT23_8P

8

R4443

7

13.3K_1%_2

6

5

R4442

R4444

21

R4441

13.3K_1%_2

2 1

P5V0AL

100K_1%_NTC 26.7K_1%_2

21

R4447 R4446

2 1 2 1

100K_1%_NTC 26.7K_1%_2

IN

PM_THRMTRIP#

41D5 52C1

11A4 11C7 49B7

IN

330_5%_2

PVCORE_PG

R4413

THRM_SHUTDWN#

R4414

2M_5%_2

2 1E C

Q4412

21

MMBT4401

C E

B

2 1

C4412

CSC0402_DY

SSM3K7002BFU

1

3

Q4411R4445

DS

G

2

OUT

56D6

15D8 40A8

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6940

A3

21-OCT-2002XXX

REFERENCE 4500~4699(CPU)

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

CN4500

P1V8S

C26

AN34

1

AL33

1

AN33

AL32

AN32

AM34

AP33

V8

AR33

2 1

PROC_SELECT#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

LOTES_ACA_ZIF_069_P01_989P

MISC

CLOCKS

DPLL_REF_CLK#

MISCDDR3

JTAG & BPM

PWR MANAGEMENT THERMAL

R4504

BI

IN

H_SNB_IVB#

TP4500

TP4501

H_PECI

CPU_PROCHOT#_R

21

PM_THRMTRIP#

LOW IN C6/C7

H_PM_SYNC

H_CPUPWRGD

TP24

41D8

OUT

21

R4502R4500

2.2K_5%_2_DY

NV_CLE

OUT

52B2

P1V05S

21A6 52C2

40A4 52C1

OUT

56_5%_2

OUT

R4503

62_5%_2

C4500

CSC0402_DY

2 1 2 1

CPU_PROCHOT#

11B7 21C3

OUT

2.2K_5%_2

2 1

41D5

OUT

PLACE CLOSE TO CPT AND NVRAM CONNECTOR

H_SNB_IVB#

R4501

1K_5%_2

PROCESS STRAP SETTING

SANDY BRIDGE ONLY

SANDY BRIDGE/IVY BRIDGE

STUFF R4502

STUFF R4500/R4501

P1V5S

DMI&FDI TERMINATIONVOLTAGE

NV_CLE (DEFAULT)

SET TOVSS WHEN LOW SET TOVCC WHEN HIGH

49B7

R4505

200_5%_2

2 1

IN

PM_DRAM_PWRGD

R4506

49A3

52C2

PM_DRAM_PWRGD_R

21

130_1%_2

51A7

31C6 36B2

IN

PLT_RST#

R4507

21

1.5K_5%_2

750_1%_2

R4508

2 1

10K_5%_2

R4509

DPLL_REF_CLK

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

BCLK#

PRDY# PREQ#

TRST#

BCLK

DBR#

TCK TMS

TDI TDO

A28

CLK_DMI_PCH_DP

A27

CLK_DMI_PCH_DN

A16 A15

CPU_DRAMRST#

R8

SM_RCOMP0

AK1 A5

SM_RCOMP1 SM_RCOMP2

A4

AP29 AP27

AR26 AR27 AP30

AR28 AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

TP30 TP30

TP30 TP30 TP30

TP30 TP30

TP30

48B3

IN

48B3

IN

TP4502 TP4503

TP4504 TP4505 TP4506

TP4507 TP4508

TP4509

IN IN IN

21

1K_5%_2

21

1K_5%_2

OUT

H_PRDY# H_PREQ#

H_TCK H_TMS H_TRST#

H_TDI H_TDO

SYS_RESET#

H_TMS H_TDI H_PREQ#

41A5

21

140_1%_2

21

25.5_1%_2

21

200_1%_2

R4516 R4517 R1418

R4510 R4511

R4512 R4513 R4514

1 1

1 1 1

1 1

1

CAD NOTE: ALL DDR_COMP SIGNALS SHOULD BE ROUTED SUCH TAHT

- MAX LENGTH = 500 MILS

- TRACE WIDTH = 15MILS AND

- MB TRACE IMPEDANCE < 68 MOHMS (WORST CASE RESISTANCE)

41C1

P1V05S

OUT

IN IN

IN

OUT

41B2 41B2 41B2

41B2

49B8

41B2

21 21 21

P1V05S

51_5%_2 51_5%_2 51_5%_2_DY

S3 CIRCUIT: DRAM_RST# TO MEMORY SHOULD BE HIGH DURING S3

41C1

H_TCK

IN

H_TRST#

IN

R4519 R4520

21

51_5%_2

21

51_5%_2

P1V5P3V3A

R4602

1K_5%_2

R4603

3

DS

G

2

R4604

1K_5%_2

DDR3_DRAMRST#

21

CPU_DRAMRST#

OUT

IN

38C3

41D2

39C3

4.99K_1%_2

2 1 2 1

45D6 45D8

48D3

OUT

DRAMRST_CNTRL_PCH

IN

DRAMRST_CNTRL

R4600

0_5%_2

0.047UF_16V_2

R4601

1K_5%_2

Q4600

21

1

SSM3K7002BFU

C4620

2 1 2 1

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6941

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 4500~4699(CPU)

P1V05S

R4522

CN4500

49D6

OUT

49D6

OUT

49D6

OUT

49C6

OUT

49C6

OUT

49C6

OUT

49C3

IN

49C3

IN

P1V05S

R4521

24.9_1%_2

2 1

49C3

IN

49C3

IN

49C3

IN

P1V0S_VCCP_EDP_COMPIO

49C6 49C6

49D6 49D6 49D6 49D6

49D3 49D3 49D3 49D3 49D3 49D3 49D3 49D3

49D3 49D3 49D3 49D3 49C3 49C3 49C3 49C3

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

OUT OUT

OUT OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

DMI_TX0_DN DMI_TX1_DN DMI_TX2_DN DMI_TX3_DN

DMI_TX0_DP DMI_TX1_DP DMI_TX2_DP DMI_TX3_DP

DMI_RX0_DN DMI_RX1_DN DMI_RX2_DN DMI_RX3_DN

DMI_RX0_DP DMI_RX1_DP DMI_RX2_DP DMI_RX3_DP

FDI_TX0_DN FDI_TX1_DN FDI_TX2_DN FDI_TX3_DN FDI_TX4_DN FDI_TX5_DN FDI_TX6_DN FDI_TX7_DN

FDI_TX0_DP FDI_TX1_DP FDI_TX2_DP FDI_TX3_DP FDI_TX4_DP FDI_TX5_DP FDI_TX6_DP FDI_TX7_DP

CAD NOTE: DP_COMPIO AND ICOMPO SIGNALS

B27 B25 A25 B24

B28 B26 A24 B23

G21 E22 F21 D21

G22 D22 F20 C21

A21 H19 E19 F18 B21 C20 D18 E17

A22 G19 E20 G18 B20 C19 D19 F17

J18 J17

H20

J19 H17

A18 A17 B16

DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3]

DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3]

DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3]

DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]

FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3]

FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3]

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI0_LSYNC FDI1_LSYNC

eDP_COMPIO eDP_ICOMPO eDP_HPD

DMI

Intel(R) FDI

PCI EXPRESS* - GRAPHICS

SHOULD BE SHORTED NEAR BALLS AND ROUTED WITH

- TYPICAL IMPEDANCE < 25 MOHMS

C15 D15

eDP_AUX eDP_AUX#

eDP

C17 F16 C16 G15

C18 E16 D16 F15

eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3]

eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3]

LOTES_ACA_ZIF_069_P01_989P

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

P1V0S_VCCP_PEG_ICOMPI

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_C_RX15_DN PEG_C_RX14_DN PEG_C_RX13_DN PEG_C_RX12_DN PEG_C_RX11_DN PEG_C_RX10_DN PEG_C_RX9_DN PEG_C_RX8_DN PEG_C_RX7_DN PEG_C_RX6_DN PEG_C_RX5_DN PEG_C_RX4_DN PEG_C_RX3_DN PEG_C_RX2_DN PEG_C_RX1_DN PEG_C_RX0_DN

PEG_C_RX15_DP PEG_C_RX14_DP PEG_C_RX13_DP PEG_C_RX12_DP PEG_C_RX11_DP PEG_C_RX10_DP PEG_C_RX9_DP PEG_C_RX8_DP PEG_C_RX7_DP PEG_C_RX6_DP PEG_C_RX5_DP PEG_C_RX4_DP PEG_C_RX3_DP PEG_C_RX2_DP PEG_C_RX1_DP PEG_C_RX0_DP

PEG_TX15_DN PEG_TX14_DN PEG_TX13_DN PEG_TX12_DN PEG_TX11_DN PEG_TX10_DN PEG_TX9_DN PEG_TX8_DN PEG_TX7_DN PEG_TX6_DN PEG_TX5_DN PEG_TX4_DN PEG_TX3_DN PEG_TX2_DN PEG_TX1_DN PEG_TX0_DN

PEG_TX15_DP PEG_TX14_DP PEG_TX13_DP PEG_TX12_DP PEG_TX11_DP PEG_TX10_DP PEG_TX9_DP PEG_TX8_DP PEG_TX7_DP PEG_TX6_DP PEG_TX5_DP PEG_TX4_DP PEG_TX3_DP PEG_TX2_DP PEG_TX1_DP PEG_TX0_DP

24.9_1%_2

2 1

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

57B1 57B1 57B1 57B1 57B1 57C1 57C1 57C1 57C1 57C1 57C1 57D1 57D1 57D1 57D1 57D1

57B1 57B1 57B1 57B1 57B1 57C1 57C1 57C1 57C1 57C1 57D1 57D1 57D1 57D1 57D1 57D1

42B3 42B3 42C3 42C3 42C3 42C3 42C3 42C3 42C3 42C3 42C3 42C3 42C3 42D3 42D3 42D3

42A3 42A3 42A3 42A3 42A3 42A3 42B3 42B3 42B3 42B3 42B3 42B3 42B3 42B3 42B3 42B3

CAD NOTE: PEG_ICOMPI AND RCOMPO SIGNALS SHOULD BE SHORTED AND ROUTED WITH

- MAX LENGTH = 500 MILS

- TYPICAL IMPEDANCE = 43 MOHMS

PEG_ICOMPO SIGNALS SHOULD BE ROUTED WITH

- MAX LENGTH = 500 MILS

- TYPICAL IMPEDANCE = 14.5 MOHMS

42B4

IN

42B4

IN

42B4

IN

42B4

IN

42B4

IN

42B4

IN

42B4

IN

42B4

IN

42B4

IN

42B4

IN

42B4

IN

42B4

IN

42B4

IN

42C4

IN

42C4

IN

42C4

IN

42A4

IN

42A4

IN

42A4 57D6

IN

42A4 57D6

IN

42A4 57D6

IN

42A4 57D6

IN

42A4 57C6

IN

42B4 57C6

IN

42B4 57C6

IN

42B4 57C6

IN

42B4

IN

42B4 57B6

IN

42B4 57B6

IN

42B4 57B6

IN

42B4 57B6

IN

42B4

IN

PEG_TX0_DN PEG_C_TX0_DN

PEG_TX1_DN

PEG_TX2_DN

PEG_TX3_DN

PEG_TX4_DN

PEG_TX5_DN

PEG_TX6_DN

PEG_TX7_DN

PEG_TX8_DN

PEG_TX9_DN

PEG_TX10_DN

PEG_TX11_DN

PEG_TX12_DN

PEG_TX13_DN

PEG_TX14_DN

PEG_TX15_DN

PEG_TX0_DP

PEG_TX1_DP

PEG_TX2_DP PEG_C_TX2_DP

PEG_TX3_DP PEG_C_TX3_DP

PEG_TX4_DP PEG_C_TX4_DP

PEG_TX5_DP PEG_C_TX5_DP

PEG_TX6_DP PEG_C_TX6_DP

PEG_TX7_DP PEG_C_TX7_DP

PEG_TX8_DP PEG_C_TX8_DP

PEG_TX9_DP PEG_C_TX9_DP

PEG_TX10_DP

PEG_TX11_DP PEG_C_TX11_DP

PEG_TX12_DP PEG_C_TX12_DP

PEG_TX13_DP PEG_C_TX13_DP

PEG_TX14_DP PEG_C_TX14_DP

PEG_TX15_DP

CLOSE TO CPU

C4580

C4581

C4582

C4583

C4584

C4585

C4586

C4587

C4588

C4589

C4590

C4591

C4592

C4593

C4594

C4595

C4596

C4597

C4598

C4599

C4600

C4601

C4602

C4603

C4604

C4605

C4606

C4607

C4608

C4609

C4610

C4611

21

0.1UF_6.3V_1

PEG_C_TX1_DN

PEG_C_TX2_DN

PEG_C_TX3_DN

PEG_C_TX4_DN

PEG_C_TX5_DN

PEG_C_TX6_DN

PEG_C_TX7_DN

PEG_C_TX8_DN

PEG_C_TX9_DN

PEG_C_TX10_DN

PEG_C_TX11_DN

PEG_C_TX12_DN

PEG_C_TX13_DN

PEG_C_TX14_DN

PEG_C_TX15_DN

PEG_C_TX0_DP

PEG_C_TX1_DP

PEG_C_TX10_DP

PEG_C_TX15_DP

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

57D6

57C6

57B6

57D6

57C6

57B6

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6942

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 4500~4699(CPU)

SOCKET,CPU,989P,TIN,3.0MM,STR,SMD,TR

CN4500

BI

M_B_DQ<63..0>

39D8 39D8 39C8

39C8 39C8 39C8

OUT OUT OUT

M_B_DQ<0>

0

M_B_DQ<1>

1

M_B_DQ<2>

2

M_B_DQ<3>

3

M_B_DQ<4>

4

M_B_DQ<5>

5

M_B_DQ<6>

6

M_B_DQ<7>

7

M_B_DQ<8>

8

M_B_DQ<9>

9

M_B_DQ<10>

10

M_B_DQ<11>

11

M_B_DQ<12>

12

M_B_DQ<13>

13

M_B_DQ<14>

14

M_B_DQ<15>

15

M_B_DQ<16>

16

M_B_DQ<17>

17

M_B_DQ<18>

18

M_B_DQ<19>

19

M_B_DQ<20>

20

M_B_DQ<21>

21

M_B_DQ<22>

22

M_B_DQ<23>

23

M_B_DQ<24>

24

M_B_DQ<25>

25

M_B_DQ<26>

26

M_B_DQ<27>

27

M_B_DQ<28>

28

M_B_DQ<29>

29

M_B_DQ<30>

30

M_B_DQ<31>

31

M_B_DQ<32>

32

M_B_DQ<33>

33

M_B_DQ<34>

34

M_B_DQ<35>

35

M_B_DQ<36>

36

M_B_DQ<37>

37

M_B_DQ<38>

38

M_B_DQ<39>

39

M_B_DQ<40>

40

M_B_DQ<41>

41

M_B_DQ<42>

42

M_B_DQ<43>

43

M_B_DQ<44>

44

M_B_DQ<45>

45

M_B_DQ<46>

46

M_B_DQ<47>

47

M_B_DQ<48>

48

M_B_DQ<49>

49

M_B_DQ<50>

50

M_B_DQ<51>

51

M_B_DQ<52>

52

M_B_DQ<53>

53

M_B_DQ<54>

54

M_B_DQ<55>

55

M_B_DQ<56>

56

M_B_DQ<57>

57

M_B_DQ<58>

58

M_B_DQ<59>

59

M_B_DQ<60>

60

M_B_DQ<61>

61

M_B_DQ<62>

62

M_B_DQ<63>

63

M_B_BS0 M_B_BS1 M_B_BS2

M_B_CAS# M_B_RAS# M_B_WE#

AJ11

AH11

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA10

D10

K10

J10

AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9

AT8 AT9

AR8

AA9 AA7

AB8 AB9

M_CLK_DDR2_DP

SB_CLK[0]

C9 A7

C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8

K9 J9

K8 K7 M5 N4 N2 N1 M4 N5 M2 M1

R6

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

RSVD_TP[11] RSVD_TP[12] RSVD_TP[13]

RSVD_TP[14] RSVD_TP[15] RSVD_TP[16]

SB_CS#[0]

SB_CS#[1] RSVD_TP[17] RSVD_TP[18]

SB_ODT[0]

SB_ODT[1] RSVD_TP[19] RSVD_TP[20]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

M_CLK_DDR2_DN

M_CLK_DDR3_DP M_CLK_DDR3_DN

M_CS#2 M_CS#3

M_ODT2 M_ODT3

M_B_DQS0_DN M_B_DQS1_DN M_B_DQS2_DN M_B_DQS3_DN M_B_DQS4_DN M_B_DQS5_DN M_B_DQS6_DN M_B_DQS7_DN

M_B_DQS0_DP M_B_DQS1_DP M_B_DQS2_DP M_B_DQS3_DP M_B_DQS4_DP M_B_DQS5_DP M_B_DQS6_DP M_B_DQS7_DP

M_B_A<0> M_B_A<1> M_B_A<2> M_B_A<3> M_B_A<4> M_B_A<5> M_B_A<6> M_B_A<7> M_B_A<8> M_B_A<9> M_B_A<10> M_B_A<11> M_B_A<12> M_B_A<13> M_B_A<14> M_B_A<15>

M_CKE2

M_CKE3

OUT OUT

10 11 12 13 14 15

OUT OUT OUT OUT OUT OUT OUT OUT

0 1 2 3 4 5 6 7 8 9

OUT OUT OUT

39C8 39C8

39B8 39B8 39B8 39B8 39B8 39B8 39B8 39B8

M_B_A<15..0>

39C8 39C8 39C8

OUT

OUT OUT OUT

38B8 38B8 38B8 38B8 38B8 38B8 38B8 38B8

39D5

38C8 38C8 38C8

OUT

38D8

BI

M_A_DQ<63..0>

38D8

OUT

38D8

OUT

38D8

OUT

38C8

OUT

38C8

OUT

38C8

OUT

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

M_A_DQ<0> M_A_DQ<1> M_A_DQ<2> M_A_DQ<3> M_A_DQ<4> M_A_DQ<5> M_A_DQ<6> M_A_DQ<7> M_A_DQ<8> M_A_DQ<9> M_A_DQ<10> M_A_DQ<11> M_A_DQ<12> M_A_DQ<13> M_A_DQ<14> M_A_DQ<15> M_A_DQ<16> M_A_DQ<17> M_A_DQ<18> M_A_DQ<19> M_A_DQ<20> M_A_DQ<21> M_A_DQ<22> M_A_DQ<23> M_A_DQ<24> M_A_DQ<25> M_A_DQ<26> M_A_DQ<27> M_A_DQ<28> M_A_DQ<29> M_A_DQ<30> M_A_DQ<31> M_A_DQ<32> M_A_DQ<33> M_A_DQ<34> M_A_DQ<35> M_A_DQ<36> M_A_DQ<37> M_A_DQ<38> M_A_DQ<39> M_A_DQ<40> M_A_DQ<41> M_A_DQ<42> M_A_DQ<43> M_A_DQ<44> M_A_DQ<45> M_A_DQ<46> M_A_DQ<47> M_A_DQ<48> M_A_DQ<49> M_A_DQ<50> M_A_DQ<51> M_A_DQ<52> M_A_DQ<53> M_A_DQ<54> M_A_DQ<55> M_A_DQ<56> M_A_DQ<57> M_A_DQ<58> M_A_DQ<59> M_A_DQ<60> M_A_DQ<61> M_A_DQ<62> M_A_DQ<63>

M_A_BS0 M_A_BS1 M_A_BS2

M_A_CAS# M_A_RAS# M_A_WE#

AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15

AE10 AF10

F10

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8

AE8 AD9 AF9

M_CLK_DDR0_DP

SA_CLK[0]

C5 D5 D3 D2 D6 C6 C2 C3

F8

G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8

N8 N7

M9 N9 M7

V6

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1] RSVD_TP[2] RSVD_TP[3]

RSVD_TP[4] RSVD_TP[5] RSVD_TP[6]

SA_CS#[0]

SA_CS#[1] RSVD_TP[7] RSVD_TP[8]

SA_ODT[0]

SA_ODT[1] RSVD_TP[9]

RSVD_TP[10]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4]

SA_DQS[5]

SA_DQS[6]

SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AB6 AA6 V9

M_CLK_DDR1_DP

AA5

M_CLK_DDR1_DN

AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

M_A_DQS0_DN

C4

M_A_DQS1_DN

G6

M_A_DQS2_DN

J3

M_A_DQS3_DN

M6

M_A_DQS4_DN

AL6

M_A_DQS5_DN

AM8

M_A_DQS6_DN

AR12

M_A_DQS7_DN

AM15

M_A_DQS0_DP

D4

M_A_DQS1_DP

F6

M_A_DQS2_DP

K3

M_A_DQS3_DP

N6

M_A_DQS4_DP

AL5

M_A_DQS5_DP

AM9

M_A_DQS6_DP

AR11

M_A_DQS7_DP

AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_CLK_DDR0_DN

M_CKE0

M_CKE1

M_CS#0 M_CS#1

M_ODT0 M_ODT1

M_A_A<0> M_A_A<1> M_A_A<2> M_A_A<3> M_A_A<4> M_A_A<5> M_A_A<6> M_A_A<7> M_A_A<8> M_A_A<9> M_A_A<10> M_A_A<11> M_A_A<12> M_A_A<13> M_A_A<14> M_A_A<15>

OUT OUT

0 1 2 3 4 5 6 7 8

9 10 11 12 13 14 15

38D8 38C8

38C8 38C8

OUT OUT OUT OUT OUT OUT OUT OUT

M_A_A<15..0>

38D5

LOTES_ACA_ZIF_069_P01_989P

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6943

A3

21-OCT-2002XXX

DOC.NUMBER

of

INVENTEC

TITLE

DATE

CODE

E

D

C

B

A

7 6 5 4 3 2 1

7 6 5 4 3

E

D

C

B

A

FF

8

CHANGE by

8

REV

2 1

SHEET

SIZE

POWER

CN4500

REFERENCE 4500~4699(CPU)

PVCORE

22UF_6.3V_5

22UF_6.3V_5 22UF_6.3V_5

2 1

C4514 C4515 C4516 C4517

22UF_6.3V_5 22UF_6.3V_5

2 1

22UF_6.3V_5

2 1

22UF_6.3V_5

2 1

C4513C4512C4511C4510

2 1

22UF_6.3V_5

C4518 C4519 C4520 C4521

22UF_6.3V_5

2 1

22UF_6.3V_5 22UF_6.3V_5

C4522 C4523 C4524 C4525

2 1

22UF_6.3V_5

2 1

22UF_6.3V_5 22UF_6.3V_5

2 1

22UF_6.3V_5

2 1

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100

CORE SUPPLY

PEG AND DDR

SVID

SENSE LINES

VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE VSSIO_SENSE

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

C4531

2 1

22UF_6.3V_5

J23

SVID SIGNAL TO VR

H_CPU_SVIDALRT#

AJ29

H_CPU_SVIDCLK

AJ30 AJ28

H_CPU_SVIDDAT

PVCORE

R4532

100_1%_2

VCCSENSE VSSSENSE

R4533

100_1%_2

2 1 2 1

AJ35 AJ34

B10 A10

P1V05S

2 1 2 1

22UF_6.3V_5

C4533

2 1

22UF_6.3V_5

C4532

2 1

PLACE CLOSE TO CPU

2 1

R4529 R4530 R4531

11D6

OUT

11D6

OUT

R4534

10_1%_2

VCC_SENSE_VCCIO VSS_SENSE_VCCIO

R4535

10_1%_2

C4534

2 1

22UF_6.3V_5

C4535

2 1

21

43_5%_2

21

0_5%_2

21

0_5%_2

OUT OUT

C4536

22UF_6.3V_5

P1V05S

2 1

9B7 9B7

2 1

R4527R4528

75_5%_2130_1%_2

P1V05S

C4537

22UF_6.3V_5

VR_SVID_ALERT# VR_SVID_CLK VR_SVID_DATA

2 1

C4542

22UF_6.3V_5

2 1

22UF_6.3V_5

OUT OUT OUT

C4541

2 1

11C7 11A3 11C7 11A3 11C7

C4540

22UF_6.3V_5

2 1

22UF_6.3V_5

LOTES_ACA_ZIF_069_P01_989P

XXX 21-OCT-2002

MODEL,PROJECT,FUNCTION

Block Diagram

CSC

1310xxxxx-0-0

44

69

X01

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

PROCESSOR DRIVEN VREF PATH WAS STUFFED BY DEFAULT: ROUTE WITH MIN. TRACE WIDTH OF 10 MILS

P0V75M_VREF

P0V75M_VREF P0V75M_VREF_H

46C4

45D6 41A8

IN

CPUDDR_WR_VREF1

DRAMRST_CNTRL

2

G

3

D S

Q4501

AM2302N

1

46C4

45D8 41A8

CPUDDR_WR_VREF2

IN

DRAMRST_CNTRL

IN

2

POWER

PVAXG

AT24 AT23 AT21 AT20 AT18 AT17

C4651 C4545 C4550C4546 C4547 C4548 C4549

22UF_6.3V_5 22UF_6.3V_5

2 1

22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5

2 1

22UF_6.3V_5

2 1

AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17

CN4500

VAXG1 VAXG_SENSE VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54

GRAPHICS

SENSE

DDR3 -1.5V RAILS

SA RAIL

G

1

LINES

D S

Q4502

AM2302N

3

VSSAXG_SENSE

SM_VREF

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

49A1

21D6 14D2 14B8

PVAXG

14A6 13A2 13D2

IN

SLP_S3#_3R

R4539

10_1%_2

GFX_VCC_SENSE

AK35

GFX_VSS_SENSE

AK34

OUT OUT

11B8 11B8

R4540

10_1%_2

P0V75M_VREF_H

2 1 2 1

AL1

NOTE : DDR_WR_VREF SHOULD HAVE 20/20 MIL WHEREVER POSSIBLE

5A

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

M27 M26 L26 J26 J25 J24 H26 H25

PVSA

2 1

10UF_6.3V_3

2 1

10UF_6.3V_310UF_6.3V_3

2 1

10UF_6.3V_3

2 1

10UF_6.3V_3

2 1

10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3

C4576C4575C4574

10UF_6.3V_3

2 1

G

1

AM2302N

Q4500

2

R4541

100K_5%_2

3

DS

2 1

R4538

0_5%_2

21

C4578

2 1

470PF_50V_2

P1V5S

+

C4572C4571C4570C4569C4568C4567

2 1

C4573

220UF_2.5V

2 1

PVSA

+

C4577

100UF_6.3V

2 1

R4544

P1V8S

L4500

21

MPZ1608S221AT

C4562 C4563 C4564

10UF_6.3V_3

2 1

1UF_6.3V_2

2 1

1UF_6.3V_2

2 1

1.2A

P1V8S_VCCPLL

C4565

22UF_6.3V_5

2 1

B6 A6 A2

VCCPLL1 VCCPLL2 VCCPLL3

1.8V RAIL

MISC VREF

VCCSA_SENSE

VCCSA_VID1

FC_C22

H23

C22 C24

LOTES_ACA_ZIF_069_P01_989P

100_5%_2

2 1

1K_5%_2

2 1

VCCSA_SENSE

VCCSA_VID0 VCCSA_VID1

R4547R4556

1K_5%_2

2 1

OUT

OUT OUT

10C4

10B4 10B4

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6945

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

CN4500

AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AJ2 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AM29 AM25 AM22 AM19 AM16 AM13 AM10

AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AJ25

AR7

AR4

AR2

AP7

AP4

AP1

AN7

AN4

AM7

AM4

AM3

AM2

AM1

AL7

AL4

AL2

AK7

AK4

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3

AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

T35 T34 T33 T32 T31 T30 T29 T28 T27 T26

N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27

K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10

G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29

VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169

P9 P8 P6 P5 P3 P2

L9 L8 L6 L5 L4 L3 L2 L1

H9 H8 H7 H6 H5 H4 H3 H2 H1

VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233

VSS_1

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

LOTES_ACA_ZIF_069_P01_989P

PEG STATIC LAN REVERSAL

LOW EDP ENABLE

PCIE PORT BIFURCATION

PEG DEFER TRAINING

46D4

CFG<2>

IN

CFG<4>

IN

CFG<5>

IN

CFG<6>

IN

CFG<7>

IN

R4550

1K_1%_2

R4551

1K_1%_2_DY

R4552

1K_1%_2_DY

R4553

1K_1%_2_DY

R4554

1K_1%_2_DY

21

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

CFG<0> CFG<1> CFG<2> CFG<3> CFG<4> CFG<5> CFG<6> CFG<7> CFG<8> CFG<9> CFG<10> CFG<11> CFG<12> CFG<13> CFG<14> CFG<15> CFG<16> CFG<17>

CPUDDR_WR_VREF1 CPUDDR_WR_VREF2

VCCIO_SEL

45D8 45D6

9C7

46A6

46A6 46A6 46A6 46A6

IN IN

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT

PEG STATIC LANE REVERSAL

CFG(2)

1 : (DEFAULT) NORMAL OPERATION 0 : LANE REVERSED

LOW EDP ENABLE

1 : (DEFAULT) EDP DISABLED

CFG(4)

0 : EDP ENABLED

PEG DEFER TRAINING

CFG(7)

1 : (DEFAULT) PEG TRAIN IMMEDIATELY FOLLOWING XXRESETB DE ASSERTION 0 : PEG WAIT FOR BIOS FOR TRAINING

PCIE PORT BIFURCATION STRAPS

11 : (DEFAULT) X16 - DEVICE 1 FUNCTION AND 2 DISABLED 10 : X8, X8 - DEVICE 1 FUNCTION 1 ENABLE ; FUNCTION 2 DISABLED

CFG[6:5]

01 : RESERVED - (DEVICE 1 FUNCTION 1 DISABLED ; FUNCTION 2 ENABLED) 00 : X8,X4,X4 - DEVICE 1 FUNCTION 1 AND 2 ENABLED

R4555

AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29

AJ31 AH31 AJ33 AH33

AJ26

21

B4 D1

F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29

J20 B18 A19

J15

10K_5%_2_DY

STRAP PIN

CN4500CN4500

L7 AG7 AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

REMOVE

AN35

CLK_XDP_CLKGEN_DP

AM35

CLK_XDP_CLKGEN_DN

AT2 AT1 AR1

B1

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17]

VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE

RSVD5

RSVD6 RSVD7

RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23

RSVD24 RSVD25 VCCIO_SEL

RSVD27

RESERVED

VCC_DIE_SENSE

RSVD28 RSVD29 RSVD30 RSVD31 RSVD32

RSVD33 RSVD34 RSVD35

RSVD37 RSVD38 RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

RSVD46 RSVD47 RSVD48 RSVD49 RSVD50

RSVD51 RSVD52

RSVD54 RSVD55

RSVD56 RSVD57 RSVD58

KEY

LOTES_ACA_ZIF_069_P01_989P

A3

21-OCT-2002XXX

MODEL,PROJECT,FUNCTION

Block Diagram

CS

X011310xxxxx-0-0

6946

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 4700~4949(PCH)

P3V3AL

21

A2A1

R4700

1K_5%_2

- +

2 1 2 1

INTVRMEN-INTEGRATE (SUS 1.05V VRM ENABLE 1:ENABLE INTERNAL VRS 0:ENABLE EXTERNAL VRS

24B1

PCSPKR_PCH_3(NO REBOOT) 1 : NO REBOOT ENABLED 0 : (DEFAULT) NO REBOOT DISABLED

FLASH OVERRIDE FLASH DESCRIPTOR SECURITY OVERIDE

1:ENABLE 0:DISABLE : (DEFAULT INTERNAL PULL-DOWN)

21D3 47B7

OUT

HDA_3S_SYNC_R(PLL ODVR VOLTAGE) 1 : VCC VRM = 1.6V

0 : VCC VRM = 1.8V(DEFAULT)

P3V3A

R4713

P3V3_RTC

3

C

D4700

BAT54C_30V_0.2A

TP4705

1

TP30

CN4700

LOTES_AAA_BAT_063_P02_A_2P

PCSPKR_PCH_3

OUT

FLASH_OVERRIDE

10K_5%_2_DY

HDA_3S_SYNC_R

21

10K_5%_2

R4720

R4714

1K_5%_2

R4706

0_5%_2_DY

21

PCH_GPIO13

P3V3A

21

P3V3_RTC

24A2

24B2

24A2

IN

R4707

330K_5%_3

2 1

BI BI

OUT

IN

STRAP

47B8 21D3

24A2

47B6

P3V3_RTC

C4700

2 1

HDA_3S_BITCLK

HDA_3S_SYNC

HDA_3S_RST#

HDA_3S_SDIN0

IN

OUT

R4718

RSC_0402_DY

21D6

21C7 21C6

21C8

20K_1%_2

R4705

2 1

1UF_6.3V_2

33_5%_2

FLASH_OVERRIDE

HDA_3S_SDOUT

21

OUT

47D3

OUT

47D3

OUT

47D3

OUT

21C7

OUT

21C8

OUT

21C8

OUT

21C6

OUT

R4703

21

R4704

20K_1%_2

1M_5%_2

R4711

1UF_6.3V_2

21

C4702

2 1

R4709

33_5%_2

21

R4712

33_5%_2

R4715

1K_5%_2

R4716

33_5%_2

47A7

IN

1

TP30

1

TP30

1

TP30

1

TP30

EC_SPI_CLK

EC_SPI_CS0#

EC_SPI_CS1#

EC_SPI_SI

EC_SPI_SO

RSC_0402_DY

C4701

2 1

1UF_6.3V_2

HDA_3S_BITCLK_R

21

HDA_3S_SYNC_R

HDA_3S_RST#_R

21

PCH_GPIO13

TP4720

TP4721

TP4722

TP4723

PCH_TCK

PCH_TMS

PCH_TDI

PCH_TDO

R4734

RTCX2

C4703

21

18PF_50V_2

4

32

10M_5%_2

2 1

R4708

RTCX1

1

X4700

32.768KHZ

C4704

21

18PF_50V_2

A20

C20

D20

G22

K22

C17

N34

L34

T10

K34

E34

G34

C34

A34

A36

C36

N32

J3

H7

K5

H1

T3

Y14

T1

V4

U3

21

U4700

RTCX1

RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

STRAPPING

HDA_BCLK

HDA_SYNC

STRAPPING

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

STRAPPING

HDA_DOCK_EN#/GPIO33

HDA_DOCK_RST#/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

ITL_BD82PPSM_QPJ4_FCBGA_989P

RTC

IHDA

JTAG

SPI

LPC

SATA

STRAPPING

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

LDRQ1#/GPIO23

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA 6G

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

LDRQ0#

SERIRQ

C38

LPC_3S_AD<0>

A38

LPC_3S_AD<1>

B37

LPC_3S_AD<2>

C37

LPC_3S_AD<3>

D36

LPC_3S_FRAME#

E36 K36

V5

PCI_3S_SERIRQ

AM3 AM1 AP7 AP5

AM10

SATA_HDD_RX_DN

AM8

SATA_HDD_RX_DP

AP11

SATA_HDD_TX_DN

AP10

SATA_HDD_TX_DP

AD7

SATA_MINICARD_RX_DN

AD5

SATA_MINICARD_RX_DP

AH5

SATA_MINICARD_TX_DN

AH4

SATA_MINICARD_TX_DP

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3

SATA_ODD_RX_DN

Y1

SATA_ODD_RX_DP

AB3

SATA_ODD_TX_DN

AB1

SATA_ODD_TX_DP

Y11

Y10

P1V05S_SATARCOMPO

AB12

AB13

P1V05S_SATA3RCOMPO

R4749

AH1

750_1%_2

P3

V14

P1

BI BI BI BI

OUT

IN

IN OUT OUT

IN

OUT OUT

29A7

IN

29A7

IN OUT OUT

37.4_1%_2

R4748

49.9_1%_2

21

27C3 21E3

29A7 29A7

R4747

P3V3A

R4736

21

0_5%_2_DY

P1V05S

R4737

21

RSC_0402_DY

R4742R4740R4738

RSC_0402_DY

2 1

RSC_0402_DY

2 1

27B7 21E3

RSC_0402_DY

2 1

RSC_0402_DY

2 1

R4744

10K_5%_2

2 1

PCH_TDI PCH_TMS PCH_TDO

47A6

OUT

47B6

OUT

47A6

OUT

27C3 21E3 27C3 21E3

P3V3S

27C3 21E3 27C3 21E3

BI

RSC_0402_DY

2 1

R4743R4741R4739

RSC_0402_DY

2 1

29D5 29D5

28C7 28C7

P1V05S

21

P1V05S

R4750

10K_5%_210K_5%_2

2 1

P3V3S

R4752R4751

10K_5%_2

2 1

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6947

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 4700~4949(PCH)

U4700

PERN1 PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6 PERP6 PETN6 PETP6

PERN7 PERP7 PETN7 PETP7

PERN8 PERP8 PETN8 PETP8

CLKOUT_PCIE0N CLKOUT_PCIE0P

PCIECLKRQ0#/GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1#/GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2#/GPIO20

CLKOUT_PCIE3N CLKOUT_PCIE3P

PCIECLKRQ3#/GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4#/GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5#/GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ#/GPIO56

CLKOUT_PCIE6N CLKOUT_PCIE6P

PCIECLKRQ6#/GPIO45

CLKOUT_PCIE7N CLKOUT_PCIE7P

PCIECLKRQ7#/GPIO46

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

ITL_BD82PPSM_QPJ4_FCBGA_989P

PCI-E*

SMBUS

Link

Controller

CLOCKS

FLEX CLOCKS

TP24 TP24

1 1

BG34 BJ34 AV32 AU32

BE34 BF34 BB32 AY32

BG36 BJ36 AV34 AU34

BF36 BE36 AY34 BB34

BG37 BH37 AY36 BB36

BJ38 BG38 AU36 AV36

BG40 BJ40 AY40 BB40

BE38 BC38 AW38 AY38

Y40 Y39

AB49 AB47

AA48 AA47

V10

Y37 Y36

J2

M1

A8

IN

IN OUT OUT

IN

IN OUT OUT

IN

IN OUT OUT

PCIE_LAN_RX_DN PCIE_LAN_RX_DP PCIE_LAN_TX_DN PCIE_LAN_TX_DP

PCIE_WLAN_RX_DN PCIE_WLAN_RX_DP PCIE_WLAN_TX_DN PCIE_WLAN_TX_DP

PCIE_USB3_RX_DN PCIE_USB3_RX_DP PCIE_USB3_TX_DN PCIE_USB3_TX_DP

R4775

10K_5%_2_DY

R4776

10K_5%_2_DY

C4724

21

C4725

0.1UF_16V_2

C4726

0.1UF_16V_2

C4793

0.1UF_16V_2

21

48D8 22C5 48C7

48D8 27C7 48B7

21

OUT

0.1UF_16V_2

C4727

0.1UF_16V_2

C4794

0.1UF_16V_2

CLKREQ_LAN#

CLKREQ_WLAN#

PCIE_LAN_TX_C_DN

21

PCIE_LAN_TX_C_DP

PCIE_WLAN_TX_C_DN

21

PCIE_WLAN_TX_C_DP

PCIE_USB3_TX_C_DN PCIE_USB3_TX_C_DP

21

R4773

10K_5%_2

R4772

10K_5%_2

P3V3A

21

P3V3S

21

22B1 22B1 22C2 22C2

27B7 27B7 27B7 27B7

31C7 31C7 31C7 31C7

48D7 22C5 48C7

48D7 27C7 48B7

OUT

CLKREQ_LAN#

CLKREQ_WLAN#

CLOCK TERMINATION FOR FICM STUFF FOR INTEGRATED CLK

48B3

48A3

48B3

CLKIN_DMI_PCH_DN

IN

CLKIN_DMI_PCH_DP

IN

CLKIN_BUF_DOT96_DN

IN

CLKIN_BUF_DOT96_DP

IN

CLKIN_PCH14

IN

CLKIN_SATA1_DP

IN

CLKIN_SATA1_DN

IN

R4777

10K_5%_2

R4778

10K_5%_2

R4779

10K_5%_2

R4780

10K_5%_2

R4781

10K_5%_2

R4782

10K_5%_2

R4783

10K_5%_2

21

22C2 22C2

48D8 22C5 48D7

27C7 27C7

48D8 27C7 48D7

31C7 31C7

31B8 31C7

OUT OUT

IN

OUT OUT

IN

OUT OUT

IN

P3V3A

CLK_PCIE_LAN_DN CLK_PCIE_LAN_DP

CLKREQ_LAN#

CLK_PCIE_WLAN_DN CLK_PCIE_WLAN_DP

CLKREQ_WLAN#

CLK_PCIE_USB3_DN CLK_PCIE_USB3_DP

CLKREQ_USB3#

TP4703

R4789

TP4704

21

10K_5%_2_DY

Y43

AB42 AB40

AK14 AK13

Y45

L12

V45 V46

L14

V40 V42

T13

V38 V37

K12

E6

20A7 39C8

38C8

48D3

20A7 39C8

38C8

BI

PCH_3S_SMDATA

BI

R4784 R4785

2.2K_5%_2

PCH_3S_SMCLK

PCH_3A_SMCLK

PCH_3A_SMDATA

R4790

R4791

R4792

R4793

21

P3V3S

2.2K_5%_2

R4786

2.2K_5%_2

2 1

P3V3A

R4787

2.2K_5%_2

2 1

SSM3K7002BFU

2

3

Q4700

DS

G

P5V0S

1

10K_5%_2_DY

3

Q4701

DS

G

SSM3K7002BFU

2

1

R4794

10K_5%_2_DY

21

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SML1ALERT#/PCHHOT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

SMBCLK

E12

PCH_3A_SMCLK

H14

PCH_3A_SMDATA

C9

DRAMRST_CNTRL_PCH

A12

PCH_3A_ALERT_CLK

C8

PCH_3A_ALERT_DAT

G12

C13

E14

M16

M7

T11

P10

48C3

OUT

M10

CLKREQ_GPU#

AB37

CLK_PEG_REF_DN

AB38

CLK_PEG_REF_DP

AV22

CLK_DMI_PCH_DN

AU22

CLK_DMI_PCH_DP

AM12 AM13

BF18

CLKIN_DMI_PCH_DN

BE18

CLKIN_DMI_PCH_DP

BJ30 BG30

G24

CLKIN_BUF_DOT96_DN

E24

CLKIN_BUF_DOT96_DP

AK7

CLKIN_SATA1_DN

AK5

CLKIN_SATA1_DP

CLKIN_PCH14

K45

H45

CLKIN_PCI_FB

V47 V49

Y47

K43

F47

H47

K49

SMB_ALERT#

OUT

48B2

P3V3A

R4795

21

10K_5%_2

SML1ALERT#

SML1_CLK

SML1_DATA

CLKREQ_GPU#

R4837

OUT OUT OUT

R4753

10K_5%_2

21

BI BI

OUT OUT

OUT

OUT OUT

IN

IN IN

48A8

41A8

27B3 48D2

48D2

48C2

21

48C3

57B6 57B6

41D2 41D2

48C8 48C8

P3V3A

48D3

48D3 27B3

48D3

33PF_50V_2

IN

BI

SML1ALERT#

PCH_3A_ALERT_CLK

PCH_3A_ALERT_DAT

SML1_CLK

EC_SMB3_CLK

SML1_DATA

EC_SMB3_DATA

X4701

25MHZ

2 1

10K_5%_2

48C8

IN

48C8

IN

48B8

IN

48B8

XTAL25_IN XTAL25_OUT

OUT OUT

IN

48B8

IN

51A7

IN

48B1 48C1

48D3

IN

SMB_ALERT#

P1V05S

R4802

21

90.9_1%_2

CLOSE TO PCH

TP24

1

TP4700

TP24

1

TP4701

TP24

1

TP4702

A3

21-OCT-2002XXX

10K_5%_2

R4797

2.2K_5%_2

R4798

2.2K_5%_2

R4799

2.2K_5%_2

R4800

2.2K_5%_2

Q4702

DS

SSM3K7002FU_DY

3

2

Q4703

DS

SSM3K7002FU_DY

32

XTAL25_OUT

R4801

1M_5%_2

2 1

XTAL25_IN

21

C4729C4728

27PF_50V_2

2 1

B500

PASSWORD_0805

MODEL,PROJECT,FUNCTION

Block Diagram

CS

R4796

G

P3V3A

1

OUT

21

6948

P3V3A

21

48A3

X011310xxxxx-0-0

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

DSWVRMEN - DEEP S4/S5 WELL ON-DIE VOLTAGE REGULATOR ENABLE

U4700

IN IN IN IN

OUT OUT OUT OUT

R4814

DMI_RX0_DN DMI_RX1_DN DMI_RX2_DN DMI_RX3_DN

DMI_RX0_DP DMI_RX1_DP DMI_RX2_DP DMI_RX3_DP

DMI_TX0_DN DMI_TX1_DN DMI_TX2_DN DMI_TX3_DN

DMI_TX0_DP DMI_TX1_DP DMI_TX2_DP DMI_TX3_DP

21

42D7 42D7 42D7

P1V05S

R4812

49.9_1%_2

2 1

P3V3S

42D7

42D7 42D7 42C7 42C7

42D7 42D7 42D7

42D7 42D7 42D7 42D7

750_1%_2

BC24 BE20 BG18 BG20

BE24 BC20 BJ18 BJ20

AW24 AW20 BB18 AV18

AY24 AY20 AY18 AU18

BJ24

BG25

BH21

DMI0RXN DMI1RXN DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

DMI

FDI

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16

AV12

BC10

AV14

BB10

FDI_TX0_DN FDI_TX1_DN FDI_TX2_DN FDI_TX3_DN FDI_TX4_DN FDI_TX5_DN FDI_TX6_DN FDI_TX7_DN

FDI_TX0_DP FDI_TX1_DP FDI_TX2_DP FDI_TX3_DP FDI_TX4_DP FDI_TX5_DP FDI_TX6_DP FDI_TX7_DP

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

OUT OUT OUT OUT OUT

42C7

IN

42C7

IN

42C7

IN

42C7

IN

42C7

IN

42C7

IN

42C7

IN

42C7

IN

42C7

IN

42C7 42D7

IN

42C7

IN

42C7

IN

42C7

IN

42C7

IN

42C7

IN

42B7

IN

42B7

HIGH-ENABLED(DEFAULT) LOW-DISABLED

STRAPPING

P3V3_RTC

R4829

330K_5%_2

2 1

R4830

330K_5%_2_DY

2 1

P3V3A

DSWVRMEN

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_LAN#/GPIO29

21

STRAPPING

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

10K_5%_2

R4815

10K_5%_2

41C1

IN

SYS_RESET#

2 1

40B4 11A4 11C7

21B6 49A6

P3V3A

D4707

41C7

OUT

49C2 21D1 21D3

49A5

2 1

2

NC

13

R4820

10K_5%_2_DY

2

D4706

21D6

IN

EC_PWRSW#

21D6

IN

BAT54_30V_0.2A

LOW_BAT#_3

NC

13

BAT54_30V_0.2A

IN

PM_DRAM_PWRGD

IN

SUS_PWR_ACK

OUT

SUSACK#

PVCORE_PG

PCH_PWROK

RSMRST#

21D6 49A5

49A5

P3V3A

R4822

21

8.2K_5%_2

21B6

IN

49B7

R4816

0_5%_2_DY

ACPRESENT

IN

PCH_PWROK

R4823

10K_5%_2

21

PM_RI#

C12

P12

L22

L10

B13

C21

K16

E20

H20

E10

A10

49A6 21D6

49B7

49A6

31C6 22B5

27C7 49B3

2 1

49A3

SUSACK#

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SUSPWRDNACK/GPIO30

INT. PU 20K

PWRBTN#

ACPRESENT/GPIO31

BATLOW#/GPIO72

RI#

ITL_BD82PPSM_QPJ4_FCBGA_989P

ACPRESENT

IN

SUS_PWR_ACK

IN

PM_RI#

IN

PCIE_WAKE#

IN

PCH_GPIO29

IN

System Power Management

INT. PD 20K

INT. PU 20K

R4824

R4825

R4826

R4827

R4821

A18

E22

B9K3

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

P3V3A

R4831

0_5%_2

PCIE_WAKE#

PCI_3S_CLKRUN#

EC_32KHZ

SLP_S5#_3R

SLP_S3#_IC_3R

SLP_SUS#

H_PM_SYNC

PCH_GPIO29

21

RSMRST#

22B5 27C7 31C6 49A5

IN

49A5

21E3

IN

21B6

OUT

41C5

BI

49A5

IN

R4832

IN

21D1 21D3

49B7

1K_5%_2_DY

2 1

P3V3_LDO

R4883

10K_5%_2_DY

P3V3_LDO

2 12

SLP_S5_3R

21D3 14D2

1

SSM3K7002FU_DY

Q4713

3

DS

G

SSM3K7002BFU

1

OUT

Q4714

G

R4834

10K_5%_2

SLP_S3_3R

2 1 3

DS

2

OUT

15A4 15B8

16A7 15B4

P3V3A

5

U4704

+-

1

2

TC7SZ08FU

3

4

SLP_S3#_3R

21

R4710

100K_5%_2

OUT

13D2 14A6

13A2 14B8 14D2

21D6 45D3

P3V3S

IN

PCI_3S_CLKRUN#

R4828

21E3 49B3

8.2K_5%_2

21

21-OCT-2002XXX

MODEL,PROJECT,FUNCTION

CS

A3

Block Diagram

X011310xxxxx-0-0

6949

REFERENCE 4700~4949(PCH)

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

P3V3S

R4855

R4857R4856

2.2K_5%_2

2 1

PCH_LVDS_DDCDATA - LVDS DETECT

HIGH-LVDS ENABLED

21E7 34D7

34B5

34C5 34C5

OUT OUT

OUT

PCH_LCM_BKLTEN PCH_LCM_VDDEN

PCH_INV_PWM_3

PCH_LVDS_DDCCLK PCH_LVDS_DDCDATA

R4858

2.37K_1%_2

LOW-LVDS DISABLED (DEFAULT)

34B8

34B8 34B8 34B8

PCH_LVDS_TXCL_DN

OUT

PCH_LVDS_TXCL_DP

OUT

PCH_LVDS_TXDL0_DN

OUT

PCH_LVDS_TXDL1_DN

OUT

PCH_LVDS_TXDL2_DN

OUT

PCH_LVDS_TXDL0_DP

OUT

PCH_LVDS_TXDL1_DP

OUT

PCH_LVDS_TXDL2_DP

OUT

100K_5%_2

2 1

J47 M45

P45

T40 K47

T45 P39

21

AF37 AF36

AE48 AE47

AK39 AK40

AN48 AM47 AK47 AJ48

AN47 AM49 AK49 AJ47

AF40 AF39

AH45 AH47 AF49 AF45

AH43 AH49 AF47 AF43

U4700

L_BKLTEN L_VDD_EN

L_BKLTCTL

L_DDC_CLK

L_DDC_DATA

L_CTRL_CLK

L_CTRL_DATA

WHEN ¡¥1¡¦- LVDS IS DETECTED

LVD_IBG LVD_VBG

LVD_VREFH LVD_VREFL

LVDSA_CLK# LVDSA_CLK

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK# LVDSB_CLK

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

LVDS

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N

Digital Display Interface

DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

PCH_HDMI_DDCCLK

P46

PCH_HDMI_DDCDATA

P42

AP47 AP49

PCH_HPDET

AT38

PCH_HDMI_TX2_DN

AY47

PCH_HDMI_TX2_DP

AY49

PCH_HDMI_TX1_DN

AY43

PCH_HDMI_TX1_DP

AY45

PCH_HDMI_TX0_DN

BA47

PCH_HDMI_TX0_DP

BA48

PCH_HDMI_TXC_DN

BB47

PCH_HDMI_TXC_DP

BB49

OUT OUT OUT OUT OUT OUT OUT OUT

36D8

BI

36D8

BI

36B5

IN

36A5 36A5 36A5 36A5 36A5 36A5 36A5 36A5

35D8 35D8 35D8

OUT OUT OUT

R4859

150_1%_2

R4860

150_1%_2

R4861

150_1%_2

PCH_CRTB PCH_CRTG PCH_CRTR

21

35A2 35A2

35B2 35B2

OUT OUT

PCH_CRT_DDCCLK PCH_CRT_DDCDATA

PCH_CRT_HSYNC PCH_CRT_VSYNC

R4862

N48 P49 T49

T39 M40

M47 M49

T43 T42

CRT_BLUE CRT_GREEN CRT_RED

CRT

CRT_DDC_CLK

CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

DAC_IREF CRT_IRTN

ITL_BD82PPSM_QPJ4_FCBGA_989P

DDPD_CTRLCLK DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

1K_1%_2

2 1

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

CLOSE TO PCH

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6950

A3

21-OCT-2002XXX

REFERENCE 4700~4949(PCH)

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

GPIO51

BBS_BIT1

GPIO19

BBS_BIT0

0 1 0

BOOT BIOS

DESTINATION

1

RESERVED(NAND)

------

1 1 SPI (DEFAULT)

00

LPC

BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45

AH12

AB46 AB45

C18 N30

AM4 AM5 Y13 K24 L24

U4700

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10

H3

TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

P3V3S

R4874

R4875

R4876

R4877

R4878

R4880

R4881

R4882

R4838

R4956

R4879

21

8.2K_5%_2

10K_5%_2

PCI_3S_INTA#

PCI_3S_INTB#

PCI_3S_INTC#

PCI_3S_INTD#

RUNSCI0#_3

DGPU_HOLD_RST#

PCI_3S_REQ2#

DGPU_PWR_EN#

SATA_ODD_DA#

PCI_3S_PIRQG#

PCI_3S_PIRQH#

51B6

BI

51B6

BI

51B6

BI

51B6

BI

21E3

IN

52D6

51B6

57A6

IN

51B6

IN

16A3

51B6

IN

51B6

29A5

IN

51B6

IN

51B6

IN

BBS STRAPING

R4885 R4886

1K_5%_2_DY

BBS_BIT1

21

ROUTE WITH 90 OHMS IMPEDANCE TOTAL LENGTH NO LONGER THAN 11 INCHES

STP_A16OVR

21

1K_5%_2_DY

32D7 33B5

51D7 51C7 51C7 51C7

51C7

57A6 51C7 51C7

16A3

BI BI

USB3_PCH_RX1_DN USB3_PCH_RX2_DN

USB3_PCH_RX1_DP USB3_PCH_RX2_DP

USB3_PCH_TX1_DN USB3_PCH_TX2_DN

USB3_PCH_TX1_DP USB3_PCH_TX2_DP

BI BI BI BI

OUT OUT OUT

DGPU_HOLD_RST# PCI_3S_REQ2# DGPU_PWR_EN#

PCI_3S_INTA# PCI_3S_INTB# PCI_3S_INTC# PCI_3S_INTD#

27C3 27C7

21E3 28C3 57A6

BI

41C7

BUF_PLT_RST#

R4888

100K_5%_2

31C6 36B2

LOW=A16 SWAP OVERRIDE STP_A16OVR TOP-BLOCK SWAP OVERRIDE

HIGH=DEFAULT

PLT_RST#

BI

U4705

4

21

TC7SZ08FU

OUT OUT

OUT

CLK_KBPCI CLKIN_PCI_FB

CLK_PCI_DEBUG

P3V3A

5

+-

3

MCAHINE ID 0: CHIEF RIVER:1 / HURON RIVER 0 MACHINE ID 1: POWER EXPRESS(YES:1 NO:0) MACHINE ID 2: UMA:1 / DISCRETE:0 MACHINE ID 3: MAINSTREAM:1 / ENTRY:0 MACHINE ID 4: HDMI:1 / NO HDMI:0 MACHINE ID 5: SLEEP&CHARGE&DOLBY:YES1 / NO 0 MACHINE ID 6: 35W CPU:1 / 17W CPU:0

21E3 48A3

27C7

1

2

P3V3A

10K_5%_2_DY

R4889 R4890

R4891

R4887

31C7 31C6

29A5 51C7

51C7

51B7

USB3_SMI#

BI

SATA_ODD_DA#

BI

PCI_3S_PIRQG#

BI

PCI_3S_PIRQH#

BI

22_5%_2 22_5%_2

22_5%_2

51A4

51A4 51A4 51A4 51A4 51A4 51A4

P3V3A_PME#

CLK_KBPCI_R CLK_PCI_FB_R

TP4717

CLK_PCI_DEBUG_R

51A2

OUT

51A2 51A4

OUT

51A2

OUT

51A2

OUT

51A2

OUT

51A2

OUT

51A2

OUT

51A2

OUT

TP24

MACHINE_ID0 MACHINE_ID1 MACHINE_ID2 MACHINE_ID3 MACHINE_ID4 MACHINE_ID5 MACHINE_ID6 MACHINE_ID1_DB

21

21 21

21

B21

M20 AY16 BG46

BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30

K40

K38

H38

G38

C46

C44

E40

D47

E42

F46

G42

G40

C42

D44

K10

C6

H49

H43

J48

K42

1

H40

TP21 TP22 TP23 TP24

USB3RN1 USB3RN2 USB3RN3 USB3RN4 USB3RP1 USB3RP2 USB3RP3 USB3RP4 USB3TN1 USB3TN2 USB3TN3 USB3TN4 USB3TP1 USB3TP2 USB3TP3 USB3TP4

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

USED AS GPIO ONLY. INT. PU 20K

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PME#

INT. PU 20K

PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 OC7#/GPIO14

ITL_BD82PPSM_QPJ4_FCBGA_989P

R4892 R4893 R4894 R4895 R4896 R4897 R4898 R4899

NOTE:10K_5%(60130B1030ZT)

RSVD

PCI

21 21 21 21 21 21 21 21

10K_5%_2 10K_5%_2 10K_5%_2 10K_5%_2 10K_5%_2 10K_5%_2 10K_5%_2 10K_5%_2

NVRAM

DEBUG PORT

USB

P3V3A

RSVD1 RSVD2 RSVD3 RSVD4

RSVD5 RSVD6

RSVD7 RSVD8

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

RSVD23

RSVD24

RSVD25

RSVD26 RSVD27

RSVD28 RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9

OC6#/GPIO10

TO BE USED AS GPIO

51A5 51A2

OUT

51A5

OUT

51A2

OUT

51A2

OUT

51A5

OUT

51A5

OUT

51A2

OUT

51A2

OUT

51A5

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5

AV10

AT8

AY5 BA2

AT12

NOTE:

BF3

USB2.0/3.0 COMBO-USB2.0 PORT 0,1 MAPPEDUSB3.0 PORT 1,2

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

MACHINE_ID0 MACHINE_ID1 MACHINE_ID2 MACHINE_ID3 MACHINE_ID4 MACHINE_ID5 MACHINE_ID6 MACHINE_ID1_DB

NOTE:10K_5%(60130B1030ZT)

USB_P0_DN USB_P0_DP USB_P1_DN USB_P1_DP USB_P2_DN USB_P2_DP

USB_CR_DN USB_CR_DP USB_WLAN_DN USB_WLAN_DP USB_CAM_DN USB_CAM_DP

USB_3G_DN USB_3G_DP

22.6_1%_3

CLOSE TO PCH

MACHINE_ID0 MACHINE_ID1 MACHINE_ID2 MACHINE_ID3 MACHINE_ID4 MACHINE_ID5 MACHINE_ID6 MACHINE_ID1_DB

R4900 R4901 R4902 R4903 R4904 R4905 R4906 R4907

R4835

21

BI BI BI BI BI BI

BI BI

IN IN IN IN IN IN IN IN

21 21 21 21 21 21 21 21

32B8

32C8

32B8

32C8 33C5 33C5 30C5 30C5

26A8 26A8 27B3 27B3 34B3 34B3

28C3 28C3

51A4 51A4 51A4 51A4 51A5 51A4 51A4 51A4 51A4

10K_5%_2_DY 10K_5%_2_DY 10K_5%_2_DY 10K_5%_2_DY 10K_5%_2_DY 10K_5%_2_DY 10K_5%_2_DY 10K_5%_2_DY

P0.P1 RESERVER FOR USB3.0

CARD READER WLAN WEBCAM

3G

51A5 51A5 51A5

51A5 51A5 51A5 51A5

21-OCT-2002XXX

A3

MODEL,PROJECT,FUNCTION

Block Diagram

CS

X011310xxxxx-0-0

6951

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 4700~4949(PCH)

P3V3A

21

21 21 21 21 21 21 21

10K_5%_2

21

1K_5%_2_DY

21

10K_5%_2

21

10K_5%_2_DY

21

10K_5%_2_DY

10K_5%_2

21

10K_5%_2_DY

R4928 R4908 R4909 R4910 R4911

P3V3S

R4927 R4916 R4917 R4915 R4919 R4920 R4921

R4727

FDI_OVRVLTG(GPIO37)

LOW- TX,RXTERMINATED TO SAME VOLTAGE

(DC COUPLING MODE) DEFAULT

P3V3S

R4934 R4935

21

10K_5%_2

21

100K_5%_2_DY

PCH_GPIO37

PLL_ODVR_EN(PLL ON DIE VR ENABLE)(GPIO28)

HIGH-ENABLED (DEFAULT)

LOW-DISABLED

P3V3A

R4950

10K_5%_2

R4936

10K_5%_2_DY

21

PLL_ODVR_EN

STRAP

PCH_GPIO27 PCH_GPIO15 PCH_GPIO8 PCH_GPIO12 PCH_GPIO24

PCH_GPIO22 PCH_GPIO38 PCH_GPIO16

SATA_ODD_PRSNT#

PCH_GPIO39 PCH_GPIO48

PCH_GPIO22

OUT

IN

52B6

52C6

OUT

OUT OUT OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT

52B6

52C6

52D6

52C6

52D6

52C6

52B6

52C6

29A5

52B6

52D7

52C7

52B6

P3V3S

52D7

P3V3S

28C6

28C2

52D7

51C7 21E3

52D7

13C8 13B2

52D7

52C7

52D7

52A7

R4929

R4930

R4932

52B7

52D7

52C7

29A5

27B7

27C7

33K_5%_2_DY

IN IN IN IN

52D7

OUT

R4721

21

MSATA_DET

3G_ON#PCH_GPIO6

PCH_GPIO6

RUNSCI0#_3

PCH_GPIO8

OUT

PCH_GPIO12

OUT

PCH_GPIO15

OUT

PCH_GPIO16

OUT

DGPU_PWRGD

IN

PCH_GPIO22

OUT

PCH_GPIO24

OUT

PCH_GPIO27

IN

PLL_ODVR_EN

21

10K_5%_2

21

10K_5%_2_DY

21

10K_5%_2

PCH_GPIO37

OUT

PCH_GPIO38

OUT

PCH_GPIO39

OUT

PCH_GPIO48

OUT

SATA_ODD_PRSNT#

BTIFON#

OUT

U4700

BMBUSY#/GPIO0

TACH1/GPIO1

TACH2/GPIO6

TACH3/GPIO7

GPIO8

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

SATA4GP/GPIO16

INT. PU 20K

TACH0/GPIO17

SCLOCK/GPIO22

GPIO24

GPIO27

GPIO28

STP_PCI#/GPIO34

GPIO35

SATA2GP/GPIO36

SATA3GP/GPIO37

SLOAD/GPIO38

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

SATA5GP/GPIO49/TEMP_ALERT#

GPIO57

VSS_NCTF_1

VSS_NCTF_2

VSS_NCTF_3

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

VSS_NCTF_8

VSS_NCTF_9

VSS_NCTF_10

VSS_NCTF_11

VSS_NCTF_12

VSS_NCTF_13

VSS_NCTF_14

ITL_BD82PPSM_QPJ4_FCBGA_989P

INT. PU 20K

INT. PD 20K STRAPPING

INT.PD 20K

INT. PU 20K

INT. PD 20K

STRAPPING

GPIO

STRAPPING

T7

A42

H36

E38

C10

C4

G2

U2

D40

T5

E8

E16

P8

K1

K4

V8

M5

N2

M3

V13

V3

D6

A4

A45

A46

A5

A6

B3

B47

BD1

BD49

BE1

BE49

BF1

BF49

NCTF

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

INT. PU 20K

A20GATE

PROCPWRGD

THRMTRIP#

INIT3_3V#

CPU/MISC

STRAPPING

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

RCIN#

DF_TVS

PECI

NC_1

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44A44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

SATA_ODD_PWREN

R4724

R4725

R4726

PCH_PECI

THRMTRIP#_R

FOLLOW EDS1.0

R4940

0_5%_2_DY

P3V3S

29B8

OUT

21

10K_5%_210K_5%_2

21

10K_5%_2_DY

21

10K_5%_2_DY

EC_3S_A20GATE

21

BOTH THESE SHOULD BE CLOSE TO PCH

H_PECI

KBRST#

H_CPUPWRGD

56_5%_2

R4941

390_5%_2

R4942

21

P1V05S

NV_CLE

21-OCT-2002XXX

21E2

IN

21A6 41D5

OUT

21D2

IN

41C5

OUT

P1V05S

R4944

56_5%_2

41D6

2 1

PM_THRMTRIP#

40A4

IN

41D5

2 1

R4943

21

0_5%_2_DY

OUT

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6952

A3

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 4700~4949(PCH)

P1V05S

1.3A

C4775C4774C4773C4772

10UF_6.3V_3

1UF_6.3V_2

2 1

1UF_6.3V_2 1UF_6.3V_2

2 1

AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31

P1V05S

20MIL

10UF_6.3V_3

C4776

P1V05S

3A

C4777 C4778 C4779

1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2

2 1

1UF_6.3V_2

2 1

C4780

P1V05S

0_5%_2_DY

2 1

R4945

21

P1V05S_VCCAPLLEXP

P3V3S

C4781

0.1UF_16V_2

2 1

15MIL

P1V5S_VCCAFDI_VRM

15MIL

P1V05S

R4946

0_5%_2_DY

21

P1V05S_VCCAFDIPLL

20MIL

15MIL

AN19

BJ22

AN16

AN17

AN21

AN26

AN27

AP21

AP23

AP24

AP26

AT24

AN33

AN34

BH29

AP16

BG6

AP17

AU20

U4700

VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17]

VCCIO[28]

VCCAPLLEXP

VCCIO[15]

VCCIO[16]

VCCIO[17]

VCCIO[18]

VCCIO[19]

VCCIO[20]

VCCIO[21]

VCCIO[22]

VCCIO[23]

VCCIO[24]

VCCIO[25]

VCCIO[26]

VCC3_3[3] VCCDFTERM[2]

VCCVRM[2]

VccAFDIPLL

VCCIO[27]

VCCDMI[2]

ITL_BD82PPSM_QPJ4_FCBGA_989P

POWER

VCC CORE

VCCIO

FDI

CRT

LVDS

DMI HVCMOS

NAND / SPI

VCCALVDS

VSSALVDS

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCDFTERM[1]

VCCDFTERM[3]

VCCDFTERM[4]

VCCADAC

VSSADAC

VCCSPI

U48

U47

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

15MIL

P3V3S_VCCADAC

15MIL

R4937

2 1

0_5%_2_DY

P1V5S_VCCAFDI_VRM

1UF_6.3V_2_DY

R4947

0_5%_2_DY

P3V3S

R4931

2 1

0_5%_2

2 1

R4933

C4782

22UF_6.3V_5

21

0.01UF_50V_2

0_5%_2_DY

15MIL

C4785 C4786 C4787

0.01UF_50V_2

2 1

C4790

P3V3AL P3V3A

21

C4792

1UF_6.3V_2

2 1

0.1UF_16V_2

21

C4788

P1V05S

21

2 1

21

R4948

0_5%_2

C4783

2 1

1UF_6.3V_2

C4784

0.1UF_16V_2

2 1

P1V8S_VCCTX_LVDS

22UF_6.3V_50.01UF_50V_2

C4789

21

C4791

0.1UF_16V_2

2 1

L4700

FBM_11_160808_121T

L4701

FBM_11_160808_121T

P1V05S

P1V8S

21

P3V3S

P1V8S

21

P3V3S

P1V5S_VCCAFDI_VRM P1V5S

R4949

21

40MIL

0_5%_3

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6953

A3

21-OCT-2002XXX

10MIL

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

L4708

0603_DY

P1V05S

P3V3A

P3V3S

20MIL

P1V05S

21

P3V3A

P3V3S

10MIL

P3V3S

P1V05S

10MIL

20MIL

D4708

R4869

C4833

D4709

R4870

P1V5S_VCCAFDI_VRM

P1V05S

21-OCT-2002XXX

REFERENCE 4700~4949(PCH)

2

BAT54_30V_0.2A

13

10_5%_5

21

0.1UF_16V_2

21

2

NC NC

BAT54_30V_0.2A

13

10_5%_5

21

C4834

21

1UF_6.3V_2

MODEL,PROJECT,FUNCTION

CS

Block Diagram

A3

P3V3A

P5V0A

P3V3S

P5V0S

X011310xxxxx-0-0

6954

P3V3S

C4802C4801

0.1UF_16V_2

10UF_6.3V_3

2 1

P3V3A

15MIL

20MIL

P1V05S

20MIL

P1V05S

1UF_6.3V_2_DY

1.1A

22UF_6.3V_5

P1V05S

1UF_6.3V_21UF_6.3V_2

2 1

P1V05S

L4706

FBM_11_160808_121T

L4707

FBM_11_160808_121T

P1V05S_VCCADPLLA

21

C4812

22UF_6.3V_5_DY 1UF_6.3V_2

21

22UF_6.3V_5_DY 1UF_6.3V_2

2 12 1

P1V05S_VCCADPLLB

C4815

C4816 C4817

2 1

C4814C4813

10UF_6.3V_3

2 1 2 1

P1V05S

C4818

C4819

C4820

C4821

C4822

P1V05S

4.7UF_6.3V_3

0.1UF_16V_2 0.1UF_16V_2

2 1

1UF_6.3V_2_DY

C4825C4824C4823

2 1

21

P3V3_RTC

0.1UF_16V_2

2 1

1UF_6.3V_2

2 1

1UF_6.3V_2

2 1

1UF_6.3V_2

2 1

0.1UF_16V_2

2 1

C4827C4826 C4828

1UF_6.3V_2

2 1

P1V05S

R4867

0_5%_2_DY

21

0_5%_2_DY

C4804

2 1

0.1UF_16V_2_DY

21

C4807C4806

2 1

C4803

0.1UF_16V_2

C4805

22UF_6.3V_5

C4810C4809C4808

1UF_6.3V_2

P1V5S_VCCAFDI_VRM

0.1UF_16V_2

2 1

R4865

0.1UF_16V_2

P1V05S_VCCACLK

21

P1V05S_VCCAPLLDMI2

2 1

C4811

15MIL

2 1

U4700

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3[5]

VCCAPLLDMI2

VCCIO[14]

POWER

R4866

0_5%_2

AD49

212 1

BH23

AL29

T16

V12

T38

USB

AL24

AA19

AA21

AA24

AA26

AA27

AA29

AA31

AC26

AC27

AC29

AC31

AD29

AD31

W21

W23

W24

W26

W29

W31

2 1

15MIL

20MIL

15MIL

10MIL

BD47

BF47

AF17 AF33 AF34 AG34

AG33

W33

N16

Y49

V16

T17 V19

BJ8

DCPSUS[3]

VCCASW[1]

VCCASW[2]

VCCASW[3]

VCCASW[4]

VCCASW[5]

VCCASW[6]

VCCASW[7]

VCCASW[8]

VCCASW[9]

VCCASW[10]

VCCASW[11]

VCCASW[12]

VCCASW[13]

VCCASW[14]

VCCASW[15]

VCCASW[16]

VCCASW[17]

VCCASW[18]

VCCASW[19]

VCCASW[20]

DCPRTC

VCCVRM[4]

VCCADPLLA

VCCADPLLB

VCCIO[7] VCCDIFFCLKN[1] VCCDIFFCLKN[2] VCCDIFFCLKN[3]

VCCSSC

DCPSST

DCPSUS[1] DCPSUS[2]

V_PROC_IO

Clock and Miscellaneous

PCI/GPIO/LPCMISC

SATA

CPU

A22

VCCRTC

ITL_BD82PPSM_QPJ4_FCBGA_989P

RTC

HDA

VCCIO[29]

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCAPLLSATA

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

V5REF

N26

P26

P28

T27

T29

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

3A

10MIL

20MIL

10MIL

V5REF

P1V05S_VCCAPLLSATA

10MIL

V5REF_SUS

P3V3A

C4841

2 1

C4830

0.1UF_16V_2

C4831

0.1UF_16V_2

C4832

2 1

1UF_6.3V_2_DY

1UF_6.3V_2

C4836

C4837

C4838

C4839

1UF_6.3V_2

C4840

1UF_6.3V_2

20MIL

0.1UF_16V_2

2 1

C4835

C4829

1UF_6.3V_2

21

10MIL

21

20MIL

0.1UF_16V_2

21

0.1UF_16V_2

21

20MIL

21

0.1UF_16V_2

21

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 4700~4949(PCH)

U4700

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39

AD40 AD42 AD43 AD45 AD46

AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38

AF42 AF46

AG19

AG31 AG48 AH11

AH36 AH39 AH40 AH42 AH46

AJ19 AJ21 AJ24 AJ33 AJ34 AK12

AC2

AD4

AD8 AE2 AE3

AF4

AF5 AF7 AF8

AG2

AH3

AH7

AK3

VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79]

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

ITL_BD82PPSM_QPJ4_FCBGA_989P

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

U4700

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

ITL_BD82PPSM_QPJ4_FCBGA_989P

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

A3

21-OCT-2002XXX

MODEL,PROJECT,FUNCTION

Block Diagram

CS

X011310xxxxx-0-0

6955

P3V3S_DGPU

DOC.NUMBER

of

INVENTEC

TITLE

DATE

CODE

E

D

C

B

A

7 6 5 4 3 2 1

7 6 5 4 3

E

D

C

B

A

FF

8

CHANGE by

8

REV

2 1

SHEET

SIZE

R5016 R5010 R5011 R5028 R5037 R5014 R5030 R5031 R5027 R5056 R5017

2 1

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

RSC_0402_DY

21

RSC_0402_DY

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2_DY 10K_5%_2

21

10K_5%_2

21

VGA_CRT_HSYNC VGA_CRT_VSYNC

PWRCNTL_0 PWRCNTL_1

PIN BASE STRAPS

GPIO_0 TRANSMITTER POWER SAVING ENABLE

GPIO_2

GPIO_8

GPIO_21

GPIO_9

GPIO_[11:13]

GPIO_22

HSYNC[1] VSYNC[0]

GEN1/GEN2 ENABLE

MUST BE LOW DURING RESET

VGA DISABLE

MEMORY APERTURE SIZE

ENABLE EXTERNAL BIOS ROM DEVICE

AUDIO[1:0]

P3V3S_DGPU

21D3 21D2 5A7 37C6

21D3 21D2 5A7 37C3 56D5

BI

EC_SMB2_CLK

EC_SMB2_DATA

PVPCIE

3

SSM3K7002BFU

P3V3S_DGPU

3

SSM3K7002BFU

P1V8S_DGPU

L5005

FBM_11_160808_121T

10UF_6.3V_3

DS

Q5001

DS

Q5002

GPIO0 GPIO1 GPIO2 GPIO5 GPIO9

GPIO11

GPIO22

0 : 50% TX OUTPUT SWING (DEFAULT) 1 : FULL TX OUTPUT SWING

0 : DE-EMPHASIS DISABLED (DEFAULT)PCIE TRANSMITTER DE-EMPHASISGPIO_1 1 : DE-EMPHASIS ENABLED

0 : GEN1 (DEFAULT) 1 : GEN2

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

56D5

GPIO11:MEMORY APERTURE SIZE 256M

35B2

56D3

35B2

56C5

56D5

13C6

56C5

13C6

LEFT UNCONNECTED

0 : ENABLE (DEFAULT)

1 : DISABLE

GPIO_13

0 : DISABLE (DEFAULT)

1 : ENABLE

GPIO_12

0

1

GPIO_11

MEMORY APERTURE SIZE

0 1 0

1

00 : NO AUDIO FUNCTION

01 : AUDIO FOR DP ONLY

10 : AUDIO FOR DP AND HDMI IF DONGLE IS DETECTED 11 : AUDIO FOR BOTH DP AND HDMI

40B1

1

G

R5094

10K_5%_2

2 1

GPU_SIC

2

1

G

R5095

10K_5%_2

2 1

GPU_SID

2

L5004

FBM_11_160808_121T

21

PVPCIE_DPLL_VDDC

C5016

P1V8S_DGPU

FBM_11_160808_121T

21

C5013

10UF_6.3V_3

2 1

L5006

56D5

BI

P1V8S_DPLL_PVDD

2 1

C5014

1UF_6.3V_2

2 1

21

P1V8S_TSVDD

C5019

10UF_6.3V_3

C5011

2 1

128M

256M

64M

32M

40A8

15D8

OUT

P3V3S_DGPU

R5061

I=75MA TRACE WIDTH>=15MIL

2 1

1UF_6.3V_2

I=125MA TRACE WIDTH>=15MIL

C5015

0.1UF_16V_2

2 1

C5017

1UF_6.3V_2

2 1

P1V8S_DGPU

THRM_SHUTDWN#

SSM3K7002BFU_DY

21

10K_5%_2

10K_5%_2_DY

C5012

2 1

0.1UF_16V_2

21

R5006

R5063

R5007

10K_5%_2_DY

Q5000

21

10K_5%_2

R5005

249_1%_2

C5018

0.1UF_16V_2

2 1

21

R5008

10K_5%_2_DY

34C5

BI

34C5

BI

21E7

OUT

3

DS

G

2

R5015

10K_5%_2

2 1

P1V8S_DGPU

2121

R5003

I=20MA TRACE WIDTH>=15MIL

R5009

10K_5%_2_DY

56F7

56F7 56F7 56C7 56D7 56F7

56F7

1

13C6 56F7

56F7

21

36B5

R5004

499_1%_2

C5010

2 1

C5211

21

10K_5%_2_DY

MEM_ID0 MEM_ID1 MEM_ID2 MEM_ID3

VGA_LVDS_DDCCLK VGA_LVDS_DDCDATA

IN IN

IN BI BI

IN

GPIO0 GPIO1 GPIO2

GPU_SID GPU_SIC

GPIO5

VGA_LCM_BKLTEN

PWRCNTL_0

PWRCNTL_1

GPIO22

TP15

TP30

TP16

TP30

R4

X5000

27MHZ

27PF_50V_2

TP5000

GPIO9

GPIO11

1

VGA_HPDET

P0V6S_VREFG

21

C5212

TP30

IN

OUT

IN

1

R5060

10K_5%_2

IN

0.1UF_16V_2

1M_5%_2

2 1

TP14

TP30

TP11

TP30

TP12

TP30

2 1

1

27PF_50V_2

AR8 AU8 AP8 AW8 AR3 AR1 AU1 AU3 AW3 AP6 AW5 AU5 AR6 AW6 AU6 AT7 AV7 AN7 AV9

AT9 AR10 AW10 AU10 AP10 AV11 AT11 AR12 AW12 AU12 AP12

AJ21 AK21

AK26 AJ26

AH20 AH18 AN16 AH23 AJ23 AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17 AL13 AJ14 AK13 AN13 AM23 AN23 AK23 AL24 AM24 AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24

AK24

AH13

AM32 AN32

AN31

AV33 AU34

AW34

AW35

AF29 AG29

AK32

AL31

AJ32 AJ33

U5001

MUTI GFX

DVPCNTL_MVP_0 DVPCNTL_MVP_1 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2

DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23

SWAPLOCKA SWAPLOCKB

I2C

SCL SDA

GENERAL PURPOSE I/O

GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCSB GPIO_23_CLKREQB JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF_HPD5 GENERICG_HPD6

HPD1

VREFG

DPLL_PVDD DPLL_PVSS

PLL/CLOCK

DPLL_VDDC

XTALIN XTALOUT

XO_IN

XO_IN2

DPLUS DMINUS

TS_FDO

TS_A/NC

TSVDD TSVSS

AMD_216_0833002_FCBGA_962P

THERMAL

DPA

DPB

DPC

DPD

DAC1

DAC2

DDC/AUX

TXCAP_DPA3P TXCAM_DPA3N

TX0P_DPA2P TX0M_DPA2N

TX1P_DPA1P TX1M_DPA1N

TX2P_DPA0P TX2M_DPA0N

TXCBP_DPB3P TXCBM_DPB3N

TX3P_DPB2P TX3M_DPB2N

TX4P_DPB1P TX4M_DPB1N

TX5P_DPB0P TX5M_DPB0N

TXCCP_DPC3P TXCCM_DPC3N

TX0P_DPC2P TX0M_DPC2N

TX1P_DPC1P TX1M_DPC1N

TX2P_DPC0P TX2M_DPC0N

TXCDP_DPD3P TXCDM_DPD3N

TX3P_DPD2P TX3M_DPD2N

TX4P_DPD1P TX4M_DPD1N

TX5P_DPD0P TX5M_DPD0N

H2SYNC/GENLK_CLK

V2SYNC/GENLK_VSYNC

VDD2DI/NC VSS2DI/NC

A2VDDQ/NC

A2VSSQ/TSVSSQ

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX5P

DDCDATA_AUX5N

DDCCLK_AUX7P

DDCDATA_AUX7N

VDD1DI VSS1DI

R2B/NC

G2B/NC

B2B/NC

COMP/NC

A2VDD/NC

R2SET/NC

DDC1CLK

DDC1DATA

DDC2CLK

DDC2DATA

DDC6CLK

DDC6DATA

HSYNC VSYNC

RSET

AVDD

AVSSQ

R2/NC

G2/NC

B2/NC

C/NC Y/NC

AUX1P AUX1N

AUX2P AUX2N

MEM_ID3

THAMES (6019B0917601)

AU24 AV23

AT25 AR24

AU26 AV25

AT27 AR26

AR30 AT29

AV31 AU30

AR32 AT31

AT33 AU32

AU14 AV13

AT15 AR14

AU16 AV15

AT17 AR16

AU20 AT19

AT21 AR20

AU22 AV21

AT23 AR22

AD39

R

RB

GB

BB

AD37

AE36

G

AD35

AF37

B

AE38

AC36 AC38

AB34

AD34 AE34

AC33 AC34

AC30 AC31

AD30 AD31

AF30 AF31

AC32 AD32 AF32

AD29 AC29

AG31 AG32

AG33

AD33

AF33

AA29

AM26 AN26

AM27 AL27

AM19 AL19

AN20 AM20

AL30 AM30

AL29 AM29

AN21 AM21

AJ30 AJ31

AK30 AK29

VGA_HDMI_TXC_DP VGA_HDMI_TXC_DN

VGA_HDMI_TX0_DP VGA_HDMI_TX0_DN

VGA_HDMI_TX1_DP VGA_HDMI_TX1_DN

VGA_HDMI_TX2_DP VGA_HDMI_TX2_DN

VGA_CRTR

VGA_CRTG

VGA_CRTB

VGA_CRT_HSYNC VGA_CRT_VSYNC

R5000

499_1%_2

VGA_HDMI_DDCCLK VGA_HDMI_DDCDATA

VGA_CRT_DDCCLK VGA_CRT_DDCDATA

21

0.1UF_16V_2

36A5

OUT

36A5

OUT

36A5

OUT

36A5

OUT

36A5

OUT

36A5

OUT

36A5

OUT

36A5

OUT

35D8

56F7

35B2 35B2

56F7

56E2

OUT

OUT OUT

I=100MA TRACE WIDTH>=15MIL

2 1

36D8

BI

36D8

BI

35A2

BI

35B2

BI

P1V8S_VDD1DI

1UF_6.3V_2

2 1

56D3

I=70MA TRACE WIDTH>=15MIL

L5001

2 1

FBM_11_160808_121T

C5004C5002C5003

10UF_6.3V_3

2 1

PLACE CLOSE TO ASIC

35D8

IN

35D8 56D3

IN

35D8 56D3

IN

0.1UF_16V_2

2 1

P1V8S_DGPU

MEM_ID2 MEM_ID1 MEM_ID0 0 0 0 0 0 0 0 0 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0

0 1 1 1

VGA_CRTR

VGA_CRTG

VGA_CRTB

1

1 1

R5072

R5073

R5074

P1V8S_AVDD

1UF_6.3V_2

2 1

0 0 1 1 0 0 1 1

0 1 1 01 0

150_1%_2

21

150_1%_2

21

150_1%_2

21

FBM_11_160808_121T

C5005C5000C5001

10UF_6.3V_3

2 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

L5000

2 1

HYNIX1GDFR*4 512MB HYNIX2GBFR*4 1GB HYNIX2GDFR*41GB RESERVE HYNIX1GDFR*8 1GB HYNIX2GBFR*8 2GB HYNIX2GDFR*82GB RESERVE AMDC11*4 512MB AMDA11*4 1GB AMDB11*4 1GB RESERVE AMDC11*8 1HB AMDA11*8 2GB AMDB11*8 2GB RESERVE1 11

P1V8S_DGPU

MODEL,PROJECT,FUNCTION

XXX 21-OCT-2002

Block Diagram

C CS

1310xxxxx-0-0

56 69

X01

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

U5001

42B1

BI

42D1

BI

42B1

BI

42D1

BI

42B1

BI

42D1

BI

42B1 42C1

42A1 42C1

BI BI

PEG_C_TX0_DP PEG_C_TX0_DN

PEG_C_TX1_DP PEG_C_TX1_DN

PEG_C_TX2_DP PEG_C_TX2_DN

PEG_C_TX3_DP PEG_C_TX3_DN

PEG_C_TX4_DP PEG_C_TX4_DN

PEG_C_TX5_DP PEG_C_TX5_DN

PEG_C_TX6_DP PEG_C_TX6_DN

PEG_C_TX7_DP PEG_C_TX7_DN

PEG_C_TX8_DP PEG_C_TX8_DN

PEG_C_TX9_DP PEG_C_TX9_DN

PEG_C_TX10_DP PEG_C_TX10_DN

AA38

Y37

Y35 W36

W38 V37

V35 U36

U38 T37

T35 R36

R38 P37

P35 N36

N38 M37

M35 L36

L38 K37

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

PCIE_RX8P PCIE_RX8N

PCIE_RX9P PCIE_RX9N

PCIE_RX10P PCIE_RX10N

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P

PCI EXPRESS INTERFACE

PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

Y33 Y32

W33 W32

U33 U32

U30 U29

T33 T32

T30 T29

P33 P32

P30 P29

N33 N32

N30 N29

L33 L32

C5022 C5023

C5024 C5025

C5026 C5027

C5028 C5029

C5030 C5031

C5032 C5033

C5034 C5035

C5036 C5037

C5038 C5039

C5040 C5041

C5042 C5043

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

PEG_C_RX0_DPPEG_RX0_DP PEG_C_RX0_DNPEG_RX0_DN

PEG_C_RX1_DPPEG_RX1_DP PEG_C_RX1_DNPEG_RX1_DN

PEG_C_RX2_DPPEG_RX2_DP PEG_C_RX2_DNPEG_RX2_DN

PEG_C_RX3_DPPEG_RX3_DP PEG_C_RX3_DNPEG_RX3_DN

PEG_C_RX4_DPPEG_RX4_DP PEG_C_RX4_DNPEG_RX4_DN

PEG_C_RX5_DPPEG_RX5_DP PEG_C_RX5_DNPEG_RX5_DN

PEG_C_RX6_DPPEG_RX6_DP PEG_C_RX6_DNPEG_RX6_DN

PEG_C_RX7_DPPEG_RX7_DP PEG_C_RX7_DNPEG_RX7_DN

PEG_C_RX8_DPPEG_RX8_DP PEG_C_RX8_DNPEG_RX8_DN

PEG_C_RX9_DPPEG_RX9_DP PEG_C_RX9_DNPEG_RX9_DN

PEG_C_RX10_DPPEG_RX10_DP PEG_C_RX10_DNPEG_RX10_DN

42C4

BI

42C4

BI

42C4

BI

42C4

BI

42C4

BI

42D4

BI

42C4

BI BI

42D4

42C4 42D4

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

1.27K_1%_2

2K_1%_2

PEG_C_RX11_DPPEG_RX11_DP PEG_C_RX11_DNPEG_RX11_DN

PEG_C_RX12_DPPEG_RX12_DP PEG_C_RX12_DNPEG_RX12_DN

PEG_C_RX13_DPPEG_RX13_DP PEG_C_RX13_DNPEG_RX13_DN

PEG_C_RX14_DP PEG_C_RX14_DN

PEG_C_RX15_DP PEG_C_RX15_DN

PVPCIE

42C4

BI

42D4

BI

42C4

BI

42D4

BI

42C4

BI

42D4

BI

42C4

BI

42D4

BI

BI BI

42C4 42D4

AB35 AA36

AH16

AA30

K35 J36

J38 H37

H35 G36

G38 F37

F35 E37

PCIE_RX11P PCIE_RX11N

PCIE_RX12P PCIE_RX12N

PCIE_RX13P PCIE_RX13N

PCIE_RX14P PCIE_RX14N

PCIE_RX15P PCIE_RX15N

CLOCK

PCIE_REFCLKP PCIE_REFCLKN

PERSTB

AMD_216_0833002_FCBGA_962P

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

CALIBRATION

PCIE_CALRP

PCIE_CALRNPWRGOOD

42A1

BI

42C1

BI

42A1

BI

42C1

U5001

LVDS CONTROL

VARY_BL

DIGON

AK27 AJ27

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

AF35 AG36

VGA_LVDS_TXCL_DP

AP34

VGA_LVDS_TXCL_DN

AR34

VGA_LVDS_TXDL0_DP

AW37

VGA_LVDS_TXDL0_DN

AU35

VGA_LVDS_TXDL1_DP

AR37

VGA_LVDS_TXDL1_DN

AU39

VGA_LVDS_TXDL2_DP

AP35

VGA_LVDS_TXDL2_DN

AR35

AN36 AP37

LVTMDP

TXCLK_UP_DPF3P TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N

TXOUT_U3P TXOUT_U3N

TXCLK_LP_DPE3P TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N

TXOUT_L3P TXOUT_L3N

VGA_INV_PWM_3 VGA_LCM_VDDEN

21

R5071

10K_5%_2

34B5

OUT

34D7

OUT

34A8

BI

34A8

BI

34A8

BI

34A8

BI

34A8

BI

34A8

BI

34A8

BI

34A8

BI

27C3

21E3 51A8 27C7

28C3 51B6

51C7

IN IN

BI

42A1

BI

42C1

BI

42A1

BI

42B1

BI

42A1

BI

42B1

BI

48C3

BI

48C3

BI

BUF_PLT_RST#

DGPU_HOLD_RST#

PEG_C_TX11_DP PEG_C_TX11_DN

PEG_C_TX12_DP PEG_C_TX12_DN

PEG_C_TX13_DP PEG_C_TX13_DN

PEG_C_TX14_DP PEG_C_TX14_DN

PEG_C_TX15_DP PEG_C_TX15_DN

CLK_PEG_REF_DP CLK_PEG_REF_DN

R5013

P3V3S_DGPU

+-

1

2

TC7SZ08FU

R5039

1K_5%_2

0_5%_2_DY

21

5

U5005

3

DGPU_PERST

4

21

L30 L29

K33 K32

J33 J32

K30 K29

H33 H32

Y30

Y29

PEG_RX14_DP PEG_RX14_DN

PEG_RX15_DP PEG_RX15_DN

GPU_PCIE_CALRP

GPU_PCIE_CALRN

C5044 C5045

C5046 C5047

C5048 C5049

C5050 C5051

C5052 C5053

R5035

R5034

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6957

AMD_216_0833002_FCBGA_962P

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

U5001U5001

DDR2 GDDR3/GDDR5

DQA<0>

62D1

62D5 63D5

63D1

BI

P1V5S_DGPU

R5052

2 1

40.2_1%_2100_1%_2

P1V5S_DGPU

R5053R5023

2 12 1

40.2_1%_2

R5045

C5204

2 1

P1V5S_DGPU

R5033 R5022

C5205

100_1%_2

2 1

0.1UF_16V_2

R5058

R5048 R5047 R5050

0

DQA<1>

1

DQA<2>

2

DQA<3>

3

DQA<4>

4

DQA<5>

5

DQA<6>

6

DQA<7>

7

DQA<8>

8

DQA<9>

9

DQA<10>

10

DQA<11>

11

DQA<12>

12

DQA<13>

13

DQA<14>

14

DQA<15>

15

DQA<16>

16

DQA<17>

17

DQA<18>

18

DQA<19>

19

DQA<20>

20

DQA<21>

21

DQA<22>

22

DQA<23>

23

DQA<24>

24

DQA<25>

25

DQA<26>

26

DQA<27>

27

DQA<28>

28

DQA<29>

29

DQA<30>

30

DQA<31>

31

DQA<32>

32

DQA<33>

33

DQA<34>

34

DQA<35>

35

DQA<36>

36

DQA<37>

37

DQA<38>

38

DQA<39>

39

DQA<40>

40

DQA<41>

41

DQA<42>

42

DQA<43>

43

DQA<44>

44

DQA<45>

45

DQA<46>

46

DQA<47>

47

DQA<48>

48

DQA<49>

49

DQA<50>

50

DQA<51>

51

DQA<52>

52

DQA<53>

53

DQA<54>

54 54

DQA<55>

55

DQA<56>

56

DQA<57>

57

DQA<58>

58

DQA<59>

59

DQA<60>

60

DQA<61>

61

0.1UF_16V_2

P1V05_REFDA_GPU P1V05_REFSA_GPU

62 63

DQA<62> DQA<63>

21

243_1%_2

21

RSC_0402_DY

21

243_1%_2

21

RSC_0402_DY

21

243_1%_2

21

243_1%_2

AG12

AH12

C37 C35 A35 E34 G32 D33 F32 E32 D31 F30 C30 A30 F28 C28 A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13 J13 H11 G10

K10

L18 L20

L27 N12

M12 M27

G8 K9

G9 A8 C8 E8 A6 C6 E6 A5

DDR3

DQA0_0/DQA_0 DQA0_1/DQA_1 DQA0_2/DQA_2 DQA0_3/DQA_3 DQA0_4/DQA_4 DQA0_5/DQA_5 DQA0_6/DQA_6 DQA0_7/DQA_7 DQA0_8/DQA_8 DQA0_9/DQA_9 DQA0_10/DQA_10 DQA0_11/DQA_11 DQA0_12/DQA_12 DQA0_13/DQA_13 DQA0_14/DQA_14 DQA0_15/DQA_15 DQA0_16/DQA_16 DQA0_17/DQA_17 DQA0_18/DQA_18 DQA0_19/DQA_19 DQA0_20/DQA_20 DQA0_21/DQA_21 DQA0_22/DQA_22 DQA0_23/DQA_23 DQA0_24/DQA_24 DQA0_25/DQA_25 DQA0_26/DQA_26 DQA0_27/DQA_27 DQA0_28/DQA_28 DQA0_29/DQA_29 DQA0_30/DQA_30 DQA0_31/DQA_31 DQA1_0/DQA_32 DQA1_1/DQA_33 DQA1_2/DQA_34 DQA1_3/DQA_35 DQA1_4/DQA_36 DQA1_5/DQA_37 DQA1_6/DQA_38 DQA1_7/DQA_39 DQA1_8/DQA_40 DQA1_9/DQA_41 DQA1_10/DQA_42 DQA1_11/DQA_43 DQA1_12/DQA_44 DQA1_13/DQA_45 DQA1_14/DQA_46 DQA1_15/DQA_47 DQA1_16/DQA_48 DQA1_17/DQA_49 DQA1_18/DQA_50 DQA1_19/DQA_51 DQA1_20/DQA_52 DQA1_21/DQA_53 DQA1_22/DQA_54 DQA1_23/DQA_55 DQA1_24/DQA_56 DQA1_25/DQA_57 DQA1_26/DQA_58 DQA1_27/DQA_59 DQA1_28/DQA_60 DQA1_29/DQA_61 DQA1_30/DQA_62 DQA1_31/DQA_63

MVREFDA MVREFSA

MEM_CALRN0 MEM_CALRN1 MEM_CALRN2

MEM_CALRP1 MEM_CALRP0 MEM_CALRP2

MEMORY INTERFACE A

DDR2 GDDR5/GDDR3 DDR3

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8

MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12

MAA1_5/MAA_13_BA2 MAA1_6/MAA_14_BA0

MAA1_7/MAA_A15_BA1

WCKA0_0/DQMA_0

WCKA0B_0/DQMA_1

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

GDDR5/DDR2/GDDR3

EDCA0_0/QSA_0/RDQSA_0 EDCA0_1/QSA_1/RDQSA_1 EDCA0_2/QSA_2/RDQSA_2 EDCA0_3/QSA_3/RDQSA_3 EDCA1_0/QSA_4/RDQSA_4 EDCA1_1/QSA_5/RDQSA_5 EDCA1_2/QSA_6/RDQSA_6 EDCA1_3/QSA_7/RDQSA_7

DDBIA0_0/QSA_0B/WDQSA_0 DDBIA0_1/QSA_1B/WDQSA_1 DDBIA0_2/QSA_2B/WDQSA_2 DDBIA0_3/QSA_3B/WDQSA_3 DDBIA1_0/QSA_4B/WDQSA_4 DDBIA1_1/QSA_5B/WDQSA_5 DDBIA1_2/QSA_6B/WDQSA_6 DDBIA1_3/QSA_7B/WDQSA_7

ADBIA0/ODTA0

ADBIA1/ODTA1

GDDR5

CLKA0B

CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

MAA0_8 MAA1_8

CLKA0

CLKA1

CKEA0 CKEA1

WEA0B WEA1B

G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17

A32 C32 D23 E22 C14 A14 E10 D9

C34 D29 D25 E20 E16 E12 J10 D7

A34 E30 E26 C20 C16 C12 J11 F8

J21 G19

H27 G27

J14 H14

K23 K19

K20 K17

K24 K27

M13 K16

K21 J20

K26 L15

H23 J19

MAA<0> MAA<1> MAA<2> MAA<3> MAA<4> MAA<5> MAA<6> MAA<7> MAA<8> MAA<9> MAA<10> MAA<11> MAA<12>

MAA_BA<2> MAA_BA<0> MAA_BA<1>

DQMA<0> DQMA<1> DQMA<2> DQMA<3> DQMA<4> DQMA<5> DQMA<6> DQMA<7>

DQSA0_DP DQSA1_DP DQSA2_DP DQSA3_DP DQSA4_DP DQSA5_DP DQSA6_DP DQSA7_DP

DQSA0_DN DQSA1_DN DQSA2_DN DQSA3_DN DQSA4_DN DQSA5_DN DQSA6_DN DQSA7_DN

ODTA0 ODTA1

CLKA0_DP CLKA0_DN

CLKA1_DP CLKA1_DN

RASA0# RASA1#

CASA0# CASA1#

CSA0#_0

CSA1#_0

CKEA0 CKEA1

WEA0# WEA1#

MAA<13>

21

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

55 56 57 58 59 60 61 62 63

DQB<0> DQB<1> DQB<2> DQB<3> DQB<4> DQB<5> DQB<6> DQB<7> DQB<8> DQB<9> DQB<10> DQB<11> DQB<12> DQB<13> DQB<14> DQB<15> DQB<16> DQB<17> DQB<18> DQB<19> DQB<20> DQB<21> DQB<22> DQB<23> DQB<24> DQB<25> DQB<26> DQB<27> DQB<28> DQB<29> DQB<30> DQB<31> DQB<32> DQB<33> DQB<34> DQB<35> DQB<36> DQB<37> DQB<38> DQB<39> DQB<40> DQB<41> DQB<42> DQB<43> DQB<44> DQB<45> DQB<46> DQB<47> DQB<48> DQB<49> DQB<50> DQB<51> DQB<52> DQB<53> DQB<54> DQB<55> DQB<56> DQB<57> DQB<58> DQB<59> DQB<60> DQB<61> DQB<62> DQB<63>

1

TP13

TP30

AA12

AD28

AK10 AL10

AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6 AG4 AH5 AH6 AJ4 AK3 AF8 AF9 AG8 AG7 AK9 AL7 AM8 AM7 AK1 AL4 AM6 AM1 AN4 AP3 AP1 AP5

Y12

C5 C3 E3 E1 F1 F3 F5 G4 H5 H6 J4 K6 K5 L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5

MAA<12..0>DQA<63..0>

0 1 2 3 4 5 6 7 8

9 10 11 12

OUT OUT OUT

BI BI BI BI BI BI BI BI

BI BI

62B3 62D4 62D7

OUT

62B5 62C4

OUT

62C7 63B4 63D4 63D8

OUT

63B5 63C8 63D4

OUT

62C4 62C7

OUT

63C4 63C8

OUT

62C4

OUT

63C4

OUT

62C4 62C7

OUT

63C4 63C8

OUT

62C4 62C7

OUT

63C4 63C8

OUT

62C4 62C7

OUT

63C4

OUT

62D4 62D8

OUT

63D4

OUT

62D4 62D7 63D4 62D4 62D7 63D4 62D4 62D7

62C7 62C7 62C4 62C4 63C4 63C4 63C8 63C8

62C4 62C7

63C8

63C4

62C7 63C8

P1V5S_DGPU

R5020

63C8

R5021

63D8

BI

63D8 63D8

63D4 63D8

P1V5S_DGPU

2 1

40.2_1%_2

C5202

100_1%_2

2 1

R5001

2 1

R5002

2 1

40.2_1%_2

C5201

100_1%_2

2 1

P3V3S_DGPU

5.11K_1%_2_DY

0.1UF_16V_2

P1V05_REFDB_GPU

P1V05_REFSB_GPU

R5012

THAMES

R5022 OPEN R5048 OPEN

SEYMOUR

R5022 STUFF

AMD_216_0833002_FCBGA_962P

R5024

2 1

1K_5%_2

DDR2 GDDR3/GDDR5 DDR3

DQB0_0/DQB_0 DQB0_1/DQB_1 DQB0_2/DQB_2 DQB0_3/DQB_3 DQB0_4/DQB_4 DQB0_5/DQB_5 DQB0_6/DQB_6 DQB0_7/DQB_7 DQB0_8/DQB_8 DQB0_9/DQB_9 DQB0_10/DQB_10 DQB0_11/DQB_11 DQB0_12/DQB_12 DQB0_13/DQB_13 DQB0_14/DQB_14 DQB0_15/DQB_15 DQB0_16/DQB_16 DQB0_17/DQB_17 DQB0_18/DQB_18 DQB0_19/DQB_19 DQB0_20/DQB_20 DQB0_21/DQB_21 DQB0_22/DQB_22 DQB0_23/DQB_23 DQB0_24/DQB_24 DQB0_25/DQB_25 DQB0_26/DQB_26 DQB0_27/DQB_27 DQB0_28/DQB_28 DQB0_29/DQB_29 DQB0_30/DQB_30 DQB0_31/DQB_31 DQB1_0/DQB_32 DQB1_1/DQB_33 DQB1_2/DQB_34 DQB1_3/DQB_35 DQB1_4/DQB_36 DQB1_5/DQB_37 DQB1_6/DQB_38 DQB1_7/DQB_39 DQB1_8/DQB_40 DQB1_9/DQB_41 DQB1_10/DQB_42 DQB1_11/DQB_43 DQB1_12/DQB_44 DQB1_13/DQB_45 DQB1_14/DQB_46 DQB1_15/DQB_47 DQB1_16/DQB_48 DQB1_17/DQB_49 DQB1_18/DQB_50 DQB1_19/DQB_51 DQB1_20/DQB_52 DQB1_21/DQB_53 DQB1_22/DQB_54 DQB1_23/DQB_55 DQB1_24/DQB_56 DQB1_25/DQB_57 DQB1_26/DQB_58 DQB1_27/DQB_59 DQB1_28/DQB_60 DQB1_29/DQB_61 DQB1_30/DQB_62 DQB1_31/DQB_63

MVREFDB MVREFSB

TESTEN

CLKTESTA CLKTESTB

MEMORY INTERFACE B

AMD_216_0833002_FCBGA_962P

DDR2 GDDR5/GDDR3 DDR3

MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8

MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12

WCKB0_0/DQMB_0

WCKB0B_0/DQMB_1

WCKB0_1/DQMB_2

WCKB0B_1/DQMB_3

WCKB1_0/DQMB_4

WCKB1B_0/DQMB_5

WCKB1_1/DQMB_6

WCKB1B_1/DQMB_7

GDDR5/DDR2/GDDR3

EDCB0_0/QSB_0/RDQSB_0 EDCB0_1/QSB_1/RDQSB_1 EDCB0_2/QSB_2/RDQSB_2 EDCB0_3/QSB_3/RDQSB_3 EDCB1_0/QSB_4/RDQSB_4 EDCB1_1/QSB_5/RDQSB_5 EDCB1_2/QSB_6/RDQSB_6 EDCB1_3/QSB_7/RDQSB_7

DDBIB0_0/QSB_0B/WDQSB_0 DDBIB0_1/QSB_1B/WDQSB_1 DDBIB0_2/QSB_2B/WDQSB_2 DDBIB0_3/QSB_3B/WDQSB_3 DDBIB1_0/QSB_4B/WDQSB_4 DDBIB1_1/QSB_5B/WDQSB_5 DDBIB1_2/QSB_6B/WDQSB_6 DDBIB1_3/QSB_7B/WDQSB_7

ADBIB0/ODTB0

ADBIB1/ODTB1

GDDR5

MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1

CSB0B_0 CSB0B_1

CSB1B_0 CSB1B_1

DRAM_RST

CLKB0

CLKB0B

CLKB1

CLKB1B

RASB0B RASB1B

CASB0B CASB1B

CKEB0 CKEB1

WEB0B WEB1B

MAB0_8 MAB1_8

P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9

H3 H1 T3 T5 AE4 AF5 AK6 AK5

F6 K3 P3 V5 AB5 AH1 AJ9 AM5

G7 K1 P1 W4 AC4 AH3 AJ8 AM3

T7 W7

L9 L8

AD8 AD7

T10 Y10

W10 AA10

P10 L10

AD10 AC10

U10 AA11

N10 AB11

T8 W8

AH11

MAB<0> MAB<1> MAB<2> MAB<3> MAB<4> MAB<5> MAB<6> MAB<7> MAB<8> MAB<9> MAB<10> MAB<11> MAB<12>

MAB_BA<2> MAB_BA<0> MAB_BA<1>

DQMB<0> DQMB<1> DQMB<2> DQMB<3> DQMB<4> DQMB<5> DQMB<6> DQMB<7>

DQSB0_DP DQSB1_DP DQSB2_DP DQSB3_DP DQSB4_DP DQSB5_DP DQSB6_DP DQSB7_DP

DQSB0_DN DQSB1_DN DQSB2_DN DQSB3_DN DQSB4_DN DQSB5_DN DQSB6_DN DQSB7_DN

ODTB0 ODTB1

CLKB0_DP CLKB0_DN

CLKB1_DP CLKB1_DN

RASB0# RASB1#

CASB0# CASB1#

CSB0#_0

CSB1#_0

MAB<13>

R5029

10_5%_2

R5025

2 1

5.1K_1%_2

CKEB0 CKEB1

WEB0# WEB1#

10 11 12

21

C5200

0 1 2 3 4 5 6 7 8 9

2 1

51_5%_2

MAB<12..0>DQB<63..0>

64D4 64D7 65D4

OUT

65D8

OUT

64D4

OUT

64D7 65D4 65D8

64C7

BI

64C4

BI

64C4

BI

64C7

BI

65C4

BI

65C4

BI

65C8

BI

65C8

BI

64C7

BI

64C4

BI

64C4

BI

64C7

BI

65C4

BI

65C4

BI

65C8

BI

65C8

BI

64C7

BI

64C4

BI

64C4

BI

64C7

BI

65C4

BI

65C4

BI

65C8

BI

65C8

BI

64C4 64C7

BI

65C4 65C8

BI

64B3 64D4 64D7

OUT

64B5 64C4 64C7

OUT

65B4 65D4 65D8

OUT

65B5 65C8 65D4

OUT

64C4 64C7

OUT

65C4 65C8

OUT

64C4 64C7

OUT

65C4 65C8

OUT

64C4 64C7

OUT

65C4 65C8

OUT

64C4 64C7

OUT

65C4 65C8

OUT

64C4 64C7

OUT

65C4 65C8

OUT

64D4 64D7 65D4 65D8

OUT

R5032

VM_RESET

21

120PF_50V_2

OUT

64D4 64D7 65D4 65D8

65D4 64D4 64D7 65D8

OUT

R5048 STUFF

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6958

A3

21-OCT-2002XXX

DOC.NUMBER

of

INVENTEC

TITLE

DATE

CODE

E

D

C

B

A

7 6 5 4 3 2 1

7 6 5 4 3

E

D

C

B

A

FF

8

CHANGE by

8

REV

2 1

SHEET

SIZE

P1V5S_DGPU

AC7

AD11

AF7

AG10

AJ7

1UF_6.3V_2

AF26 AF27 AG26 AG27

AF23 AF24 AG23 AG24

AF13 AF15 AG13 AG15

AD12 AF11 AF12 AG11

AM10

AN10

AF28

AG28

AH29

AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10

K11 K13

L12 L16 L21 L23 L26

M11 N11

R11 U11

Y11

M20 M21

V12 U12

AN9

J7 J9

K8

L7

P7

U7

Y7

H7 H8

C5077

2 1

C5078

1UF_6.3V_2

2 1

C5079

1UF_6.3V_2

2 1

C5080

1UF_6.3V_2

2 1

C5081

1UF_6.3V_2

2 1

C5082

1UF_6.3V_2

2 1

C5083

1UF_6.3V_2

2 1

C5084

1UF_6.3V_2

2 1

C5085

2 1

1UF_6.3V_2

C5086

1UF_6.3V_2

2 1

10UF_6.3V_3

P3V3S_DGPU

P1V8S_DGPU

P1V8S_MPV

0.1UF_16V_2

C5088

C5089

2 1

10UF_6.3V_3

C5093

2 1

10UF_6.3V_3

C5098

L5010

FBM_11_160808_121T

P1V8S_DGPU

L5015

FBM_11_160808_121T

C5090

10UF_6.3V_3

1.8V_110MA

C5094

2 1

10UF_6.3V_3

2 1

10UF_6.3V_3

C5095

1UF_6.3V_2

C5099

2 1

21

P1V8S_SPV18

21

C5091

2 1

C5106

C5206

C5092

10UF_6.3V_3

C5096

1UF_6.3V_2

C5100

1UF_6.3V_2

2 1

1UF_6.3V_2

2 1

10UF_6.3V_3

2 1

C5102

C5207

10UF_6.3V_3

C5097

1UF_6.3V_2

C5101

1UF_6.3V_2

2 1

1UF_6.3V_2

2 1

1UF_6.3V_2

2 1

C5103

C5208

0.1UF_16V_21UF_6.3V_2

2 1

0.1UF_16V_2

2 1

P1V8S_VDDCT

P1V8S_VDDR4

C5108

2 1

0.1UF_16V_2

C5087

P1V8S_DGPU

L5009

21

FBM_11_160808_121T

P1V8S_DGPU

FBM_11_160808_121T

L5014

21

2 1

C5107

2 1

1UF_6.3V_2

C5104

C5105

2 1

10UF_6.3V_3

PVPCIE

L5016

FBM_11_160808_121T

21

PVPCIE_SPV10

C5209

2 1

C5210

2 1

10UF_6.3V_3

C5213

2 1

1UF_6.3V_2

0.1UF_16V_2

MEM I/O

VDDR1#1 VDDR1#2 VDDR1#3 VDDR1#4 VDDR1#5 VDDR1#6 VDDR1#7 VDDR1#8 VDDR1#9 VDDR1#10 VDDR1#11 VDDR1#12 VDDR1#13 VDDR1#14 VDDR1#15 VDDR1#16 VDDR1#17 VDDR1#18 VDDR1#19 VDDR1#20 VDDR1#21 VDDR1#22 VDDR1#23 VDDR1#24 VDDR1#25 VDDR1#26 VDDR1#27 VDDR1#28 VDDR1#29 VDDR1#30 VDDR1#31 VDDR1#32 VDDR1#33 VDDR1#34

LEVEL TRANSLATION

VDD_CT#1 VDD_CT#2 VDD_CT#3 VDD_CT#4

I/O

VDDR3#1 VDDR3#2 VDDR3#3 VDDR3#4

VDDR4#4 VDDR4#5 VDDR4#7 VDDR4#8

VDDR4#1 VDDR4#2 VDDR4#3 VDDR4#6

NC_VDDRHA NC_VSSRHA

NC_VDDRHB NC_VSSRHB

PLL

MPV18#1 MPV18#2

SPV18

SPV10

SPVSS

VOLTAGE SENESE

FB_VDDC

FB_VDDCI

FB_GND

PCIE

PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8

PCIE_VDDR/PCIE_PVDD

PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8

PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12

CORE

POWER

VDDC/BIF_VDDC#33

VDDC/BIF_VDDC#42

ISOLATED CORE I/O

VDDC#1 VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8

VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15 VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23 VDDC#24 VDDC#25 VDDC#26 VDDC#27 VDDC#28 VDDC#29 VDDC#30 VDDC#31 VDDC#32

VDDC#34 VDDC#35 VDDC#36 VDDC#37 VDDC#38 VDDC#39 VDDC#40 VDDC#41

VDDC#43 VDDC#44 VDDC#45 VDDC#46 VDDC#47 VDDC#48 VDDC#49 VDDC#50 VDDC#51 VDDC#52 VDDC#53 VDDC#54 VDDC#55 VDDC#56 VDDC#57 VDDC#58

VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8 VDDCI#9

VDDCI#10 VDDCI#11 VDDCI#12 VDDCI#13 VDDCI#14 VDDCI#15 VDDCI#16 VDDCI#17 VDDCI#18 VDDCI#19 VDDCI#20 VDDCI#21 VDDCI#22

AA31 AA32 AA33 AA34 V28 W29 W30 Y31 AB37

G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 AH27 AH28

PVCORE_DGPU

M26 N24 N27 R18 R21 R23 R26 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

P1V8S_PCIE_VDDR

C5119

2 1

C5266

1UF_6.3V_2

C5265

C5110

0.1UF_16V_2

2 1

1UF_6.3V_2

C5188

2 1

C5167

2 1

C5120

2 1

C5166

2 1

1UF_6.3V_2

10UF_6.3V_3

C5111

2 1

0.01UF_50V_2

C5121

0.1UF_16V_2

C5129

2 1

1UF_6.3V_21UF_6.3V_2

C5143

2 1

C5147C5159

2 12 1

1UF_6.3V_2

10UF_6.3V_3

C5189

2 1

C5168

2 1

C5112

0.1UF_16V_2

2 1

1UF_6.3V_2

C5130

C5144

C5148

2 1

C5160

2 1

C5190

1UF_6.3V_2

C5169

10UF_6.3V_3

2 1

C5122

2 1

1UF_6.3V_2

10UF_6.3V_3

2 1

1.8V_504MA

1UF_6.3V_2

2 1

1UF_6.3V_2

C5132

2 1

1UF_6.3V_2

C5145

1UF_6.3V_2

C5150

2 1

C5161

2 1

C5191

1UF_6.3V_2

10UF_6.3V_3

C5113

2 1

C5123

2 1

1UF_6.3V_2

2 1

1UF_6.3V_2

10UF_6.3V_3

2 1

C5114

1UF_6.3V_2

C5124

1UF_6.3V_2

C5133

2 1

C5146

2 1

C5151

2 1

C5163

2 1

C5192

2 1

1UF_6.3V_2

2 1

1UF_6.3V_2

2 1

1UF_6.3V_2

C5152

1UF_6.3V_2

C5164

10UF_6.3V_3

1UF_6.3V_2

C5134

2 1

C5193

C5115

2 1

C5125

2 1

1UF_6.3V_2

10UF_6.3V_3

2 1

10UF_6.3V_3

1UF_6.3V_2

C5135

1UF_6.3V_2

C5153

2 1

C5165

2 1

C5195

1UF_6.3V_2

PVPCIE

C5126

2 1

1UF_6.3V_2

C5154

1UF_6.3V_2

10UF_6.3V_3

PVCORE_DGPU

2 1

1UF_6.3V_2

L5013

BLM18PG600SN1D

10UF_6.3V_3

PVCORE_DGPU

C5136

2 1

1UF_6.3V_2

2 1

1UF_6.3V_2

C5197

2 1

1UF_6.3V_2

P1V8S_DGPU

21

U5001

AMD_216_0833002_FCBGA_962P

MODEL,PROJECT,FUNCTION

Block Diagram

CSC

1310xxxxx-0-0

59 69

XXX 21-OCT-2002

X01

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

P1V8S_DGPU P1V8S_DGPU

L5019

BLM18PG600SN1D

21

C5226

2 1

60C6

60B3 60B3 60C3

C5227

10UF_6.3V_3

IN

2 1

DPCD_VDD18

C5228

2 1

1UF_6.3V_2

DPCD_VDD18

0.1UF_16V_21UF_6.3V_2

AP20 AP21

AP13 AT13

AN17 AP16 AP17 AW14 AW16

AP22 AP23

PVPCIE

L5020

BLM18PG600SN1D

P1V8S_DGPU

L5021

BLM18PG600SN1D

21

DPCD_VDD10

C5229

2 1

10UF_6.3V_3

DPEF_VDD18

C5230

AP14 AP15

C5231

2 1

0.1UF_16V_2

AN19 AP18 AP19 AW20 AW22

AW18

150_1%_2

AH34 AJ34

DP C/D POWER

DPCD/DPC_VDD18#1 DPCD/DPC_VDD18#2

DPCD/DPC_VDD10#1 DPCD/DPC_VDD10#2

DP/DPC_VSSR#1 DP/DPC_VSSR#2 DP/DPC_VSSR#3 DP/DPC_VSSR#4 DP/DPC_VSSR#5

DPCD/DPD_VDD18#1 DPCD/DPD_VDD18#2

DPCD/DPD_VDD10#1 DPCD/DPD_VDD10#2

DP/DPD_VSSR#1 DP/DPD_VSSR#2 DP/DPD_VSSR#3 DP/DPD_VSSR#4 DP/DPD_VSSR#5

DPCD_CALR

DP E/F POWER

DPEF/DPE_VDD18#1 DPEF/DPE_VDD18#2

DP A/B POWER

DPAB/DPA_VDD18#1 DPAB/DPA_VDD18#2

DPAB/DPA_VDD10#1 DPAB/DPA_VDD10#2

DP/DPA_VSSR#1 DP/DPA_VSSR#2 DP/DPA_VSSR#3 DP/DPA_VSSR#4 DP/DPA_VSSR#5

DPAB/DPB_VDD18#1 DPAB/DPB_VDD18#2

DPAB/DPB_VDD10#1 DPAB/DPB_VDD10#2

DP/DPB_VSSR#1 DP/DPB_VSSR#2 DP/DPB_VSSR#3 DP/DPB_VSSR#4 DP/DPB_VSSR#5

DP PLL POWER

DPAB_VDD18/DPA_PVDD

DP_VSSR/DPA_PVSS

DPAB_CALR

AN24 AP24

AP31 AP32

AN27 AP27 AP28 AW24 AW26

AP25 AP26

AN33 AP33

AN29 AP29 AP30 AW30 AW32

AW28

AU28 AV27

DPAB_VDD18

R5040R5041

150_1%_2

DPAB_VDD18

C5220

2 1

DPAB_VDD18

DPAB_VDD10

C5223

2 1

2121

C5221

0.1UF_16V_2

C5224

0.1UF_16V_2

IN

2 1

C5222

1UF_6.3V_2

IN

C5225

1UF_6.3V_2

60C3

2 1

10UF_6.3V_3

L5017

BLM18PG600SN1D

L5018

BLM18PG600SN1D

21

PVPCIE

21

U5001

C5232

2 1

C5233

10UF_6.3V_3

2 1

C5234

1UF_6.3V_2

2 1

0.1UF_16V_2

60B6

60B3

DPEF_VDD18

IN

AL33 AM33

AN34 AP39 AR39 AU37

AF34 AG34

DPEF/DPE_VDD10#1 DPEF/DPE_VDD10#2

DP/DPE_VSSR#1 DP/DPE_VSSR#2 DP/DPE_VSSR#3 DP/DPE_VSSR#4

DPEF/DPF_VDD18#1 DPEF/DPF_VDD18#2

PVPCIE

L5022

BLM18PG600SN1D

21

C5235

2 1

DPEF_VDD10

C5236

10UF_6.3V_3

2 1

C5237

1UF_6.3V_2

150_1%_2

2 1

R5042

0.1UF_16V_2

21

AK33 AK34

AF39 AH39 AK39 AL34 AM34

AM39

DPEF/DPF_VDD10#1 DPEF/DPF_VDD10#2

DP/DPF_VSSR#1 DP/DPF_VSSR#2 DP/DPF_VSSR#3 DP/DPF_VSSR#4 DP/DPF_VSSR#5

DPEF_CALR

AMD_216_0833002_FCBGA_962P

DPAB_VDD18/DPB_PVDD

DP_VSSR/DPB_PVSS

DPCD_VDD18/DPC_PVDD

DP_VSSR/DPC_PVSS

DPCD_VDD18/DPD_PVDD

DP_VSSR/DPD_PVSS

DPEF_VDD18/DPE_PVDD

DP_VSSR/DPE_PVSS

DPEF_VDD18/DPF_PVDD

DP_VSSR/DPF_PVSS

AV29 AR28

AU18 AV17

AV19 AR18

AM37 AN38

AL38 AM35

DPCD_VDD18

DPEF_VDD18

60C6

IN

60B6

IN

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6960

A3

21-OCT-2002XXX

DOC.NUMBER

of

INVENTEC

TITLE

DATE

CODE

E

D

C

B

A

7 6 5 4 3 2 1

7 6 5 4 3

E

D

C

B

A

FF

8

CHANGE by

8

REV

2 1

SHEET

SIZE

U5001

AB39

E39 F34 F39 G33 G34 H31 H34 H39 J31 J34 K31 K34 K39 L31 L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39 W31 W34 Y34 Y39

F15 F17 F19 F21 F23 F25 F27 F29 F31 F33

J27

K14

L11 L17

L22 L24

M17 M22 M24 N16 N18

N21 N23 N26

R15 R17

R20 R22 R24 R27

T11 T13 T16 T18 T21 T23 T26 U15 U17

U20 U22 U24 U27

V11 V16 V18 V21 V23 V26

Y15 Y17 Y20 Y22 Y24 Y27 U13 V13

F7 F9 G2 G6 H9 J2

J6 J8

K7

L2

L6

N2

N6

R2

R6

U2

U6

W2 W6

PCIE_VSS#1 PCIE_VSS#2 PCIE_VSS#3 PCIE_VSS#4 PCIE_VSS#5 PCIE_VSS#6 PCIE_VSS#7 PCIE_VSS#8 PCIE_VSS#9 PCIE_VSS#10 PCIE_VSS#11 PCIE_VSS#12 PCIE_VSS#13 PCIE_VSS#14 PCIE_VSS#15 PCIE_VSS#16 PCIE_VSS#17 PCIE_VSS#18 PCIE_VSS#19 PCIE_VSS#20 PCIE_VSS#21 PCIE_VSS#22 PCIE_VSS#23 PCIE_VSS#24 PCIE_VSS#25 PCIE_VSS#26 PCIE_VSS#27 PCIE_VSS#28 PCIE_VSS#29 PCIE_VSS#30 PCIE_VSS#31 PCIE_VSS#32 PCIE_VSS#33 PCIE_VSS#34 PCIE_VSS#35

GND#100 GND#101 GND#102 GND#103 GND#104 GND#105 GND#106 GND#107 GND#108 GND#109 GND#110 GND#111 GND#112 GND#113 GND#114 GND#115 GND#116 GND#117 GND#118 GND#119 GND#120 GND#121 GND#122 GND#123 GND#124 GND#125 GND#126 GND#127 GND#128 GND#129 GND#130 GND#131 GND#132 GND#133 GND#134 GND#135 GND#136 GND#137 GND#138 GND#139 GND#140 GND#141 GND#142 GND#143 GND#144 GND#145 GND#146 GND#147 GND#148 GND#149 GND#150 GND#151 GND#153 GND#154 GND#155 GND#156 GND#157 GND#158 GND#159 GND#160 GND#161 GND#163 GND#164 GND#165 GND#166 GND#167 GND#168 GND#169 GND#170 GND#171 GND#172 GND#173 GND#174 GND#175 GND#152 GND#162

GND

GND/PX_EN#61

VSS_MECH#1 VSS_MECH#2 VSS_MECH#3

GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8

GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55 GND#56 GND#57 GND#58 GND#59 GND#60

GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86 GND#87 GND#88 GND#89 GND#90 GND#91 GND#92 GND#93 GND#94 GND#95 GND#96 GND#97 GND#98

A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 AL21 AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13

A39 AW1 AW39

PX_EN

IN

AMD_216_0833002_FCBGA_962P

MODEL,PROJECT,FUNCTION

XXX 21-OCT-2002

Block Diagram

C CS

1310xxxxx-0-0

61 69

X01

C5516

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

62D4

R5541R5540

40.2_1%_2

2 1

0.01UF_50V_2

IN

62B4 62B2

58A5 58D4 62D8 63D4 63D8

63C4 65C4 65C8 64C7 65C4

62C7

2121

VRAM_VREFC_A<2>

IN

VRAM_VREFD_A<1>

IN

MAA<13..0>

BI

58D5 62D7 63D4 63D8

BI

58D5 62D7 63D4 63D8

BI

58D5 62D7 63D4 63D8

BI

58B5 62B3 62D7

IN

58B5 62B5 62C7

IN

58B5 62C7

IN

58C5 62C7

IN

58B5 62C7

IN

58B5 62C7

IN

58B5 62C7

IN

58A5 62C7

IN

58C5

BIBI

58C5

58D5

BIBI

58D5

58C5

BI

58C5

58A1 63C8 64C4

IN

58B5 62D4 62D7

C5502

2 1

MAA_BA<0> MAA_BA<1> MAA_BA<2>

CLKA0_DP CLKA0_DN CKEA0

ODTA0 CSA0#_0 RASA0# CASA0# WEA0#

DQSA3_DP DQSA2_DP

DQMA<3> DQMA<2>

DQSA3_DN DQSA2_DN

VM_RESET

P1V5S_DGPU

R5504R5505

0.1uF_16V_2

2121

MAA<0>

0

MAA<1>

1

MAA<2>

2

MAA<3>

3

MAA<4>

4

MAA<5>

5

MAA<6>

6

MAA<7>

7

MAA<8>

8

MAA<9>

9

MAA<10>

10

MAA<11>

11

MAA<12>

12

MAA<13>

13

243_1%_2

4.99K_1%_24.99K_1%_2

R5508

21

SAM_K4B1G1646D_HCF7_FBGA_100P

K10

J10 L10

A11

M9 H2

N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8

M3 N9 M4

J8 K8

K2 L3 J4 K4 L4

F4 C8

E8 D4

G4 B8

T3

L9

J2 L2

A1

62D4

U5501U5500

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10_AP A11 A12 A13 A14 A15_BA3

BA0 BA1 BA2

CK CK CKE_CKE0

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET

ZQ_ZQ0

NC_ODT NC_CSI NC_CE1 NC_ZQ1

NC NC

E4

VDD#B3

VDD#D10

VDD#G8 VDD#K3 VDD#K9 VDD#N2

VDD#N10

VDD#R2

VDD#R10

VDDQ#A2 VDDQ#A9 VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2 VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4 VSS#E2 VSS#G9 VSS#J3 VSS#J9 VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2 VSSQ#D9 VSSQ#E3 VSSQ#E9

VSSQ#F10

VSSQ#G2

VSSQ#G10

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQA<26>

F8

DQA<31>

F3

DQA<29>

F9

DQA<25>

H4

DQA<24>

H9

DQA<28>

G3

DQA<27>

H8

DQA<30>

D8

DQA<19>

C4

DQA<18>

C9

DQA<21>

C3

DQA<16>

A8

DQA<23>

A3

DQA<17>

B9

DQA<22>

A4

DQA<20>

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

T1

NC

T11

NC

P1V5S_DGPU

BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI

58D8 58D8 58D8 58D8 58D8 58D8 58D8 58D8

58D8 58D8 58D8 58D8 58D8 58D8 58D8

P1V5S_DGPU

58D8

P1V5S_DGPU

2121

VRAM_VREFD_A<1>VRAM_VREFC_A<2>

IN

C5503

2 1

R5506R5507

4.99K_1%_24.99K_1%_2

0.1uF_16V_2

62A8 62A7

58A5 58D4 62D4 63D4 63D8

VRAM_VREFC_A<0>

IN

VRAM_VREFD_A<3>

IN

MAA<13..0>

BI

0 1 2 3 4 5 6 7 8 9 10 11 12 13

MAA<0> MAA<1> MAA<2> MAA<3> MAA<4> MAA<5> MAA<6> MAA<7> MAA<8> MAA<9> MAA<10> MAA<11> MAA<12> MAA<13>

IN IN IN

IN IN IN IN IN

IN

MAA_BA<0> MAA_BA<1> MAA_BA<2>

CLKA0_DP CLKA0_DN CKEA0

ODTA0 CSA0#_0 RASA0# CASA0# WEA0#

DQSA0_DP DQSA1_DP

DQMA<0> DQMA<1>

DQSA0_DN DQSA1_DN

VM_RESET

R5509

243_1%_2

64C7

62D4

58D5 62D4 63D4 63D8

BI

58D5 62D4 63D4 63D8

BI

58D5 63D4 63D8

BI

58B5 62B3 62D4 58B5 62B5 62C4 58B5 62C4

58C5 62C4 58B5 62C4 58B5 62C4 58B5 62C4 58A5 62C4

58C5 58C5

BI BI

58D5 58D5

BI BI

58C5

BI

58C5

BI BI

58A1 62C4 63C4 63C8 64C4 65C8

M9 H2

N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8

M3 N9 M4

J8 K8

K10

K2 L3 J4 K4 L4

F4 C8

E8 D4

G4 B8

T3

L9

21

J2

L2 J10 L10

A1 A11

E4

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10_AP A11 A12 A13 A14 A15_BA3

BA0 BA1 BA2

CK CK CKE_CKE0

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET

ZQ_ZQ0

NC_ODT NC_CSI NC_CE1 NC_ZQ1

NC NC

VDD#B3

VDD#D10

VDD#G8 VDD#K3 VDD#K9 VDD#N2

VDD#N10

VDD#R2

VDD#R10

VDDQ#A2 VDDQ#A9 VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2 VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4 VSS#E2 VSS#G9 VSS#J3 VSS#J9 VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2 VSSQ#D9 VSSQ#E3 VSSQ#E9

VSSQ#F10

VSSQ#G2

VSSQ#G10

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQA<3>

F8

DQA<0>

F3

DQA<4>

F9

DQA<2>

H4

DQA<6>

H9

DQA<1>

G3

DQA<5>

H8

DQA<7>

D8

DQA<12>

C4

DQA<13>

C9

DQA<9>

C3

DQA<15>

A8

DQA<10>

A3

DQA<14>

B9

DQA<8>

A4

DQA<11>

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

T1

NC

T11

NC

62C4

58D8

BI

58D8

BI BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI BI

P1V5S_DGPU

58D8

P1V5S_DGPU

THAMES: 40OHM SEYMOUR: 56OHM

(60130B5600ZT)

58B5 62C7

CLKA0_DN CLKA0_DP

IN

40.2_1%_2

SAM_K4B1G1646D_HCF7_FBGA_100P

62D7

IN

P1V5S_DGPU

VRAM_VREFC_A<0>

C5500

2 1

0.1uF_16V_2

P1V5S_DGPU

2121

R5500R5501

4.99K_1%_2

62D7

VRAM_VREFD_A<3>

IN

C5501

2 1

0.1uF_16V_2

P1V5S_DGPU

2121

R5502R5503

4.99K_1%_2

P1V5S_DGPU

C5520

2 1

1UF_6.3V_2

C5521

2 1

1UF_6.3V_2

C5522

2 1

1UF_6.3V_2

C5523

2 1

1UF_6.3V_2

C5524

2 1

1UF_6.3V_2

C5525

2 1

2.2UF_6.3V_2

C5526

C5527

10UF_6.3V_310UF_6.3V_3

2 1

C5528

2 1

1UF_6.3V_2

C5529

2 1

1UF_6.3V_2

C5530

2 1

1UF_6.3V_2

C5531

2 1

1UF_6.3V_2

C5532

2 1

1UF_6.3V_2

10UF_6.3V_310UF_6.3V_3

2 1

C5534C5533

2 1

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6962

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

63A8 63A6

58A5 58D4 62D4 62D8 63D4

VRAM_VREFC_A<4>

IN

VRAM_VREFD_A<7>

IN

MAA<13..0>

BI

0 1 2 3 4 5 6 7 8 9 10 11 12 13

MAA<0> MAA<1> MAA<2> MAA<3> MAA<4> MAA<5> MAA<6> MAA<7> MAA<8> MAA<9> MAA<10> MAA<11> MAA<12> MAA<13>

IN IN IN

IN IN IN IN IN

IN

MAA_BA<0> MAA_BA<1> MAA_BA<2>

CLKA1_DP CLKA1_DN CKEA1

ODTA1 CSA1#_0 RASA1# CASA1# WEA1#

DQSA6_DP DQSA7_DP

DQMA<6> DQMA<7>

DQSA6_DN DQSA7_DN

VM_RESET

R5519

21

63C4

58D5 62D4 62D7 63D4 58D5 62D4 62D7 63D4 58D5 62D4 62D7 63D4

58B5 63B4 63D4 58B5 63B5 63D4 58B5 63C4

58B5 63C4 58B5 63C4 58B5 63C4 58B5 63C4 58A5 63C4

58C5 58C5

58A1 62C4 62C7 64C4 64C7 65C4 65C8

BI BI BI

BI BI

K10

U5502

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10_AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15_BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK CKE_CKE0

K2

ODT

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ_ZQ0

243_1%_2

J2

NC_ODT

L2

NC_CSI

J10

NC_CE1

L10

NC_ZQ1

A1

A11

NC NC

E4

DQA<54>

F8

DQA<51>

F3

DQA<53>

F9

DQA<49>

H4

DQA<52>

H9

DQA<50>

G3

DQA<55>

H8

DQA<48>

D8

DQA<62>

C4

DQA<60>

C9

DQA<58>

C3

DQA<61>

A8

DQA<59>

A3

DQA<57>

B9

DQA<56>

A4

DQA<63>

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

T1

NC

T11

NC

63C8 58B5

63D4

VDD#B3

VDD#D10

VDD#G8 VDD#K3 VDD#K9 VDD#N2

VDD#N10

VDD#R2

VDD#R10

VDDQ#A2 VDDQ#A9 VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2 VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4 VSS#E2 VSS#G9 VSS#J3 VSS#J9 VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2 VSSQ#D9 VSSQ#E3 VSSQ#E9

VSSQ#F10

VSSQ#G2

VSSQ#G10

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

BI BI BI BI BI BI BI BI

P1V5S_DGPU

IN

58D8 58D8 58D8 58D8 58D8 58D8 58D8 58D8

58D8 58D8 58D8 58D8 58D8 58D8 58D8

P1V5S_DGPU

63D8

58D8

THAMES: 40 OHM SEYMOUR: 56 OHM

(60130B5600ZT)

R5543R5542

40.2_1%_240.2_1%_2

C5517

2 1

0.01UF_50V_2

SAM_K4B1G1646D_HCF7_FBGA_100P

63D8

P1V5S_DGPU

2121

VRAM_VREFC_A<4>

IN

C5504

2 1

P1V5S_DGPU

R5510R5511

0.1uF_16V_2

4.99K_1%_2

63D8

VRAM_VREFD_A<7>

IN

C5505

2 1

0.1uF_16V_2

P1V5S_DGPU

2121

R5512R5513

4.99K_1%_2 4.99K_1%_2

63D4

IN

63A4 63A3

58A5 58D4 62D4 62D8

CLKA1_DPCLKA1_DN

2121

VRAM_VREFC_A<6>

P1V5S_DGPU

58D5 62D4 62D7 63D8 58D5 62D4 62D7 63D8 58D5 62D4 62D7 63D8

58B5 63B4 63D8 58B5 63B5 63C8 58B5 63C8

58B5 63C8 58B5 63C8 58B5 63C8 58B5 63C8 58A5 63C8

58C5 58C5

58D5 58C5

58C5 58C5

58A1 62C4 62C7 63C8 64C4 64C7 65C4 65C8

BI

IN IN

IN

MAA<13..0>

BI BI BI

IN IN IN

IN IN IN IN IN

BI BI

IN

58B5 63D4 63D8

C5506

VRAM_VREFC_A<6> VRAM_VREFD_A<5>

MAA_BA<0> MAA_BA<1> MAA_BA<2>

CLKA1_DP CLKA1_DN CKEA1

ODTA1 CSA1#_0 RASA1# CASA1# WEA1#

DQSA4_DP DQSA5_DP

DQMA<4> DQMA<5>

DQSA4_DN DQSA5_DN

VM_RESET

P1V5S_DGPU P1V5S_DGPU

2121

R5514R5515

2 1

0.1uF_16V_2

MAA<0>

0

MAA<1>

1

MAA<2>

2

MAA<3>

3

MAA<4>

4

MAA<5>

5

MAA<6>

6

MAA<7>

7

MAA<8>

8

MAA<9>

9

MAA<10>

10

MAA<11>

11

MAA<12>

12

MAA<13>

13

R5518

21

243_1%_2

K10

J10 L10

A11

U5503

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10_AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15_BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK CKE_CKE0

K2

ODT

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ_ZQ0

J2

NC_ODT

L2

NC_CSI NC_CE1 NC_ZQ1

A1

NC NC

VDD#B3

VDD#D10

VDD#G8 VDD#K3 VDD#K9 VDD#N2

VDD#N10

VDD#R2

VDD#R10

VDDQ#A2 VDDQ#A9 VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2 VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4 VSS#E2 VSS#G9 VSS#J3 VSS#J9 VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2 VSSQ#D9 VSSQ#E3 VSSQ#E9

VSSQ#F10

VSSQ#G2

VSSQ#G10

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

E4

DQA<35>

F8

DQA<38>

F3

DQA<33> DQA<39>

F9 H4

DQA<32>

H9

DQA<37>

G3

DQA<34>

H8

DQA<36>

DQA<44>

D8 C4

DQA<43>

C9

DQA<47>

C3

DQA<42>

A8

DQA<46>

A3

DQA<40>

B9

DQA<45>

A4

DQA<41>

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

T1

NC

T11

NC

BI BI BI BI BI BI BI BI

P1V5S_DGPU

SAM_K4B1G1646D_HCF7_FBGA_100P

21

4.99K_1%_2 4.99K_1%_2

63D4

VRAM_VREFD_A<5>

IN

C5507

2 1

0.1uF_16V_2

R5516

21

R5517

4.99K_1%_2 4.99K_1%_2

58D8 58D8 58D8 58D8 58D8 58D8 58D8 58D8

58D8 58D8 58D8 58D8 58D8 58D8 58D8

P1V5S_DGPU

58D8

C5549

2 1

C5535

2 1

1UF_6.3V_2

C5536

2 1

1UF_6.3V_2

C5537

2 1

1UF_6.3V_2

C5538

2 1

1UF_6.3V_2

C5539

2 1

1UF_6.3V_2

C5540

10UF_6.3V_3 10UF_6.3V_3

2 1

C5541

2.2UF_6.3V_2

1UF_6.3V_2

C5548

10UF_6.3V_3

2 1

C5543

C5542

2 1

1UF_6.3V_2

C5544

2 1

1UF_6.3V_2

C5545

2 1

1UF_6.3V_2

C5546

2 1

1UF_6.3V_2

C5547

10UF_6.3V_3

2 1

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6963

A3

21-OCT-2002XXX

C5518

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

2 1

64D4

R5545R5544

40.2_1%_2

0.01UF_50V_2

64B4 64B2

58A1 58D1 64D7 65D4 65D8

2121

CLKB0_DPCLKB0_DN

VRAM_VREFC_B<2> VRAM_VREFD_B<1>

VRAM_VREFC_B<2>

IN

VRAM_VREFD_B<1>

IN

MAB<13..0>

BI

58D1 64D7 65D4 65D8

BI

58D1 64D7 65D4 65D8

BI

58D1 64D7 65D4 65D8

BI

58B1 64B3 64D7

IN

58B1 64B5 64C7

IN

58B1 64C7

IN

58C1 64C7

IN

58B1 64C7

IN

58B1 64C7

IN

58B1 64C7

IN

58A1 64C7

IN

58C1

BI

58C1

BI

58D1

BI

58D1

BI

58C1

BI

58C1

BI

58A1 62C4 62C7 63C4 63C8 64C7

IN

MAB_BA<0> MAB_BA<1> MAB_BA<2>

CLKB0_DP CLKB0_DN CKEB0

ODTB0 CSB0#_0 RASB0# CASB0# WEB0#

DQSB1_DP DQSB2_DP

DQMB<1> DQMB<2>

DQSB1_DN DQSB2_DN

58B1 64D4 64D7

MAB<0>

0

MAB<1>

1

MAB<2>

2

MAB<3>

3

MAB<4>

4

MAB<5>

5

MAB<6>

6

MAB<7>

7

MAB<8>

8

MAB<9>

9

MAB<10>

10

MAB<11>

11

MAB<12>

12

MAB<13>

13

VM_RESET

243_1%_2

P1V5S_DGPU

2121

R5524R5525

R5528

21

SAM_K4B1G1646D_HCF7_FBGA_100P

IN

C5510

2 1

0.1uF_16V_2

4.99K_1%_2 4.99K_1%_2

K10

J10 L10

A11

M9 H2

N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8

M3 N9 M4

J8 K8

K2 L3 J4 K4 L4

F4 C8

E8 D4

G4 B8

T3

L9

J2 L2

A1

64D4

U5505

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10_AP A11 A12 A13 A14 A15_BA3

BA0 BA1 BA2

CK CK CKE_CKE0

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET

ZQ_ZQ0

NC_ODT NC_CSI NC_CE1 NC_ZQ1

NC NC

IN

VDD#B3

VDD#D10

VDD#G8 VDD#K3 VDD#K9 VDD#N2

VDD#N10

VDD#R2

VDD#R10

VDDQ#A2 VDDQ#A9 VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2 VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4 VSS#E2 VSS#G9 VSS#J3 VSS#J9 VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2 VSSQ#D9 VSSQ#E3 VSSQ#E9

VSSQ#F10

VSSQ#G2

VSSQ#G10

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

E4

DQB<10>

F8

DQB<12>

F3

DQB<9>

F9

DQB<14>

H4

DQB<13>

H9

DQB<11>

G3

DQB<8>

H8

DQB<15>

D8

DQB<20>

C4

DQB<19>

C9

DQB<23>

C3

DQB<16>

A8

DQB<21>

A3

DQB<17>

B9

DQB<22>

A4

DQB<18>

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

T1

NC

T11

NC

P1V5S_DGPU

BI BI BI BI BI BI BI BI

58D4 58D4 58D4 58D4 58D4 58D4 58D4 58D4

58D4 58D4 58D4 58D4 58D4 58D4 58D4

P1V5S_DGPU

2121

R5526R5527

C5511

2 1

0.1uF_16V_2

4.99K_1%_2 4.99K_1%_2

64A8 64A7

58A1 58D1 64D4 65D4 65D8

VRAM_VREFC_B<0>

IN

VRAM_VREFD_B<3>

IN

MAB<13..0>

BI

0 1 2 3 4 5 6 7 8 9 10 11 12 13

MAB<0> MAB<1> MAB<2> MAB<3> MAB<4> MAB<5> MAB<6> MAB<7> MAB<8> MAB<9> MAB<10> MAB<11> MAB<12> MAB<13>

IN IN IN

IN IN IN IN IN

IN

MAB_BA<0> MAB_BA<1> MAB_BA<2>

CLKB0_DP CLKB0_DN CKEB0

ODTB0 CSB0#_0 RASB0# CASB0# WEB0#

DQSB3_DP DQSB0_DP

DQMB<3> DQMB<0>

DQSB3_DN DQSB0_DN

VM_RESET

R5529

243_1%_2

64C4

58D1

64D4 65D4 65D8 64D4 65D4 65D8 64D4 65D4 65D8

64B3 64D4 64B5 64C4 64C4

64C4 64C4

58D1 58D1

58C1 58C1

58D1 58D1

58C1 58C1

58B1 58B1 58B1

58C1 58B1 58B1 64C4 58B1 58A1

58A1 62C4 62C7 63C4 63C8 65C4 65C8

BI BI BI

BI BI

M9 H2

N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8

M3 N9 M4

J8 K8

K10

K2 L3 J4 K4 L4

F4 C8

E8 D4

G4 B8

T3

L9

21

J2

L2 J10 L10

A1 A11

U5504

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10_AP A11 A12 A13 A14 A15_BA3

BA0 BA1 BA2

CK CK CKE_CKE0

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET

ZQ_ZQ0

NC_ODT NC_CSI NC_CE1 NC_ZQ1

NC NC

VDD#D10

VDD#N10

VDD#R10

VDDQ#A2 VDDQ#A9 VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2 VDDQ#H3

VDDQ#H10

VSS#A10

VSS#M10

VSS#P10

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2 VSSQ#D9 VSSQ#E3 VSSQ#E9

VSSQ#F10

VSSQ#G2

VSSQ#G10

VDD#B3

VDD#G8 VDD#K3 VDD#K9 VDD#N2

VDD#R2

VSS#B4 VSS#E2 VSS#G9 VSS#J3 VSS#J9 VSS#M2

VSS#P2

VSS#T2

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

E4

DQB<26>

F8

DQB<24>

F3

DQB<29>

F9

DQB<31>

H4

DQB<28>

H9

DQB<25>

G3

DQB<30>

H8

DQB<27>

D8

DQB<6>

C4

DQB<3>

C9

DQB<2>

C3

DQB<7>

A8

DQB<1>

A3

DQB<4>

B9

DQB<0>

A4

DQB<5>

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

T1

NC

T11

NC

P1V5S_DGPU

58B1 64C4 64C7

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI BI

P1V5S_DGPU

65C8

58D4

65C4

THAMES: 40 OHM SEYMOUR: 56 OHM

(60130B5600ZT)

IN

40.2_1%_2

SAM_K4B1G1646D_HCF7_FBGA_100P

64D7

IN

P1V5S_DGPU

VRAM_VREFC_B<0>

C5508

2 1

0.1uF_16V_2

P1V5S_DGPU

2121

R5520R5521

4.99K_1%_2

64D7

VRAM_VREFD_B<3>

IN

C5509

2 1

0.1uF_16V_2

P1V5S_DGPU

2121

R5522R5523

4.99K_1%_2 4.99K_1%_2

P1V5S_DGPU

C5550

2 1

1UF_6.3V_2

C5551

2 1

1UF_6.3V_2

C5552

2 1

1UF_6.3V_2

C5553

2 1

1UF_6.3V_2

C5554

2 1

1UF_6.3V_2

C5555

2 1

C5556

10UF_6.3V_3 10UF_6.3V_3

2 1

2.2UF_6.3V_2

C5557

C5558

2 1

1UF_6.3V_2

C5559

2 1

1UF_6.3V_2

C5560

2 1

1UF_6.3V_2

C5561

2 1

1UF_6.3V_2

C5562

10UF_6.3V_3

2 1

1UF_6.3V_2

10UF_6.3V_3

2 1

C5564C5563

2 1

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6964

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

65A8 65A6

58A1 58D1 64D4 64D7 65D4

VRAM_VREFC_B<4>

IN

VRAM_VREFD_B<7>

IN

MAB<13..0>

BI

0 1 2 3 4 5 6 7 8 9 10 11 12 13

MAB<0> MAB<1> MAB<2> MAB<3> MAB<4> MAB<5> MAB<6> MAB<7> MAB<8> MAB<9> MAB<10> MAB<11> MAB<12> MAB<13>

IN IN IN

IN IN IN IN IN

IN

MAB_BA<0> MAB_BA<1> MAB_BA<2>

CLKB1_DP CLKB1_DN CKEB1

ODTB1 CSB1#_0 RASB1# CASB1# WEB1#

DQSB6_DP DQSB7_DP

DQMB<6> DQMB<7>

DQSB6_DN DQSB7_DN

VM_RESET

R5539

21

63C4

62C7

58D1 64D4 64D7 65D4 58D1 64D4 64D7 65D4 58D1 64D4 64D7 65D4

58B1 65B4 65D4 58B1 65B5 65D4 58B1 65C4

58B1 65C4 58B1 65C4 58B1 65C4 58B1 65C4 58A1 65C4

58C1 58C1

58A1 62C4 63C8 64C4 64C7 65C4

BI BI BI

BI BI

K10

U5506

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10_AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15_BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK CKE_CKE0

K2

ODT

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ_ZQ0

243_1%_2

J2

NC_ODT

L2

NC_CSI

J10

NC_CE1

L10

NC_ZQ1

A1

A11

NC NC

SAM_K4B1G1646D_HCF7_FBGA_100P

E4 F8 F3 F9 H4 H9 G3 H8

D8 C4 C9 C3 A8 A3 B9 A4

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

T1 T11

DQB<55> DQB<54> DQB<51> DQB<52> DQB<48> DQB<53> DQB<49> DQB<50>

DQB<59> DQB<63> DQB<62> DQB<58> DQB<60> DQB<56> DQB<61> DQB<57>

58B1 65C8 65D4

VDD#B3

VDD#D10

VDD#G8 VDD#K3 VDD#K9 VDD#N2

VDD#N10

VDD#R2

VDD#R10

VDDQ#A2 VDDQ#A9 VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2 VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4 VSS#E2 VSS#G9 VSS#J3 VSS#J9 VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2 VSSQ#D9 VSSQ#E3 VSSQ#E9

VSSQ#F10

VSSQ#G2

VSSQ#G10

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

NC NC

BI BI BI BI BI BI BI BI

P1V5S_DGPU

IN

58D4 58D4 58D4 58D4 58D4 58D4 58D4 58D4

58D4 58D4 58D4 58D4 58D4 58D4 58D4

P1V5S_DGPU

64D7

58D4

THAMES: 40 OHM SEYMOUR: 56 OHM

(60130B5600ZT)

CLKB1_DN CLKB1_DP

R5547R5546

40.2_1%_240.2_1%_2

C5519

2 1

0.01UF_50V_2

P1V5S_DGPU P1V5S_DGPU

2121

R5532R5533

4.99K_1%_24.99K_1%_2

65D4

IN

65D8

VRAM_VREFC_B<4>

P1V5S_DGPU

C5512

2 1

2121

R5530R5531

0.1UF_16V_2

4.99K_1%_24.99K_1%_2

65D8

ININ

VRAM_VREFD_B<7>

C5513

2 1

0.1UF_16V_2

65A4 65A3

58A1 58D1 64D4 65D8

62C7 63C8 64C4 65C8 64C7

2121

58D1 64D4 64D7 65D8 58D1 64D4 64D7 65D8 58D1 64D4 64D7 65D8

58B1 65B4 65D8 58B1 65B5 65C8 58B1 65C8

58B1 65C8 58B1 65C8 58B1 65C8 58B1 65C8 58A1 65C8

58C1 58C1

58D1 58C1

58C1 58C1

58A1 62C4 63C4

BI

IN IN

IN

MAB<13..0>

BI BI BI

IN IN IN

IN IN IN IN IN

BI BI

IN

VRAM_VREFC_B<6> VRAM_VREFD_B<5>

MAB_BA<0> MAB_BA<1> MAB_BA<2>

CLKB1_DP CLKB1_DN CKEB1

ODTB1 CSB1#_0 RASB1# CASB1# WEB1#

DQSB4_DP DQSB5_DP

DQMB<4> DQMB<5>

DQSB4_DN DQSB5_DN

VM_RESET

58B1 65D4 65D8

MAB<0>

0

MAB<1>

1

MAB<2>

2

MAB<3>

3

MAB<4>

4

MAB<5>

5

MAB<6>

6

MAB<7>

7

MAB<8>

8

MAB<9>

9

MAB<10>

10

MAB<11>

11

MAB<12>

12

MAB<13>

13

R5538

21

243_1%_2

K10

J10 L10

A11

U5507

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10_AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15_BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK CKE_CKE0

K2

ODT

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ_ZQ0

J2

NC_ODT

L2

NC_CSI NC_CE1 NC_ZQ1

A1

NC NC

VDD#B3

VDD#D10

VDD#G8 VDD#K3 VDD#K9 VDD#N2

VDD#N10

VDD#R2

VDD#R10

VDDQ#A2 VDDQ#A9 VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2 VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4 VSS#E2 VSS#G9 VSS#J3 VSS#J9 VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2 VSSQ#D9 VSSQ#E3 VSSQ#E9

VSSQ#F10

VSSQ#G2

VSSQ#G10

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

E4

DQB<39>

F8

DQB<37>

F3

DQB<36>

F9

DQB<38>

H4

DQB<35>

H9

DQB<32>

G3

DQB<33>

H8

DQB<34>

DQB<41>

D8

DQB<44>

C4 C9

DQB<42>

C3

DQB<45>

A8

DQB<40>

A3

DQB<47>

B9

DQB<43>

A4

DQB<46>

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

T1

NC

T11

NC

P1V5S_DGPU

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI BI

P1V5S_DGPU

58D4

SAM_K4B1G1646D_HCF7_FBGA_100P

P1V5S_DGPU P1V5S_DGPU

2121

R5536R5537

4.99K_1%_24.99K_1%_2

0.1UF_16V_2

P1V5S_DGPU

C5514

2 1

0.1UF_16V_2

R5534R5535

2121

4.99K_1%_24.99K_1%_2

65D4

VRAM_VREFD_B<5>VRAM_VREFC_B<6>

IN

C5515

2 1

C5579

2 1

C5565

2 1

1UF_6.3V_2

C5566

2 1

1UF_6.3V_2

C5567

2 1

1UF_6.3V_2

C5568

2 1

1UF_6.3V_2

C5569

2 1

1UF_6.3V_2

C5570

2 1

10UF_6.3V_3

2.2UF_6.3V_2

10UF_6.3V_3

2 1

1UF_6.3V_2

C5578

10UF_6.3V_3

2 1

C5573

C5572C5571

2 1

1UF_6.3V_2

C5574

2 1

1UF_6.3V_2

C5575

2 1

1UF_6.3V_2

C5576

2 1

1UF_6.3V_2

C5577

10UF_6.3V_3

2 1

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6965

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

USB BOARD

P5V0A_USB3_DB

C9100

22UF_6.3V_5

2 1

DGND_USB3_DB

CN9100

1

VCC

2

DATA-

3

DATA+

4 G4

GND G4

SUYIN_020173GR004M555ZL_4P

G1

G2

G3

DGND_USB3_DB

66B5 66B5

DGND_USB3_DB

BI BI

USB_P2_DN_DB USB_P2_DP_DB USB_L_P2_DP_DB

L9100

WCM_2012_900T

USB_L_P2_DN_DB

34 21

P5V0A_USB3_DB

PAD9100

SMDPAD_1P_40X120

66C6

BI

66C6

BI

USB_P2_DN_DB

USB_P2_DP_DB

SMDPAD_1P_40X120

1

PAD9101

1

PAD9102

1

PAD9103

1

DGND_USB3_DB

S9100

1

SCREW240_800_1P

S9101

1

SCREW300_1000_1P

DGND_USB3_DB

FIX9100

1

FIX_MASK

FIX9101

1

FIX_MASK

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

69

66

A3

XXX 21-OCT-2002

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

TPUCH PAD BOARD

TOUCHPAD TO MODULE CONN

P5V0S_TPB

R9201

BI BI BI BI

IN

TP_IM_CLK_5 TP_IM_DAT_5 TP_IM_DAT_5 TP_IM_CLK_5 LEFT_TP

RIGHT_TP

LEFT_TP

67C4

67B4

67C7 67B4

67C4

67C7

DGND_TP

BI BI

67B4

67B6

67C4

67C7

67C4 67B4

67B6

67C7

67B6

67B4 67C4

67C7

67B4

67B6

67C4

67C7

67B4 67A2

67C7

67A2

67B4

67A2 67B4

67C7

R9202 R9203 R9204 R9205 R9206

R9207 R9208

TP_IM_CLK_5 TP_IM_DAT_5

21

0_5%_2

21

0_5%_2_DY

21

0_5%_2

21

0_5%_2_DY

21

0_5%_2

21

0_5%_2_DY

21

0_5%_2

21

0_5%_2_DY

R9213

2 1 2 1

R9214

P3V3S_TPM

0_5%_2 0_5%_2_DY

2 1

R9210R9209

2 1

ACES_50592_0060N_001_6P

47K_5%_2 47K_5%_2

P5V0S_TPB

R9211 R9212

0_5%_2

2 1

1 2 3 4 5

CN9201

1 2 3 4 5

P3V3S_TPM

2 1

G16 G2

0_5%_2_DY

G16 G2

DGND_TP

TOUCHPAD TO MB CONN

P3V3S_TPM

DGND_TP

ACES_50503_0084N_001_8P

67B4 67B4

67C4 67C4

67B6

67B4

67C7 67B6

67B4

67C7

67C4

67B6 67C7 67C4

67B6 67C7

67C7

67A2 67A2

67C7

BI BI BI BI

BI BI

IN

IN BI BI

P5V0S_TPB

TP_IM_CLK_5 TP_IM_DAT_5 TP_PCH_3S_SMCLK TP_PCH_3S_SMDATA

TP_IM_DAT_5 TP_IM_CLK_5

RIGHT_TP LEFT_TP TP_PCH_3S_SMCLK TP_PCH_3S_SMDATA

P3V3S_TPM

SMDPAD1_28X118 SMDPAD1_28X118 SMDPAD1_28X118 SMDPAD1_28X118 SMDPAD1_28X118 SMDPAD1_28X118 SMDPAD1_28X118 SMDPAD1_28X118

CN9203

1

2

3

4

5

6

7

8

1

PAD9201

1

PAD9202

1

PAD9203

1

PAD9204

1

PAD9205

1

PAD9206

1

PAD9207

1

PAD9208

G1

G2

DGND_TP

1

FIX_MASK

FIX9201

1

FIX9202

1

FIX_MASK

DGND_TP

FIX9203

FIX9204

1

FIX_MASKFIX_MASK

S9201

1

SCREW230_800_1P

S9202

1

SCREW230_500_1P

S9203

1

SCREW230_800_1P

FIX9205

1

FIX9206

1

FIX_MASKFIX_MASK

SW9201

4

A B

5

6

1 2 3

DC

RIGHT_TP

OUT

67C7

67B4

MISAKI_NTC017_DA1G_E160T_6P

SW9202

4

A B

5

6

MISAKI_NTC017_DA1G_E160T_6P

DGND_TP

1 2 3

DC

LEFT_TP

2

1

D9201

PHP_PESD5V2S2UT_SOT23_3P_DY

3

OUT

67C7

67B4

DGND_TP

21-OCT-2002XXX

MODEL,PROJECT,FUNCTION

CS

A3

Block Diagram

X011310xxxxx-0-0

6967

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

REFERENCE 9000~9999(SMALL BOARD)

POWER BUTTON

4 5 6

MISAKI_NTC017_DA1G_E160T_6P

DGND_PWRSW_DB

SW9000

A B

1 2 3

DC

PHP_PESD5V2S2UT_SOT23_3P_DY

D9000

2

1

C9000

3

1000PF_50V_2_DY

2 1

PAD9000

1

SMDPAD_1P_40X120

PAD9001

1

SMDPAD_1P_40X120

FIX9005FIX9004FIX9003

1

SCREW220_800_1P

DGND_PWRSW_DB

1

FIX_MASK

S9000

1

S9001

1

FIX_MASK FIX_MASK

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6968

A3

21-OCT-2002XXX

DOC.NUMBER

DATE

SIZE

CODE

8

8 7

7 6

6 5

5 4

3 2 1

D

CC

B

AA

4

1

of

SHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

C7501

21

0.1UF_16V_2_DY

C7502

21

0.1UF_16V_2_DY

C7503

21

0.1UF_16V_2_DY

C7504

21

0.1UF_16V_2_DY

C7505

21

0.1UF_16V_2_DY

P1V5 P5V0S_AUDIO_AVDD

C7506

21

0.1UF_16V_2

C7507

21

0.1UF_16V_2_DY

PVCORE

C7511

21

0.1UF_16V_2_DY

C7512

21

0.1UF_16V_2_DY

P3V3S

C7515

21

0.1UF_16V_2

P3V3S

P1V5S_DGPU

P5V0A

C7508

0.1UF_16V_2_DY

C7509

0.1UF_16V_2_DY

C7516

0.1UF_16V_2

C7517

0.1UF_16V_2

21

P5V0S_AUDIO_AVDD

21

P3V3S

21

P1V5S_DGPU

21

P3V3S

0.1UF_16V_2_DY

P1V5S_DGPU

C7510

C7518

0.1UF_16V_2

P5V0S_AUDIO_AVDDP5V0SPVBAT

21

PVCORE_DGPU

21

MODEL,PROJECT,FUNCTION

CS

Block Diagram

X011310xxxxx-0-0

6969

A3

21-OCT-2002XXX

Inventec Dakar 10F 6050A2491301, Dakar FG 6050A2491301, Dakar R 6050A2491301, Dakar RG 6050A2491301 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual