Inventec Cycloned Discrete 6050A2566401 Schematic
THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC
CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT
WRITTEN PERMISSION,INVENTEC CORPORATION, ALL RIGHT RESERVED.
8
7 6 5 4 3 2 1
2013
HSF Property:ROHS or Halogen-Free
E
D
FF
E
CYCLONE DISCRETE
D
DB BUILD
2012.11.26
C
B
A
26-NOV-2012
DATE CHANGE NO.
8
A2012-ECO-XXXXXX
REV
7 6 5 4 3
DRAWER
CHANG,YUNGYU
TSENG,PAUL
YEN,ALEX
DU,DAVID
XXX
26-NOV-2012
26-NOV-2012
26-NOV-2012
DESIGN
CHECK
RESPONSIBLE
SIZE=
A3 X01
FILE NAME:
CYCLONED-6050A2566401-MB-X01.BRD
P/N
6050A2566401
POWER
HSIEH,ALAN
HSIEH,ALAN26-NOV-2012
HSIEH,ALAN
HSIEH,ALAN
2
26-NOV-2012
26-NOV-2012
26-NOV-2012
26-NOV-2012
VER:
C
B
A
DATEDATEEE
INVENTEC
TITLE
CYCLONE_DIS
SHARKBAY MAIN BOARD
CODE
SIZE
A3
1310A25664-0-ALG1310A25664
CS
SHEET
DOC.NUMBER REV
of
90
1
1
X01
8 7
6 5
4
3 2 1
TABLE OF CONTENTS
D
1. PROJECT NAME
2. TABLE OF CONTENTS
3. BLOCK DIAGRAM
4. POWER DIAGRAM
5. SYSTEM POWER(CHARGER)
6. SYSTEM POWER(OCP)
7. SYSTEM POWER(P3V3A&P5V0A)
8. P3V3A&P5V0A_CHG PORT
9. SYSTEM POWER(PVDDQ)
10. SYSTEM POWER(P1V05_M)
11. SYSTEM POWER(P1V5S)
12. SYSTEM POWER(PVCORE1)
13. SYSTEM POWER(PVCORE2)
14. SYSTEM POWER(PVCORE DGPU1)
B
8
15. SYSTEM POWER(P1V5S DGPU)
16. SYSTEM POWER (P1V8S)
17. SYSTEM POWER(PVPCIE)
18. SYSTEM POWER(SELECT)
19. POWER (SLEEP)
20. POWER (SEQUENCE)
21.FAN & THERMAL
22. XDP CONN
23. HASWELL_1 (CLK,MISC,JTAG)
24. HASWELL_2 (POWER)
25. HASWELL_3 (DMI,DP,PEG,FDI)
26. HASWELL_4 (DDR3)
27. HASWELL_5 (CFG)
28. HASWELL_6 (GND,RESERVED)
7 6
29. DDR3_SO-DIMM0
30. DDR3_SO-DIMM1
31. LYNX POINT_1 (RTC,JTAG,SATA)
32. LYNX POINT_2 (SPI,SMBUS,CL)
33. LYNX POINT_3 (CLK)
34. LYNX POINT_4 (DMI,FDI,SPM)
35. LYNX POINT_5 (CRT,DP)
36. LYNX POINT_6 (PCIE,USB)
37. LYNX POINT_7 (GPIO,VSS,MISC)
38. LYNX POINT_8 (POWER)
39. LYNX POINT_9 (POWER)
40. LYNX POINT_10 (GND)
41. VGA SWITCH / CRT
42. DISPLAY PORT CNTR
43. EDP& WEBCAM
44. SATA HDD&ODD CNTR
45. USB CONN(RIGHT)
46. FINGER PRINTER CNTR
47. ACCELEMETOR
48. KBC & SPI
49. KEYBOARD
50. SUPER I/O
51. TPM
52. NIC
53. LAN( SWITCH , TRANSFORMER)
54. WLAN
55. WWAN NGFF
56. NFC
5 4
57. DOCKING CNTR
58. AUDIO
59. EXT. MIC / MIC / HP
60. SCREW
61. RF SOLUTION
62. MB SIDE CONN
63. SMART CARD
64. POWER BUTTON BOARD
65. FUNCTION BUTTON BOARD
66. 14 B TO B CONNECTOR
67. 14" USB3.0 REDRIVER
68. 14" USB CONN (CHARGE)
69. 14" USB CONN
70. 14" CARD READER
71. 14" LAN CONN
72. 15 B TO B CONNECTOR
73. 15" USB3.0 REDRIVER
74 15" USB CONN (CHARGE)
75. 15" USB CONN
76. 15" CARD READER
77. 15" LAN CONN / SERIAL PORT
78. 15" SATA ODD DB
79. MIC BOARD
80. MARS-1
81. MARS-2
82. MARS-3
83. MARS-4
84. MARS-5
CHANGE by
XXX
XXX
DATE
26-NOV-2012
23
85. MARS-6
86. MARS-7
87 MARS-8
88. VRAM-1
89. VRAM-2
INVENTEC
TITLE
CYCLONE_DIS
TABLE OF CONTENTS
DOC.NUMBER
CODE
SIZE
1310A256641310A2566401-0-ALG
CS
A3
SHEET
of
22
90
1
REV
X01X01
D
CC
B
AA
8
7 6 5 4 3 2 1
FF
E
D
C
E
D
C
B
A
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
DOC.NUMBER
CODE
SIZE
1310A25664
CS
CHANGE by
8
7 6 5 4 3
XXX
DATE
26-NOV-2012
2 1
C
SHEET
of
3
B
A
REV
X01
90
8 7
6 5
4
3 2 1
OCPADAPTER
OCP_A_IN
LIMIT_SIGNAL
D
PVBAT
SDA_BAT_CHG
SCL_BAT_CHG
CHARGER
(BQ24736)
PVPACK
EN_PVPCIE
EN_1V8S
1.1V/1.8V
(RT8068)
PVPCIE
P1V8S
D
P5V0DS
3.3/5V
EN_3V_5V
EN_VRPVTT
EN_VRPVDDQ
(TPS51225)
1.35V
(TPS51216)
1.05V
EN_P1V05
B
(TPS51363)
P3V3DS
P5V0AL
P3V3AL
P1V35
P0V675S
P0V675M_VREF
P1V05M
EN_1V5S
1.5S
(APW7104)
P1V5S_PCH
CC
B
VCORE
EN_PVCORE
(TPS51631)
DGPU
EN_DGPU
(TPS51219)
1.35S
EN_P1V35S_DGPU
8
7 6
(TPS51362)
PVCORE
PVCORE_DGPU
P1V35S_DGPU
5 4
CHANGE by
XXX
DATE
26-NOV-2012
23
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
DOC.NUMBER
CODE
SIZE
1310A25664
CS
A3
SHEET
of
90
4
1
REV
X01
AA
8 7
6 5
4
3 2 1
Q6009
PVADPTR
C6019
2 1
220K_5%_2
0.1UF_16V_2
R6016
2 1
220K_5%_2
1
G
3
Q6013
P3V3DS
DS
1
G
100K_5%_2
SSM3K7002BFU
2
IN
ADP_EN
R6028
4.3K_5%_2
2 1
OUT
ADP_DET
21
R6021
127K_1%
2 1
3
DS
R6023
2 1
2
R6022
1M_5%_2
C6022
2 1
20K_1%_2
R6024
21
ACDET>0.6V:SMBUS OK
ACDET>2.4V&<3.1V:ACOK
100PF_50V_2
5
ICS
SDA_BAT_CHG
SCL_BAT_CHG
3
CHR_ILIM
3
V_3.9K
7 6
PVPACK
8
7
6
Q6012
D
PMOS_4D3S
AON7401L
1
S
2
3
45
G
D
PVBAT
Q6011
1
S
2
3
4 5
G
21
D6017
DB2J31300L
NMOS_4D3S
RQ3E080BNFU7TB
R6018
4.3K_5%_2
2 1
TI_BQ24736RGRR_QFN_20P
8
D
7
6
U6000
6
7
8
9
10
22K_5%_2
R6049
10K_5%_2
C6032
2 1
0.01UF_50V_2
21
OUT
BI
BI
C6049
2 1
100PF_50V_2
IN
IN
R6000
21
43
0.01_1%_6
C6028
21
0.1UF_16V_2
21
ACDET
IOUT
SDA
SCL
ILIM
C6029
1UF_25V_3
5
3
ACPRES
ACDRV
CMSRC
DLIM
SRN
SRP
13
12
11
C6030
2 1
CSC0402_DY
5
VADP_DEBUG
214
ACP
ACN
TML
VCC
PHASE
HIDRV
BTST
REGN
LODRV
GND
15
14
21
20
19
18
17
16
C6025
2 1
SHORT_0402_15
C6027
1UF_25V_3
2 1
2.2_5%_2
2 1
DB2J31300L
1UF_10V_2
C6031
2 1
0.01UF_50V_2
5 4
R6015
R6025
IN
21
D6016
21
R6027
10_5%_5
2 1
C6015
0.047UF_16V_2
R6020
SHORT_0402_15
12
PAD6015
2 1
POWERPAD_2_0610
IN
21
PVBAT_CHG
C6024
2 1
0.1UF_25V_2
R6001
0.02_1%_6
C6023
0.1UF_16V_2
PVPACK
21
43
C6012
C6011
21
C6010
2 1
2 1
10UF_25V_5
D6049
2 1
10UF_25V_5
CSC0805_DY
2 1
C6021
2 1
0.1UF_25V_2
876
5 4
LQ3E080BNFU7TB
21
LQ3E080BNFU7TB
21
Q6000
D
NMOS_4D3S
G
S
2
3
1
C6001
C6000
2 1
2 1
10UF_25V_5
10UF_25V_5
L6000
ETQP3W4R7WFN
678
Q6001
D
NMOS_4D3S
G
S
3
2145
R7600
2 1
C7600
CSC0402_DY
2 1
RSC_0603_DY
CC
B
LITEON_B0530W_DIODE
AA
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
CHANGE by
XXX
DATE
26-NOV-2012
23
SIZE
DOC.NUMBER
CODE
1310A25664
CS
A3
SHEET
of
5
1
REV
X01
90
VADPBL
3
1
S
2
3
45
G
R6017
8
7
6
OUT
Q6010
D
PMOS_4D3S
AON7401L
2 1
D
SSM3K7002BFU
3
DS
2
1
R6005
2
B
P5V0S PVADPTR P3V3DS
R6029
18.2K_1%_2
2 1
R6030
10K_1%_2
2 1
D6018
2 1
2 1
DA2J10100L
CHG_RST
IN
SSM3K7002BFU
1
Q6019
G
8
8 7
1
IN
VADPBL
R6933
274K_1%_2
21
6 5
P5V0DS P3V3DS
R6931
2 1
200K_1%_2
D
21
R6930
R6934
22K_5%_2
2 1
86.6K_1%_2
IN
52
U6903
+
1
+
OUT
3
-
-
AZV331KTR_E1
C6906
2 1
CSC0402_DY
3V3REF
4
21
R6935
4
5
2
47K_5%_2
OUT
ADP_PRES
OCP_MAIN#
LIMIT_SIGNAL_100R
3
LIMIT_SIGNAL
3
1
V_3.9K
VBIAS
B
4
P5V0S
R6920
21
665K_1%_2 1UF_10V_2
R6922
200K_1%_2
21
1
2
R6924
2 1
IN
2 1
R6925
118K_1%_2
200K_1%_2
R6923
1M_1%_2
2 1
BCD_AZV321KTR_E1_SOT23_5P
OUT
IN
IN
OUT
1
R6918
100_5%_2
P3V3DS
CHR_ILIM
Q6902
2
21
LES_LBSS84LT1G_SOT23_3P
R6916
2 1
2 1
47K_5%_2
S
RSC_0402_DY
R6914
3
D
G
1
C6902
2 1
3900PF_16V_2
LMBT3904WT1G
OUT
R6915
Q6901
3 2 1
C6904
21
U6902
IN+
VEE
D6902
R6937
2 1
0_5%_2_DY
BAV70W
3
VCC
OUTPUTIN-
5
43
21
P5V0S
C6903
R6919
2K_5%_2
2 1
P3V3DS
1
B
2 3
CE
PMBT3906
2 1
Q6903
0.1UF_16V_2
R6917
619_1%_2
2 1
1
B
C E
2 1
100K_5%_2
23
D6901
2 1
BZT52-B4V7S_DY
21
R6936
3.24K_1%_2
OUT
OCP_A_IN
D
CC
B
PVADPTR
R6902
2 1
R6903
2 1
VBIAS
130K_1%_2 220K_5%_2
LIMIT_SIGNAL_100R
3
OUT
VBIAS
LIMIT_SIGNAL_100R
IN
R6910
2 1
R6909
2 1
R6904
2 1
ADP_A_ID
45.3K_1%_2 8.66K_1%_2 8.06K_1%_2
3
P3V3DS
BASE
1
2 3
EMITTER COLLECTOR
Q6900
LES_LMBT3906WT1G_SOT323_3P
OUT
ADP_A_ID
3
AA
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
26-NOV-2012
23
1310A25664
CS
A3
SHEET
of
6
1
DOC.NUMBER
CODE
REV
X01
90
8 7
6 5
4
3 2 1
OCP=7AMP OCP=8AMP
P3V3DS
PAD6100
2 1
POWERPAD_2_0610
12
IN
VRP3V3A
PVBAT
D
12
VRPVBAT_3V
IN
C6110
2 1
L6100
ETQP3W3R3WFN
R6100
6.8K_1%_2
R6101
10K_1%_2
PAD6110
CSC0805_DY
21
2 1
8
DRVH2
SW2
DRVL2
VFB2
CS2
EN2
PGOOD
VREG3
U6100
VBST2
IN
C6122
2 1
1UF_25V_3
R6165
12
VIN
17
VBST1
16
DRVH1
18
SW1
15
DRVL1
14
VO1
2
VFB1
1
CS1
20
EN1
19
VCLK
13
VREG5
TMD
21
VRP5V0A_LDO
0_5%_3
VRP5V0A_HG
VRP5V0A_PH
VRP5V0A_LG
OUT
21
C6165
0.1UF_16V_2
R6160
2 1
VRP5V0A_VIN
678
C6111
2 1
R7610
2 1
AON7752
RSC_0603_DYCSC0402_DY
C7610
2 1
10UF_25V_5
Q6101
D
Q6100
NMOS_4D3S
G
S
3
214 5
678
D
G
S
3
214 5
AON7410
C6115
0.1UF_16V_2
21
VRP3V3A_HG
VRP3V3A_PH
VRP3V3A_LG
R6110
2 1
54.9K_1%_2
R6115
2.2_5%_3
8
OUT
VRP3V3A_LDO
OUT
21
TI_TPS51225CRUKR_QFN_20P
5V_PG
9
10
8
11
4
5
6
7
3
VRP5V0A_PH
OUT
54
NMOS_4D3S
Q6150
21
G
3
678
Q6151
AON7752
G
54.9K_1%_2
3
VRP3V3A
OUT
POWERPAD_2_0610
8 7
12
2 1
+
C6100
150UF_6.3V
2 1
B
VO=((6.8K/10K)+1)*2
3V3REF
EN_3V
8
16
IN
OUT
21
R6117
0_5%_2
C6121
2 1
1UF_6.3V_2
IN
EN_5V
C6120
2 1
1UF_6.3V_2
VRP5V0A_CLK
OUT
14
VRP5V0A
IN
7
2
214 5
876
D
S
1
D
S
AON7410
0.1UF_16V_2
P5V0DS
POWERPAD_2_0610
POWERPAD_2_0610
VRPVBAT_5V
PAD6160
78
IN
2 1
L6150
ETQP3W4R7WFN
R7615
2 1
RSC_0603_DYCSC0402_DY
C7615
2 1
3
2 1
C6156
PAD6150
2 1
12
PVBAT
12
2 1
C6161
C6160
2 1
10UF_25V_5
21
2 1
2 1
21
D6150
DIODES_BAV99
10UF_25V_5
R6161
SHORT_0402
R6150
15.4K_1%_210K_1%_2
+
C6150
2 1
150UF_6.3V
R6151
VO=((15.4K/10K)+1)*2
IN
VR_VDD5
21
VRP5V0A
OUT
VRP5V0A
OUT
14
7
D
CC
14
B
D6151
3
DATE
21
C6159
1UF_25V_3
2 1
26-NOV-2012
23
C6158
0.1UF_16V_2
2 1
P15V0A
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
DOC.NUMBER
CODE
SIZE
1310A25664
CS
A3
SHEET
7
AA
REV
of
X01
90
1
OUT
OUT
EN_3V
EN_5V
3
3
P3V3AL
PAD6103
2 1
12
POWERPAD1X1M
8
7 6
IN
VRP3V3A_LDO
R6987
21
SHORT_0402
R6988
SHORT_0402
21
P5V0AL
5 4
IN
EN_3V_5V
PAD6105
2 1
12
POWERPAD1X1M
VRP5V0A_CLK
IN
IN
CHANGE by
VRP5V0A_LDO
XXX
C6157
0.1UF_16V_2
2 1
DIODES_BAV99
8 7
PVBAT
6 5
4
3 2 1
PMC
D6997
21
R6999
2 1
SHORT_0603_25
SHORT_0603_25
PANJIT_MMSZ5252A
R6983
D
21
VADP_DEBUG
1
D
4
VRP5V0A_VIN
OUT OUT
PVADPTR
CC
R6913
46.4K_1%_2
21
21
C6900
R6990
2 1
0.22UF_6.3V_2
RSC_0402_DY
OUTIN
CURRENT_ADC
4
ICS
B
R6996
49
C6999
2 1
2 1
R6995
49.9K_1%_2
576K_1%_3
100PF_50V_2
21
C6998
R6994
2 1
2 1
49.9K_1%_2
0.22UF_6.3V_2
OUT
VOLTAGE_ADC
49
B
AA
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
26-NOV-2012
23
1310A25664
CS
A3
SHEET
of
8
1
DOC.NUMBER
CODE
REV
X01
90
8 7
6 5
4
3 2 1
D
P1V35
PVBAT
12
VR_VDD5
IN
678
3
214 5
678
3
D
S
D
S
2145
PVBAT_VDDQ
Q6200
Q6201
VRPVDDQ_PG
C6211
2 1
10UF_25V_5CSC0402_DY
21
R7620
RSC_0603_DY
C7620
2 1
P0V675S
C6216
2 1
2.2UF_6.3V_3
U6200
15
15
EN_VRPVTT
EN_VRPVDDQ
IN
IN
R6200
21
16.5K_1%_2
B
21
R6201
C6217
2 1
52.3K_1%_2
VOUT=REFIN=1.8*(52.3K/(16.5K+52.3K))
MODE=100KOHM:TRACKING DISCHARGE
C6218
2 1
0.01UF_50V_2
0.1UF_16V_2
R6203
200K_5%_2
2 1
17
16
6
8
7
19
18
21
TI_TPS51216RUKR_QFN_20P
R6202
75K_1%_2
S3
S5
VREF
REFIN
GND
MODE
TRIP
DRVH
DRVL
PGND
PGOOD
VDDQSNS
VLDOIN
VTTSNS
VTTGND
VTTREF
1512
VBSTV5IN
14
13
SW
11
10
20
9
2
3
VTT
1
4
5
21
TML
VRPVDDQ_HG
VRPVDDQ_PH
VRPVDDQ_LG
P0V675M_VREF
C6220
2 1
10UF_6.3V_3
R6215
0_5%_3
12
21
C6221
C6215
0.1UF_16V_2
0.22UF_6.3V_2
21
AON7410
NMOS_4D3S
G
AON7752
G
OUT
PAD6210
2 1
POWERPAD_2_0610
OUT
C6210
2 1
10UF_25V_5_DY
L6200
PAN_ETQP3W1R0WFN_4P
15
1 2
3 4
21
43
PAD6200
2 1
POWERPAD_2_0610
12
21
1 2
PAD6220
POWERPAD1X1M
+
2 1
OCP=10AMP
OUT
C6200
330UF_2V_9MR_PANA_-35%
IN
VRPVDDQ
VRPVDDQ
D
8
CC
8
B
AA
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
26-NOV-2012
23
1310A25664
CS
A3
SHEET
of
9
1
DOC.NUMBER
CODE
REV
X01
90
8 7
6 5
4
3 2 1
D
VR_VDD5 CHANGE TO P5V0A
P5V0A
R6304
VRP1V05
EN_P1V05
IN
IN
P1V05_PG
SHORT_0402_15
C6318
2 1
0.22UF_6.3V_2
P3V3DS
OUT
R6300
0_5%_2
21
0_5%_2
24
21
25
26
27
28
29
R6305
0_5%_2_DY
R6303
U6300
B
REFIN2
REFIN
VREF
RA
EN
TML
21
C6317
C6316
2700PF_50V_2
21
232221
GSNS
PGOOD
1
R6306
2.2UF_6.3V_3
2 1
2 1
2 1
0.1UF_25V_2
PAN_ETQP3W1R0WFN_4P
21
2 1
C6310
2 1
L6300
1 2
3 4
C6311
1918171615
20
V5
VIN
VIN
VIN
GND
TRIP
VSNS
SLEW
LP#
2
21
10
PGND
11
PGND
12
PGND
13
PGND
14
PGND
SWSWSWSWBSTNCMODE
TI_TPS51363RVER_QFN_28P
9876543
VRP1V05_PH
RSC_0603_DY
R7630
0_5%_2
C6315
21
2 1
0.1UF_16V_2
R6315
C7630
4.7_5%_2
CSC0402_DY
PAD6310
2 1
POWERPAD_2_0610
10UF_25V_5
21
C6300
21
43
PVBAT
12
21
C6301
22UF_6.3V_5
MODE= FLOAT FSW= 800K
TRIP =5V OCP=10A
REFIN =GND VOUT=1.05V
21
21
C6303
C6302
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
OUT
VRP1V05
VRP1V05
IN
PAD6300
1 2
POWERPAD_2_0610
P1V05M
21
IOUT=6A
D
CC
B
AA
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
26-NOV-2012
23
1310A25664
CS
A3
SHEET
of
1
DOC.NUMBER
CODE
REV
X01
9010
8 7
6 5
4
3 2 1
D
D
P3V3DS
PAD6360
21
1 2
POWERPAD1X1M
C6360
2 1
4.7UF_6.3V_3
EN_1V5S
IN
ANPEC_APW7104BTI_TRG_5P
B
VRP1V5_1V5IN
13
OUT
U6350
4 3
VIN SW
1
RUN
GND
2
VRP1V5S_PH
5
FB
L6350
PAN_ELL5PR2R2N
CC
OUT
VRP1V5S
2 1
10UF_6.3V_3
PAD6350
1 2
POWERPAD1X1M
21
R6350
C6353
2 1
2 1
330PF_50V_2
C6350
R6351
2 1
200K_1%_2 3 09K_1%_2
OCP=1.6AMP
P1V5S_PCH
21
B
VOUT=((309K/200K)+1)*0.6
AA
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
26-NOV-2012
23
1310A25664
CS
A3
SHEET
of
11
1
DOC.NUMBER
CODE
REV
X01
90
8 7
6 5
4
3 2 1
VFB
GFB
CSN3
CSP3
CSP2
CSN2
CSN1
CSP1
C6644
2 1
0.1UF_16V_2_DY
R6661
P5V0A
0.47UF_6.3V_2
21
COMP
DROOP
VBAT
SLEWA
16151413121110
21
R6658
10K_1%_2
21
100K_5%_NTC
VREF
THERM
21
10_5%_3
V5A
GND
IMON
OCP-I
R6665
1UF_6.3V_2
2 1
3032928272625
VR_HOT#
B-RAMP
21
R6654
21
R6655
C6643
333231
VCLK
PWPD
ALERT#
VDIO
VDD
PGOOD
PWM3
PWM2
PWM1
SKIP#
VR_ON
F-IMAX
O-USR
TI_TPS51631RSM_QFN_32P
9
39K_1%_2
95.3K_1%_2
C6645
2 1
VR_VDD5 CHANGE TO P5V0A
VREF_CPU
11
OUT
D
21
21
10K_5%_3
21
R6660
R6651
2.94K_1%_2
24
23
22
21
20
19
18
17
21
C6646
2 1
39K_1%_2
CPU_IMON
OUT
R6656
10K_1%_2
C6640
2.2PF_50V_2
R6662
11
VCCSENSE
11
VSSSENSE
12
CPU_CSP2
12
CPU_CSN2
CPU_CSN1
12
12
CPU_CSP1
PVBAT_CPU
IN
IN
IN
CPU_CSN3
CPU_CSP3
R6664
0_5%_2
21
P3V3A
0_5%_2_DY
2 1
R6663
0_5%_2_DY
2 1
B
IN
IN
IN
IN
IN
IN
R6657
21
R6659
RSC_0402
VREF_CPU
11
IN
R6646
R6649
R6655
R6662
R6663
R6619
R6629
R6639
37W
2 PHASE
487K
549K
178K
POP
POP
17.8K
2.94KR6651
47W
3 PHASE
274K
300K
95K
DNP
DNP
17.8K
2.94K
57W
3 PHASE
274K
255K
91K
DNP
DNP
17.8K
2.94K
PS: TOTAL OUTPUT CAPACITOR IS 38X22UF (0805) WITH 1MHZ SWITCHING FREQUENCY IS DEPEND ON -2.85MV/A DROOP SPEC
8
7 6
5 4
PVCCIO_OUT
D
CC
B
R6653
R6652
1
2
4
5
6
7
8
U6600
21
21
11
11
PVCORE_PG
CPU_PWM3
CPU_PWM2
CPU_PWM1
CPU_SKIP#
VR_ON
11
IN
18
19
19
11
19
11
12
12
12
12
P3V3A
21
R6645
10_5%_3
C6642
29
15
1UF_6.3V_2
2 1
VR_ON
C6641
2 1
0.1UF_10V_2_DY
OUT
130_1%_2
54.9_1%_2
21
R6643
21
R6644
R6640
R6641
10K_1%_2
VR_SVID_DATA
21
VR_SVID_CLK
21
IN
OUT
OUT
EN_PVCORE
19
11
11
19
15
4.99K_1%_2
OUT
CPU_PROCHOT#
IN
VR_SVID_CLK
IN
VR_SVID_ALERT#
IN
VR_SVID_DATA
OUT
OUT
OUT
OUT
OUT
IN
21
21
R6647
R6650
150K_1%_2
21
R6649
RSC_0402
150K_1%_2
150K_1%_2
21
R6646
VREF_CPU
274K_1%_2
300K_1%_2
4700PF_50V_2
DATE
57W
9V TO 20V
95A
33A
60A
105A
1MHZ
1.7V
1.5MOHM
26-NOV-2012
23
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
DOC.NUMBER
CODE
SIZE
1310A25664
CS
A3
SHEET
of
9012
1
REV
X01
AA
INPUT VOLTAGE RANGE
MAX CURRENT
THERMAL DESIGN CURRENT
DYNAMIC CURRENT
OVER CURRENT LEVEL
SWITCHING FREQUENCY
BOOT VOLTAGE
DC LOAD-LINE
CHANGE by
XXX
37W
9V TO 20V
55A
21A
35A
70A
1MHZ
1.7V
1.5MOHM
47W
9V TO 20V
85A
27A
60A
105A
1MHZ
1.7V
1.5MOHM
8 7
CPU_CSN1
OUT
CPU_CSP1
D
IN
IN
R6615
2.2_5%_3 0.1UF_16V_2
PVBAT_CPU
IN
VR_VDD5 CHANGE TO P5V0A
CPU_SKIP#
CPU_PWM1
C6615
21
TI_CSD97374CQ4M_SON_8P
21
U6610
8
PWM
SKIP#
7
BOOT
VDD
6
BOOT_R
PGND
5 4
VIN VSW
PGND
9
OUT
P5V0A
C6616
1UF_10V_2
1
2 1
2
3
R6616
2.32K_1% 10K_1%_NTC
6 5
C6618
21
CSC0402_DY
C6617
21
0.15UF_10V_2
R6619
21
17.8K_1%_2
21
R7661
RSC_0603_DY
R6617
ETQP4LR15AFM
3 4
1 2
L6610
21
R6618
3.01K_1%_2
43
21
21
PVCORE
2 1
C7661
CSC0402_DY
2 1
4
PVBAT
POWERPAD_2_0610
PAD6610
1 2
3 2 1
21
+
C6610
C6699
2 1
2 1
10UF_25V_5
100UF_25V_DY
C6620
C6611
2 1
2 1
10UF_25V_5
10UF_25V_5
C6630
C6621
2 1
10UF_25V_5
PVBAT_CPU
OUT
D
C6631
2 1
2 1
10UF_25V_5
10UF_25V_5
PVCORE
C6600
2 1
C6602
C6601
2 1
2 1
CSC0805_DY
22UF_6.3V_5
C6604
C6603
2 1
22UF_6.3V_5
C6605
2 1
2 1
CSC0805_DY
22UF_6.3V_5
C6607
C6606
2 1
2 1
CSC0805_DY
22UF_6.3V_5
C6609
C6608
2 1
2 1
CSC0805_DY
CSC0805_DY
CSC0805_DY
CC
CPU_CSN3
U6630
SKIP#
PGND
PGND
9
OUT
C6638
CSC0402_DY
C6637
R6639
17.8K_1%_2
21
43
21
21
21
21
R6638
B
21
PVCORE
AA
CPU_CSP3
OUT
P5V0A
C6636
1UF_10V_2
2 1
1
2
VDD
3
R6636
2.32K_1%
0.15UF_10V_2
R6637
21
10K_1%_NTC 3.01K_1%_2
ETQP4LR15AFM
3 4
1 2
L6630
R7663
RSC_0603_DY
2 1
C7663
CSC0402_DY
2 1
CPU_CSN2
OUT
CPU_CSP2
U6620
SKIP#
PGND
PGND
9
OUT
P5V0A
C6626
1UF_10V_2
1
2 1
2
VDD
3
R6626
2.32K_1%
21
10K_1%_NTC 3.01K_1%_2
R7662
RSC_0603_DY
B
VR_VDD5 CHANGE TO P5V0A
CPU_SKIP#
IN
CPU_PWM2
IN
R6625
21
2.2_5%_3 0.1UF_16V_2
PVBAT_CPU
IN
TI_CSD97374CQ4M_SON_8P
C6625
8
PWM
21
7
BOOT
6
BOOT_R
5 4
VIN VSW
CSC0402_DY
0.15UF_10V_2
17.8K_1%_2
R6627
21
ETQP4LR15AFM
3 4
1 2
L6620
C6628
C6627
R6629
43
21
21
VR_VDD5 CHANGE TO P5V0A
21
21
R6628
21
PVCORE
CPU_SKIP#
IN
CPU_PWM3
IN
R6635
2.2_5%_3 0.1UF_16V_2
PVBAT_CPU
IN
C6635
21
TI_CSD97374CQ4M_SON_8P
8
PWM
7
21
6
5 4
BOOT
BOOT_R
VIN VSW
2 1
C7662
CSC0402_DY
2 1
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
26-NOV-2012
23
1310A25664
CS
A3
SHEET
of
1
DOC.NUMBER
CODE
REV
X01
9013
8 7
6 5
4
3 2 1
D
B
DGPU_VID1
DGPU_VID2
DGPU_VID3
DGPU_VID4
DGPU_VID5
IN
IN
IN
IN
IN
8
R6766
SHORT_0402
R6767
SHORT_0402
R6768
SHORT_0402
R6769
SHORT_0402
R6770
SHORT_0402
21
U6751
ANPEC_APL6502A8I_TRG_8P
21
5
VID0
2
VID1
21
1
VID2
8
VID3
7 6
VID4 GND
21
21
R6752
P3V3S
3
VDA
4
VDD
10_5%_2
C6770
2 1
C6773
0.033UF_16V_2
2 1
1UF_6.3V_3
7 6
D
PVCORE_DGPU
MAX=50A
OCP=42A
VRPVCORE_DGPU
PVBAT
PAD6750
21
IN
1 2
POWERPAD_2_0610
CC
EN_DGPU
IN
+
C6799
2 1
R6755=100K , FSW=300KHZ
OUT
51219VREF
21
DGPU_PG
R6750
0_5%_2_DY
2 1
1
2
3
4
C6769
R6751
0_5%_2_DY
2 1
C6768
2 1
2 1
1000PF_50V_2
0.1UF_16V_2
2 1
0.01UF_50V_2
R6755
2 1
OUT
17
U6750
PWPD
VREF
REFIN
TI_TPS51219RTER_QFN_16P
GSNS
VSNS
COMP
C6767
5
R6756
VSNS
GSNS
C6774
1000PF_50V_2
2 1
R6755=200K , FSW=400KHZ
200K_5%_2
R6755=1K , FSW=500KHZ
14
EN
MODE
GND
PGND
7
64.9K_1%_2
10_1%_2
SHORT_0402_15
13
BST
R6759
R6760
SW
DH
DL
V5
16815
PGOOD
TRIP
6
2 1
R6765
2.2_5%_3
21
12
VRPVCORE_DGPU_PH
11
VRPVCORE_DGPU_HG
10
VRPVCORE_DGPU_LG
9
C6766
2 1
2.2UF_6.3V_3
21
21
IN
IN
IN
0.1UF_16V_2
VR_VDD5
C6765
21
6134
7
GPU_VCC_SENSE
GPU_VSS_SENSE
Q6750
TI_CSD87588N_LGA_5P
1
TG
21
4
BG
R6762
SHORT_0603_25
C6775
CSC0402_DY
21
Q6751
TI_CSD87588N_LGA_5P
R6763
1
TG
SHORT_0603_25
4
BG
CHANGE by
VIN
Control
FET
VSW
Sync
FET
PGND
3
21
VIN
Control
FET
VSW
Sync
FET
PGND
3
5 4
XXX
12
PAD6760
15UF_25V_DY
2 1
POWERPAD_2_0610
2
5
2
5
VRPVBAT_DGPU
C6761
C6760
2 1
10UF_25V_5
PCMC104T_R36MN
R7675
2 1
RSC_0603_DYCSC0402_DY
C7675
2 1
2 1
L6750
C6763
C6762
2 1
2 1
10UF_25V_5
10UF_25V_5
21
43
0.1UF_25V_2
OUT
VRPVCORE_DGPU
B
1
+
C6750
470UF_2V
3
2
AA
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
DATE
26-NOV-2012
23
SIZE
DOC.NUMBER
CODE
1310A25664
CS
A3
SHEET
of
1
REV
X01
9014
8 7
6 5
4
3 2 1
D
C6255
PVBAT_P1V35S_DGPU
21
R6258
0_5%_2
24
25
26
27
28
29
R6253
U6250
REFIN2
REFIN
VREF
RA
EN
TML
C6256
2700PF_50V_2
21
232221
GSNS
PGOOD
1
2.2UF_6.3V_3
2 1
2 1
C6261
2 1
1918171615
20
V5
VIN
VIN
VIN
GND
TRIP
VSNS
SLEW
LP#
2
21
R6256
0_5%_2
C6265
21
PGND
PGND
PGND
PGND
PGND
SWSWSWSWBSTNCMODE
9876543
VRP1V35S_DGPU_PH
2 1
0.1UF_16V_2
R6265
2.2_5%_3
0.1UF_25V_2
10
11
12
13
14
TI_TPS51363RVER_QFN_28P
RSC_0603_DY
R7625
PAN_ETQP3W1R0WFN_4P
21
C7625
2 1
CSC0402_DY
POWERPAD_2_0610
C6260
2 1
10UF_25V_5
21
1 2
43
3 4
L6250
OCP=10A
MODE= FLOAT FSW= 800K
VOUT=2V*R6251/(R6250+R6251)=1.35V
R6254
1213
7
VR_VDD5
VRP1V35S_DGPU
EN_1V35S_DGPU
IN
1V35S_DGPU_PG
B
IN
IN
R625121R6250
210K_1%_2
C6257
2 1
0.22UF_6.3V_2
SHORT_0402_15
21
100K_1%_2
OUT
P3V3DS
2 1
0_5%_2_DY
PAD6260
1 2
PVBAT
21
21
21
21
21
C6250
C6252
C6251
22UF_6.3V_5
C6253
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
VRP1V35S_DGPU
VRP1V35S_DGPU
INOUT
PAD6250
1 2
POWERPAD_2_0610
21
P1V35S_DGPU
IOUT=8A
D
CC
B
AA
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
26-NOV-2012
23
1310A25664
CS
A3
SHEET
of
1
DOC.NUMBER
CODE
REV
X01
9015
8 7
6 5
4
3 2 1
D
D
P5V0DS
PAD6971
21
1 2
POWERPAD_2_0610
CC
C6975
2 1
10UF_6.3V_3
RICHTEK_RT8068AZQW_WDFN_10P
C6972
EN_1V8S
2 1
B
1UF_6.3V_2
U6970
11
TML
10 1
LX
PVIN
9
LX
PVIN
8
LX
SVIN
7
PGOOD
NC
6 5
EN
FB
IN
VRP1V8S_PH
2
3
4
OUT
L6970
21
ELL5PR1R2N
1V8S_PG
21
R6970
R6971
2 1
VREF=0.6V
15K=1.5V
10K=1.2V
20.5K=1.83V
MODE= FLOAT=SKIP MODE
MODE=VIN=FCCM MODE
IOUT=1.68A
OUT
VRP1V8S
C6974
C6970
2 1
20.5K_1%_2
10K_1%_2
2 1
CSC0402_DY
22UF_6.3V_5
VRP1V8S
IN
PAD6970
POWERPAD_2_0610
1 2
P1V8S
21
B
AA
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
26-NOV-2012
23
1310A25664
CS
A3
SHEET
of
1
DOC.NUMBER
CODE
REV
X01
9016
8 7
6 5
4
3 2 1
D
P5V0DS
PAD6951
21
1 2
POWERPAD_2_0610
OUT
VRPVPCIE
OCP=4.5AMP
PVPCIE
D
CC
C6955
2 1
10UF_6.3V_3
11
TML
10 1
PVIN
9
PVIN
8
SVIN
7
NC
6 5
FB
B
RICHTEK_RT8068AZQW_WDFN_10P
C6952
2 1
1UF_6.3V_2
U6950
PGOOD
LX
LX
LX
EN
VRPVPCIE_PH
2
3
4
PVPCIE_PG
OUT
IN
EN_PVPCIE
L6950
ELL5PR1R2N
PAD6950
21
POWERPAD_2_0610
VOUT=((5.9K/10K)+1)*0.6
R6950
2 1
C6950
C6954
5.9K_1%_2
2 1
2 1
CSC0402_DY
22UF_6.3V_5
1 2
21
B
R6951
10K_1%_2
2 1
AA
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
26-NOV-2012
23
1310A25664
CS
A3
SHEET
of
1
DOC.NUMBER
CODE
REV
X01
9017
OUT
4
CN6000
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
ACES_59011_0087N_001_8P
6012B0156001-005
LIMIT_SIGNAL
3 2 1
D
6
57
8 7
D
6 5
PVADPTR
C6037
C6038
2 1
100PF_50V_2
2 1
1000PF_50V_2
L6035
NFE31PT222Z1E9L
4
3
21
1
2
1
D6035
C6035
C6036
2 1
2 1
100PF_50V_2
1000PF_50V_2
2
3
3
PANJTT_PJSOT24C_SOT23_3P
CC
P3V3DS
21
D7504
12
2 1
R6057
1K_5%_2
2 1
R6058
100K_5%_2
C7501
PHP_PESD5V0S1BB_SOD523_2P
21
2 1
C7503
R6050
2.2K_5%_2
2 1
R6051
100_5%_2
R6053
100_5%_2
3
D7502
C7500
2 1
100PF_50V_2
21
21
21
P3V3DS
3
PVPACK
48
48
SDA_MAIN
SCL_MAIN
BI
BI
R6052
2 1
2.2K_5%_2
B
P3V3DS
21
21
3
D7500
D7501
BAV99W_7_F
BAV99W_7_F
BAV99W_7_F
OUT
12
2 1
100PF_50V_2
2 1
P3V3DS
21
100PF_50V_2
D7503
MAIN_BAT_DET#
D7505
PHP_PESD5V0S1BB_SOD523_2P
R6055
3
BAV99W_7_F
12
2 1
2 1
100_5%_2
OUT
BATTERY OCP PWM#
48
D7506
C7502
PHP_PESD5V0S1BB_SOD523_2P
OCP_MAIN#
0.1UF_25V_2
CN6050
8
8
7
6
5
4
3
2
1
6012B0421501
G2
7
G
G1
6
G
5
4
3
2
1
TAIT_PMPCRD_08MLBS2ZZ4H0_8P
6
B
AA
INVENTEC
TITLE
CYCLONE_DIS
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
26-NOV-2012
23
1310A25664
CS
A3
SHEET
of
1
DOC.NUMBER
CODE
REV
X01
9018
8 7
REFERENCE NUMER : 7000~7350
P5V0DS
1
2
5
SPWON
C7050
2 1
10UF_6.3V_3
D
P15V0A
IN
20
19
SSM3K7002BFU
P3V3DS P3V3S P5V0S
Q7050
1
D
2
5
G
NMOS_4D1S
AO6402AL AO6402AL
MAX 3.3A
4
S
36
SPWON
R7101
21
3
470K_5%_2
DS
Q7055
1
G
R7050
47_5%_2
2 1
2
3
Q7051
DS
1
G
SSM3K7002BFU
2
Q7100
D
NMOS_4D1S
6 5
P1V05M
MAX 7.5A
P1V35
MAX 2.8A
4
S
36
G
Q7151
8
D
7
6
5 4
NMOS_4D3S
FDMS7692
P1V35S
1
S
2
3
G
SPWON
PAD2990
1 2
POWERPAD_2_0610_DY
Q7153
8
D
7
6
FDMS0310AS
SPWON
4
P1V05S
NON-IAMT INSTALL
21
1
S
2
3
45
G
PAD2990
UN-INSTALL INSTALL
IAMT
C2995
C2994
2 1
22UF_6.3V_5_DY
P0V675S
2 1
CSC0402_DY
C7100
R7100
100_5%_2
2 1
2 1
10UF_6.3V_3
3
Q7101
DS
1
G
SSM3K7002BFU
2
C7150
1
Q7150
G
C7151
R7150
220_5%_2
2 1
2 1
3
DS
SSM3K7002BFU
2
10UF_6.3V_3
2 1
CSC0402_DY
C7152
1
Q7154
G
C7153
R7152
220_5%_2
2 1
2 1
3
DS
SSM3K7002BFU
2
10UF_6.3V_3
Q7155
1
3 2 1
Q7153
UN-INSTALL
C2996
2 1
2 1
22UF_6.3V_5_DY
G
10UF_6.3V_3
21
R7153
22_5%_2
3
DS
SSM3K7002BFU
2
19
SLP_LAN#
Q2971 WHETHER CAN CHANGE TO
6015B0017101 PMV65XP OR NOT
1
SSM3K7002BFU
Q2970
G
SLP_LAN#
IN
4834
P3V3DS
R2971
2 1
3
DS
2
47K_5%_2
SSM3K7002BFU
Q7056
1
G
P3V3DS P3V3M
Q2971
1
D
2
5
NMOS_4D1S
AO6402AL
470K_5%_2
1
IN
P15V0A
20
R7102
I113
2
3
DS
SSM3K7002BFU
2
4
S
36
G
19
2 1
R2972
3
Q2972
DS
1
G
2
D
C2971
47_5%_2
2 1
10UF_6.3V_3
CC
SLP_S3_5R
19
5423
B
26
48
62
58
34
SLP_S3#_3R
42
IN
19
41
20
P1V05M
C2990
C2993
2 1
22UF_6.3V_5_DY
REFERENCE NUMER : 2950~2999
8
SLP_S3_5R
OUT
Q7002
1
SSM3K7002BFU
2 1
10UF_6.3V_3
NON-IAMT INSTALL
IAMT
P5V0DS
R7005
2 1
200K_5%_2
3
1
DS
G
SSM3K7002BFU
2
FOR IAMT
PAD2990
UN-INSTALL
P1V8SPVPCIE
21
R7301
Q7301
1
G
Q7302
G
R7302
47_5%_2
3
DS
2
Q2992,Q2993
R2992,R2993
UN-INSTALL
INSTALL
C7302
2 1
10UF_6.3V_3_DY
SSM3K7002BFU
7 6
MAX 1.5A
21
C7301
47_5%_2
3
DS
2
R7033
21
EN_PVCOREPWR_GOOD_3
0_5%_2
D7033
21
R7023
R7020
R7019
EN_DGPU
15
2 1
1N4148WS_7_F
21
21
21
C7037
14
EN_3V_5V
7
OUTIN
OUTIN
C7035
CSC0402_DY
CSC0402_DY
2 1
2 1
R7110
OUT IN
10K_5%_2
21
CHANGE by
IN
VGATE
34
12
PVCORE_PG
2 1
10UF_6.3V_3_DY
DGPU_PWR_EN
7
19
SLP_S3#_3R
20
48
PM_SLP_A#
62
19
80
5V_PG
IN
IN OUT
R7031
21
R7032
C7031
2 1
CSC0402_DY
21
SHORT_0402
4.7K_5%_2
SHORT_0402
OUTIN
OUT
EN_1V35S_DGPU
R7430
0_5%_2_DY
SHORT_0402
SHORT_0402
C7032
2 1
0.1UF_16V_2
5 4
12
IN
RSMRST#
EN_1V5S
EN_P1V05
DGPU_PWR_EN
19
19
DGPU_PWR_EN
22
34
48
11
10
9
OUT IN
48
SLP_S3#_3R
582026
34
62
19
41
42
IN
IN
EN_VRPVDDQ
1K_5%_2
10K_5%_2
R7044
SHORT_0402
R7013
SHORT_0402
R6252
21
R7034
21
EN_VRPVTT
21
2 1
CSC0402_DY
21
2 1
CSC0402_DY
EN_P1V5
C7034
EN_PVPCIE
C7039
EN_1V8S
OUTIN
OUT
OUT
23
57
9
POWER TO EE NET NAME CONNECTION
R7111
100K_5%_2
0.1UF_16V_2
21
VRP3V3A_LDO
7
DATE
26-NOV-2012
INVENTEC
TITLE
CYCLONE_DIS
POWER (SLEEP)
DOC.NUMBER
CODE
SIZE
23
CSA3
1310A25664
SHEET
of
90
19
1
21
C7110
2 1
XXX
16
17
B
AA
REV
X01
8 7
6 5
4
3 2 1
I217
REFERENCE NUMER : 7400~7450
D7400
1
2
3V3REF
6
7
20
IN
3
3
R7409
10K_5%_2
R7410
57.6K_1%_2
21
21
R7418
C7403
2 1
22.6K_1%_2
3300PF_50V_2
21
R7408
21
10K_5%_2
21
R7401
C7401
2 1
53.6K_1%_2
3300PF_50V_2
D
P1V5S_PCH
19
342641
42
586248
20
34
48
SLP_S3#_3R
IN
IN
P5V0S
M_PWROK
R7405
21
76.8K_1%_2
R7416
21
23.2K_1%_2
R7414
21
3.3K_5%_2
R7415
21
3.3K_5%_2
PANASONIC_DB3X313J0L_SOT_3P
1
2
P1V05S
R7426
21
16.2K_1%_2
R7423
15
16
17
1V35S_DGPU_PG
IN
IN
PVPCIE_PG
IN
9
IN
1V8S_PG
P3V3S
VRPVDDQ_PG
R7425
51.1K_1%_2
0_5%_2
R7424
0_5%_2
R7429
0_5%_2
21
3.3K_1%_2
R7428
21
21
21
R7411
3.3K_5%_2_DY
21
B
21
C7402
2 1
1000PF_50V_2
5
6
21
R7412
31.6K_1%_2
3
2
R7407
21
1M_5%_2
P5V0A
V+
U7400
+IN
+
OUT
-
-IN
V-
ON_LMV393DMR2G_SOP_8P
4 8
R7406
21
1M_5%_2
P5V0A
C7400
0.1UF_16V_2
V+
U7400
+IN
+
OUT
-
-IN
V-
ON_LMV393DMR2G_SOP_8P
4 8
7
ON_LMV393DMR2G_SOP_8P
48
23
48
OUT
PWR_GOOD_3
IN
L2N7002DW1T1G
6015B0098401
KBC_PWR_ON
P3V3S
R7404
2 1
7
21
3.3K_5%_2
1
P5V0DS
C7420
21
0.1UF_16V_2
V+
U2950
OUT
5
+IN
+
-
6
-IN
V-
4 8
P5V0DS
IN
P15V0A
470K_5%_2
C7351
R7352
2 1
19
1
Q7354
21
R7354
3
DS
G
2
I223
R7350
100K_5%_2
2 1
Q7350
1
S1
2
G1
6
D1
3
D2
5
G2
4
S2
SSM3K7002BFU
CSC0402_DY
21
100_5%_2
C7350
10UF_6.3V_3
2 1
1
8
7
6
Q7355
Q7351
D
NMOS_4D3S
FDMC7692
3
DS
G
2
S
G
I220
R7355
2 1
100_5%_2
I219
SSM3K7002BFU
1
2
3
45
C7355
2 1
P3V3DSP5V0DS
Q7353
8
D
7
6
NMOS_4D3S
FDMC7692
R7353
2 1
3
100_5%_2
Q7352
DS
1
G
2
SSM3K7002BFU
10UF_6.3V_3
P3V3AP5V0A
1
S
2
3
45
G
D
C7352
2 1
10UF_6.3V_3
CC
B
3V3REF
IN
6
20
7
FOR IAMT
P3V3M
P1V05M
19
34 20
48
PM_SLP_A#
62
IN
PM_SLP_A#
REFERENCE NUMER : 2950~2999
8
R2957
3.3K_5%_2
R2950
46.4K_1%_2
R2959
41.2K_1%_2
R2958
13K_1%_2
21
21
21
21
21
R2951
C2950
2 1
35.7K_1%_2
1000PF_50V_2
3
3
D2951
1
2
2
1
PANASONIC_DB3X313J0L_SOT_3P
21
R2960
0_5%_2_DY
7 6
C2952
2 1
R2955
10K_5%_2
3300PF_50V_2
P3V3A
R2953
21
1M_5%_2
P5V0DS
V+
3
21
2
U2950
+IN
+
OUT
-
-IN
V-
ON_LMV393DMR2G_SOP_8P
4 8
R2956
1M_5%_2
C2951
0.068UF_10V_2
R2954
2 1
3.3K_5%_2
1
21
21
M_PWROK
R2952
2 1
OUT
M_PWROK
1K_1%_2
5 4
20
34 48
AA
INVENTEC
TITLE
CYCLONE_DIS
POWER(SEQUENCE)
CHANGE by
XXX
DATE
26-NOV-2012
23
SIZE
DOC.NUMBER
CODE
1310A25664
CS
A3
SHEET
of
1
REV
X01
9020
8 7
6 5
4
3 2 1
REFERENCE NUMBER:4450~4499
D
48
PWM_3S_FAN#
B
REFERENCE NUMBER:4400~4349
22_5%_2_DY
P5V0S
5
U4300
+
1
2
-
TC7SET00F
3
21
THERM#
IN
IN
R4300
4
21
R4302
22_5%_2
TACH_FAN_IN_1126
21
P5V0S
48
OUT
R4453
2 1
0_5%_2_DY
P3V3S
C4450
2 1
2.2K_5%_2
R4955
0.1UF_16V_2
U4450
1
VDD
2
DP
3
DN
SMSC_EMC1412_1_ACZL_TR_MSOP_8P
21
SMCLK
SMDATA
ALERT#
R4452
10K_5%_2
2 1
8
7
6
54
GNDTHERM#/ADDR
R4451
R4450
2 1
2 1
2.2K_5%_2
2.2K_5%_2
32
80
32
80
37
OUT
BI
BI
THERM_CLK_GPU
THERM_DATA_GPU
THERM_SCI#
P3V3S
21
R4301
10K_5%_2
ACES_50273_0047N_001_4P
3
2
1
CN4300
G2
GG4
G1
GPU_THRM_DPLUS
80
OUT
GPU_THRM_DMINUS
80
OUT
7
1921
EN_3V_5V
21
THERM#
OUT
OUT
4
3
2
1
6012A0081607
C4300
2 1
1
PMBT3904_DY
B
C E
Q4450
C4451
1000PF_50V_2
23
21
R4454
0_5%_2
21
D
CC
0.1UF_16V_2_DY
CYCLONE-UMACYCLONE-DIS
INSTALLUNINSTALL
Q4450
*
B
AMBIENT TEMP SENSE
P5V0DS
THERM SENSOR
R4412
150_5%_2
21
TI_TMP708AIDBVR_SOT23_5P
C4411
2 1
0.1UF_16V_2
U4411
5 1
VCC SET
GND
OTHYST
2
34
EN_3V_5V
IN
R4411
EN_3V_5V
21
7
19 21
25.5K_1%_2
AA
REFERENCE NUMBER:4411~4449
8
7 6
RSET (K OHM) = 0.0012T^2 - 0.9308T + 96.147
THERMAL SHUTDOWN AT 85 DEG.
5 4
CHANGE by
XXX
DATE
26-NOV-2012
23
INVENTEC
TITLE
CYCLONE_DIS
FAN & THERMAL
DOC.NUMBER
CODE
SIZE
1310A25664
CS
A3
SHEET
of
21
90
1
REV
X01
8 7
6 5
4
3 2 1
PVCCIO_OUT
CN4920
GND0
TP16
3
OBSFN_A0
5
OBSFN_A1
GND2
9
OBSDATD_A0
11
OBSDATD_A1
GND4
15
OBSDATD_A2
17
OBSDATD_A4
GND6
21
OBSFN_B0
23
OBSFN_B1
GND8
27
OBSDATA_B0
29
OBSDATA_B1
GND10
33
OBSDATA_B2
35
OBSDATA_B3
GND12
39
PWRGOOD_HOOK0
41
HOOK1
VCC_OBS_AB
45
HOOK2
47
HOOK3
GND14
51
SDA
53
1
SCL
TCK1
57
TCK0
GND16
SAMTEC_BSH_030_01_L_D_A_TR_60P
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSFN_D0
OBSFN_D1
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK_HOOK4
ITPCLK#_HOOK5
VCC_OBS_CD
RESET#_HOOK6
DBR#_HOOK7
23
H_PREQ#
23
D
23
23
23
37
22
34 6248
H_PWRGD
PWR_BTN_OUT#
VGATE
C4937
2 1
0.1UF_16V_2
H_PRDY#
27
CFG<0>
27
CFG<1>
27
CFG<2>
22
27
CFG<3>
H_BPM0_XDP#
H_BPM1_XDP#
CFG<4>
27
CFG<5>
27
CFG<6>
27
CFG<7>
R4926
IN
IN
24
PWR_DEBUG
32
PCH_3A_SMDATA
32
PCH_3A_SMCLK
23
H_TCK
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
1K_5%_2
21
OUT
BI
BI
IN
TP4920
GND1
GND11
GND13
GND15
TRSTn
GND17
GND3
GND5
GND7
GND9
21
4
6
87
10
12
1413
16
18
2019
22
24
2625
28
30
3231
34
36
3837
40
42
4443
46
48
5049
52
TDO
54
5655
TDI
58
TMS
6059
R4748
R4921
21
1K_5%_2_DY
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
CFG<17>
CFG<16>
CFG<8>
CFG<9>
CFG<10>
CFG<11>
CFG<19>
CFG<18>
CFG<12>
CFG<13>
CFG<14>
CFG<15>
21
CFG<3>
1K_5%_2
27
27
27
27
27
27
27
27
2727
27
27
27
OUT
R4922
1K_5%_2
2 1
22
27
PVCCIO_OUTP3V3S
R4526
51_5%_2
2 1
R4526 PLACE IT NEAR XDP
BUF_PLT_RST#
IN
IN
XDP_DBRESET#
IN
H_TDO
IN
H_TRST#
IN
H_TDI
IN
H_TMS
51
62 34 23
23
23
23
22
23
D
31
35
48
54
5562
CC
CLOSE XDP CONN
CPU XDP CONNECTOR
REV
X01
B
AA
B
CN4936
G1
G
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
G2
ACES_50525_02601_001_26P_DY
G
PCH XDP CONNECTOR
CHANGE by
XXX
DATE
26-NOV-2012
23
INVENTEC
TITLE
CYCLONE_DIS
XDP CONN
DOC.NUMBER
CODE
SIZE
1310A25664
CS
A3
SHEET
of
9022
1
NON-INSTALL CN4936,R4937,R4936 ON PV BUILD
8
7 6
19
3448
22
48
22
34 23 62
6234
31
31
31
RSMRST#
PWR_BTN_OUT#
34
PCH_PWROK
XDP_DBRESET#
32
PCH_TDO
32
PCH_TDI
32
PCH_TMS
31
PCH_TCK
IN
OUT
IN
IN
IN
IN
IN
IN
R4937
R4936
P3V3A
C4936
21
PVCCIO_OUT
21
R4938
0_5%_2_DY
2 1
0.01UF_50V_2
1K_5%_2_DY
1K_5%_2_DY
21
5 4
8 7
6 5
4
3 2 1
REFERENCE NUMBER:4500~4699
D
34
PM_DRAM_PWRGD
20
48
B
PWR_GOOD_3
NXP_74AHC1G09GV_SOT753_5P
19
54
33
8
IN
IN
SLP_S3_5R
32
IN
48
IN
FOR DEEP S3
P3V3S
R4529
200_1%_2
2 1
U4502
1
B
2
A
3
GND
IN
SSM3K7002BFU_DY
R4580
10K_5%_2
PCH_DDR_RST
KBC_DS3_EN
R4585
20K_5%_2
P1V35S
21
C4523
2 1
0.1UF_16V_2
1UF_6.3V_2
R4527
C4524
P3V3A
2 1
1.8K_1%_2
5
VCC
1
Y
Q4501
4
R4528
2 1
3
DS
G
21
R4542
39_5%_2_DY
PM_SYS_PWRGD_BUFF
3.3K_1%_2
2
R4583
20K_5%_2_DY
R4581
3.3K_5%_2
Q4580
1
21
G
DDR_RST_EN
3
DS
SSM3K7002BFU_DY
21
21
2
D4581
BAT54C
7 6
12
23
PCH_PLTRST_CPU
37
P3V3DS
21
OUT
R4586
20K_5%_2
3
C
A2A1
CPU_PROCHOT#
22
H_PWRGD
37
PVCCIO_OUT
10K_5%_2_DY
R4555
10K_5%_2_DY
R4554
23
EN_P1V5
R4587
21
0_5%_2
R4588
0_5%_2_DY
21
SLP_S4#_3R
IN
2 1
47PF_50V_2
C4514
IN
IN
CK_DP_SSC_DP
21
CK_DP_SSC_DN
21
23
IN
OUT
SLP_S4#_KBC
21
21
C4513
R4510
DDR_RST_EN
34
IN
PVCCIO_OUT
R4517
62_5%_2
2 1
56_5%_2
2 1
R4513
0_5%_2
33
CK_DP_NONSSC_R_DN
33
CK_DP_NONSSC_R_DP
33
33
33
CLK_DMI_PCH_DN
33
CLK_DMI_PCH_DP
C4570
2 1
470PF_50V_2
R4550
2 1
4.99K_1%_2
KBC_PROCHOT
48
EN_P1V5
19
OUT
6245
R4515
CSC0402_DY
10K_5%_2
21
21
CK_DP_SSC_DN
CK_DP_SSC_DP
BSS138LT1
57
48
37 23
48
21
37
80
PM_THRMTRIP#
34
PLTRSTIN#
3
Q4502
DS
1
G
2
IN
23
5 4
H_PECI
H_PM_SYNC
R4530
0_5%_2
IN
IN
IN
IN
IN
IN
R4556
21
0_5%_2
R4551
0_5%_2
TP689
TP503
OUT
OUT
BI
21
P1V35
R4553
1K_1%_2
2 1
R4552
21
DDR3_DRAMRST#
1K_5%_2
21
R4589
0_5%_2_DY
21
DDR3_DRAMRST#_CPU
P3V3S
C4505
2 1
1
0.1UF_16V_2
NC
2
R4516
2 1
100K_5%_2
Haswell rPGA EDS
CN4555
AP32
1
SKTOCC*
AN32
1
CATERR*
AR27
PECI
AK31
FC
AM30
PROCHOT*
AM35
THERMTRIP*
AT28
PM_SYNC
AL34
PWRGOOD
AC10
SM_DRAMPWROK
AT26
PLTRSTIN*
G28
DPLL_REF_CLKN
H28
DPLL_REF_CLKP
F27
SSC_DPLL_REF_CLKN
E27
SSC_DPLL_REF_CLKP
D26
BCLKN
E26
BCLKP
MISC
THERMAL
DDR3
PWR
CLOCK
SOCKET,CPU,947P,1.0MM,1.0CC,GOLD,15U,BGA,TRAY
6026B0231701
30
29
OUT
23
IN
5
U4501
+
4
OUT
-
TC7SZ05F
3
CPU_PROCHOT#
CHANGE by
XXX
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
SM_DRAMRST*
JTAG
BPM_N_0
BPM_N_1
BPM_N_2
BPM_N_3
BPM_N_4
BPM_N_5
BPM_N_6
BPM_N_7
12
23
PRDY*
PREQ*
TCK
TMS
TRST*
TDI
TDO
DBR*
AP3
R4518
AR3
R4541
AP2
R4540
AN3
NEED CLOSED TO CPU AT 500MIL
AR29
AT29
AM34
AN33
AM33
AM31
AL33
AP33
AR30
AN31
H_BPM2_XDP#
AN29
H_BPM3_XDP#
AP31
H_BPM4_XDP#
AP30
H_BPM5_XDP#
AN28
H_BPM6_XDP#
AP29
H_BPM7_XDP#
AP28
22
23
22
23
DATE
26-NOV-2012
23
21
100_1%_2
21
75_1%_2
21
100_1%_2
OUT
DDR3_DRAMRST#_CPU
OUT
H_PRDY#
OUT
H_PREQ#
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
1
1
1
1
1
1
PLACE R4508 NEAR CPU
23
H_TDI
22
H_TMS
22
23
H_TCK
22
H_TCK
22
H_TMS
H_TRST#
22
H_TDI
22
H_TDO
XDP_DBRESET#
H_BPM0_XDP#
H_BPM1_XDP#
TP4552
TP4553
TP4554
TP4555
TP4556
TP4557
IN
IN
IN
PVCCIO_OUT
21
R4920
IN
H_TDO
PLACE R4920 NEAR XDP
INVENTEC
TITLE
CYCLONE_DIS
HASWELL_1 (CLK,MISC,JTAG)
DOC.NUMBER
CODE
SIZE
1310A25664
CS
A3
SHEET
22
22
23
23
22
23
23
62 34
22
22
PVCCIO_OUT
21
R4508
51_5%_2_DY
51_5%_2
of
1
22
PVCCIO_OUT
21
R4507
51_5%_2_DY
21
R4509
51_5%_2
9023
REV
X01
D
CC
B
AA
D
B
PVCCIO2PCH_R
PVCCIO_OUT_R
8 7
P1V35S P1V35S
C4146
2 1
0.1UF_16V_2
P1V35
C4147
2 1
0.1UF_16V_2
R4514,R4524 CLOSE TO CPU
12
VR_SVID_ALERT#
12
VR_SVID_CLK
12
VR_SVID_DATA
R4547
21
P1V05S
PVCCIO2PCH
P1V05S
PVCCIO_OUT
0_5%_3_DY
R4548
21
0_5%_3
C4554
2 1
R4568
21
0_5%_2
R4569
21
0_5%_2_DY
C4555
2 1
8
+
C4527
C4515
C4528
C4516
C4546
2 1
2 1
2 1
10UF_6.3V_3
2 1
10UF_6.3V_3
C4525
2 1
10UF_6.3V_3
10UF_6.3V_3
330UF_2V_15MR_PANA_-35%
PVCORE
ROUTE VCCSENSE WITH 27.4OHM IMPEDANCE
12
PVCCIO_OUT
21
R4514
OUT
OUT
OUT
130_1%_2
OUT
R4524
2 1
75_1%_2
VCCSENSE
VCCIOA_OUT
APPLY POWER
R4525
43_5%_2
2 1
PVCCIO_OUT
21
R4570
150_5%_2
PWR_DEBUG
21
4.7UF_6.3V_3_DY
R4571
IN
PWR_DEBUG
10K_5%_2_DY
4.7UF_6.3V_3
7 6
6 5
CN4555
K27
RSVD
L27
RSVD
T27
RSVD
V27
RSVD
AB11
VDDQ
AB2
VDDQ
AB5
VDDQ
AB8
VDDQ
AE11
VDDQ
AE2
VDDQ
AE5
C4526
2 1
2 1
10UF_6.3V_3
PVCORE
R4521
100_1%_2
2 1
PVCCIO_OUT_R
PVCCIO2PCH_R
TP4562
TP4563
TP4564
TP4565
22
24
22UF_6.3V_5_DY
VCCIOA_OUT
PWR_DEBUG
1
1
1
1
AH11
W11
AL27
AK27
AL35
AN35
AL16
AL13
AM28
AM29
AL28
AP35
AP34
AT35
AR35
AR32
AL26
AT34
AL22
AT33
AM21
AM25
AM22
AM20
AM24
AL19
AM23
AT32
AE8
N11
W32
K11
N8
T11
T2
T5
T8
W2
W5
W8
N26
K26
E17
A23
F22
J27
H27
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
RSVD
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
RSVD
VCOMP_OUT
RSVD
RSVD
RSVD
RSVD
VIDALERT*
VIDSCLK
VIDSOUT
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
IVR_ERROR
RSVD_TP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PVCORE
Y25
VCC
Y26
VCC
Y27
VCC
Y28
VCC
Y29
VCC
Y30
VCC
Y31
VCC
Y32
VCC
Y33
VCC
Y34
VCC
Y35
VCC
LOTES_AZIF0012_P001B_947P
Haswell rPGA EDS
5 4
4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AA26
AA28
AA34
AA30
AA32
AB26
AB29
AB25
AB27
AB28
AB30
AB31
AB33
AB34
AB32
AC26
AB35
AC28
AD25
AC30
AD28
AC32
AD31
AC34
AD34
AD26
AD27
AD29
AD30
AD32
AD33
AD35
AE26
AE32
AE28
AE30
AG28
AG34
AE34
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AG26
AH26
AH29
AG30
AG32
AH32
AH35
AH25
AH27
AH28
AH30
AH31
AH33
AH34
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
G25
H25
J25
K25
L25
M25
N25
P25
R25
T25
U25
U26
V25
V26
W26
W27
3 2 1
PVCORE
C4550
C4541
2 1
C4543
2 1
2 1
10UF_25V_5
10UF_25V_5
C4559
C4545
2 1
2 1
10UF_25V_5
10UF_25V_5
C4561
C4560
2 1
2 1
10UF_25V_5
10UF_25V_5
C4581
C4580
2 1
2 1
10UF_25V_5
10UF_25V_5
C4583
C4582
2 1
2 1
10UF_25V_5
10UF_25V_5
10UF_25V_5
D
C4539
2 1
2 1
22UF_6.3V_5
22UF_6.3V_5
2 1
2 1
22UF_6.3V_5
22UF_6.3V_522UF_6.3V_5
2 1
2 1
22UF_6.3V_5
22UF_6.3V_5
C4538
C4544
C4529
C4521
C4530
CC
C4522
2 1
22UF_6.3V_5
C4542
2 1
22UF_6.3V_5
2 1
2 1
22UF_6.3V_5
C4532
C4536
2 1
2 1
22UF_6.3V_5
22UF_6.3V_5
2 1
2 1
C4537
2 1
22UF_6.3V_5
22UF_6.3V_5
C4540
C4547
C4548
2 1
22UF_6.3V_5
2 1
22UF_6.3V_5
C4549
2 1
2 1
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
C4534
C4535
C4531
C4533
B
AA
INVENTEC
TITLE
CYCLONE_DIS
HASWELL_2 (POWER)
CHANGE by
XXX
DATE
26-NOV-2012
23
SIZE
DOC.NUMBER
CODE
1310A25664
CS
A3
SHEET
of
1
REV
X01
9024
8 7
6 5
4
3 2 1
Haswell rPGA EDS
CN4555
R4537
PEG_RCOMP
PEG
PEG_RXN_0
PEG_RXN_1
PEG_RXN_2
PEG_RXN_3
PEG_RXN_4
PEG_RXN_5
PEG_RXN_6
PEG_RXN_7
PEG_RXN_8
PEG_RXN_9
PEG_RXN_10
PEG_RXN_11
PEG_RXN_12
PEG_RXN_13
PEG_RXN_14
PEG_RXN_15
PEG_RXP_0
PEG_RXP_1
PEG_RXP_2
PEG_RXP_3
PEG_RXP_4
PEG_RXP_5
PEG_RXP_6
PEG_RXP_7
PEG_RXP_8
PEG_RXP_9
PEG_RXP_10
PEG_RXP_11
PEG_RXP_12
PEG_RXP_13
PEG_RXP_14
PEG_RXP_15
PEG_TXN_0
PEG_TXN_1
PEG_TXN_2
PEG_TXN_3
PEG_TXN_4
PEG_TXN_5
PEG_TXN_6
PEG_TXN_7
PEG_TXN_8
PEG_TXN_9
PEG_TXN_10
PEG_TXN_11
PEG_TXN_12
PEG_TXN_13
PEG_TXN_14
PEG_TXN_15
PEG_TXP_0
PEG_TXP_1
PEG_TXP_2
PEG_TXP_3
PEG_TXP_4
PEG_TXP_5
PEG_TXP_6
PEG_TXP_7
PEG_TXP_8
PEG_TXP_9
PEG_TXP_10
PEG_TXP_11
PEG_TXP_12
PEG_TXP_13
PEG_TXP_14
PEG_TXP_15
DMI_TX0_DN
34
OUT
DMI_TX1_DN
34
OUT
DMI_TX2_DN
34
OUT
DMI_TX3_DN
34
OUT
DMI_TX0_DP
34
OUT
DMI_TX1_DP
34
OUT
DMI_TX2_DP
34
OUT
DMI_TX3_DP
34
34
34
34
34
34
34
34
34
34
34
OUT
DMI_RX0_DN
IN
DMI_RX1_DN
IN
DMI_RX2_DN
IN
DMI_RX3_DN
IN
DMI_RX0_DP
IN
DMI_RX1_DP
IN
DMI_RX2_DP
IN
DMI_RX3_DP
IN
OUT
OUT
FDI_CSYNC
FDI_INT
D
D21
C21
B21
A21
D20
C20
B20
A20
D18
C17
B17
A17
D17
C18
B18
A18
H29
J29
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
FDI_CSYNC
FDI_INT
FDIDMI
B
E23
M29
24.9_1%_2
K28
M31
L30
M33
L32
M35
L34
E29
D28
E31
D30
E35
D34
E33
E32
L29
L28
L31
K30
L33
K32
L35
K34
F29
E28
F31
E30
F35
E34
F33
D32
H35
PEG_TX0_DN
H34
PEG_TX1_DN
J33
PEG_TX2_DN
H32
PEG_TX3_DN
J31
PEG_TX4_DN
G30
PEG_TX5_DN
C33
PEG_TX6_DN
B32
PEG_TX7_DN PEG_TX7_C_DN
B31
A30
B29
A28
B27
A26
B25
A24
PEG_TX0_DP
J35
PEG_TX1_DP
G34
H33
PEG_TX2_DP
G32
PEG_TX3_DP
H31
PEG_TX4_DP
H30
PEG_TX5_DP
B33
PEG_TX6_DP
A32
PEG_TX7_DP
C31
B30
C29
B28
C27
B26
C25
B24
LOTES_AZIF0012_P001B_947P
8
7 6
VCCIOA_OUT
21
21
0.22UF_6.3V_2
C4578
21
0.22UF_6.3V_2
C4577
21
0.22UF_6.3V_2
C4576
21
0.22UF_6.3V_2
C4575
21
0.22UF_6.3V_2
C4574
21
0.22UF_6.3V_2
C4573
21
0.22UF_6.3V_2
C4572
21
0.22UF_6.3V_2
C4571
21
0.22UF_6.3V_2
C4598
21
0.22UF_6.3V_2
C4597
21
0.22UF_6.3V_2
C4596
21
0.22UF_6.3V_2
C4595
21
0.22UF_6.3V_2
C4594
21
0.22UF_6.3V_2
C4593
21
0.22UF_6.3V_2
C4592
21
0.22UF_6.3V_2
C4591
5 4
IN
PEG_RX0_C_DN
IN
PEG_RX1_C_DN
IN
PEG_RX2_C_DN
IN
PEG_RX3_C_DN
IN
PEG_RX4_C_DN
IN
PEG_RX5_C_DN
IN
PEG_RX6_C_DN
IN
PEG_RX7_C_DN
PEG_RX0_C_DP
IN
PEG_RX1_C_DP
IN
PEG_RX2_C_DP
IN
PEG_RX3_C_DP
IN
PEG_RX4_C_DP
IN
PEG_RX5_C_DP
IN
IN
PEG_RX6_C_DP
IN
PEG_RX7_C_DP
PEG_TX0_C_DN
OUT
PEG_TX1_C_DN
OUT
PEG_TX2_C_DN
OUT
PEG_TX3_C_DN
OUT
PEG_TX4_C_DN
OUT
PEG_TX5_C_DN
OUT
PEG_TX6_C_DN
OUT
OUT
PEG_TX0_C_DP
OUT
PEG_TX1_C_DP
OUT
PEG_TX2_C_DP
OUT
PEG_TX3_C_DP
OUT
PEG_TX4_C_DP
OUT
PEG_TX5_C_DP
OUT
PEG_TX6_C_DP
OUT
PEG_TX7_C_DP
OUT
42
OUT
42
OUT
42
OUT
42
OUT
42
OUT
42
OUT
42
OUT
42
OUT
LOTES_AZIF0012_P001B_947P
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
DPD0_DN
DPD0_DP
DPD1_DN
DPD1_DP
DPD2_DN
DPD2_DP
DPD3_DN
DPD3_DP
82
82
82
82
82
82
82
82
CN4555
Haswell rPGA EDS
T28
DDIB_TXBN_0
U28
DDIB_TXBP_0
T30
DDIB_TXBN_1
U30
DDIB_TXBP_1
U29
DDIB_TXBN_2
V29
DDIB_TXBP_2
U31
DDIB_TXBN_3
V31
DDIB_TXBP_3
T34
DDIC_TXCN_0
U34
DDIC_TXCP_0
U35
DDIC_TXCN_1
V35
DDIC_TXCP_1
U32
DDIC_TXCN_2
T32
DDIC_TXCP_2
U33
DDIC_TXCN_3
V33
DDIC_TXCP_3
P29
DDID_TXDN_0
R29
DDID_TXDP_0
N28
DDID_TXDN_1
P28
DDID_TXDP_1
P31
DDID_TXDN_2
R31
DDID_TXDP_2
N30
DDID_TXDN_3
P30
DDID_TXDP_3
CHANGE by
XXX
eDP
EDP_RCOMP
EPD_DISP_UTIL
EDP_TXN_1
EDP_AUXN
EDP_AUXP
EDP_HPD
EDP_TXN_0
EDP_TXP_0
EDP_TXP_1
FDI_TXN_0
FDI_TXP_0
FDI_TXN_1
FDI_TXP_1
DDI
DATE
M27
N27
P27
E24
R27
P35
R35
N34
P34
P33
R33
N32
P32
26-NOV-2012
23
OUT
EDP_AUX_DN
OUT
EDP_AUX_DP
43
IN
EDP_HPD#
2 1
24.9_1%_2
R4544
OUT
EDP_TX0_DN
OUT
EDP_TX0_DP
OUT
EDP_TX1_DN
OUT
EDP_TX1_DP
OUT
FDI_TX0_DN
OUT
FDI_TX0_DP
OUT
FDI_TX1_DN
OUT
FDI_TX1_DP
INVENTEC
TITLE
CYCLONE_DIS
HASWELL_3 (DMI,DP,PEG,FDI)
DOC.NUMBER
CODE
SIZE
1310A25664
CS
A3
SHEET
VCCIOA_OUT
43
43
43
43
43
43
34
34
34
34
of
25 90
1
REV
X01
D
CC
B
AA
8 7
6 5
4
3 2 1
Haswell rPGA EDS
CN4555
AC7
RSVD_AC7
U4
29
M_CLK_DDR0_DN
29
M_CLK_DDR0_DP
29
29
M_CLK_DDR1_DN
29
M_CLK_DDR1_DP
29
M_CKE0
M_CKE1
OUT
OUT
OUT
OUT
OUT
OUT
D
29
M_CS#0
29
M_CS#1
29
M_ODT0
29
M_ODT1
29
M_A_BS0
29
M_A_BS1
29
M_A_BS2
29
M_A_RAS#
29
M_A_WE#
29
M_A_CAS#
29
M_A_A<15..0>
29
M_A_DQS0_DN
29
M_A_DQS1_DN
29
M_A_DQS2_DN
29
M_A_DQS3_DN
29
M_A_DQS4_DN
29
M_A_DQS5_DN
29
M_A_DQS6_DN
29
M_A_DQS7_DN
29
B
M_A_DQS0_DP
29
M_A_DQS1_DP
29
M_A_DQS2_DP
29
M_A_DQS3_DP
29
M_A_DQS4_DP
29
M_A_DQS5_DP
29
M_A_DQS6_DP
29
M_A_DQS7_DP
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SA_CK_N_0
V4
SA_CK_P_0
AD9
SA_CKE_0
U3
SA_CK_N_1
V3
SA_CK_P_1
AC9
SA_CKE_1
U2
SA_CK_N_2
V2
SA_CK_P_2
AD8
SA_CKE_2
U1
SA_CK_N_3
V1
SA_CK_P_3
AC8
SA_CKE_3
M7
SA_CS_N_0
L9
SA_CS_N_1
M9
SA_CS_N_2
M10
SA_CS_N_3
M8
SA_ODT_0
L7
SA_ODT_1
L8
SA_ODT_2
L10
SA_ODT_3
V5
SA_BS_0
U5
SA_BS_1
AD1
SA_BS_2
V10
VSS
U6
SA_RAS*
U7
SA_WE*
U8
SA_CAS*
V8
0
SA_MA_0
AC6
1
SA_MA_1
V9
SA_MA_2
U9
3
SA_MA_3
AC5
4
SA_MA_4
AC4
5
SA_MA_5
AD6
6
SA_MA_6
AC3
7
SA_MA_7
AD5
8
SA_MA_8
AC2
9
SA_MA_9
V6
10
SA_MA_10
AC1
11
SA_MA_11
AD4
12
SA_MA_12
V7
13
SA_MA_13
AD3
14
SA_MA_14
AD2
15
SA_MA_15
AP15
SA_DQS_N_0
AP8
SA_DQS_N_1
AJ8
SA_DQS_N_2
AF3
SA_DQS_N_3
J3
SA_DQS_N_4
E2
SA_DQS_N_5
C5
SA_DQS_N_6
C11
SA_DQS_N_7
AP14
SA_DQS_P_0
AP9
SA_DQS_P_1
AK8
SA_DQS_P_2
AG3
SA_DQS_P_3
H3
SA_DQS_P_4
E3
SA_DQS_P_5
C6
SA_DQS_P_6
C12
SA_DQS_P_7
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
AR15
AT14
AM14
AN14
AT15
AR14
AN15
AM15
AM9
AN9
AM8
AN8
AR9
AT9
AR8
AT8
AJ9
AK9
AJ6
AK6
AJ10
AK10
AJ7
AK7
AF4
AF5
AF1
AF2
AG4
AG5
AG1
AG2
J1
J2
J5
H5
H2
H1
J4
H4
F2
F1
D2
D3
D1
F3
C3
B3
B5
E6
A5
D6
D5
E5
B6
A6
E12
D12
B11
A11
E11
D11
B12
A12
AM3
DDR_WR_VREF01
F16
F13
DDR_WR_VREF02
BI
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
332
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
M_A_DQ<63..0>
P0V675M_VREF_H
29
30
M_CLK_DDR2_DN
30
M_CLK_DDR2_DP
30
30
M_CLK_DDR3_DN
30
M_CLK_DDR3_DP
30
30
30
30
30
30
30
30
30
M_B_RAS#
30
M_B_WE#
30
M_B_CAS#
30
M_B_A<15..0>
30
M_B_DQS0_DN
30
M_B_DQS1_DN
30
M_B_DQS2_DN
30
M_B_DQS3_DN
30
M_B_DQS4_DN
30
M_B_DQS5_DN
30
M_B_DQS6_DN
30
M_B_DQS7_DN
30
M_B_DQS0_DP
30
M_B_DQS1_DP
30
M_B_DQS2_DP
30
M_B_DQS3_DP
30
M_B_DQS4_DP
30
M_B_DQS5_DP
30
M_B_DQS6_DP
30
M_B_DQS7_DP
M_CKE2
M_CKE3
M_CS#2
M_CS#3
M_ODT2
M_ODT3
M_B_BS0
M_B_BS1
M_B_BS2
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Haswell rPGA EDS
CN4555
AG8
RSVD
Y4
SB_CKN0
AA4
SB_CK0
AF10
SB_CKE_0
Y3
SB_CKN1
AA3
SB_CK1
AG10
SB_CKE_1
Y2
SB_CKN2
AA2
SB_CK2
AG9
SB_CKE_2
Y1
SB_CKN3
AA1
SB_CK3
AF9
SB_CKE_3
P4
SB_CS_N_0
R2
SB_CS_N_1
P3
SB_CS_N_2
P1
SB_CS_N_3
R4
SB_ODT_0
R3
SB_ODT_1
R1
SB_ODT_2
P2
SB_ODT_3
R7
SB_BS_0
P8
SB_BS_1
AA9
SB_BS_2
R10
VSS
R6
SB_RAS*
P6
SB_WE*
P7
SB_CAS*
R8
SB_MA_0
Y5
SB_MA_1
Y10
SB_MA_2
AA5
SB_MA_3
Y7
SB_MA_4
AA6
SB_MA_5
Y6
SB_MA_6
AA7
SB_MA_7
Y8
SB_MA_8
AA10
SB_MA_9
R9
SB_MA_10
Y9
SB_MA_11
AF7
SB_MA_12
P9
SB_MA_13
AA8
SB_MA_14
AG7
SB_MA_15
AP18
SB_DQS_N_0
AP11
SB_DQS_N_1
AP5
SB_DQS_N_2
AJ3
SB_DQS_N_3
L3
SB_DQS_N_4
H9
SB_DQS_N_5
C8
SB_DQS_N_6
C14
SB_DQS_N_7
AP17
SB_DQS_P_0
AP12
SB_DQS_P_1
AP6
SB_DQS_P_2
AK3
SB_DQS_P_3
M3
SB_DQS_P_4
H8
SB_DQS_P_5
C9
SB_DQS_P_6
C15
SB_DQS_P_7
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
AR18
AT18
AM17
AM18
AR17
AT17
AN17
AN18
AT12
AR12
AN12
AM11
AT11
AR11
AM12
AN11
AR5
AR6
AM5
AM6
AT5
AT6
AN5
AN6
AJ4
AK4
AJ1
AJ2
AM1
AN1
AK2
AK1
L2
M2
L4
M4
L1
M1
L5
M5
G7
J8
G8
G9
J7
J9
G10
J10
A8
B8
A9
B9
D8
E8
D9
E9
E15
D15
A15
B15
E14
D14
A14
B14
BI
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
M_B_DQ<63..0>
30
D
CC
B
LOTES_AZIF0012_P001B_947P
LOTES_AZIF0012_P001B_947P
P1V35
P0V675S_DIMM0_VREF_CA
P0V675S_DIMM0_VREF_DQ
DIMM_VREF_ON
26
IN
8
R4538
0_5%_2_DY
3
DS
Q4503
21
2
DDR_WR_VREF01
G
R4539
1
2 1
1K_5%_2_DY
SSM3K7002BFU
6015B0110701-001
26
7 6
P0V675S_DIMM1_VREF_DQ
0_5%_2_DY
3
DIMM_VREF_ON
IN
Q4504
R4560
DS
G
1
21
2
R4561
2 1
SSM3K7002BFU
6015B0110701-001
DDR_WR_VREF02
1K_5%_2_DY
R4502
2 1
1K_1%_2_DY
M_VREF_M1
62
SLP_S3#_3R
34
41
R4501
2 1
IN
19
42
48
1K_1%_2_DY
20
58
5 4
DDR_RST_EN
0_5%_2_DY
R4511
3.3K_5%_2
R4512
0_5%_2_DY
R4503
0_5%_2
R4504
DIMM_VREF_ON
21
21
21
21
CHANGE by
0_5%_2_DY
3
Q4500
C4500
XXX
R4506
DS
G
1
2 1
21
2
P0V675M_VREF_H
AA
21
R4505
100K_5%_2_DY
SSM3K7002BFU
6015B0110701-001
470PF_50V_2
C4502
DATE
2 1
2.2UF_6.3V_3_DY
C4501
2 1
26-NOV-2012
23
0.1UF_16V_2_DY
INVENTEC
TITLE
CYCLONE_DIS
HASWELL_4 (DDR3)
CODE
SIZE
1310A25664
CS
A3
SHEET
DOC.NUMBER
of
REV
X01
9026
1
8 7
D
49.9_1%_2
TP4520
TP4521
1
CFG<1>
CFG<0>
1
B
49.9_1%_2
27
27
27
27
27
LOTES_AZIF0012_P001B_947P
6 5
I108
1
TP4558
1
TP4559
R4520
TESTLO_G26
21
PVCORE
I109
1
TP4560
1
TP4561
R4523
H_CPU_RSVD40
21
22
CFG<0>
22
CFG<1>
22
CFG<2>
22
CFG<3>
22
CFG<4>
22
CFG<5>
22
CFG<6>
22
CFG<7>
22
CFG<8>
22
CFG<9>
22
CFG<10>
22
CFG<11>
22
CFG<12>
22
CFG<13>
22
CFG<14>
22
CFG<15>
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Haswell rPGA EDS
CN4555
AT1
RSVD_TP
AT2
RSVD_TP
AD10
RSVD
A34
RSVD_TP
A35
RSVD_TP
W29
RSVD_TP
W28
RSVD_TP
G26
TESTLO
W33
RSVD
AL30
RSVD
AL29
RSVD
F25
VCC
C35
RSVD_TP
B35
RSVD_TP
AL25
RSVD_TP
W30
RSVD_TP
W31
RSVD_TP
W34
TESTLO
AT20
CFG_0
AR20
CFG_1
AP20
CFG_2
AP22
CFG_3
AT22
CFG_4
AN22
CFG_5
AT25
CFG_6
AN23
CFG_7
AR24
CFG_8
AT23
CFG_9
AN20
CFG_10
AP24
CFG_11
AP26
CFG_12
AN25
CFG_13
AN26
CFG_14
AP25
CFG_15
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
CFG_RCOMP
CFG_16
CFG_18
CFG_17
CFG_19
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
VSS
VSS
4
3 2 1
D
C23
B23
D24
D23
49.9_1%_2
R4519
AT31
AR21
AR23
AP21
AP23
AR33
G6
FC
AM27
AM26
F5
AM2
K6
E18
U10
P10
B1
NC
A2
AR1
E21
E20
AP27
AR26
AL31
AL32
21
IN
CFG<16>
IN
CFG<18>
IN
CFG<17>
IN
CFG<19>
22
22
22
22
CC
B
R4534
1K_1%_2_DY
PEGX16 STATIC LANE REVERSAL
DISPLAYPORT PRESENCE STRAP
PCIE PORT BIFURCATION STRAP
PEG DEFER TRAINING
27
27
27
22
CFG<2>
27
22
CFG<4>
27
22
CFG<5>
22
CFG<6>
22
CFG<7>
IN
IN
IN
IN
IN
STRAP PIN
R4532
R4533
R4535
R4536
21
1K_1%_2
21
1K_1%_2_DY
21
1K_1%_2_DY
21
1K_1%_2_DY
21
AA
INVENTEC
TITLE
CYCLONE_DIS
HASWELL_5 (CFG)
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
26-NOV-2012
23
1310A25664
CS
A3
SHEET
of
1
DOC.NUMBER
CODE
REV
X01
9027
8 7
6 5
4
3 2 1
CN4555
Haswell rPGA EDS
A10
VSS
A13
VSS
A16
VSS
A19
AA11
AA25
AA27
AA31
AA29
AB1
AB10
AA33
AA35
AC25
AC27
AC11
AD11
AC29
AC31
AC33
AC35
AE1
AE10
AE25
AE29
AE27
AE35
AF11
AG11
AG25
AE31
AG31
AE33
AG6
AH1
AH10
AG27
AG29
AG33
AG35
AJ11
AK11
AK25
AK26
AK28
AK29
AK30
AK32
A22
A25
A27
A29
A31
A33
AB3
AB4
AB6
AB7
AB9
AD7
AE3
AE4
AE6
AE7
AE9
AF6
AF8
AH2
AH3
AH4
AH5
AH6
AH7
AH8
AH9
E19
VSS
VSS
VSS
VSS
VSS
A3
VSS
VSS
VSS
A4
VSS
A7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D
B
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK34
AK5
AL1
AL10
AL11
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
E22
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AM10
AM13
AM16
AM19
E25
AM32
AM4
AM7
AN10
AN13
AN16
AN19
AN2
AN21
AN24
AN27
AN30
AN34
AN4
AN7
AP1
AP10
AP13
AP16
AP19
AP4
AP7
W25
AR10
AR13
AR16
AR19
AR2
AR22
AR25
AR28
AR31
AR34
AR4
AR7
AT10
AT13
AT16
AT19
AT21
AT24
AT27
AT3
AT30
AT4
AT7
B10
B13
B16
B19
B2
B22
LOTES_AZIF0012_P001B_947P LOTES_AZIF0012_P001B_947P
8
7 6
5 4
CN4555
Haswell rPGA EDS
B34
VSS
B4
VSS
B7
VSS
C1
VSS
C10
VSS
C13
VSS
C16
VSS
C19
VSS
C2
VSS
C22
VSS
C24
VSS
C26
VSS
C28
VSS
C30
VSS
C32
VSS
C34
VSS
C4
VSS
C7
VSS
D10
VSS
D13
VSS
D16
VSS
D19
VSS
D22
VSS
D25
VSS
D27
VSS
D29
VSS
D31
VSS
D33
VSS
D35
VSS
D4
VSS
D7
VSS
E1
VSS
E10
VSS
E13
VSS
E16
VSS
E4
VSS
E7
VSS
F10
VSS
F11
VSS
F12
VSS
F14
VSS
F15
VSS
F17
VSS
F18
VSS
F20
VSS
F21
VSS
F23
VSS
F24
VSS
F26
VSS
F28
VSS
F30
VSS
F32
VSS
F34
VSS
F4
VSS
F6
VSS
F7
VSS
F8
VSS
F9
VSS
G1
VSS
G11
VSS
G2
VSS
G27
VSS
G29
VSS
G3
VSS
G31
VSS
G33
VSS
G35
VSS
G4
VSS
G5
VSS
H10
VSS
H26
VSS
H6
VSS
H7
VSS
J11
VSS
J26
VSS
VSS
J30
VSS
J32
VSS
J34
VSS
J6
VSS
K1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
RSVD
K10
K2
K29
K3
K31
K33
K35
K4
K5
K7
K8
K9
L11
L26
L6
M11
M26
M28
M30
M32
M34
M6
N1
N10
N2
N29
N3
N31
N33
N35
N4
N5
N6
N7
N9
P11
P26
P5
R11
R26
R28
R30
R32
R34
R5
T1
T10
T29
T3
T31
T33
T35
T4
T6
T7
T9
U11
U27
V11
V28
V30
V32
V34
W1
W10
W3
W35
W4
W6
W7
W9
Y11
H11
AL24
F19
T26J28
AK35
AK33
OUT
ROUTE VSSSENSE WITH 27.4OHM IMPEDANCE
R4522
100_1%_2
2 1
CHANGE by
XXX
VSSSENSE
DATE
12
26-NOV-2012
23
INVENTEC
TITLE
CYCLONE_DIS
HASWELL_6 (GND,RESERVED)
DOC.NUMBER
CODE
SIZE
1310A25664
CS
A3
SHEET
of
9028
1
REV
X01
D
CC
B
AA
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