Inventec Carlisle Schematics

CARLISLE CS Bulid

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TABLE OF CONTENTS

SYSTEM BLOCK DIAGRAM

POWER BLOCK DIAGRAM
DC & BATTERY CHARGER

SYSTEM POWER (+V3A / +V5A)

SYSTEM POWER (+VGFX_CORE)

CPU POWER (+VCC_CORE)

SYSTEM POWER (+VCCP / +V1.5)

SYSTEM POWER(+V1.8/+V0.75S)

SYSTEM POWER (+V3S/+5VS/+V1.5S)

CLOCK GENERATOR

PENRYN (1/4)
PENRYN (2/4)
PENRYN (3/4)

PENRYN (4/4)
CANTIGA (1/7)
CANTIGA (2/7)
CANTIGA (3/7)
CANTIGA (4/7)
CANTIGA (5/7)
CANTIGA (6/7)
CANTIGA (7/7)
DDR III CONNECTOR (DIMM 0)
DDR III CONNECTOR (DIMM 1)

BLANK

SDVO TO DVI

PAGE

27
28
29
30
31
32
33
34

35
36
37

38
39
40
41
42
43
44
45
46
47
48
49
50

51
52

CRT CONNECTOR

LCD CONNECTOR I/F

BLANK
ICH9 (1/5)
ICH9 (2/5)
ICH9 (3/5)
ICH9 (4/5)
ICH9 (5/5)

SATA HDD CONN & SATA ODD CONN

BLANK

LAN CONTROLLER

LAN SWITCH

RJ45 CONNECTOR

KBC CONTROLLER
SUPER I/O CONTROLLER & BIOS

THERMAL SENSOR & FAN

KB CONN & USB CONN

CARDBUS CONTROLLER
CARDBUS CONNECTOR

5 IN 1 CONTROLLER & CONN
1394 CONTROLLER

AUDIO CODEC
AUDIO AMP & JACK
MINI CARD

DOCKING CONNECTOR

SCREW AND HOLE

PAGE

53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70

71
72

73
74
75

76
77

POWER BUTTON BOARD

FINGERPRINT BOARD
SIM CARD BOARD

HOTKEY BOARD (Daughter/B)

MDC / BLUETOOTH CONN
TPM1.2
BLANK

LED & SWITCH

DATE

CHANGE NO.

REV

DRAWER
DESIGN
CHECK
RESPONSIBLE

SIZE =
FILE NAME :

XXXXXXXXXXXX

P/N

EE

3

XXXX-XXXXXX-XX

DATE

POWER

VER :

DATE

INVENTEC

TITLE

Carlisle

SIZE

CODE

CS

SHEET

DOC. NUMBER

162

A3

REV

X01Model_No

OF

DVI

CRT

DVI Level shifter

PI3VDP411LST

PENRYN

(uFCPGA)

ICS9LPRS365

Clock Generator

CRT ( MB )

LCM

12.1" TFT

XGA/SXGA

Docking

USB 7

USB 6

USB 8

USB 9

PORT REPLICATOR

USB 5

Camera

SPI Flash 4M x1

USB 4

Finger Printer

Blue Tooth

Switch

FSA66P5X

USB 3

Express Card

MDC / Modem

Module 56K

RJ11

USB 2

CONN C

iTPM1.2

USB 1

CONN B

3.3V, AZALIA

MIC-JACK

USB 0

CONN A

AUDIO CODEC

AZALIA
ALC268

FSB, 667/800/1066 MHz

CANTIGA

1299 FCBGA

DMI x4

ICH9-M

676 BGA

3.3V, LPC_Interface,33MHz

1.5V/0.75V, DDR3 Interface, 800-1066 MHz

1.5V/0.75V, DDR3 Interface, 800-1066 MHz

TURBO

MEMORY

SATA_ODD

SATA_HDD

HDD

PCI_EXPRESS X1

EXPRESS CARD

( DOCK )

3.3V, PCI_Interface,33MHz

ODD

DDR3_SODIMM0

MINI CARD

INTEL WIRELESS LAN

TI_PCI7412

5 IN 1

SLOT

CARDBUS

TYPE II

DDR3_SODIMM1

LAN SW

PI3L500

LAN CONTROLLER IC

BROADCOM

1394 PORT 1

(6 Pin)

On Docking

1394 PORT 2

On Docking

RJ45 ( MB )

RJ45 ( DOCK )

BCM5764M

(4 Pin)

BATTERY

System Charger &

DC/DC System power

(IMVP-6

VR)

HP-JACK
SPEAKER

ITE

IT8512E

BIOS

SPI Flash

Touch PAD

FIR

SERIAL PORT

( DOCK )

CHANGE by

SUPER I/O

IT8305E

PARALLEL PORT

( DOCK )

Paul_Hsu 18-Dec-2007

TPM 1.2

INVENTEC

TITLE

Carlisle

BLOCK DIAGRAM

CODE

SIZE

A3

DOC. NUMBER

Model_No X01

CS

SHEET

REV

OF

622

Adaptor

(65W)

Docking
Power In

+VBAT

+V5AUXON
THER_SD#

5V/3.3V

+V5A
+V3A
+V5AL

+V3AL

TPC6104

SLP_S3#_3R

TPC6104

SLP_S3#_3R

G916T1

+V3A

+V5S

+V3S

+V1.8

CHG_EN#

SRSET

Charger

BQ24721C

Main Battery

ACPRES

MAXADPT

SLP_S4#_3R

SLP_S3#_3R

DFGT_VR_EN

CLK_PWRGD

PM_DPRSLPVR

PWR_GOOD_3

SLP_S4#_3R

+V1.5

SLP_S3#_3R

(SC412A)

+VCCP

(SC412A)

NB/VGA POWER

(SC472B)

(TPS51620)

IMVP 6

(G2998)

+V0.75S

FDC637AN

+V1.5

+V1.5S

V1.5_PG

+VCCP

VCCP_PG

+VGFX_CORE

VGFX_PG

+VCC_CORE

VR_PWRGD

PWRMON

CHANGE by SHEET

Paul_Hsu

2-Nov-2007

M_VREF

INVENTEC

TITLE

Carlisle

BLOCK DIAGRAM

SIZE

A3

DOC. NUMBER

Model_No X01

CS

REVCODE

OF

623

JACK600

1
2
3

G2

G1

SINGA_2DC_G028_I04_3P

Q5

8

D

7
6
5

FDS6675BZ

1

2

C635

33uF_25v

1

R83

432K_1%

2

R82

12

1

31.6K_1%

2

CHARGE_GND

ACPRES_KBC

CHG_EN#

BAT1_CLK

BAT1_DATA

1

C608

2

10pF_50v

1

S

2
3

R36

4

12

G

100K_5%

ACPRES
C75

OPEN

40-

4-,5-,7-,9-,10-,30-,31-,32-,33-,38-,40-,41-,50-,51-,53-,56-,57-,58-,60-

40-

4-,40-,42-

4-,40-,42-

1
2

1

R78

47K_5%

2

C72

1uF_10v

1

R77

100K_5%

2

MAX_ADP_RST

L602

NFM60R30T222

12

C607

4

0.01uF_25v

1

2

CHARGE_GND

+V3A

4-,5-,7-,9-,10-,30-,31-,32-,33-,38-,40-,41-,50-,51-,53-,56-,57-,58-,60-

40-

3

0.1uF_25v

1
2

CHARGE_GND

1

R137

100K_5%

2

1

R134

100K_5%

2

R84

1

2

10K_5%

TI_LMV393IDGKR_SOP_8P

C609

1
2

10pF_50v

C76

CHARGE_GND

C120

0.1uF_25v

R130

100K_5%

U12-A

1
2

12

1

0.01_1%_1W

+V3A

8

OUT

4

DOCK_PW

C610

1
2

0.01uF_25v

R37

12

12

C77

0.1uF_25v

2VREF

4-,5-

R73

47K_1%

3

+

2

-

51-

CHARGE_GND

1

2

1

R131

16.5K_1%

2

1

C78

0.1uF_25v

2

R136

12

10K_5%

0.1uF_25v

C119

1
2

1
2

12

1153-

10

15

14
13
25

17

C121

100pF_50v

U14

VCC

3

ACN

4

ACP

6

BYPASS#

5

ACDET

VREF5

AGND

TS

1

CHGEN#

SCL
SDA
ALARM#

IOUT

TI_BQ24721C_QFN_32P

2VREF

4-,5-

1

R75

47K_1%

2

5
6

1

R76

23.2K_1%

2

2

ACDRV#

23

SYS

24

BATDRV#

32

PVCC

30

HIDRV

29

PH

BTST

REGN

LODRV

PGND
SYNP
SYNN

SRP
SRN
BAT

EAO

EAI

FBO

ISYNSET

TML

2

+V3A

4-,5-,7-,9-,10-,30-,31-,32-,33-,38-,40-,41-,50-,51-,53-,56-,57-,58-,60-

8

+

OUT

-

TI_LMV393IDGKR_SOP_8P

4

12

31

28

27
26
22
21
20
19
18

7

8
9

16
33

R133

1

0_5%

CHARGE_GND

R74

12

100K_5%

7

U12-B

10_5%R85

21

SDM20U30

D11

1

R135

51K_5%

2

+VPACK

4-

1
2

1
2

C79

0.1uF_25v

C80

0.1uF_25v

1

1

2

40-

BATTERY1_IN

BAT1_DATA

BAT1_CLK

C636

1000pF_50v

2

C126

1

R80

200K_1%

1
2

MAX_ADPT

1uF_25v

2

1

R79

18K_5%

2

C71

100pF_50v

40­4-,40-,42­4-,40-,42-

D603

1

UDZS5.6B2

Q6

Q1

1

Q2

8

FAIR_FDMS9620S_MLP_8P

1
2

C74

56pF_50v

+V3A

4-,5-,7-,9-,10-,30-,31-,32-,33-,38-,40-,41-,50-,51-,53-,56-,57-,58-,60-

1

R614

OPEN

2

2

1
2

C29

0.1uF_25v

2
3
4
9

10

5
6
7

1

D602

3

AZ23C6V2

C28

10uF_25v_K_X5R

1
2

L605

12

PCMB0603T_8R2MS

10uF_25v_K_X5R

7

7

6

6

5

5

4

4

3

3

2

2

1

1

CN603

SYN_250133MR007G115ZR_7P

1
2

C27

10uF_25v_K_X5R

1

C637

2

1

R81

10K_1%

2
1

2

C73

1500pF_50v

CHARGE_GND CHARGE_GND

Paul_Hsu 27-Nov-2007

0.01_1%_1W

1
2

0.1uF_25v

R71

12

OPEN

12

C65

0.01uF_50v

R38

12

12
C124

0.1uF_25v

1
2C125

CHARGE_GND

1

S

2
3
4

FDS6675BZ

1

C26

2

0.1uF_25v

+VPACK

1
2

C123

0.1uF_25v

+VBAT

Q11

8

D

7
6
5

G

1
2

C2512

0.1uF_25v

FOR EMI

4-

Q12

FDS6675BZ

S

D

8

1

7

2

6

3

5

4

G

C70

10uF_25v_K_X5R

Near MOS

1

C122

2

0.1uF_25v

NEAR IC

INVENTEC

TITLE

Carlisle

DC & BATTERY CHARGER

SIZE CODE

A3

DOC. NUMBER

Model_No X01

CS

SHEET

4

5-,6-,7-,8-,9-,28-,49-

1

C68

2

0.1uF_25v

C24

0.1uF_25v

R72

12

OPEN

12

C69

0.01uF_50v

OFCHANGE by

REV

62

+V3A

4-,7-,9-,10-,30-,31-,32-,33-,38-,40-,41-,50-,51-,53-,56-,57-,58-,60-

2

MAX : 6A

18pF_50v

PAD8

POWERPAD_2_0610

1

1

C285

2

1

R316

R317

0_5%

13.3K_1%

2

1

2

1

R318

20K_1%

2

C393

1uF_6.3v

4.7uF_25v

1
2

C334

1
2

L22

CYNTEC_PCMC063_4R7

1

C394

330uF_6.3v

2

12

4.7_5%

1000pF_50v

THER_SD#

+V5AUXON

C333

10uF_25v_K_X5R

1
2

Q41

FDS8884

1

R394

2

1

C364

2

8765

D

S

8

D

S

123

9-,42-

9-,53-

23

76

G

41

5

G

4

FDS6690AS

D18

SDM20U30_OPEN

21

SSM3K7002FU

R395

0_5%

12

12

R368

0_5%

Q37

+V5AL

5-,9-,10-,53-

1

2

SSM3K7002FU

Q28

3

D

1

G

S

2

R321

12

0_5%

R361

12

OPEN

C304

0.1uF_25v

+V3AL

40-

R319

100K_5%

Q613

3

D

G

1

S

2

Q31

D

1

G

12

S

12

0_5%

SSM3K7002FU

TI_TPS51125_QFN_24P

12

0_5%

1

C286

10uF_10v

2

3

80.6K_1%

2

R359

R362

R4002

8
9

12

U27

R360

820K_5%

VO2
VREG3

DRVH2
LL2

+VBAT

R396

0_5%

R397

0_5%

Q43

FDS6690AS

4-,6-,7-,8-,9-,28-,49-

POWERPAD_2_0610

G

4

2

G

41S23

PAD6

1
2

C336

765

8

10uF_25v_K_X5R

D

Q42

FDS8884

S

123

CYNTEC_PCMC063_4R7

8765

1

D

R369

4.7_5%

2

1
2

C339

1000pF_50v

C335

1
2

1

C337

4.7uF_25v

2

L23

12

C395

330uF_6.3v

0.1uF_25v

1

2

1
2

1
2

C396

1uF_6.3v

C307

0.1uF_25v

FOR EMI

1
2

C309

0.1uF_25v

1

R324

31.6K_1%

2

1

R323

20K_1%

2

C338

1
2

0.1uF_25v

POWERPAD_2_0610

1

C288

2

18pF_50v

1

R322

0_5%

2

+V5A

8-,10-,33-,34-,43-,48-,49-

PAD9

MAX : 6A

2VREF

6

VFB2

SKIPSEL

13

5

TONSEL

GND

14

1
2

4

15

4-

3

1

2

VFB1

VREF

ENTRIP1

PGOOD

VBST1VBST2
DRVH1

DRVL1DRVL2

VIN

VREG5

VCLK

16

17

18

C305

2.2uF_25v

VO1

LL1

1

R320

80.6K_1%

2

1
2

247
23
22
2110
2011
19

+V5AL

C287

0.22uF_16v

C308

0.1uF_25v

R325

12

12

0_5%

5-,9-,10-,53-

1

C306

10uF_10v

2

1

12

1

2

25

TML

ENTRIP2

EN0

1

2

CHANGE by

INVENTEC

TITLE

Carlisle

BATTERY CONN & SELECT

CODE

CS

SHEET

DOC. NUMBER

Model_No

OF

562

REV

X01

SIZE

9-Oct-2007Paul_Hsu

A3

DFGT_VR_EN

SLP_S3#_3R

7-,8-,9-,10-,11-,16-,17-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

DFGT_VID_4
DFGT_VID_3
DFGT_VID_2
DFGT_VID_1
DFGT_VID_0

16­16­16­16­16-

C96

OPEN

1
2

16-

8-,9-,10-,31-,40-

+V3S

VGFX_PG

1

R105

130K_1%

2

1

R106

49.9K_1%

2

R45

12

0_5%

R46

12

OPEN

12

10K_5%

TP3009
TP3010
TP3011
TP3012
TP3013

C98

OPEN

1
2

1
2

R44

1

R108

130K_1%

2

1

R107

100K_1%

2

C46

OPEN

1
2
3
4
5
6

1
2

VID4
VID3
VID2
VID1
VID0
HYS

23

25

BSTCLSET

TML-PAD

U4

7

8

C97

1000pF_50v

SC472B_GND

R104

12

4.7_5%

FOR EMI

22

19

21BG24

20

V5

TG

DRN

PMON

PWRGO

RAMP

SS

ERROUT

FB-

AGND

VREF

9

SEMTECH_SC472B_MLP_24P

12

10

11

1
2

C53

100pF_50v

EN

CS+

CS-

FB+

18
17
16
15
14
13

1

R52

10K_5%

2

1
2

C54

2200pF_50v

+V5S

7-,10-,26-,27-,28-,31-,33-,35-,40-,42-,44-,45-,48-,49-,51-,54-,60-

C45

1uF_10v

1
2

2

D13

1

SDM20U30

1

C95

1uF_25v

2

C48

1000pF_50v

12

12

R47

SC472B_GND

10K_1%

1
2

1
2

C649

0.01uF_16v

C52

100pF_50v

1
2

SC472B_GND

SC472B_GND

C49

OPEN

1
2

41S23

65

87

G

41S23

G

1

R49

5.1K_1%

2

C50

100pF_50v

C647

10uF_25v_K_X5R

1
2

D

Q605

FDS8876

8765

D

Q604

FDS6690AS

SC472B_GND

SC472B_GND

1

2

1
2

1
2

1
2

1
2

R618

22_5%

C646

680pF_50v

FOR EMI

C47

100pF_50v

C51

100pF_50v

R619

1

0_5%

C648

4.7uF_25v

R102

16.2K_1%

2

SC472B_GND

C664

2

0.1uF_25v

PCMC063T_1R0MN

1

1

C94

OPEN

2

2

R48

12

249_1%

R50

2

1

249_1%

PAD602

POWERPAD_2_0610

FOR EMI

L610

12

R103

12

18.2K_1%

0.022uF_16v

R51

12

12

R53

+VBAT

4-,5-,7-,8-,9-,28-,49-

1
2

R101

12

33K_1%

12

C93

0_5%

0_5%

20-

20-

C665

11
2

0.1uF_25v

10uF_6.3v

VCC_AXG_SENSE
VSS_AXG_SENSE

C650

0.1uF_25v

C92

+VGFX_CORE

PAD604

POWERPAD_2_0610

1

1

2

C663

330uF_2v_9mR_Panasonic

2

20-

CHANGE by

INVENTEC

TITLE

Carlisle

SYSTEM PWR (+V3A/+V5A)

CODE

SIZE

13-Feb-2008Paul_Hsu

A3

DOC. NUMBER REV

CS

SHEET OF

662

X01Model_No

VR_PWRGD

H_VID6
H_VID5
H_VID4
H_VID3
H_VID2
H_VID1
H_VID0

PSI#

H_DPRSTP#

PM_DPRSLPVR

PWR_GOOD_3

VR_PWRGD

CLK_PWRGD

1
2

1

C260

2

1000pF_50v

VCOREGND

R294

12

68.1K_1%

C258

18pF_50v

C263

330pF_50v

14­14­14­14­14­14­14­13­13-,16-,30-

16-,31-

7-,40-,42­7-,11-,31-

11-,31-

VCOREGND

7-,11-,31-

12

499_1%

12

R296

12

OPEN

1

R298

OPEN

2

C261

220pF_25v

12

1
2

R302

12

330K_5%

R290

R291

R292

+V3S

R293

0_5%

VCOREGND

1

R300

1.65K_1%

2

R299

0_5%

R297

0_5%

12
12

1

R295

10K_5%

2

4700pF_25v

C239

0.012uF_16v

12

CSREF

12

14-

12

14-

C264

1

0.47uF_6.3v

2

TP3002

TP3003

TP3004

0_5%
0_5%

C259

C238

680pF_50v

12

+V5S

7-

VCCSENSE
VSSSENSE

TP3005

TP3006

TP3007

TP3008

12

3

1
2
3
4
5
6
7
8

9
10
11
12

1000pF_50v

+V3A

4-,5-,7-,9-,10-,30-,31-,32-,33-,38-,40-,41-,50-,51-,53-,56-,57-,58-,60-

5

U25-B

R301

12

4

2

EN
PWRGD
PGDELAY
CLKEN
FBRTN
FB
COMP
SS
ST
VARFREQ
VRTT
TTSEN

115K_1%

C235

0_5%

TSB_TC7PA17FU_SSOP_6P

46

49

48

47

45

44

43

41

PSI

TML

VID0

VID1

VID242VID3

DPRSLP

DPRSTP

U21

ADI_ADP3208_LFCSP_48P

LLINE

CSSUM

CLIM

CSCOMP

CSFEF

PMON

PMONFS

16

20

19

15

17

18

13

14

1

R261

2

1

VCOREGND

1
2

VCOREGND

1000pF_50v

C236

2

VCOREGND

1
2

40

39

VID4

VID5

VID6

VRPM

RAMP22RPM23RT SP

21

1

R251

80.6K_1%

2

R253

274K_1%

1

C234

1000pF_50v

2

1
2

PM_PWROK

16-,31-,40-,42-

6-,7-,10-,26-,27-,28-,31-,33-,35-,40-,42-,44-,45-,48-,49-,51-,54-,60-

1

R288

10_5%

2

C257

1
2

BST1

SW1

SW2

BST2

1

R249

237K_1%

2

VCOREGND

R252

1K_1%

R256

R254

R258

2.2uF_6.3v

VCOREGND

R287

12

36
35

2.2_5%

34
33
32
31
30
29
28
27
26
25

C255

2.2uF_6.3v

R248

12

0_5%

+VBAT

12

1

R260

76.8K_1%

2

1
2

4-,5-,6-,7-,8-,9-,28-,49-

1

R289

0_5%

2

37

38

VCC

DRVH1

PVCC1
DRVL1
PGND1
PGND2
DRVL2
PVCC2

DRVH2

GND

24

12

C233

1000pF_50v

191K_1%

12

12

191K_1%

12

187K_1%

C237

120pF_50v

+V5S

3

12

D20

BAT54A

C254

12

0.1uF_25v

12

R250

2.2_5%
+V5S

6-,7-,10-,26-,27-,28-,31-,33-,35-,40-,42-,44-,45-,48-,49-,51-,54-,60-

1

C256

2

2.2uF_6.3v

1

R629

220K_5%

2

C232

12

0.1uF_25v

+VBAT

4-,5-,6-,7-,8-,9-,28-,49-

PAD2

POWERPAD_2_0610

1
2

C690

1
2

0.01uF_50v

C669

0.01uF_50v

C182

1
2

10uF_25v

C132

1
2

10uF_25v

C181

1
2

10uF_25v

C131

1
2

10uF_25v

6-,7-,8-,9-,10-,11-,16-,17-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

SLP_S3#_5R

+VCCP_PG

10-

BAT54A

8-

+V3S

1

D21

3

2

1
2

1

R328

100K_5%

2

C291

0.1uF_16v

+V3A

1

56789

G

Q24

SI7686DP_T1_E3

4321

L617

1

9

8D765

G

S

123

4

Q23

FDMS8660S

R224

4.7_5%

C205

1000pF_50v

ETQP4LR36WFC_PANASONIC

1

2

1
2

CSREF

7-

56789

Q19

SI7686DP_T1_E3

1

4G32

L614

1

8D765

9

R174

Q20

S

FDMS8660S

4.7_5%

C157

1000pF_50v

G

4

123

CHANGE by SHEET

ETQP4LR36WFC_PANASONIC

1

2

1
2

Paul_Hsu 9-Oct-2007

4-,5-,7-,9-,10-,30-,31-,32-,33-,38-,40-,41-,50-,51-,53-,56-,57-,58-,60-

12

C262

0.1uF_16v

5

U25-A

7-,40-,42-

6

TSB_TC7PA17FU_SSOP_6P

2

2

1

R201

10_1%

2

2

10_1%

1

R202

2

INVENTEC

TITLE

Carlisle

CPU POWER (+VCC_CORE)

CODESIZE

A3

PWR_GOOD_3

MAX : 44A

DOC. NUMBER REV

Model_No X01

CS

+VCC_CORE

14-

OF

627

6-,7-,9-,10-,11-,16-,17-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

SLP_S3#_3R

+VCCP_PG

6-,9-,10-,31-,40-

R99

12

21K_1%

7-

12

0.047uF_10v

C89

+V3S

1

R98

100K_5%

2

+V5A

5-,8-,10-,33-,34-,43-,48-,49-

1

8

765

G

123

4

8765

G

41S23

1

2

2

4.7uF_25v

C91

10uF_25v_K_X5R

D

Q8

S

FDS8884

L609

12

CYNTEC_PCMC063_3R3

1

D

R617

22_5%

2

C641

1

680pF_50v

2

FOR EMI

C41

LX

BST

VCC

DL

PAD

17

2

1

1
2

1

R97

12

2

0_5%

310

4

D9

SDM20U30

1
2

C32

0.1uF_25v

Q603

FDS6690AS

C87

1uF_10v

U9

SEMTECH_SC412A_MLPQ_16P

1

R95

OPEN

2

12

EN

11

1
2

VCCP_GND

PGOOD

VOUT

9

FB

C88

0.01uF_16v

R96

12

0_5%

1

OPEN1

R94

10K_1%

C86

2

2

1

R93

24.9K_1%

2

VCCP_GND

13

ILIM

NC2

8

14

NC3

NC1

7

VCCP_GND

R100

12

12K_1%

15

16

DH

NC4

GND

RTN

5

6

R92

12

0_5%

PAD1

POWERPAD_2_0610

C42

1
2

0.1uF_25v

FOR EMI

C44

1
2

0.1uF_25v

+VBAT

4-,5-,6-,7-,8-,9-,28-,49-

C43

1
2

0.1uF_25v

220uF_2v_15mR_Panasonic

+VCCP

PAD603

POWERPAD_2_0610

1

1
2

C90

2

10uF_6.3v

C661

11-,12-,13-,14-,16-,18-,20-,21-,30-,33-

MAX : 8A

SLP_S4#_3R

+V1.5_PG

R407

12

0_5%

9-,31-,40-,43-,44-,45-,57-

16-

+V5A

5-,8-,10-,33-,34-,43-,48-,49-

87

65

G

41S23

8

765

G

123

4

1
2

C389

10uF_25v_K_X5R

D

Q40

FDS8884

CYNTEC_PCMC063_3R3

D

S

1
2

LX

BST

VCCVOUT

DL

PAD

17

2

1

1
2

1

R409

12

2

0_5%

3

4

D22

SDM20U30

1
2

C387

0.1uF_25v

Q39

FDS6690AS

C388

1uF_10v

U29

SEMTECH_SC412A_MLPQ_16P

1

R406

OPEN

2

12

EN

11

2

V1.5_GND

1
2

C386

0.01uF_16v

PGOOD

10

9

FB

R387

1

OPEN

C358

V1.5_GND

0_5%

1

R388

30.9K_1%

2

1

R390

30.1K_1%

2

C385

1
2

OPEN

1
2

13

ILIM

NC2

8

14

15

NC3

NC4

NC1

RTN

7

6

12

V1.5_GND

R408

12

12K_1%

16

DH

GND

5

R389

0_5%

POWERPAD_2_0610

1
2

C360

4.7uF_25v

L20

12

1

R391

4.7_5%

2

C359

1000pF_50v

PAD7

C363

1
2

0.1uF_25v

+VBAT

4-,5-,6-,7-,8-,9-,28-,49-

C390

1

1

2

2

0.1uF_25v

C362

0.1uF_25v

FOR EMI

220uF_2v_15mR_Panasonic

+V1.5

PAD5

POWERPAD_2_0610

1

1

C327

2

2

10uF_6.3v

9-,10-,16-,20-,21-,23-,24-,33-,57-

MAX : 8A

C326

INVENTEC

TITLE

Carlisle

SYSTEM PWR (+VCCP/+V1.5S)

CHANGE by

SIZE

12-Oct-2007Paul_Hsu

A3

DOC. NUMBER

CODE REV

CS

SHEET

862

X01Model_No

OF

SLP_S4#_3R

SLP_S3#_3R

+V1.5

8-,10-,16-,20-,21-,23-,24-,33-,57-

8-,31-,40-,43-,44-,45-,57-

6-,8-,10-,31-,40-

C141

10uF_6.3v

R185

12

OPEN

R492

12

0_5%

1
2

+V3A

4-,5-,7-,10-,30-,31-,32-,33-,38-,40-,41-,50-,51-,53-,56-,57-,58-,60-

U17

GMT_G2998F11U_SOP_8P

1

C176

2

0.1uF_10v

1

GND

2

EN

3

VTTS

VREF

VTT_IN

VDDQ

TML-PAD

8

VTT

7

6

VCC

54
9

THER_SD#

1

C143

2

1uF_6.3v

R313

12

0_5%

1

C140

10uF_6.3v

2

R183

12

0_5%

R4003

12

5-,42-

0_5%

+V0.75S

1
2

R184

1

0_5%

+VBAT

4-,5-,6-,7-,8-,28-,49-

1
R118

1M_5%

2

1

R119

56.2K_1%

2

1
R120

180K_1%

2

23-,24-

POWERPAD_2_0610

C175

10uF_6.3v

2

MAX : 2A

PAD3

R284

12

0_5%

U10

3

LTH

2

GND

1

HTH

GMT_G680LT1_SOT23_5P

16-

24-

23-

24-

23-

RESET#

VCC

M_VREF

M_VREF_CA_DIMM1

M_VREF_CA_DIMM0

M_VREF_DQ_DIMM1

M_VREF_DQ_DIMM0

R169

12

4

10K_5%

5

5-,53-

C276

1uF_6.3v

+V5AUXON

6-,7-,8-,10-,11-,16-,17-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

+V3S

U22

GMT_G916T1Uf_SOT23_5_5P

15

IN

OUT

SET

3

SHDN#

1
2

GND

2

1

R282

4

44.2K_1%

2

1

R283

100K_1%

2

PAD4

POWERPAD_2_0610

1

C243

1uF_6.3v

2

+V5AL

5-,10-,53-

C144

1
2

0.1uF_16v

+V1.8

21-

MAX : 300mA

CHANGE by

INVENTEC

TITLE

Carlisle

SYSTEM PWR (+V1.8/+VGAVCC)

CODE

CS

SHEET

DOC. NUMBER

962

SIZE

12-Oct-2007Paul_Hsu

A3

REV

X01Model_No

OF

SLP_S3#_3R

6-,8-,9-,31-,40-

Q33

1

G

SSM3K7002F

+V5AL

5-,9-,10-,53-

1

R327

47K_5%

2

3

D

S

2

+V3A

4-,5-,7-,9-,30-,31-,32-,33-,38-,40-,41-,50-,51-,53-,56-,57-,58-,60-

Q46

4

D

S

G

TPC6104

C416

12

OPEN

1

R440

270K_5%

2

1

SSM3K7002F

+V5A

5-,8-,33-,34-,43-,48-,49-

+V3S

6-,7-,8-,9-,11-,16-,17-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

Q610

C786

12

1000pF_50v_OPEN

1

R694

220K_5%

2

4

S

TPC6104

SSM3K7002F

Q45

G

1
2
5
63

1

C415

10uF_6.3v

2

1

R439

100_5%

2

3

D

S

2

G

D

R690

470_5%

1
2
5
63

Q609
1

G

+V5S

1

2

D

S

6-,7-,26-,27-,28-,31-,33-,35-,40-,42-,44-,45-,48-,49-,51-,54-,60-

1

C805

10uF_6.3v

2

3

2

Q32

1

G

SSM3K7002F

+V5AL

5-,9-,10-,53-

1

R326

47K_5%

2

3

D

S

2

+V1.5

8-,9-,16-,20-,21-,23-,24-,33-,57-

1

R370

270K_5%

2

Q36

4

6

S

D

5
2

3

1

G

FDC637AN

C310

12

1000pF_50v_OPEN

SSM3K7002F

+V1.5S

1

2

Q38

D

G

1

S

14-,21-,33-,48-,50-

1
2

10uF_6.3v

R371

470_5%

3

2

C311

7-

SLP_S3#_5R

SLP_S3_5R

INVENTEC

TITLE

Carlisle

SYSTEM POWER

SIZE REV

CODE DOC. NUMBER

A3

CHANGE by OFSHEET

2-Nov-2007Paul_Hsu

CS

10 62

X01Model_No

+VCCP

8-,11-,12-,13-,14-,16-,18-,20-,21-,30-,33-

L15

BLM11A121S

1

2

1

10uF_10v

2

8-,11-,12-,13-,14-,16-,18-,20-,21-,30-,33-

2

R272

R308

OPEN

OPEN

CPU_BSEL1

CPU_BSEL2
CLK_R3S_ICH14
CLK_R3S_SIO14

FSA

FSB

1

1
0

1
0

0

13­13­31­41-

C269

1

(For EMI)

OPEN

2

6-,7-,8-,9-,10-,11-,16-,17-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

CLK_PWRGD

FSC

0

0

0

33_5%

VR_PWRGD

FSB CLOCK
FREQUENCY

667
800

1066

1

10K_5%

1

12
12

R307

12

0_5%_OPEN

7-,31-

R273

7-,31-

0_5%_OPEN

HOST CLOCK
FREQUENCY

*CLKREQ# pin controls SRC Table.

Byte5: bit6 =0(PWD)

SRC0

CR#_A

Byte5: bit7=0, disable CR#_A; 1,enable CR#_A

Byte5: bit2 =0(PWD)

SRC0

CR#_C

Byte5: bit3=0, disable CR#_C; 1,enable CR#_C

Byte5: bit6 =1

SRC2

Byte5: bit2 =1

SRC2

Layout note: All decoupling 0.1uF disperse closed to pin

C275

1
2

C272

0.1uF_16v

1

0.1uF_16v

2

C294

1
2

0.1uF_16v

CPU_BSEL0

8-,11-,12-,13-,14-,16-,18-,20-,21-,30-,33-

+VCCP

2

1

2

12

R276

12

+VCCP

2

R305

OPEN

6-,7-,8-,9-,10-,11-,16-,17-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

1

R303

R304

FSLC

R30633_5%

6-,7-,8-,9-,10-,11-,16-,17-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

DOCK_NEWCARD_R_CLKEN#

0_5%

ICH_3S_SMCLK

ICH_3S_SMDATA

166

CLK_PCMCIA48

CLK_SB48

CLKREQ_R_SATA#

+V3S

51-

R332

12

10K_5%_OPEN

CLK_R3S_SIOPCI

CLK_R3S_LPCPCI

CLK_R3S_TPMPCI

23-,24-,31-,50­23-,24-,31-,50-

1

C267

33pF_50v

2

Please place close to CLKGEN within 500mils

200
266

Byte5: bit4 =0(PWD)

CR#_B

CR#_D

SRC1

Byte5: bit5=0, disable CR#_B; 1,enable CR#_B

Byte5: bit0 =0(PWD)

SRC1

Byte5: bit1=0, disable CR#_D; 1,enable CR#_D

C274

C296

1

0.1uF_16v

2

8-,11-,12-,13-,14-,16-,18-,20-,21-,30-,33-

13-

44-

31-

12

31-

10K_5%

R335 12.1_1%

R337

1
2

R344

R330

10K_5%

R329

C266

33pF_50v

+V3S

R331

12

10K_5%

41­50­58-

X4

14.31818MHZ

12

30PPM

C273

1

0.1uF_16v

2

+VCCP

2

R269

OPEN

1

2

R270

OPEN

1

12

22_1%R345

12

22_1%

+V3S

12

12
1

2

12

Byte5: bit4 =1

SRC4

Byte5: bit0 =1

SRC4

C295

1

0.1uF_16v

2

R343

12

R334

R333

1

475_1%

12.1_1%R336

33_1%

2.2K_5%

CLK_R_SB48

475_1%

12

DOCK_NEWCARD_CLKEN#

2

CR#_E

CR#_F

CR#_G

CR#_H

+V3S

6-,7-,8-,9-,10-,11-,16-,17-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

Layout note: All decoupling 0.1uF disperse closed to pin

L14

BLM11A121S

1

CLKREQ_STAT#

CLK_3S_LPCPCI

2

U26

26

VDDSRC_IO

45

VDDSRC_IO

36

VDDSRC_IO

12

VDD96_IO

39

VDDSRC_IO

61

VDDREF

20

VDDPLL3_IO

49

VDDCPU_IO

9

VDD48

2

VDDPCI

55

VDDCPU

16

VDD

10

SUB_48MHZ_FSLA

57

FSLB_TEST_MODE

62

REF0_FSLC_TEST_SEL

1

PCI0_CR#_A

3

PCI1_CR#_B

4

PCI2_TME

5

PCI3

56

CK_PWRGD_PD#

64

SCLK

63

SDTAT

60

X1

59

X2

8

GNDPCI

11

GND48

15

GND

19

GND

23

GNDSRC

29

GNDSRC

42

GNDSRC

58

GNDREF

52

GNDCPU

ICS_ICS9LPRS365_TSSOP_64P

C265

1
2

10uF_10v

PCI_STOP#

CPU_STOP#

CPUT2_ITP_SRCT8

CPUC2_ITP_SRCC8

SRCT11_CR#_H
SRCC11_CR#_G

SRCT7_CR#_F

SRCC7_CR#_E

PCI4_27_Select
PCI_F5_ITP_EN

SRCT3_CR#_C
SRCC3_CR#_D

SRCT2_SATAT

SRCC2_SATAC

27MHz_NonSS_SRCT1_SE1

27MHz_SS_SRCC1_SE2

SRCC0_DOTT_96
SRCT0_DOTC_96

CPUT1_F

CPUC1_F

CPUT0

CPUC0

SRCT10
SRCC10

SRCT9

SRCC9

SRCT6

SRCC6

SRCT4

SRCC4

C271

1

1

2

2

0.1uF_16v

48

NC

38
37

CLK_NBCLK

51

CLK_NBCLK#

50

CLK_CPUBCLK

54

CLK_CPUBCLK#

53

CLK_PCIE_ROBSON

47

CLK_PCIE_ROBSON#

46

CLKREQ_MCH#

33

CLKREQ_LAN#

32

CLK_PEG_MCH

34

CLK_PEG_MCH#

35

CLK_PCIE_LAN

30

CLK_PCIE_LAN#

31

CLKREQ_ROBSON#

44

CLKREQ_WLAN#

43

CLK_PCIE_WLAN

41

CLK_PCIE_WLAN#

40

CLK_R_CBPCI

6

CLK_R_KBPCI

7

CLK_R_PCIE_CARDDOCK

27

CLK_R_PCIE_CARDDOCK#

28

CLK_PCIE_SB

24
25

CLK_PCIE_SB#

CLK_SATA1

21

CLK_SATA1#

22

CLKSS1_DREF

17

CLKSS1_DREF#

18

CLK_DREF

13

CLK_DREF#

14

C270

0.1uF_16v

6-,7-,8-,9-,10-,11-,16-,17-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

6-,7-,8-,9-,10-,11-,16-,17-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

C292

C268

1

1

2

2

0.1uF_16v

0.1uF_16v

Byte6: bit7=0, disable CR#_E; 1,enable CR#_E

SRC6

Byte6: bit6=0, disable CR#_F; 1,enable CR#_F

SRC8

Byte6: bit5=0, disable CR#_G; 1,enable CR#_G

SRC9

Byte6: bit4=0, disable CR#_H; 1,enable CR#_H

SRC10

CHANGE by

6-,7-,8-,9-,10-,11-,16-,17-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

1
2

C293

0.1uF_16v

R281

OPEN

+V3S

2

1

R311

OPEN

2

1

475_1%
475_1%

475_1%
475_1%

12.1_1%

+V3S

1

R279

10K_5%

2

2

R312

1

12

R346

R309

2

1

R310

2

1

12

12
12

ITP_EN=0:

SRC8/SRC8#

ITP_EN=1:

ITP/ITP#

+V3S

1

1

R280

10K_5%

2

R34033_5%

R342
R34112.1_1%

R338

1

10K_5%

1

R641

10K_5%

10K_5%

2

2

R339

12

10K_5%

2

R347

31-

PCISTOP#_3

31-

CPUSTOP#_3

18-

CLK_NBCLK

18-

CLK_NBCLK#

12-

CLK_CPUBCLK

12-

CLK_CPUBCLK#

50-

CLK_PCIE_ROBSON

50-

CLK_PCIE_ROBSON#

16-

CLKREQ_R_MCH#

37-

CLKREQ_R_LAN#

16-

CLK_PEG_MCH

16-

CLK_PEG_MCH#

37-

CLK_PCIE_LAN

37-

CLK_PCIE_LAN#

50-

CLKREQ_R_ROBSON#

50-

CLKREQ_R_WLAN#

50-

CLK_PCIE_WLAN

50-

CLK_PCIE_WLAN#

44-

CLK_CBPCI

32-

CLK_ICHPCI

40-

CLK_KBPCI

51-

CLK_R_PCIE_CARDDOCK

51-

CLK_R_PCIE_CARDDOCK#

31-

CLK_PCIE_SB

31-

CLK_PCIE_SB#

30-

CLK_SATA1

30-

CLK_SATA1#

16-

CLKSS1_DREF

16-

CLKSS1_DREF#

16-

CLK_DREF

16-

CLK_DREF#

27_Selet =0

LCD_SST 100MHZ

27_Selet =1

27MHZ non-spread clock

INVENTEC

TITLE

Carlisle

CLOCK_GENERATOR

SIZE

CODE

DOC. NUMBER

Paul_Hsu 30-Oct-2007

A3

Model_No X01

CS

SHEET

OF

REV

6211

H_A#(35:3)

H_ADSTB#1

H_STPCLK#

H_A20M#
H_FERR#

H_IGNNE#

H_INTR

H_NMI

H_SMI#

18-

H_A#(3)
H_A#(4)
H_A#(5)
H_A#(6)
H_A#(7)
H_A#(8)
H_A#(9)
H_A#(10)
H_A#(11)
H_A#(12)
H_A#(13)
H_A#(14)
H_A#(15)
H_A#(16)

H_REQ#(4:0) H_RS#(0:2)

H_A#(17)
H_A#(18)
H_A#(19)
H_A#(20)
H_A#(21)
H_A#(22)
H_A#(23)
H_A#(24)
H_A#(25)
H_A#(26)
H_A#(27)
H_A#(28)
H_A#(29)
H_A#(30)
H_A#(31)
H_A#(32)
H_A#(33)
H_A#(34)
H_A#(35)

18-

30­30­30-

30­30­30­30-

18-

H_REQ#(0)
H_REQ#(1)
H_REQ#(2)
H_REQ#(3)
H_REQ#(4)

H_ADSTB#0

18-

U605-1

J4

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD01

N5

RSVD02

T2

RSVD03

V3

RSVD04

B2

RSVD05

C3

RSVD06

D2

RSVD07

D22

RSVD08

D3

RSVD09

F6

RSVD010

FOX_PZ4782K_274M_41_478P

GMCH

CPU

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

ADDR GROUP 0

INIT#

CONTROL

LOCK#

RESET#

RS0#
RS1#
RS2#

TRDY#

HIT#

HITM#

BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#

TCK

ADDR GROUP 1

TDO
TMS

XDP/ITP SIGNALS

TRST#

DBR#

THERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

ICH

H CLK

BCLK0
BCLK1

RESERVED

H1
E2
G5

H5
F21
E1

F1

D20
B3

H4

C1
F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6

TDI

AB3
AB5
AB6
C20

+VCCP

D21
A24
B25

C7

A22
A21

ICH8

56_5%R162

12

+VCCP

8-,11-,12-,13-,14-,16-,18-,20-,21-,30-,33-

10mils/10mils

18-

H_ADS#

18-

H_BNR#

18-

H_BPRI#

18-

H_DEFER#

18-

H_DRDY#

18-

H_DBSY#

18-

H_BREQ#0

30-

H_INIT#

18-

H_LOCK#

18-

H_CPURST#

18-

H_TRDY#

18-

H_HIT#

18-

H_HITM#

12-

H_BPM5_PREQ#

12-

H_TCK

12-

TDI_FLEX

12-

H_TMS

31-

XDP_DBRESET#

42-

H_THERMDA

42-

H_THERMDC

16-,30-,42-

PM_THRMTRIP#

11-

CLK_CPUBCLK

11-

CLK_CPUBCLK#

+VCCP

8-,11-,12-,13-,14-,16-,18-,20-,21-,30-,33-

H_RS#(0)
H_RS#(1)
H_RS#(2)

R264

12

56_5%

R267

12

56_5%

R266

12

56_5%

R259

12

56_5%

18-

12-

12-

12-

12-

+VCCP

CLOSED TO CPU

H_BPM5_PREQ#

TDI_FLEX

H_TMS

H_TCK

8-,11-,12-,13-,14-,16-,18-,20-,21-,30-,33-

1

R161

56_5%

2

H_TRST#

1

R262

56_5%

2

PM_THRMTRIP# should be T at CPU

INVENTEC

TITLE

Carlisle

Penryn (1/4)

SIZE DOC. NUMBER

CODE REV

A3

CHANGE by OF

Paul_Hsu

9-Oct-2007

CS

SHEET

12 62

X01Model_No

H_D#(63:0)

H_DSTBN#0

H_DSTBP#0

H_D#(63:0)

+VCCP

8-,11-,12-,14-,16-,18-,20-,21-,30-,33-

1

R158

1K_1%

2

1

R157

2K_1%

2

13-,18-

18­18-

H_DINV#0

18-

13-,18-

H_DSTBN#1
H_DSTBP#1

GTLREF

Layout note: Zo=55 ohm,

0.5" max for GTLREF.

H_DINV#1

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

U605-2

H_D#(0)
H_D#(1)
H_D#(2)
H_D#(3)
H_D#(4)
H_D#(5)
H_D#(6)
H_D#(7)
H_D#(8)
H_D#(9)
H_D#(10)
H_D#(11)
H_D#(12)
H_D#(13)
H_D#(14)
H_D#(15)

H_D#(16)
H_D#(17)
H_D#(18)
H_D#(19)
H_D#(20)
H_D#(21)
H_D#(22)
H_D#(23)
H_D#(24)
H_D#(25)
H_D#(26)
H_D#(27)
H_D#(28)
H_D#(29)
H_D#(30)
H_D#(31)

18­18­18-

11­11­11-

E22

D0#

F24

D1#

E26

D2#

G22

D3#

F23

D4#

G25

D5#

E25

D6#

E23

D7#

K24

D8#

G24

DATA GRP 0

D9#

J24

D10#

J23

D11#

H22

D12#

F26

D13#

K22

D14#

H23

D15#

J26

DSTBN0#

H26

DSTBP0#

H25

DINV0#

N22

D16#

K25

D17#

P26

D18#

R23

D19#

L23

D20#

M24

D21#

L22

D22#

M23

D23#

P25

D24#

P23

D25#

P22

DATA GRP 1

D26#

T24

D27#

R24

D28#

L25

D29#

T25

D30#

N25

D31#

L26

DSTBN1#

M26

DSTBP1#

N24

DINV1#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

MISC

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL0

B23

BSEL1

C21

BSEL2

FOX_PZ4782K_274M_41_478P

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#

DATA GRP 2DATA GRP 3

D41#
D42#
D43#
D44#
D45#
D46#
D47#

DSTBN2#

DSTBP2#

DINV2#

D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DSTBN3#

DSTBP3#

DINV3#

COMP0
COMP1
COMP2
COMP3

DPRSTP#

DPSLP#
DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_COMP0
H_COMP1

H_COMP2
H_COMP3

(18mil)
(5mil)
(18mil)
(5mil)

shorter than 0.5"

7-,16-,30-

12

R160 27.4_1%

2

1

R159 54.9_1%

12

27.4_1%R263

12

R265 54.9_1%

H_DPRSTP#

CLOSED TO CPU

H_D#(32)
H_D#(33)
H_D#(34)
H_D#(35)
H_D#(36)
H_D#(37)
H_D#(38)
H_D#(39)
H_D#(40)
H_D#(41)
H_D#(42)
H_D#(43)
H_D#(44)
H_D#(45)
H_D#(46)
H_D#(47)

H_D#(48)
H_D#(49)
H_D#(50)
H_D#(51)
H_D#(52)
H_D#(53)
H_D#(54)
H_D#(55)
H_D#(56)
H_D#(57)
H_D#(58)
H_D#(59)
H_D#(60)
H_D#(61)
H_D#(62)
H_D#(63)

30­18­30­18-

7-

18­18­18-

H_DPSLP#

H_DPWR#
H_PWRGD
H_CPUSLP#
PSI#

H_DSTBN#3
H_DSTBP#3
H_DINV#3

13-,18-

13-,18-

18­18­18-

H_D#(63:0)

H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#(63:0)

1

R164

OPEN

2

GMCH_BSEL0

GMCH_BSEL1

GMCH_BSEL2

1

2

R163

OPEN

16-

16-

16-

C133

1

Close to CPU

OPEN

2

1K_5%

R271

12

1K_5%

R274

1K_5%

R268

Close to Clock Gen.

12

12

INVENTEC

TITLE

Carlisle

Penryn (2/4)

CODE

SIZE

CHANGE by OF

Paul_Hsu 9-Oct-2007

A3

DOC. NUMBER

Model_No X01

CS

SHEET

REV

6213

C692

1

22uF_6.3v_OPEN

2

C695

1

22uF_6.3v_OPEN

2

C691

1

22uF_6.3v_OPEN

2

C694

1

22uF_6.3v_OPEN

2

2

1

3

900uF_2.5v

7-,14-

C183

U605-3

A7

VCC001

A9

VCC002

A10

VCC003

A12

VCC004

A13

VCC005

A15

VCC006

A17

VCC007

A18

VCC008

A20

VCC009

B7

VCC010

B9

VCC011

B10

VCC012

B12

VCC013

B14

VCC014

B15

VCC015

B17

VCC016

B18

VCC017

B20

VCC018

C9

VCC019

C10

VCC020

C12

VCC021

C13

VCC022

C15

VCC023

C17

VCC024

C18

VCC025

D9

VCC026

D10

VCC027

D12

VCC028

D14

VCC029

D15

VCC030

D17

VCC031

D18

VCC032

E7

VCC033

E9

VCC034

E10

VCC035

E12

VCC036

E13

VCC037

E15

VCC038

E17

VCC039

E18

VCC040

E20

VCC041

F7

VCC042

F9

VCC043

F10

VCC044

F12

VCC045

F14

VCC046

F15

VCC047

F17

VCC048

F18

VCC049

F20

VCC050

AA7

VCC051

AA9

VCC052

AA10

VCC053

AA12

VCC054

AA13

VCC055

AA15

VCC056

AA17

VCC057

AA18

VCC058

AA20

VCC059

AB9

VCC060

AC10

VCC061

AB10

VCC062

AB12

VCC063

AB14

VCC064

AB15

VCC065

AB17

VCC066

AB18

VCC067

FOX_PZ4782K_274M_41_478P

VCC068
VCC069
VCC070
VCC071
VCC072
VCC073
VCC074
VCC075
VCC076
VCC077
VCC078
VCC079
VCC080
VCC081
VCC082
VCC083
VCC084
VCC085
VCC086
VCC087
VCC088
VCC089
VCC090
VCC091
VCC092
VCC093
VCC094
VCC095
VCC096
VCC097
VCC098
VCC099

VCC0100

VCCP01
VCCP02
VCCP03
VCCP04
VCCP05
VCCP06
VCCP07
VCCP08
VCCP09
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16

VCCA01
VCCA02

VCCSENSE

VSSSENSE

+VCC_CORE+VCC_CORE

7-,14-

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6

VID0

AF5

VID1

AE5

VID2

AF4

VID3

AE3

VID4

AF3

VID5

AE2

VID6

AF7

AE7

+VCCP

8-,11-,12-,13-,14-,16-,18-,20-,21-,30-,33-

1

220uF_2v_15mR_Panasonic

2

7-

H_VID0

7-

H_VID1

7-

H_VID2

7-

H_VID3

7-

H_VID4

7-

H_VID5

7-

H_VID6

18mil

18mil

C693

+VCC_CORE

7-,14-

1

R255

100_1%

2

1

R257

100_1%

2

7-

7-

+VCCP

8-,11-,12-,13-,14-,16-,18-,20-,21-,30-,33-

C683

1
2

0.1uF_16v

VCCSENSE

VSSSENSE

C684

1

2

0.1uF_16v

LAYOUT NOTE:

PLACE C739 NEAR PIN B26

PLACE THESE INSIDE SOCKET
CAVITY ON L8 (NORTH SIDE
SECONDARY)

C719

C685

1

1

2

2

0.1uF_16v

0.1uF_16v

10-,21-,33-,48-,50-

0.01uF_16v

C671

1
2

+V1.5S

1
2

C720

0.1uF_16v

C718

1
2

0.1uF_16v

1

10uF_6.3v

2

C670

LAYOUT NOTE:
ROUTE VCCSENSE AND VSSSENSE TRACE AT

24.7 OHM WITH 50 MIL SPACEING
PLACE PU AND PD WITHIN I INCH OF CPU

CHANGE by

INVENTEC

TITLE

Carlisle

Penryn (3/4)

CODE

CS

SHEET

DOC. NUMBER

14 62

SIZE

13-Dec-2007Paul_Hsu

A3

REV

X01Model_No

OF

U605-4

A4

VSS001

A8

VSS002

A11

VSS003

A14

VSS004

A16

VSS005

A19

VSS006

A23

VSS007

AF2

VSS008

B6

VSS009

B8

VSS010

B11

VSS011

B13

VSS012

B16

VSS013

B19

VSS014

B21

VSS015

B24

VSS016

C5

VSS017

C8

VSS018

C11

VSS019

C14

VSS020

C16

VSS021

C19

VSS022

C2

VSS023

C22

VSS024

C25

VSS025

D1

VSS026

D4

VSS027

D8

VSS028

D11

VSS029

D13

VSS030

D16

VSS031

D19

VSS032

D23

VSS033

D26

VSS034

E3

VSS035

E6

VSS036

E8

VSS037

E11

VSS038

E14

VSS039

E16

VSS040

E19

VSS041

E21

VSS042

E24

VSS043

F5

VSS044

F8

VSS045

F11

VSS046

F13

VSS047

F16

VSS048

F19

VSS049

F2

VSS050

F22

VSS051

F25

VSS052

G4

VSS053

G1

VSS054

G23

VSS055

G26

VSS056

H3

VSS057

H6

VSS058

H21

VSS059

H24

VSS060

J2

VSS061

J5

VSS062

J22

VSS063

J25

VSS064

K1

VSS065

K4

VSS066

K23

VSS067

K26

VSS068

L3

VSS069

L6

VSS070

L21

VSS071

L24

VSS072

M2

VSS073

M5

VSS074

M22

VSS075

M25

VSS076

N1

VSS077

N4

VSS078

N23

VSS079

N26

VSS080

P3

VSS081

FOX_PZ4782K_274M_41_478P

VSS082
VSS083
VSS084
VSS085
VSS086
VSS087
VSS088
VSS089
VSS090
VSS091
VSS092
VSS093
VSS094
VSS095
VSS096
VSS097
VSS098
VSS099
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

INVENTEC

TITLE

Carlisle

Penryn (4/4)

SIZE

26-Oct-2007Paul_Hsu

A3

CODE

CS

SHEET

DOC. NUMBER REV

15 62

X01Model_No

OFCHANGE by

MCH_CFG(5)

MCH_CFG(13:12)

XOR/ALLZ

NOTE: CFG[2:0] STRP : 010b : 800 MT/S

6-,7-,8-,9-,10-,11-,16-,17-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

MCH_CFG(19)
MCH_CFG(20)

LOW=DMIx2

HIGH=DMIx4

00=PARTIAL CLOCK GATING DISABLE
01=XOR MODE ENABLE
10=ALL-Z MODE ENABLE
11=NORMAL OPERATION

011b : 667 MT/S

000b : 1066 MT/S

16-

16-

+V1.5

8-,9-,10-,16-,20-,21-,23-,24-,33-,57-

1

R631

80.6_1%

2

16-

16-

1

R632

80.6_1%

2

+V3S

1

R277

OPEN

2

SM_RCOMP

SM_RCOMP#

MCH_CFG(7)

(CPU Strap)

1

2

R275

OPEN

LOW=RSVD
HIGH=Mobile CPU

MCH_CFG(16)

(FSB Dynamic

ODT)

MCH_CFG(6)

(ITPM Host

Interface)

GMCH_BSEL0
GMCH_BSEL1
GMCH_BSEL2

MCH_CFG(17:3)

SM_RCOMP/SM_RCOMP#

R644

80.6_1%

R645

80.6_1%

CANTIGA

STUFF

Value

+V3S

6-,7-,8-,9-,10-,11-,16-,17-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

12

R227 10K_5%

12

MCH_CFG(20)
DIGITAL DISPLAY
PORT(SDVO/DP/iHDMI)
CONCURRENT WITH PCIE

16-

PM_EXTTS#0

10K_5%R110

LOW=ONLY DIGITAL DISPLAY PORT
(SDVO/DP/iHDMI)OR PCIEIS OPERATIONAL
HIGH= DIGITAL DISPLAY PORT
(SDVO/DP/iHDMI)AND PCIE ARE OPERATING

VIA THE PEG PORT

PM_EXTTS#1

LOW=ITPM Host Interface

HIGH=ITPM Host Interface

MCH_CFG(18)
MCH_CFG(19)
MCH_CFG(20)

BM_BUSY#

H_DPRSTP#

PM_EXTTS#0

TS#_DIMM0_1

PM_PWROK

PLT_RST#

PM_THRMTRIP#

PM_DPRSLPVR

MCH_CFG(9)
PCIE Graphics
Lane

LOW=Dynamic ODT

Disable

HIGH=Dynamic ODT

Enable

Enable

Disable

13­13­13-

16-

16­16-

31­7-,13-,30­16­23-,24­7-,16-,31-,40-,42­32-,40-,41­12-,30-,42­7-,31-

LOW=Reverse Lane
HIGH=Normal operation

MCH_CFG(3)
MCH_CFG(4)
MCH_CFG(5)
MCH_CFG(6)
MCH_CFG(7)
MCH_CFG(8)
MCH_CFG(9)
MCH_CFG(10)
MCH_CFG(11)
MCH_CFG(12)
MCH_CFG(13)
MCH_CFG(14)
MCH_CFG(15)
MCH_CFG(16)
MCH_CFG(17)

12

R167
R126

R225

100_5%

12
12

0_5%

0_5%

PM_EXTTS#1

THE RECOMMENDED

NOTE :

PULL-UP RESISTOR VALUE IS 4.02K OHM

PULL-DOWN RESISTOR VALUE IS 2.21K OHM

U606-2

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

AH13

AL34

AK34

AN35

AM35

AY21

BG23

BF23

BH18

BF18

AT40

AT11

BG48

BF48

BD48

BC48

BH47

BG47

BE47

BH46

BF46

BG45

BH44

BH43

K12

T24

B31

AJ6

M1

A47

T25

R25

P25

P20

P24

C25

N24

M24

E21

C23

C24

N21

P21

T21

R20

M20

L21

H21

P29

R28

T28

R29

B7

N33

P32

T20

R32

BH6

BH5

BG4

BH3

BF3

BH2

BG2

BE2

BG1

BF1

BD1

BC1

F1

RSVD7

RSVD8

RSVD9

RSVD10

RSVD11

RSVD12

RSVD13

RSVD14

RSVD15

RSVD16

RSVD17

RSVD20

RSVD21

RSVD22

RSVD23

RSVD24

RSVD25

CFG_0

CFG_1

CFG_2

CFG_3

CFG_4

CFG_5

CFG_6

CFG_7

CFG_8

CFG_9

CFG_10

CFG_11

CFG_12

CFG_13

CFG_14

CFG_15

CFG_16

CFG_17

CFG_18

CFG_19

CFG_20

PM_SYNC#

PM_DPRSTP#

PM_EXT_TS#_0

PM_EXT_TS#_1

PWROK

RSTIN#

THERMTRIP#

DPRSLPVR

NC_1

NC_2

NC_3

NC_4

NC_5

NC_6

NC_7

NC_8

NC_9

NC_10

NC_11

NC_12

NC_13

NC_14

NC_15

NC_16

NC_17

NC_18

NC_19

NC_20

NC_21

NC_22

NC_23

NC_24

NC_25

SA_CK#_0

SA_CK#_1

SB_CK#_0

SB_CK#_1

SA_CKE_0

SA_CKE_1

SB_CKE_0

SB_CKE_1

SA_CS#_0

SA_CS#_1

SB_CS#_0

SB_CS#_1

SA_ODT_0

SA_ODT_1

SB_ODT_0

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_PWROK

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK#

DMI_RXN_0

DMI_RXN_1

DMI_RXN_2

DMI_RXN_3

DMI_RXP_0

DMI_RXP_1

DMI_RXP_2

DMI_RXP_3

DMI_TXN_0

DMI_TXN_1

DMI_TXN_2

DMI_TXN_3

DMI_TXP_0

DMI_TXP_1

DMI_TXP_2

DMI_TXP_3

GFX_VID_0

GFX_VID_1

GFX_VID_2

GFX_VID_3

GFX_VID_4

GFX_VR_EN

CL_PWROK

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

ICH_SYNC#

HDA_BCLK

HDA_RST#

HDA_SYNC

ITL_CANTIGA_ACER_FCBGA_1329P

SA_CK_0

SA_CK_1

SB_CK_0

SB_CK_1

SM_VREF

SM_REXT

PEG_CLK

CL_CLK

CL_DATA

CL_RST#

CL_VREF

CLKREQ#

TSATN

HDA_SDI

HDA_SDO

AP24

AT21

AV24

AU20

AR24

AR21

AU24

AV20

BC28

AY28

AY36

BB36

BA17

AY16

AV16

AR13

BD17

AY17

BF15

AY13

BG22

BH21

BF28

BH28

AV42

AR36

BF17

BC36

B38

A38

E41

F41

F43

E43

AE41

AE37

AE47

AH39

AE40

AE38

AE48

AH40

AE35

AE43

AE46

AH42

AD35

AE44

AF46

AH43

B33

B32

G33

F33

E33

C34

AH37

AH36

AN36

AJ35

AH34

N28

M28

G36

E36

K36

H36

B12

B28

B30

B29

C29

A28

12

R182 499_1%

CL_VREF

TP3

R229

12

0_5%_OPEN

MA_CLK_DDR1
MA_CLK_DDR2
MB_CLK_DDR1
MB_CLK_DDR2

MA_CLK_DDR1#
MA_CLK_DDR2#
MB_CLK_DDR1#
MB_CLK_DDR2#

MA_CKE0
MA_CKE1
MB_CKE0
MB_CKE1

MA_CS0#
MA_CS1#
MB_CS0#
MB_CS1#

MA_ODT0
MA_ODT1
MB_ODT0
MB_ODT1

SM_RCOMP

SM_RCOMP#
SM_RCOMP_VOH

SM_RCOMP_VOL

9-

M_VREF

DDR3_RST#

CLK_DREF
CLK_DREF#
CLKSS1_DREF
CLKSS1_DREF#

16­16­16­16­16-

12

R213

2.2K_1%_OPEN

Open to disable

iTPM

+V1.5

8-,9-,10-,16-,20-,21-,23-,24-,33-,57-

1

R634

1K_1%

2

1

R635

3K_1%

2

1

R633

1K_1%

2

C216

1
2

0.1uF_16v

19-Dec-2007

1

2

+V1.5

1
2

1
2

+VCCP

1

R207

OPEN

8-,9-,10-,16-,20-,21-,23-,24-,33-,57-

R179

OPEN

2

12

R232

10K_5%

8-

+V1.5_PG

R220

1K_1%

R231

C707

1
2

2.2uF_6.3v

C706

1
2

2.2uF_6.3v

C705

0.01uF_16v

C704

0.01uF_16v

8-,11-,12-,13-,14-,16-,18-,20-,21-,30-,33-

1

2

1

511_1%

2

INVENTEC

TITLE

Carlisle

CANTIGA(1/7)

SIZE REV

CODE

A3

CS

SHEET

1

R178

OPEN

2

16-

16-

DOC. NUMBER

16 62

MCH_CFG(16)

MCH_CFG(9)
MCH_CFG(7)
MCH_CFG(5)
MCH_CFG(6)

23­23­24­24-

23­23­24­24-

23­23­24­24-

23­23­24­24-

23­23­24­24-

16­16-

16­16-

23-,24-

11­11­11­11-

11-

CLK_PEG_MCH

11-

CLK_PEG_MCH#

31-

DMI_TXN(0)
DMI_TXN(1)
DMI_TXN(2)
DMI_TXN(3)

DMI_TXP(0)
DMI_TXP(1)
DMI_TXP(2)
DMI_TXP(3)

DMI_RXN(0)
DMI_RXN(1)
DMI_RXN(2)
DMI_RXN(3)

DMI_RXP(0)
DMI_RXP(1)
DMI_RXP(2)
DMI_RXP(3)

7-,16-,31-,40-,42-

+V3S

6-,7-,8-,9-,10-,11-,16-,17-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

+VCCP

CHANGE by

DMI_TXN(3:0)

31-

DMI_TXP(3:0)

31-

DMI_RXN(3:0)

31-

DMI_RXP(3:0)

6-

DFGT_VID_0

6-

DFGT_VID_1

6-

DFGT_VID_2

6-

DFGT_VID_3

6-

DFGT_VID_4

6-

DFGT_VR_EN

31-

CL_CLK0

31-

CL_DATA0

PM_PWROK

31-

CL_RST#0

26-

SDVO_CTRCLK

26-

SDVO_CTRDAT

11-

CLKREQ_R_MCH#

31-

MCH_ICH_SYNC#

8-,11-,12-,13-,14-,16-,18-,20-,21-,30-,33-

1

R177

56_5%

2

Paul_Hsu

1

R211

OPEN

2

SM_RCOMP_VOH

SM_RCOMP_VOL

X01Model_No

OF

INV_PWM_3

LCM_3S_BKLTEN

28-,40­28-

1

R210

100K_5%

2

R153

12

OPEN

LCM_3S_VDDEN

28-

LCM_DDCPCLK

LCM_DDCPDATA

1

R214

100K_5%

2

27-

CRTB

27-

CRTG

27-

CRTR

28­28-

1

R640

2.37K_1%

2

1

R208

75_1%

2

1

2

R209

75_1%

1

2

Close to MCH

1

R205

150_1%

2

1

2

1

R204

150_1%

2

Close to MCH

U_CRT_DDCCLK

U_CRT_DDCDATA

CRT_HSYNC_U

CRT_VSYNC_U

R212

75_1%

R206

150_1%

LVDS_TXCLN
LVDS_TXCLP

LVDS_TXDL0N
LVDS_TXDL1N
LVDS_TXDL2N

LVDS_TXDL0P
LVDS_TXDL2P

27­27­27­27-

+V3S

6-,7-,8-,9-,10-,11-,16-,21-,23-,24-,26-,27-,28-,30-,31-,32-,33-,35-,37-,40-,41-,42-,44-,45-,46-,47-,48-,50-,51-,53-,55-,56-,57-,58-,60-

1

1

R226

R228

10K_5%

10K_5%

2

2

U606-3

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

28­28-

28­28­28-

28­28­28-

C41

C40

B37

A37

H47

E46

G40

A40

H48

D45

F40

B40

A41

H38

G37

J37

B42

G38

F37

K37

F25

H25

K25

H24

C31

E32

E28

G28

J28

G29

H32

J32

J29

E29

L29

LVDSA_CLK#

LVDSA_CLK

LVDSB_CLK#

LVDSB_CLK

LVDSA_DATA#_0

LVDSA_DATA#_1

LVDSA_DATA#_2

LVDSA_DATA#_3

LVDSA_DATA_0

LVDSA_DATA_1

LVDSA_DATA_2

LVDSA_DATA_3

LVDSB_DATA#_0

LVDSB_DATA#_1

LVDSB_DATA#_2

LVDSB_DATA#_3

LVDSB_DATA_0

LVDSB_DATA_1

LVDSB_DATA_2

LVDSB_DATA_3

TVA_DAC

TVB_DAC

TVC_DAC

TV_RTN

TV_DCONSEL_0

TV_DCONSEL_1

CRT_BLUE

CRT_GREEN

CRT_RED

CRT_IRTN

CRT_DDC_CLK

CRT_DDC_DATA

CRT_HSYNC

CRT_TVO_IREF

CRT_VSYNC

ITL_CANTIGA_ACER_FCBGA_1329P

1

R203

1.02K_0.5%

2

PEG_COMPI

PEG_COMPO

PEG_RX#_0

PEG_RX#_1

PEG_RX#_2

PEG_RX#_3

PEG_RX#_4

PEG_RX#_5

PEG_RX#_6

PEG_RX#_7

PEG_RX#_8

PEG_RX#_9

PEG_RX#_10

PEG_RX#_11

PEG_RX#_12

PEG_RX#_13

PEG_RX#_14

PEG_RX#_15

PEG_RX_0

PEG_RX_1

PEG_RX_2

PEG_RX_3

PEG_RX_4

PEG_RX_5

PEG_RX_6

PEG_RX_7

PEG_RX_8

PEG_RX_9

PEG_RX_10

PEG_RX_11

PEG_RX_12

PEG_RX_13

PEG_RX_14

PEG_RX_15

PEG_TX#_0

PEG_TX#_1

PEG_TX#_2

PEG_TX#_3

PEG_TX#_4

PEG_TX#_5

PEG_TX#_6

PEG_TX#_7

PEG_TX#_8

PEG_TX#_9

PEG_TX#_10

PEG_TX#_11

PEG_TX#_12

PEG_TX#_13

PEG_TX#_14

PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9

PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_13

PEG_TX_14

PEG_TX_15

+VCC_PEG

C207
C208
C210
C211
C242
C241
C212
C209

12
12
12
12
12
12
1
12

21-

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

2

0.1uF_10v

26-

26-

26-

26-

26-

26-

26-

26-

SDVOB_R+
SDVOB_R­SDVOB_G+
SDVOB_G­SDVOB_B+
SDVOB_B­SDVOB_CLK+
SDVOB_CLK-

R230

PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
PEG_TXP2
PEG_TXN2
PEG_TXP3
PEG_TXN3

12

49.9_1%

17-

17-

17-

17-

17-

17-

17-

17-

FOR DVI WITH DOCKING

T37

T36

H44

J46

L44

L40

N41

P48

N44

T43

U43

Y43

Y48

Y36

AA43

AD37

AC47

AD39

H43

J44

L43

L41

26-

17­17­17­17-

17­17­17­17-

PEG_RX_3LVDS_TXDL1P

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3

N40

P47

N43

T42

U42

Y42

W47

Y37

AA42

AD36

AC48

AD40

J41

M46

M47

M40

M42

R48

N38

T40

U37

U40

Y40

AA46

AA37

AA40

AD43

AC46

J42

L46

M48

M39

M43

R47

N37

T39

U36

U39

Y39

Y46

AA36

AA39

AD42

AD46

CHANGE by

INVENTEC

TITLE

Carlisle

CANTIGA (2/7)

SIZE DOC. NUMBER

CODE

A3

CS

3-Mar-2008Paul_Hsu

SHEET

17 62

REV

X01Model_No

OF

MCH_HSWING

MCH_HRCOMP

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#

H_BPRI#

H_BREQ#0

H_DEFER#

H_DBSY#
CLK_NBCLK
CLK_NBCLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#
H_LOCK#

H_TRDY#

H_REQ#(0)
H_REQ#(1)
H_REQ#(2)
H_REQ#(3)
H_REQ#(4)

12-

H_A#(35:3)

H_RS#(0)
H_RS#(1)
H_RS#(2)

12-

H_REQ#(4:0)

12-

H_RS#(2:0)

H_D#(63:0)

+VCCP

8-,11-,12-,13-,14-,16-,18-,20-,21-,30-,33-

1

R625

221_1%

R165

2

1

R626

100_1%

2

12

1
2

24.9_1%

C687

0.1uF_16v

MCH_HSWING
MCH_HRCOMP

H_CPURST#
H_CPUSLP#

18-

18-

13-

18­18-

12­13-

H_D#(0)
H_D#(1)
H_D#(2)
H_D#(3)
H_D#(4)
H_D#(5)
H_D#(6)
H_D#(7)
H_D#(8)
H_D#(9)
H_D#(10)
H_D#(11)
H_D#(12)
H_D#(13)
H_D#(14)
H_D#(15)
H_D#(16)
H_D#(17)
H_D#(18)
H_D#(19)
H_D#(20)
H_D#(21)
H_D#(22)
H_D#(23)
H_D#(24)
H_D#(25)
H_D#(26)
H_D#(27)
H_D#(28)
H_D#(29)
H_D#(30)
H_D#(31)
H_D#(32)
H_D#(33)
H_D#(34)
H_D#(35)
H_D#(36)
H_D#(37)
H_D#(38)
H_D#(39)
H_D#(40)
H_D#(41)
H_D#(42)
H_D#(43)
H_D#(44)
H_D#(45)
H_D#(46)
H_D#(47)
H_D#(48)
H_D#(49)
H_D#(50)
H_D#(51)
H_D#(52)
H_D#(53)
H_D#(54)
H_D#(55)
H_D#(56)
H_D#(57)
H_D#(58)
H_D#(59)
H_D#(60)
H_D#(61)
H_D#(62)
H_D#(63)

Layout notes:

Trace need be 10 mils

8-,11-,12-,13-,14-,16-,18-,20-,21-,30-,33-

+VCCP

1

R176

1K_1%

2

1

R175

2K_1%

2

C158

12

0.1uF_10v_OPEN

U606-1

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

ITL_CANTIGA_ACER_FCBGA_1329P

H_A#_3

H_A#_4

H_A#_5

H_A#_6

H_A#_7

H_A#_8

H_A#_9

H_A#_10

H_A#_11

H_A#_12

H_A#_13

H_A#_14

H_A#_15

H_A#_16

H_A#_17

H_A#_18

H_A#_19

H_A#_20

H_A#_21

H_A#_22

H_A#_23

H_A#_24

H_A#_25

H_A#_26

H_A#_27

H_A#_28

H_A#_29

H_A#_30

H_A#_31

H_A#_32

H_A#_33

H_A#_34

H_A#_35

H_ADS#

H_ADSTB#_0

H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#

H_TRDY#

H_DINV#_0

H_DINV#_1

H_DINV#_2

H_DINV#_3

H_DSTBN#_0

H_DSTBN#_1

H_DSTBN#_2

H_DSTBN#_3

H_DSTBP#_0

H_DSTBP#_1

H_DSTBP#_2

H_DSTBP#_3

H_REQ#_0

H_REQ#_1

H_REQ#_2

H_REQ#_3

H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A#(3)
H_A#(4)
H_A#(5)
H_A#(6)
H_A#(7)
H_A#(8)
H_A#(9)
H_A#(10)
H_A#(11)
H_A#(12)
H_A#(13)
H_A#(14)
H_A#(15)
H_A#(16)
H_A#(17)
H_A#(18)
H_A#(19)
H_A#(20)
H_A#(21)
H_A#(22)
H_A#(23)
H_A#(24)
H_A#(25)
H_A#(26)
H_A#(27)
H_A#(28)
H_A#(29)
H_A#(30)
H_A#(31)
H_A#(32)
H_A#(33)
H_A#(34)
H_A#(35)

12­12­12­12­12­12­12­12­11­11­13­12­12­12­12­12-

A14

C15

F16

H13

C18

M16

J13

P16

R16

N17

M13

E17

P17

F17

G20

B19

J16

E20

H16

J20

L17

A17

B17

L16

C21

J17

H20

B18

K17

B20

F21

K21

L20

H12

B16

G17

A9

F11

G12

E9

B10

AH7

AH6

J11

F9

H9

E12

H11

C9

J8

L3

Y13

Y1

L10

M7

AA5

AE6

L9

M8

AA6

AE5

B15

K13

F13

B13

B14

B6

F12

C8

13­13­13­13-

13­13­13­13-

13­13­13­13-

INVENTEC

TITLE

Layout note:

L < 100mils

CHANGE by

Paul_Hsu

26-Oct-2007

Carlisle

CANTIGA (3/7)

CODESIZE

A3

CS

SHEET

DOC. NUMBER

OF

18 62

REV

X01Model_No

23-

MA_DATA(63:0)

U606-4

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

ITL_CANTIGA_ACER_FCBGA_1329P

SA_BS_0

SA_BS_1

SA_BS_2

SA_RAS#

SA_CAS#

SA_WE#

SA_DM_0

SA_DM_1

SA_DM_2

SA_DM_3

SA_DM_4

SA_DM_5

SA_DM_6

SA_DM_7

SA_DQS_0

SA_DQS_1

SA_DQS_2

SA_DQS_3

SA_DQS_4

SA_DQS_5

SA_DQS_6

SA_DQS_7

SA_DQS#_0

SA_DQS#_1

SA_DQS#_2

SA_DQS#_3

SA_DQS#_4

SA_DQS#_5

SA_DQS#_6

SA_DQS#_7

SA_MA_0

SA_MA_1

SA_MA_2

SA_MA_3

SA_MA_4

SA_MA_5

SA_MA_6

SA_MA_7

SA_MA_8

SA_MA_9

SA_MA_10

SA_MA_11

SA_MA_12

SA_MA_13

SA_MA_14

MB_DATA(63:0)

BD21

BG18

AT25

BB20

BD20

AY20

AM37

AT41

AY41

AU39

BB12

AY6

AT7

AJ5

AJ44

AT44

BA43

BC37

AW12

BC8

AU8

AM7

AJ43

AT43

BA44

BD37

AY12

BD8

AU9

AM8

BA21

BC24

BG24

BH24

BG25

BA24

BD24

BG27

BF25

AW24

BC21

BG26

BH26

BH17

AY25

23-

MA_CAS#

MA_DQS(0)
MA_DQS(1)
MA_DQS(2)
MA_DQS(3)
MA_DQS(4)
MA_DQS(5)
MA_DQS(6)

MA_DQS(7)
MA_DQS#(0)
MA_DQS#(1)
MA_DQS#(2)
MA_DQS#(3)
MA_DQS#(4)
MA_DQS#(5)
MA_DQS#(6)
MA_DQS#(7)

MA_DM(0)
MA_DM(1)
MA_DM(2)
MA_DM(3)
MA_DM(4)
MA_DM(5)
MA_DM(6)
MA_DM(7)

MA_A(0)
MA_A(1)
MA_A(2)
MA_A(3)
MA_A(4)
MA_A(5)
MA_A(6)
MA_A(7)
MA_A(8)

MA_A(9)
MA_A(10)
MA_A(11)
MA_A(12)
MA_A(13)

23­23­23-

23-

23-

MA_BS0#
MA_BS1#
MA_BS2#

MA_RAS#
MA_WE#

23-

23-

23-

24-

U606-5

AK47

SB_DQ_0

AH46

SB_DQ_1

AP47

SB_DQ_2

AP46

SB_DQ_3

AJ46

SB_DQ_4

AJ48

SB_DQ_5

AM48

SB_DQ_6

AP48

SB_DQ_7

AU47

SB_DQ_8

AU46

SB_DQ_9

BA48

SB_DQ_10

MA_DM(7:0)

MA_DQS(7:0)

MA_DQS#(7:0)

23-

MA_A(13:0)

23-

MA_A(14) MB_A(14)

AY48

SB_DQ_11

AT47

SB_DQ_12

AR47

SB_DQ_13

BA47

SB_DQ_14

BC47

SB_DQ_15

BC46

SB_DQ_16

BC44

SB_DQ_17

BG43

SB_DQ_18

BF43

SB_DQ_19

BE45

SB_DQ_20

BC41

SB_DQ_21

BF40

SB_DQ_22

BF41

SB_DQ_23

BG38

SB_DQ_24

BF38

SB_DQ_25

BH35

SB_DQ_26

BG35

SB_DQ_27

BH40

SB_DQ_28

BG39

SB_DQ_29

BG34

SB_DQ_30

BH34

SB_DQ_31

BH14

SB_DQ_32

BG12

SB_DQ_33

BH11

SB_DQ_34

BG8

SB_DQ_35

BH12

SB_DQ_36

BF11

SB_DQ_37

BF8

SB_DQ_38

BG7

SB_DQ_39

BC5

SB_DQ_40

BC6

SB_DQ_41

AY3

SB_DQ_42

AY1

SB_DQ_43

BF6

SB_DQ_44

BF5

SB_DQ_45

BA1

SB_DQ_46

BD3

SB_DQ_47

AV2

SB_DQ_48

AU3

SB_DQ_49

AR3

SB_DQ_50

AN2

SB_DQ_51

AY2

SB_DQ_52

AV1

SB_DQ_53

AP3

SB_DQ_54

AR1

SB_DQ_55

AL1

SB_DQ_56

AL2

SB_DQ_57

AJ1

SB_DQ_58

AH1

SB_DQ_59

AM2

SB_DQ_60

AM3

SB_DQ_61

AH3

SB_DQ_62

AJ3

SB_DQ_63

ITL_CANTIGA_ACER_FCBGA_1329P

SB_BS_0

SB_BS_1

SB_BS_2

SB_RAS#

SB_CAS#

SB_WE#

SB_DM_0

SB_DM_1

SB_DM_2

SB_DM_3

SB_DM_4

SB_DM_5

SB_DM_6

SB_DM_7

SB_DQS_0

SB_DQS_1

SB_DQS_2

SB_DQS_3

SB_DQS_4

SB_DQS_5

SB_DQS_6

SB_DQS_7

SB_DQS#_0

SB_DQS#_1

SB_DQS#_2

SB_DQS#_3

SB_DQS#_4

SB_DQS#_5

SB_DQS#_6

SB_DQS#_7

SB_MA_0

SB_MA_1

SB_MA_2

SB_MA_3

SB_MA_4

SB_MA_5

SB_MA_6

SB_MA_7

SB_MA_8

SB_MA_9

SB_MA_10

SB_MA_11

SB_MA_12

SB_MA_13

SB_MA_14

BC16

BB17

BB33

AU17

BG16

BF14

AM47

AY47

BD40

BF35

BG11

BA3

AP1

AK2

AL47

AV48

BG41

BG37

BH9

BB2

AU1

AN6

AL46

AV47

BH41

BH37

BG9

BC2

AT2

AN5

AV17

BA25

BC25

AU25

AW25

BB28

AU28

AW28

AT33

BD33

BB16

AW33

AY33

BH15

AU33

24-

MB_CAS#

MB_A(10)
MB_A(11)
MB_A(12)
MB_A(13)

MB_A(0)
MB_A(1)
MB_A(2)
MB_A(3)
MB_A(4)
MB_A(5)
MB_A(6)
MB_A(7)
MB_A(8)
MB_A(9)

24-

24-

24­24­24-

MB_RAS#
MB_WE#

24-

24-

24-

24-

MB_BS0#
MB_BS1#
MB_BS2#

MB_DM(7:0)

MB_DQS(7:0)

MB_DQS#(7:0)

MB_A(13:0)

24-

INVENTEC

TITLE

Carlisle

CANTIGA (4/7)

DOC. NUMBERSIZE

CODE

CHANGE by OF

Paul_Hsu

26-Oct-2007

A3

Model_No X01

CS

SHEET

REV

6219