5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RTCVCC
PCH_DPWROK
t200a min=0ms
(DPWROK)
PCH_RTCRST#
(VCCRTC)
(RTCRST#)
t200 min=9ms
+V5AUD
+VIO3.3_A
+V5_SCALAR
+V3.3_SCALAR
+V1.8_SCALAR
(VCCDSW3_3)
PWM TPS51125RGER, Turn on by +VIN
PWM TPS51125RGER, Turn on by +VIN
+VIN
PSON_SCALAR
<<Single>>
Controller Single from EC.
(1) PC Mode, When push power button system entry S0.
(2) Monitor Mode, Plug VGA or HDMI machine in S5 state.
WAKE Event (1) PC Mode = Power Button (2) Monitor Mode = VGA_IN or HDMI_IN = High
Adapter in (19V)
PMOS, +V5AUD => +V5_SCALAR. Turn on by PSON_SCALAR
PMOS, +VIO3.3_A => +V3.3_SCALAR. Turn on by PSON_SCALAR
LDO, +V3.3_SCALAR => +V1.8_SCALAR, Turn on by +V3.3_SCALAR
Could already be high before this sequence begins (to support M3),but will never go high later than SLP_S3#PM_SLP_LAN#
+V5AUD
+VIO3.3_A
+V5A
+V3.3A
t202 min=95ms
PM_SLP_S4#
PM_SLP_S3#
t204 min=30us
From PCH
From PCH
From PCH
(VCCDSW3_3)
(SUS_SLP#)
PWM TPS51125RGER, Turn on by +VIN
+1.5VDIMM
PWM TPS51218DSCR, Turn on by PM_SLP_S4#
PWM TPS51125RGER, Turn on by +VIN
+VIN
PM_SLP_SUS#
(DPWROK)
Adapter in (19V)
Generated by M/B Logic
From PCH
(SLP_S5#)
(SLP_S4#)
(SLP_S3#)
Power rails rise = 0.2~20ms
PSU <= 20ms, NMOS +V5AUD => +V5S, Turn on by SYS_ON (From PS_ON# Logic)
PSU <= 20ms, NMOS +VIO3.3_A => +V3.3S, Turn on by SYS_ON (From PS_ON# Logic)
PSU <= 20ms, PWM TPS54231DR, Turn on by PSON_3V (From PS_ON# Logic)
PMOS, +V5AUD => +V5A. Turn on by SLP_SUS_FET
PMOS, +VIO3.3_A => +V3.3A. Turn on by SLP_SUS_FET
t200c min=0ms
PS_ON#
PCH_DPWROK
SLP_SUS_FET
Generated by M/B Logic
PM_SLP_A#
PM_SLP_S5#
t203 min=30us
From EC, based on PM_SLP_S3# / PM_SLP_S4# / PM_SLP_S5#
(SLP_A#) Could already be high before this sequence begins (to support M3),but will never go high later than SLP_S3#
(SLP_LAN#)
t200b min=10ms
PM_RSMRST#(RSMRST#)
t201 min=10ms
Generated by M/B Logic
+V5S
+V3.3S
+V12S
RTC Power
Scalar Power
System Power
WAKE Event (Power Button)
Scalar power can turn on before SUS_PWR (+V5A / +V3.3A) or later, ,but will never go high later than SLP_S3#
=500ms
VCC3_ME
VCC1_05_ME
LDO, +V3.3A => VCC1_05_ME, Turn on by PM_SLP_A#
PMOS, +V3.3A => VCC3_ME, Turn on by PM_SLP_A#
VCC1_05_PCH
PMOS, +V1.8_SCALAR => VCC1_8_PCH. Turn on by +V3.3S
PWM TPS51218DSCR, Turn on by +V3.3S
VCC1_8_PCH
ME Power
=50ms
CPU_VTT
VCCSA
PWM TPS51218DSCR, Turn on by CPU_VTT_EN (From VCC1_05_PCH Logic)=50ms
PWM TPS51218DSCR, Turn on by CPU_VTT_PWRGD
VCC1_05_PCH -> CPU_VTT -> VCCSA
+V1.5S
+0.75VTT
VCORE
CPU_VAXG
NMOS, +1.5VDIMM => +V1.5S, Turn on by PWR_EN# (From PM_SLP_S3# Logic)
LDO, +1.5VDIMM => +0.75VTT, Turn on by PWR_EN# (From PM_SLP_S3# Logic)
Controller single, Generated by PM_SLP_S3# Logic
VR_EN
Ramp will occur after PLTRST#
PWRGD_3V
base on +V3.3S (delay 100ms)
OEM MODEL
Size
Rev
Date
Sheet
of
T&I MODEL
PCB NAME
remark
T&I (TPV-INVENTA TECHNOLOGY CO., LTD)
Key Component
Circuit diagram NO. CA202M DVT_0.1
CA203M Custom
41 42Monday, November 12, 2012
6050A2546301
<remark>
Power Sequence
<Circuit diagram NO.>
OEM MODEL
Size
Rev
Date
Sheet
of
T&I MODEL
PCB NAME
remark
T&I (TPV-INVENTA TECHNOLOGY CO., LTD)
Key Component
Circuit diagram NO. CA202M DVT_0.1
CA203M Custom
41 42Monday, November 12, 2012
6050A2546301
<remark>
Power Sequence
<Circuit diagram NO.>
OEM MODEL
Size
Rev
Date
Sheet
of
T&I MODEL
PCB NAME
remark
T&I (TPV-INVENTA TECHNOLOGY CO., LTD)
Key Component
Circuit diagram NO. CA202M DVT_0.1
CA203M Custom
41 42Monday, November 12, 2012
6050A2546301
<remark>
Power Sequence
<Circuit diagram NO.>