Inventec Bandit M2 HD+ 6050A2514101 Schematic
THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC
CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT
WRITTEN PERMISSION,INVENTEC CORPORATION, ALL RIGHT RESERVED.
8
7 6 5 4 3 2 1
2012
HSF Property:ROHS or Halogen-Free
E
D
FF
E
BANDIT M2 HD+
D
MV BUILD
2013.01.04
C
B
A
2012/09/10 2012-ECO-017507 A
DATE CHANGE NO.
8
REV
7 6 5 4 3
DRAWER
DESIGN
CHECK
RESPONSIBLE
SIZE=
FILE NAME:
P/N
XXX
XXX
XXX
XXX
A3
BANDIT-MB-1310A2514101
6050A2514101
21-OCT-2002
21-OCT-2002
21-OCT-2002
POWER
IRAY CHEN
IRAY CHEN
IRAY CHEN
IRAY CHEN
2
21-OCT-200221-OCT-2002
21-OCT-2002
21-OCT-2002
21-OCT-2002
VER:
C
B
A
DATEDATEEE
A02
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
ULTRABOOK MAIN BOARD
CODE
SIZE
A3
1310xxxxx-0-0
CS
SHEET
DOC.NUMBER REV
of
80
1
1
X01
8 7
6 5
4
3 2 1
D
1. PROJECT NAME
2. TABLE OF CONTENTS
3. BLOCK DIAGRAM
4. SYSTEM POWER FLOW
5. SYSTEM POWER(CHARGER)
6. SYSTEM POWER(BATT SELECTOR)
7. SYSTEM POWER(OCP)
8. SYSTEM POWER(P3V3A&P5V0A)
8. SYSTEM POWER(P5V0A _CHG
10. SYSTEM POWER(P1V5)
11. SYSTEM POWER(P1V05M)
12. SYSTEM POWER(P1V05S)
13. SYSTEM POWER(P1V8S)
B
14. SYSTEM POWER(PVSA)
15. SYSTEM POWER(PVCORE1)
16. SYSTEM POWER(PVCORE2)
17. POWER TEST POINT
18. POWER PAD
19. POWER(SLEEP)
20. POWER(SEQUENCE)
21. XDP CONN
22. FAN & THERMAL
TABLE OF CONTENTS
23. IVY BRIDGE_1 (CLK,MISC,JTAG)
24. IVY BRIDGE_2 (POWER)
25. IVY BRIDGE_3 (DMI,DP,PEG,FDI)
26. IVY BRIDGE_4 (DDR3)
27. IVY BRIDGE_5 (GRAPHICS POWER)
28. IVY BRIDGE_6 (GND,RESERVED)
29. DDR3_SO-DIMM0
30. DDR3_SO-DIMM1
31. PANTER POINT_1 (HDA,JTAG,SPI,SATA)
32. PANTER POINT_2 (PCI-E,SMBUS,CLK)
33. PANTER POINT_3 (DMI,FDI,GPIO)
34. PANTER POINT_4 (LVDS,DDI)
35. PANTER POINT_5 (PCI,USB,NVRAM)
36. PANTER POINT_6 (GPIO,VSS_NCFT,RSVD)
37. PANTER POINT_7 (POWER)
38. PANTER POINT_8 (POWER)
39. PANTER POINT_9 (GND)
40. CRT / DISPLAY PORT CNTR
41. LCM & WEBCAM
42. SATA & MSATA CNTR
43. USB CNTR & USB CHARGER
44. FINGER PRINTER CNTR
47. KEYBOARD
48. TPM
49. LAN INTERFACE
50. LAN RJ45 CNTR
51. WLAN
52. WWAN & SIM CARD
53. DOCKING CNTR
54. STICK POINT & B2B CNTR
55. CODEC
56. EXT MIC AMP
57. JACK & USB3 CNTR
58. CARD READER
59. BUTTON LED
60. SMART VARD & LED DB
61. MIC DB
62. SCREW
63. EMI & RF SOLUTION
64. SYSTEM SEQUENCE
D
CC
B
AA
45. ACCELEMETOR
46. KBC / SPI
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
TABLE OF CONTENTS
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
1310xxxxx-0-0
CS
A3
SHEET
of
2
1
DOC.NUMBER
CODE
REV
X01
80
8 7
PRIMARY LI-LON BATTERY
6 5
4
3 2 1
SECOND LI-LON BATTERY
D
CRT
THERMAL SENSOR
SMSC_EMC1412
LED PANEL
R.G.B
LVDS
IVY BRIDGE
ULV BGA1023
31MM X 24MM
ACCELEROMETER
1666MT/S
1666MT/S
DDR3_SODIMM
DDR3_SODIMM
SATA0
HDD(GEN3)
D
ST_HP3DC2TR
DISPLAY PORT
DISPLAY PORT X 2
FDI/DMI
DDP
SATA
HDA
AUDIO CODEC
IDT 92HD91WC
SATA2
MSATA
CC
(DOCKING)
PCH
USB3.0
PANTHER POINT QM77
MEDIA CARD CONTROLLER
B
RJ45
PCIE3
PCIE4
WLAN
PCIE6
GBE PHY
INTEL 82579LM
PCIE
LPC
KBC
SMSC 1126
25MM X 25MM
TPM1.2
SLB9635
USB2.0
USB0 - DOCKING
USB1 - CHARGER
USB2 - RIGHT 1
USB5 - BLUETOOTH
USB7 - SMART CARD
USB8 - FINGER
USB1 - DOCKING
B
USB2 - LEFT
USB3 - RIGHT 1
USB4 - RIGHT 2
AA
TOUCH PAD
SPI 16MB
USB3 - RIGHT2
USB10 - CAMERA
POINT STICKKEYBOARD
USB12- WWAN
DOCKING CONNECTOR
LINE IN/LINE OUT
8
7 6
RJ-45USB3.0 PORT X 4
5 4
DP1.2
VGA
CHANGE by
XXX
DATE
21-OCT-2002
23
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
BLOCK DIAGRAM
DOC.NUMBER
CODE
SIZE
1310xxxxx-0-0
CS
A3
SHEET
of
80
3
1
REV
X01
8 7
LIMIT_SIGNAL
D
6 5
ADP_EN
OCP
ICS
OCP_OC#
4
ADP_PRES
KBC_PW_ON
SLP_S3#_3R
EN0
5/3.3V
(TPS51123)
3 2 1
P5V0A_CHG
P3V3ALW
P5V0AL
P3V3AL
SLP_S3#_3R
SLP_S3#_3R
SLP_S3#_3R
PM_SLP_A_#
RICHTEK
8086AZQW
TPS51463
AO6402AL
P1V8S
PVSA
P5V0S
D
P1V05M
RICHTEK
8086AZQW
P3V3S
P3V3A
CC
ADAPTER
(65W)
CHARGER
BQ24736
CHARGER_DAT
CHARGER_CLK
SPWON
EN_P3V3A
AO6402AL
FDC638APZ
2ND BATTERY
PVBAT
MAIN BATTERY
DDR3 / 1.5V
SLP_LAN#
WWWAM_OFF
FDC638APZ
FDC638APZ
P3V3M
PVSIM
DDR3L/1.35V
SLP_S4#_3R
B
P1V8S
SLP_S3#_3R
8
7 6
GMT
G966A
P1V5S_LDO
5 4
KBC_GPIO22
SLP_S4#_KBC
EN_VCCP
EN_CPU
TPS51216
VCCP
TPS51219
IMVP VI
ISL95833
CHANGE by
P1V5
VCCP_PG
PVAXG
PVCORE
VGATE
XXX
FDMS7692SPWON
P1V5S
B
AA
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
BLOCK DIAGRAM POWER
DATE
21-OCT-2002
23
SIZE
DOC.NUMBER
CODE
1310xxxxx-0-0
CS
A3
SHEET
of
4
1
REV
X01
80
8 7
7
Q6010
IN
17
1
1
2
2
3
3
45
45
C6019
R6017
2 1
2 1
220K_5%_2
0.1UF_16V_2
100K_5%_2
1
Q6009
1
R6015
2
3
DS
G
2
48
ADP_DET
PVADPTR P3V3ALP5V0S
OUT
VADPBL
D S
8
8
7
7
6
6
FAIR_FDMC4435BZ_8P
G
D
48
ADP_EN
SSM3K7002FU
B
PVADPTR
C6017
C6018
2 1
100PF_50V_2
2 1
1000PF_50V_2
4.3K_5%_2
R6028
2 1
L6015
NFE31PT222Z1E9L
OUT
21
Q6019
R6021
127K_1%
2 1
3
DS
G
R6023
2 1
2
R6022
1M_5%_2
C6022
2 1
20K_1%_2
R6029
18.2K_1%_2
2 1
R6030
10K_1%_2
2 1
2 1
2 1
1SS355VMTE_17
48
CHG_RST
D6018
IN
SSM3K7002FU
1
R6024
21
ACDET>0.6V:SMBUS OK
ACDET>2.4V&<3.1V:ACOK
100PF_50V_2
7
ICS
48
CHR_ILIM
7
V_3.9K
48
CHARGER_DAT
CHARGER_CLK
7
8
7 6
6 5
21
4
3
C6015
C6016
2 1
2 1
100PF_50V_2
1
S
2
3
4 5
G
NMOS_4D3S
21
D6017
BAT54WS
AON7410
4.3K_5%_2
R6018
2 1
17
PVBAT_IN
TI_BQ24736RGRR_QFN_20P
22K_5%_2
C6049
2 1
100PF_50V_2
OUT
BI
BI
IN
IN
R6049
0_5%_2
IN
D6015
1000PF_50V_2
Q6011
PVADPTR_IN
1
1
3
3
FAIR_FDMC4435BZ_8P
8
D
7
6
IN
U6000
6
7
8
9
10
C6048
2 1
0.01UF_50V_2
21
65
17
CN6000
1
1
2
3
2
2
4
5
6
OUT
SEM_SM24_SOT23_3 P
G
4 5
4 5
3
3
2
2
1
1
DS
Q6012
R6000
0.01_1%_6
C6028
0.1UF_16V_2
2
3
4
5
6
ACES_50224_0060N_001_6P
6
7
8
G
G
LIMIT_SIGNAL
PVPACK
6
7
8
21
43
21
G1
G2
21
ACDET
IOUT
SDA
SCL
ILIM
C6029
1UF_25V_3
5
3
ACPRES
ACDRV
CMSRC
DLIM
SRN
SRP
13
12
11
C6030
2 1
CSC0402_DY
48
9
VADP_DEBUG
214
ACP
ACN
PHASE
LODRV
GND
15
14
HIDRV
BTST
REGN
1UF_25V_3
21
TML
20
VCC
19
18
17
16
C6025
2 1
1UF_10V_2
C6047
2 1
0.01UF_50V_2
5 4
55
7
C6027
2 1
R6026
0_5%_2
D6016
2 1
BAT54WS
R6025
0_5%_2
4
IN
21
0.047UF_16V_2
21
R6027
2 1
R6020
0_5%_2
10_5%_5
C6026
3 2 1
D
PVBAT
12
PAD6015
2 1
POWERPAD_2_0610
IN
678
Q6000
D
AON7410 AON7410
NMOS_4D3S
G
C6000
C6001
2 1
2 1
10UF_25V_5
S
3
214 5
10UF_25V_5
21
678
Q6001
D
NMOS_4D3S
G
S
3
214 5
R7600
2 1
C7600
CSC0402_DY
2 1
RSC_0603_DY
PVBAT_CHG
L6000
ETQP3W4R7WFN
PVPACK
R6001
0.02_1%_6
C6023
21
43
D6049
C6011
21
C6010
2 1
2 1
10UF_25V_5
10UF_25V_5
B0530W_7
2 1
C6021
2 1
0.1UF_25V_2
21
0.1UF_16V_2
C6024
2 1
0.1UF_25V_2
21
CC
B
AA
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
CHANGE by
XXX
DATE
21-OCT-2002
23
SIZE
DOC.NUMBER
CODE
1310xxxxx-0-0
CS
A3
SHEET
of
5
1
REV
X01
80
8 7
6 5
4
3 2 1
D
B
48
48
LATCHED_ALARM
FET_A
OUT
D
P3V3AL
D7504
12
PVPACK
SBR3M30P1_7
Q6050
1
1
2
2
3
3
4 5
4 5
FAIR_FDMC4435BZ_8P FAIR_FDMC4435BZ_8P
21
Q6051
DS
8
7
6
G
D S
8
8
7
7
6
6
1
8
2
7
3
6
45
G
R6064
470K_5%_2
2 1
D6050
3
2 1
D6058
BAV99W_7_F
R6097
0_5%_2
R6099
100_5%_2
21
21
IN
OUT
MFET_A
IN
MFET_B
2
5
2N7002DW
1
2
3
45
Q6053
G1
G2
PVBATA
48
48
SDA_MAIN
SCL_MAIN
R6052
2K_1%_2
2 1
BI
BI
R6079
2 1
220K_5%_2
65
R6080
0_5%_2
2 1
1
S1
6
D1
3
D2
4
S2
R6050
2K_1%_2
2 1
R6051
100_5%_2
R6053
100_5%_2
C7500
2 1
100PF_50V_2
21
21
2 1
R6057
1K_5%_2
P3V3AL
2 1
R6058
C7501
PHP_PESD5V0S1BB_SOD523_2P
21
2 1
C7503
100K_5%_2
OUT
12
2 1
100PF_50V_2
2 1
P3V3AL
21
100PF_50V_2
D7503
MAIN_BAT_DET#
D7505
C7524
PHP_PESD5V0S1BB_SOD523_2P
R6055
3
BAV99W_7_F
12
2 1
100PF_50V_2
2 1
2 1
100_5%_2
OUT
BATTERY OCP PWM#
48
D7506
21
C7502
G2
PHP_PESD5V0S1BB_SOD523_2P
G1
OCP_MAIN#
0.1UF_25V_2
CN6050
G2
G1
8 POWER
8
7 POWER
7
6
6
5
5
4
4
3
3
2 GND
2
1 GND
1
FOX_BP0208C_B25AAD1_9H_8P
CC
B
AA
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
A3
CS
1310xxxxx-0-0
SHEET
6
of
1
DOC.NUMBER
CODE
REV
X01
80
8 7
5
17
VADPBL
IN
6 5
R6933
21
255K_1%_2
4
3 2 1
P5V0AL P3V3AL
D
5
ICS
R6931
2 1
200K_1%_2
R6930
2 1
41.2K_1%_3
C6906
R6934
22K_5%_2
2 1
IN
R6913
46.4K_1%_2
21
C6900
2 1
IN
V+
3
2
2 1
CSC0402_DY
2VREF
+IN
+
-
-IN
V-
4 8
7
U6903
OUT
TI_LMV393IDGKR_SOP_8P
8 9
0.22UF_6.3V_2
21
R6935
47K_5%_2
1
OUT
ADP_PRES
48
D
P5V0S
U6902
IN+
VEE
C6904
1UF_10V_2
D6902
BAV70W_7_F
3
21
P5V0S
5
VCC
C6903
43
OUTPUTIN-
2 1
0.1UF_16V_2
CC
R6919
2K_5%_2
2 1
21
R6920
21
665K_1%_2
R6922
21
20
200K_1%_2
1
2
R6924
2 1
200K_1%_2
R6923
2 1
R6918
Q6902
2
21
S
LES_LBSS84LT1G_SOT23_3P
1
BCD_AZV321KTR_E1_SOT23_5P
1M_1%_2
3
D
G
OUT
CURRENT_ADC
2 1
VBIAS
V_3.9K
OUT
IN
IN
OUT
IN
IN
R6925
118K_1%_2
2 1
R6921
118K_1%_2
100_5%_2
OCP_MAIN#
48
OCP_TRAVEL#
LIMIT_SIGNAL_100R
20
55
LIMIT_SIGNAL
20
5
B
PVPACK
IN
2VREF
7 8 9
P3V3AL
20
P3V3AL
R6916
2 1
R6914
2 1
47K_5%_2
P5V0AL
R6928
R6929
8
7 6
R6927
0_5%_2
200K_1%_264.9K_1%_2
R6997
2 1
3
Q6999
DS
SSM3K7002FU
2
2 1
5
6
V+
U6903
+IN
+
OUT
-
-IN
V-
TI_LMV393IDGKR_SOP_8P
4 8
C6905
2 1
0.1UF_16V_2
39.2K_1%_2
1
G
2 1
2 1
R6926
1M_5%_2
7
R6932
2 1
21
100K_5%_2
48
OUT
LATCHED_ALARM
5 4
CHR_ILIM
OUT
CHANGE by
C6902
2 1
3.9K_5%_2
LMBT3904WT1G
R6915
3900PF_16V_2
C E
Q6901
XXX
R6917
100_5%_2
2 1
OUT
2 1
100K_5%_2
1
B
23
D6901
UDZV4.7B
2 1
OCP_A_IN
48
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
DOC.NUMBER
CODE
DATE
21-OCT-2002
23
SIZE
A3
CS
1310xxxxx-0-0
SHEET
7
of
80
1
REV
X01
B
AA
8 7
6 5
4
3 2 1
D
VRP3V3A
P3V3ALW
B
OUT
OCP=7AMP
PAD6100
2
POWERPAD_2_0610
12
6.8K_1%_2
10K_1%_2
VO=((6.8K/10K)+1)*2
1
R6122
R6121
EN_5V
EN_3V
IN
IN
IN
VRP5V0A_VIN
9
D
PVBAT
12
POWERPAD_2_0610
6465
89
IN
VBATP
21
21
C6100
2 1
PAD6110
2 1
R6120
75K_1%_2
2 1
R6119
OUT
75K_1%_2
2 1
2VREF
7209
TON=3.3V:300KHZ/375KHZ
OUT
Q6100
C6110
2 1
L6100
ETQP3W3R3WFN ETQP3W3R3WFN
2 1
CSC0805_DY
21
5 4
S2 D1
10UF_25V_5
6
S2
7
S2
8
G2
9
PH
FAIR_FDMS7620S_8P
C6111
10
D1
Q2
3
D1
2
D1
1
G1
Q1
VRP3V3A_HG
VRP3V3A_PH
VRP3V3A_LG
C6113
0.1UF_16V_2
R6114
21
21
25
TML
7 24
VO2 VO1
8
VREG3
9 22
VBST2
10 21
DRVH2
11 20
LL2
12 19
DRVL2
1
4
3
5
2
TONSEL
TRIP2
VREF
VFB1
VFB2
SKIPSEL
VREG5
GND
EN0
VIN
R7610
14
17
16
15618
R6111
13
2 1
1UF_25V_3
2 1
4.7_5%_3
+
150UF_6.3V
2 1
P3V3AL
C7610
2 1
0.0015UF_50V_2
PAD6103
1 2
POWERPAD1X1M
21
VRP3V3_LDO
4.7UF_6.3V_3
330K_5%_2_DY
C6103
2 1
C6114
2 1
TRIP1
23
PGOOD
VBST1
DRVH1
DRVL1
ENC
TI_TPS51123RGER_QFN_24P
VRP5V0_LDO
LL1
2.2_5%_22.2_5%_2
U6100
2 1
POWERPAD1X1M
C6112
C6105
2 1
10UF_6.3V_3
0.22UF_6.3V_2
R6109
PAD6105
21
12
C6108
0.1UF_16V_2
P5V0AL
21
VRP5V0A_HG
VRP5V0A_LG
18
5V_PG
FAIR_FDMS7620S_8P
10
D1
Q2
3
D1
2
D1
1
G1
Q1
Q6150
S2D1
S2
S2
G2
PH
VRP5V0A_PH
C6161
54
2 1
6
10UF_25V_5
7
8
9
R7615
RSC_0603_DY
2 1
C7615
CSC0402_DY
2 1
6465
CSC0805_DY
VBATP
8 9
OUT
VRP5V0A
IN
C6160
2 1
CC
OCP=7AMP
P5V0A_CHG
POWERPAD_2_0610
21
15.4K_1%_2
R6117
21
10K_1%_2
R6118
PAD6150
1 2
21
B
L6150
21
+
C6150
2 1
150UF_6.3V
VO=((15.4K/10K)+1)*2
SKIP:OOA=3.3V; PWM=2VREF; AUTO=GND
SKIP_5V_3V
20
EN_5V_3V
IN
IN
AA
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
A3
CS
1310xxxxx-0-0
SHEET
8
of
1
DOC.NUMBER
CODE
REV
X01
80
8 7
6 5
4
3 2 1
PVADPTR
8 7
20
R6197
R6105
2 1
D
C6198
2 1
100PF_50V_2
49.9K_1%_2
576K_1%_3
21
C6109
R6104
2 1
2 1
49.9K_1%_2
0.22UF_6.3V_2
OUT
VOLTAGE_ADC
48
2VREF
IN
R6116
20K_5%_2
21
U6102
1
IN+
2
VEE
BCD_AZV321KTR_E1_SOT23_5P
R6107
100K_1%_2
R6115
200K_1%_2
5
VCC
43
OUTPUTIN-
21
P5V0AL
C6115
10UF_6.3V_3
2 1
OUT
48
ADC_VREF_1126
D
2 1
CC
P3V3AL
R6101
D6100
21
21
1SS355VMTE_17
R6102
48
KBC_PWR_ON
IN
B
21
0_5%_2
C6102
Q6102
S1
2
G1
D1
D2
5
G2
S2
2N7002DW
2 1
0.015UF_10V_2
100K_5%_2
2 1
1
6
3
4
R6199
0_5%_2_DY
R6195
47_5%_2
OUT
EN_P3V3A
21
OUT
EN_3V
P3V3A
21
18
8
65
8
64
VRP5V0A_VIN
VBATP
IN
OUT
21
21
D6102
1SS355VMTE_17
D6101
2 1
PANJIT_MMSZ5252A
PVBATA
R6113
100_5%_3
D6104
21
BAV70W_7_F
3
21
PVADPTRPVBATB
21
21
D6105
1SS355VMTE_17
48
OUT
VADP_DEBUG
B
Q7351
G
CSC0402_DY
21
R7352
C7350
P5V0AP5V0A_CHG
D
8
8
7
7
6
6
5
5 4
AA
2 1
212019
57554845423527
18
SLP_S3#_3R
20
EN_5V_3V
R6126
P5V0AL
SHORT_0402_5
P3V3AL
R6106
R6198
21
0_5%_2
C6199
21
OUT
21
100K_5%_2
R6100
100K_5%_2_DY
2 1
0.1UF_16V_2
SKIP_5V_3V
RSC_0402_DY
21
4
R6103
P3V3AL
21
5
U6104
I0
O
I1
GND VCC
3
TOSHIBA_TC7SZ32FU_SSOP_5P
1
2
R6110
R6108
0_5%_2_DY
21
21
0_5%_2
IN
IN
IN
48
KBC_PWR_ON
CPPWR_EN
KBC_GPIO51
KBC_PWR_ON
4845
48
R7350
100K_5%_2
2 1
R7351
21
Q7350
S1
2
48
IN
G1
5
G2
2N7002DW
D1
D2
S2
0_5%_2
1
6
3
4
S
1
1
2
2
3
3
4
FAIR_FDMC6675BZ_8P
C7351
2 1
100_5%_2
10UF_6.3V_3
IN
IN
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
A3
CS
1310xxxxx-0-0
SHEET
9
of
1
DOC.NUMBER
CODE
REV
X01
80
8 7
MEM_1V5-> HI DDR-> 1.35V
MEM_1V5-> LOW DDR-> 1.5V
D
18
EN_0V75
1821
3545
SLP_S4#_3R
18
EN_1V5
DDR3L_SEL
B
48
MEM_1V5
IN
R6211
2 1
IN
IN
IN
IN
VOUT=REFIN=1.8*(52.3K/(10K+52.3K))
MODE=100KOHM:TRACKING DISCHARGE
R6210
R6204
RSC_0402_DY
0_5%_2
R6207
2 1
52.3K_1%_2
1
21
Q6202
200K_5%_2
C6212
2 1
R6208
2 1
3
DS
G
2
21
2 1
10K_1%_2
0.01UF_50V_2
71.5K_1%_2
SSM3K7002FU
R6206
OUT
DDR3L_SEL
P5V0A_CHG
6 5
4
3 2 1
D
PVBAT
C6205
1512
14
VRP1V5_HG
13
VRP1V5_PH
11
VRP1V5_LG
10
20
9
2
3
1
4
5
21
P0V75S
2.2_5%_3
P0V75M_VREF
C6207
2 1
10UF_6.3V_3
R6205
C6208
2 1
21
0.1UF_16V_2
0.22UF_6.3V_2
C6204
3
2
1
21
2 1
2.2UF_6.3V_3
U6200
VBSTV5IN
17
S3
16
S5
6
VREF
8
REFIN
7
GND
19
MODE
C6209
2 1
0.1UF_16V_2
R6202
18
TRIP
R6203
TI_TPS51216RUKR_QFN_20P
2 1
2 1
100K_5%_2
30.1K_1%_2
DRVH
SW
DRVL
PGND
PGOOD
VDDQSNS
VLDOIN
VTT
VTTSNS
VTTGND
VTTREF
TML
Q6200
FAIR_FDMS3668S_8P
D1
Q2
D1
D1
PHASE
G1
Q1
TML
54
S2
S2
S2
G2
C6210
6
7
C6211
2 1
2 1
10UF_25V_5
10UF_25V_5
OUT
VRP1V5
8
9
L6200
21
1 2
43
3 4
PAN_ETQP3W1R0WFN_4P
R7620
2 1
RSC_0603_DY
C7620
2 1
CSC0402_DY
C6200
PAD6200
1 2
POWERPAD_2_0610
+
2 1
330UF_2V_9MR_PANA_-35%
21
OCP=12AMP
P1V5
CC
B
AA
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
A3
CS
1310xxxxx-0-0
SHEET
of
1
DOC.NUMBER
CODE
REV
X01
8010
8 7
6 5
4
3 2 1
D
13
VRP1V8_1V05IN
VRP1V8_1V05IN
IN
B
IN
OUT
VRP1V05_LAN_M
C6410
2 1
R6402
10_5%_2
2 1
10UF_6.3V_3
RICHTEK_RT8068AZQW_WDFN_10P
U6400
11
TML
10 1
9
8
7
6 5
LX
PVIN
LX
PVIN
LX
SVIN
PGOOD
NC
EN
FB
VRP1V05_LAN_M_PH
2
3
4
IN
C6401
2 1
0.1UF_16V_2
VOUT=((7.68K/10K)+1)*0.6
L6400
PAN_ELL5PR2R2N
18
EN_P1V05
PAD6400
21
POWERPAD_2_0610
R6400
2 1
C6400
C6403
2 1
2 1
7.68K_1%_2
CSC0402_DY
22UF_6.3V_5
1 2
21
R6401
10K_1%_2
2 1
OCP=4.5AMP
P1V05M
D
CC
B
AA
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
A3
CS
1310xxxxx-0-0
SHEET
11
of
1
DOC.NUMBER
CODE
REV
X01
80
8 7
6 5
4
3 2 1
D
D
MODE=100KHZ:300KHZ
18
EN_VCCP
20
VCCP_PG
26
VCCIO_SEL
26
VSS_SENSE_VTT
26
C6308
2 1
2.2UF_6.3V_3
VTT_SENSE
R6305
0_5%_2
2 1
B
C6320
R6308
2 1
2 1
11.3K_1%_2
0.01UF_50V_2
VOUT=2*11.3/(10+11.3)=1.06V
IN
OUT
IN
IN
IN
R6306
21
0_5%_2_DY
TI_TPS51219RTER_QFN_16P
1
2
3
4
C6307
0.01UF_50V_2
R6304
2 1
100K_1%_2
21
0.1UF_16V_2
P5V0A
C6305
2 1
C6304
2.2UF_6.3V_3
21
3
2
1
Q6300
FAIR_FDMS3668S_8P
D1
Q2
D1
D1
PHASE
G1
Q1
TML
54
S2
6
S2
7
S2
8
G2
9
R6302
17
16815
14
13
BST
SW
DH
DL
V5
2.2_5%_3
12
VRP1V05S_VCCP_PH
11
VRP1V05S_VCCP_HG
10
VRP1V05S_VCCP_LG
9
U6300
VREF
REFIN
GSNS
VSNS
EN
MODE
PWPD
PGOOD
TRIP
GND
COMP
5
PGND
6
7
21
R6301
2 1
41.2K_1%_2
PVBAT
CC
C6310
C6311
2 1
2 1
10UF_25V_5
CSC0805_DY
L6300
21
1 2
43
3 4
CYN_PCMB063T_R68MS_4P
R7630
2 1
RSC_0603_DY
C7630
CSC0402_DY
2 1
+
C6300
2 1
OUT
VRP1V05S_VCCP
PAD6300
1 2
POWERPAD_2_0610
OCP=15AMP
P1V05S_VCCP
21
B
330UF_2V_9MR_PANA_-35%
AA
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
A3
CS
1310xxxxx-0-0
SHEET
of
1
DOC.NUMBER
CODE
REV
X01
8012
8 7
6 5
4
3 2 1
D
D
P5V0A_CHG
PAD6971
21
1 2
POWERPAD_2_0610
VRP1V8_1V05IN
IN
R6970
C6975
2 1
10UF_6.3V_3
10_5%_2
2 1
C6972
2 1
0.1UF_16V_2
B
13
OUT
VRP1V8_1V05IN
U6970
11
TML
10 1
PVIN
9
PVIN
8
SVIN
7
NC
6 5
FB
RICHTEK_RT8068AZQW_WDFN_10P
PGOOD
LX
LX
LX
EN
VRP1V8S_PH
2
3
4
PAN_ELL5PR2R2N
OUT
P1V8S_PG
IN
EN_1V8
VOUT=((20.5K/10K)+1)*0.6
L6970
21
20
18
R6973
R6972
OUT
VRP1V8S
OCP=4.5AMP
P1V8S
CC
PAD6970
21
1 2
POWERPAD_2_0610
C6970
C6974
2 1
20.5K_1%_2
10K_1%_2
2 1
2 1
2 1
CSC0402_DY
22UF_6.3V_5
B
AA
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
A3
CS
1310xxxxx-0-0
SHEET
of
1
DOC.NUMBER
CODE
REV
X01
8013
8 7
6 5
4
3 2 1
D
P5V0A_CHG
C6510
2 1
0.1UF_16V_2
C6505
21
0.01UF_50V_2
2 1
C6506
0.1UF_16V_2
VRPVSA_PH
21
IN
EN_PVCCSA
0_5%_2
R6506
2 1
RSC_0402_DY
L6500
1 2
3 4
CYN_PCMB063T_R33MS_4P
CHOKE_4PIN_2PIN
C6550
0.22UF_6.3V_2
TML
VIN
VIN
VIN
PGND
PGND
PGND
2 1
R6500
2 1
1
3
2
GND
VREF
COMP
U6500
V5FILT
V5DRV
PGOOD
1817161514
3300PF_50V_2
5.1K_1%_2
654
SLEW
VOUT
MODE
SW
SW
SW
SW
SW
BST
VID0
VID1
EN
13
R6501
RSC_0402_DY
TI_TPS51463RGER_QFN_24P
7
8
9
10
11
12
C6504
2 1
25
24
23
22
21
C6511
2 1
22UF_6.3V_5
20
19
P5V0A
R6502 SHORT FOR REMOTE SENSE
R6506 SHORT FOR LOCAL SENSE
R6502
21
21
43
IN
VCCSA_SENSE
C6500
2 1
2 1
27
C6501
2 1
C6502
22UF_6.3V_522UF_6.3V_522UF_6.3V_5
OUT
VRPVSA
PAD6500
1 2
POWERPAD_2_0610
OCP=7AMP
PVSA
21
B
C6503
C6509
2 1
1UF_6.3V_2
C6508
2 1
1UF_6.3V_2
CSC0402_DY
21
27
27
20
OUT
IN
IN
VCCSA_VID0
VCCSA_VID1
VCCSA_PG
D
CC
B
AA
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
A3
CS
1310xxxxx-0-0
SHEET
of
1
DOC.NUMBER
CODE
REV
X01
8014
8 7
6 5
4
3 2 1
IN
GFX_VSS_SENSE
IN
2 1
C6740
470PF_50V_2
OUT
OUT
GFX_VCC_SENSE
R6742
2.61K_1%_2
VRPVAXG_PH1
VRPVAXG_LG1
OUT
VRPVCORE_LG1
OUT
VRPVCORE_PH1
OUT
VRPVCORE_HG1
OUT
VRPVCORE_BOOT1
OUT
CORE_PG
C6743
CSC0402_DY
R6737
619_1%_2
21
C6742
21
C6741
21
21
CSC0402_DY0.01UF_50V_2
16
VSUMNG
R6743
21
C6733
2 1
IN
0.1UF_16V_2
RSC_0402_DY
D
R6735
10K_5%_NTC
16
VSUMPG
2 1
21
R6734
IN
21
R6732
27.4K_1%_2
21
R6733
470K_5%_NTC
21
R6632
27.4K_1%_2
21
R6633
470K_5%_NTC
2.61K_1%_2
R6736
R6731
3.83K_1%_2
R6631
3.83K_1%_2
2 1
21
21
B
11K_1%_2
VR_SVID_CLK
VR_SVID_ALERT#
VR_SVID_DATA
CPU_PROCHOT#
C6734
2 1
EN_CPU
26
26
P5V0A
C6735
2 1
0.01UF_50V_2
29
30
32
U6600
FBG
1
NTCG
2
IN
OUT
OUT
OUT
OUT
23
VR_ON
3
SCLK
4
ALERT#
5
SDA
6
VR_HOT#
7
NTC
8
ISEN2
PAD
33
RTNG
ISUMPG
ISUMNG
ISUMP
ISEN1
9
10 31
COMPG
ISUMN
FB
RTN
13 28
12
11
16
20
VRPVAXG_BOOT1
AXG_PG
VRPVAXG_HG1
OUT
OUT
OUT
25
27
BOOTG
PHASEG
UGATEG
PGOODG
LGATEG
VCCP
VDD
PWM2
LGATE1
PHASE1
UGATE1
PGOOD
COMP
BOOT1
INTERSIL_ISL95833HRTZ_T_TQFN_32P
142616
15
24
23
22
21
20
19
18
17
21
2 1
R6741
499_1%_2
18
27
2 1
R6740
2K_1%_2
2 1
267K_1%_2
R6739
330PF_50V_2
150PF_50V_2
C6737
47PF_50V_2
C6739
2 1
C6738
21
21
R6738
21
154K_1%_2
D
P5V0A
P1V05S_VCCP
21
R6626
SHORT_0402_5
21
R6625
C6626
2 1
1UF_6.3V_2
SHORT_0402_5
C6625
2 1
1UF_6.3V_2
R6697
130_1%_2
R6696
54.9_1%_2
21
21
OUT
OUT
26
VR_SVID_DATA
26
VR_SVID_CLK
CC
B
C6640
2 1
470PF_50V_2 33PF_50V_2
C6641
C6642
R6642
1.96K_1%_2
21
21
16
16
8
VSUMP
VSUMN
IN
R6634
2 1
2.61K_1%_2
R6636
2 1
R6635
2 1
IN
10K_5%_NTC
C6634
11K_1%_2
2 1
0.1UF_16V_2 0.1UF_16V_2
C6633
2 1
0.1UF_16V_2
7 6
R6643
649_1%_2
C6635
2 1
2200PF_50V_2
R6637
21
649_1%_2
21
C6643
2200PF_50V_2
21
CSC0402_DY
0.01UF_50V_2
5 4
R6641
499_1%_2
21
IN
IN
21
VCCSENSE
VSSSENSE
CHANGE by
26
2 1
R6639
267K_1%_2
2 1
R6640
2K_1%_2
XXX
C6637
21
C6638
150PF_50V_2
C6639
330PF_50V_2
21
21
DATE
R6638
42.2K_1%_2
21-OCT-2002
23
21
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
DOC.NUMBER
CODE
SIZE
A3
CS
1310xxxxx-0-0
SHEET
AA
REV
of
X01
8015
1
VRPVCORE_BOOT1
D
VRPVCORE_HG1
VRPVCORE_PH1
VRPVCORE_LG1
8 7
IN
C6621
0.22UF_25V_3
PAD6610
21
POWERPAD_2_0610
65
16
VBATR_CPU
R6621
2.2_5%_3
IN
IN
IN
21
IN
PVBAT
FDMS7692
FDMS0300S
6 5
12
2 1
678
Q6610
D
NMOS_4D3S
G
G
3
678
3
C6610
2 1
S
214 5
Q6611
D
R7661
RSC_0603_DY
2 1
S
C7661
214 5
CSC0402_DY
2 1
C6611
2 1
0.1UF_25V_3
10UF_25V_5
PVCORE
L6610
21
43
470UF_2V
C6600
1
1
C6601
+
+
470UF_2V
3
2
3
2
VRPVAXG_BOOT1
15
15
VSUMP
VSUMN
OUT
OUT
R6611
3.65K_1%_2
R6612
1_5%_2
ETQP4LR36AFM
21
21
VRPVAXG_HG1
VRPVAXG_PH1
VRPVAXG_LG1
4
65
16
VBATR_CPU
POWERPAD_2_0610
VBATR_GPU
R6721
2.2_5%_3
IN
0.22UF_25V_3
21
IN
IN
IN
3 2 1
IN
12
PAD6710
IN
C6721
2 1
678
FDMS7692
21
FDMS0306AS
Q6710
D
NMOS_4D3S
G
3
214 5
+
C6710
15UF_25V
2 1
S
678
Q6711
D
R7671
4.7_5%_30.00 15UF_50V_2
G
2 1
S
3
2145
C7671
2 1
15
VSUMPG
VSUMNG
OUT
OUT
R6711
3.65K_1%_2
R6712
1_5%_2
ETQP4LR36AFM
21
21
L6710
21
43
470UF_2V
C6700
PVAXG
1
+
2
D
CC
3
B
B
AA
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
A3
CS
1310xxxxx-0-0
SHEET
of
1
DOC.NUMBER
CODE
REV
X01
8016
8 7
6 5
4
3 2 1
D
PVBAT_IN
65
PVADPTR_IN
IN
B
VADPBL
IN
PVPACK PVBATB
IN
TP6039
1
TP30
TP6040
1
TP30
TP6041
1
TP30
TP6007
1
TP30
1
TP30
1
TP30
PVADPTR
1
TP30
1
TP30
1
TP30TP30
TP6002
TP6003
TP6004
TP6005
TP6006
TP6001
1
TP6008
1
TP30
TP6009
1
TP30
TP6010
1
TP30
1
TP30
1
TP30
1
TP30
PVBAT PVBATA
TP6011
1
TP30
TP6012
1
TP30
TP6013
1
TP30
1
TP30
1
TP30
1
TP30
TP6014
TP6015
TP6016
P5V0A_CHG
TP6017
TP6018
P3V3ALW PVSA
TP6019
P5V0AL
TP6020
1
TP30
TP6021
1
1
TP30
TP30
P3V3AL
TP6022
P5V0A
TP6023
1
TP30
P1V05M
TP6025
1
TP30
1
TP40
TP6026
1
P1V05S_VCCP
1
P1V8S
TP7351
1
TP30
1
P1V5
TP6024
1
TP30
TP6027
1
TP30
1
TP6028
TP30
TP6029
TP30
TP6030
TP30
TP6031
TP30
PVAXG
1
TP30
PVCORE
1
TP30
P0V75S
1
TP30
P0V75M_VREF
1
TP30
TP6032
TP6033
TP6037
TP6038
D
CC
B
AA
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
A3
CS
1310xxxxx-0-0
SHEET
of
1
DOC.NUMBER
CODE
REV
X01
8017
8 7
21
D7680
1SS355VMTE_17
35
55
57
35
D
45
48
45485742
10
21
23
SLP_S3#_3R
9
SLP_S4#_3R
KBC_GPIO22
21
19
PM_SLP_A#
20
48
35
IN
IN
IN
SHORT_0402_5
1819
20
21
27
R7680
1K_5%_2
R7683
21
21
A2A1
D7681
21
20K_5%_2
BAT54C
3
C
21
R7681
C7683
2 1
6 5
21
C7680
2 1
0.1UF_16V_2
R7682
21
21
SHORT_0402_5
R7690
20K_1%_2
OUT
EN_P1V05
11
OUTIN
OUT
OUT
EN_0V75
SLP_S4#_KBC
EN_1V5
4
10
3 2 1
P3V3S
R7687
1K_5%_2
R7688
R7689
21
21
CORE_PG
21
1815
15
D
15
18
CORE_PG
4855
10
35
VGATE
33
2348820
PWR_GOOD_3 EN_CPU
IN
IN OUT
SHORT_0402_5
IN OUT
SHORT_0402_5
CC
R6125
IN OUT
5V_PG
SHORT_0402_5
21
RSMRST#
483533
0.1UF_16V_2_DY
R7684
R7685
0_5%_2
21
C7684
2 1
21
454855
SLP_S3#_3R
21
2742 35
20
1819
SHORT_0402_5
9
B
45 42 35485557
SLP_S3#_3R
202127
19 18
IN
9
OUTIN
EN_VCCP
CSC0402_DYCSC0402_DY
OUT
C7685
2 1
CSC0402_DY
EN_1V8
12
P3V3ALW
P3V3AL
C7200
0.1UF_16V_2
2 1
R7200
100K_5%_2
21
EN_P3V3A
13
IN
PAD7200
1 2
POWERPAD1X1M_DY
Q7200
4
S
3 6
G
PMOS_4D1S
TPC6111
P3V3A
21
B
TP7201
1
1
D
2
TP30
5
C7201
10UF_6.3V_3
2 1
57
55 48 45
42
8
SLP_S3#_3R
27351920
21
R7686
IN
SHORT_0402_5
9
18
21
OUT
EN_PVCCSA
14
AA
C7686
2 1
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
POWER SEQUENCE
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
SIZE
DOC.NUMBER
CODE
1310xxxxx-0-0
CS
A3
SHEET
of
1
REV
X01
8018
8 7
6 5
4
3 2 1
REFERENCE NUMER : 7000~7350
P3V3S P5V0A_CHG P1V5S
S
G
1
P5V0A
G
MAX 3.3A
TP7051
1
4
TP30 TP30 TP30
36
19
CSC0402_DY
R7050
C7050
C7060
47_5%_2
2 1
10UF_6.3V_3
SSM3K7002FU
2 1
0.1UF_16V_2
Q7051
R7004
R7005
2 1
3
DS
G
2
2 1
100K_5%_2
2 1
200K_5%_2
3
DS
SSM3K7002FU
2
D
B
35
SLP_S3#_3R
9
20
21
27
42
45
48
55
57
Q7050
1
D
2
5
NMOS_4D1S
AO6402AL
19
C7102
2 1
Q7002
SLP_S3#_3R
IN
19
18
1
OUT
1
B
Q7000
MMBT3906
Q7100
1
D
2
5
AO6402AL
SLP_S3_5R
23
Q7001
C E
MMBT3906
23
B
CE
NMOS_4D1S
1
Q2971 WHETHER CAN CHANGE TO
6015B0017101 PMV65XP OR NOT
P0V75S
P5V0SP3V3ALW
MAX 2.8A MAX 7.5A
1
4
S
36
G
19
TP6035
P1V5
Q7151
8
D
7
6
NMOS_4D3S
FDMS7692
INININ
SPWONSPWONSPWON
1
1
S
2
3
45
G
TP6036
Q7152
1
R7151
2 1
3
DS
G
SSM3K7002FU_DY
22_5%_2_DY
2
C7103
2 1
R7100
CSC0402_DY
C7100
100_5%_5
2 1
2 1
10UF_6.3V_3
3
Q7101
DS
1
G
SSM3K7002FU
2
23
SPWON
100K_5%_2_DY
19
C7000
2 1
0.1UF_25V_2
2
D7000
BAV99W_7_F
3
1
OUT
R7001
R7002
2 1
2 1
124K_1%_2
2 1
R7003
61.9K_1%_2
C7150
2 1
CSC0402_DY
R7150
C7151
220_5%_5
2 1
2 1
10UF_6.3V_3
3
Q7150
DS
1
G
SSM3K7002FU
2
P1V05M
21
R2973
3
Q2974
DS
1
G
2
21
35 48
20
PM_SLP_A#
18
IN
SSM3K7002FU
100K_5%_2
Q2973
1
R2974
G
P5V0A
2 1
3
DS
2
47_5%_2
SSM3K7002FU
1
21
Q7153
G
SLP_LAN#
35
19
48
C2975
P1V8S
R7152
2 1
3
DS
SSM3K7002FU
2
10UF_6.3V_3
2 1
22_5%_2
SLP_LAN#
IN
SSM3K7002FU
C2976
10UF_6.3V_3
2 1
Q2970
1
P3V3ALW
P3V3ALW
G
4
S
3 6
G
PMOS_4D1S
TPC6111
C2970
2 1
CSC0402_DY
R2971
47K_5%_2
2 1
3
DS
2
Q2971
1
D
2
5
R2970
2 1
330K_5%_2
1
SSM3K7002FU
Q2972
1
G
TP2971
TP30
P3V3M
R2972
2 1
3
DS
2
D
C2971
47_5%_2
2 1
10UF_6.3V_3
CC
B
AA
VRP5V0A_PH
IN
R7000
10_5%_2
C7001
21
0.01UF_50V_2
21
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
POWER(SLEEP)
REFERENCE NUMER : 2950~2999
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
SIZE
A3
CODE
CS
DOC.NUMBER
1310xxxxx-0-0
SHEET
of
1
REV
X01
8019
8 7
6 5
4
3 2 1
PVADPTR
LIMIT_SIGNAL_100R
REFERENCE NUMER : 7400~7450
P5V0S
R7405
21
SLP_S3#_3R
IN
IN
IN
76.8K_1%_2
R7416
11.5K_1%_2
R7415
3.3K_5%_2
21
R7417
3.3K_5%_2
R7414
3.3K_5%_2
21
R7411
22.6K_1%_2
49.9K_1%_2
R7402
RSC_0402_DY
R7400
3.3K_5%_2
R7425
3.3K_5%_2
R7413
R7410
89
7
2VREF
20
21
21
21
D7414
2VREF
IN
34.8K_1%_2
C7402
2 1
21
1000PF_50V_2
R7407
21
1M_5%_2
P3V3S
P5V0A
5
6
R7406
P5V0A
3
2
V+
U7400
+IN
+
-
-IN
V-
4 8
V+
+IN
+
-
-IN
V-
4 8
7
OUT
TI_LMV393IDGKR_SOP_8P
21
1M_5%_2
C7400
0.1UF_16V_2
U7400
1
OUT
TI_LMV393IDGKR_SOP_8P
R7418
2 1
21
C7403
2 1
RSC_0402_DY
2 1
R7409
0_5%_2
3300PF_50V_2
R7408
0_5%_2
C7401
3300PF_50V_2
21
R7412
2 1
49.9K_1%_2
21
3
BAT54A
21
21
21
21
21
R7401
27.4K_1%_2
R7404
2 1
3.3K_5%_2
PWR_GOOD_3
21
48
VCCSA_PG
14
D
18
9
SLP_S3#_3R
57
45
42
55 27
19
20
21
20
M_PWROK
3335
IN
35
IN
M_PWROK
IN
P1V5S
P3V3S
15
AXG_PG
12
VCCP_PG
13
P1V8S_PG
P0V75S
R6902
2 1
R6903
2 1
130K_1%_2 220K_5%_2
OUT
7
OUT
VBIAS
PWR_GOOD_3
20
7
18
4823
IN
R6910
8.06K_1%_2
2 1
LES_LMBT3906WT1G_SOT323_3P
R6909
2 1
R6904
2 1
45.3K_1%_2 8.66K_1%_2
P3V3AL
1
BASE
Q6900
2 3
EMITTER COLLECTOR
OUT
ADP_A_ID
48
D
CC
B
20
89 7
2VREF
19
18
20
35
48
21
IN
PM_SLP_A#
2VREF
IN
REFERENCE NUMER : 2950~2999
8
R2950
41.2K_1%_3
PM_SLP_A#
21
C2950
2 1
P3V3M
R2951
2 1
1000PF_50V_2
R2959
46.4K_1%_2
71.5K_1%_2
P1V05M
R2958
14.7K_1%_2
R2957
21
3.3K_5%_2
D2951
7 6
B
AMBIENT TEMP SENSE
21
4
R2956
1M_5%_2
C2951
P3V3A
21
21
R2954
3.3K_5%_2
2 1
M_PWROK
R2961
1K_1%_2
2 1
OUT
M_PWROK
332035
R2953
1M_5%_2
P5V0A
52
U2950
21
21
3
BAT54A
R2955
21
0_5%_2
R2960
C2952
2 1
2 1
86.6K_1%_2
3300PF_50V_2
21
1
3
+
+
OUT
-
-
AZV331KTR_E1
0.068UF_10V_2
5 4
P5V0S
0.1UF_16V_2
CHANGE by
R2962
150_1%_2
C4411
21
21
XXX
U2951
5 1
VCC SET
2
GND
34
OTHYST
GMT_G708T1U_SOT23_5P
75 DEG. => 36 KOHM
110 DEG. => 10 KOHM
DATE
36K_1%_3
21-OCT-2002
23
R2963
21
IN
EN_5V_3V
8
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
POWER(SEQUENCE)
CODE
SIZE
1310xxxxx-0-0
CS
A3
SHEET
9
DOC.NUMBER
AA
REV
of
X01
8020
1
8 7
6 5
4
3 2 1
D
D
CC
P3V3A
CN4921
ENTERY_3703K_Q08N_11R_8P_DY
1
SLP_S3#_3R
SLP_S4#_3R
SLP_S5#_3R
PM_SLP_A#
55
61
49
ON_OFF#
48 35
19
SLP_LAN#
B
IN
IN
IN
IN
IN
IN
ME DEBUG
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
G1
G1
G2
G2
B
AA
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
XDP CONN
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
1310xxxxx-0-0
CS
A3
SHEET
of
1
DOC.NUMBER
CODE
REV
X01
8021
8 7
6 5
4
3 2 1
REFERENCE NUMBER:4400~4349
P3V3S
D
48
PWM_3S_FAN#
22
THERM#
P5V0S
20 MILS
U4300
5
+
1
IN
2
-
3
TC7SET00F
4
R4300
22_5%_2
TACH_FAN_IN_1126
21
48
C4300
2 1
R4301
0_5%_2
2 1
OUTIN
CN4300
1
1
2
3
4
ACES_50271_0040N_001_4P
G
2
G
3
4
G1
G2
0.1UF_16V_2_DY
D
CC
REFERENCE NUMBER:4450~4499
THERM SENSOR
P3V3S
B
H_THERMDA
H_THERMDC
OUT
THERM#
22
1
B
C E
Q4450
MMBT3904
2200PF_50V_2
C4451
23
R4453
2 1
21
2.2K_5%_2
SMSC_EMC1412_1_ACZL_TR_MSOP_8P
C4450
2 1
0.1UF_16V_2
U4450
1
2
3
SMCLK
VDD
SMDATA
DP
ALERT#
DN
GNDTHERM#/ADDR
R4452
0_5%_2
2 1
8
7
6
54
OUT
BI
BI
THERM_CLK
THERM_DATA
THERM_SCI#
47
34
47
34
38
B
AA
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
FAN & THERMAL
REFERENCE NUMBER:4411~4449
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
SIZE
A3
CODE
CS
DOC.NUMBER
1310xxxxx-0-0
SHEET
22
of
1
REV
X01
80
8 7
6 5
P1V8S
4
3 2 1
U4500
R4535
1K_5%_2_DY
2 1
P1V05S_VCCP
SNB_IVB#
38
OUT
D
CLOSE U6600
R4531
62_5%_2
CPU_PROCHOT#
1523
IN
P3V3S
200_1%_2
35
PM_DRAM_PWRGD
IN
NXP_74LVC2G07GW_SC88A_6P
B
18
48
20
PWR_GOOD_3
IN
2 1
C4697
2 1
47pF_50V_2
P3V3A
R4529
2 1
U4502
1Y1A
VCCGND
2Y2A
0.1UF_16V_2
61
52
43
C4605
2 1
P1V5S
C4523
2 1
1UF_6.3V_2
R4528
39_5%_2_DY
2 1
3
Q4505
DS
1
G
SSM3K7002FU_DY
50
2
37
BUF_PLT_RST#
48
53
54
60
38
H_PWRGD
R4527
200_1%_2
2 1
IN
NXP_74LVC1G07GW_TSSOP_5P
38
IN
SLP_S3_5R
IN
P3V3S
C4688
2 1
1
5
0.1UF_16V_2
U4607
NC
+
48
KBC_PROCHOT
IN
R4607
100K_5%_2
2
2 1
-
TC7SZ05F
3
4
R4539
R4536
21
1K_5%_2
48
H_PECI
38
PM_THRMTRIP#
R4570
21
0_5%_2
19
U4501
2
1
1848
IN
CPU_PROCHOT#
2.2K_5%_2
2 1
R4540
56_5%_2
P3V3S
5
+
2
4
NC
-
3
34
H_SNB_IVB#
OUT
21
H_PROCHOT#_R
OUT
35
H_PM_SYNC
R4530
130_1%_2
P1V05S_VCCP
R4567
2 1
4
PCH_DDR_RST
KBC_GPIO22
15
23
TP1
TP24
TP4503
TP24
21
75_5%_2
R4555
43_5%_2
F49
PROC_SELECT#
1
C57
PROC_DETECT#
1
C49
CATERR#
A48
PECI
C45
PROCHOT#
D45
THERMTRIP#
TP2438
TP30
C48
PM_SYNC
1
BI
TP2439
TP30
B46
UNCOREPWRGOOD
1
TP2440
TP30
BE45
SM_DRAMPWROK
1
TP2441
TP30
D44
RESET#
1
ITL_IVY_BRIDGE_BGA1023_2C_GT1_1023P
21
R4571
IN
IN
R4561
21
20K_1%_2
1
SSM3K7002FU
20K_5%_2
DDR3_DRAMRST#_CPU
2 1
Q4595
G
3
DS
DDR_RST_EN
2
23
CLOCKS
JTAG & BPM MISCDDR3
PWR MANAGEMENTTHERMALMISC
P3V3AL
R4655
2 1
20K_1%_2_DY
Q4522
1
BSS138
IN
DPLL_REF_CLK
DPLL_REF_CLK#
BCLK_ITP#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
P1V5
R4563
1K_1%_2
2 1
3
DS
G
2
R4562
0_5%_2_DY
BCLK
BCLK#
BCLK_ITP
PRDY#
PREQ#
TCK
TMS
TRST#
TDI
TDO
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
XDP_DBRESET#
H_TDO
H_TMS
H_TDI
H_TRST#
H_TCK
R4564
1K_5%_2
21
J3
H2
AG3
AG1
N59
N58
IN
CLK_DMI_PCH_DP
IN
CLK_DMI_PCH_DN
1K_5%_2
1K_5%_2
21
21
R4500
R4501
XDP_BCLK_ITP_DP
XDP_BCLK_ITP_DN
34
34
TP4520
TP4521
P1V05S_VCCP
1
1
TP24
TP24
FOR IVB 2C FINAL SYMBOL MOVE TO OTHER BLOCK
AT30
BF44
BE43
BG43
TP2430
TP30
N53
N55
L56
L55
J58
M60
L59
K58
G58
E55
E59
G55
G59
H60
J59
J61
21
OUT
DDR3_DRAMRST#_CPU
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
TP2432
TP30
TP2431
TP30
1
1
1
TP2437
TP30
1
H_BPM0_XDP#
H_BPM1_XDP#
H_BPM2_XDP#
H_BPM3_XDP#
H_BPM4_XDP#
H_BPM5_XDP#
H_BPM6_XDP#
H_BPM7_XDP#
35
IN
IN
IN
IN
IN
IN
OUT
DDR3_DRAMRST#
R4551
R4552
R4553
R4554
R4556
R4557
TP2433
TP30
R4558
R4559
R4560
TP2434
TP30
TP2435
TP30
1
1
1
1
TP30
1
TP30
1
TP30
1
TP30
1
TP30
1
TP30
1
TP30
1
TP30
TP2436
TP30
21
1K_5%_2
51_5%_2
21
51_5%_2
21
51_5%_2
21
51_5%_2
21
51_5%_2
21
29
31
30
1
23
21
140_1%_2
21
25.5_1%_2
21
200_1%_2
H_PRDY#
H_PREQ#
H_TCK
H_TMS
H_TRST#
H_TDI
H_TDO
XDP_DBRESET#
TP2450
TP2451
TP2452
TP2453
TP2454
TP2455
TP2456
TP2457
P3V3S
P1V05S_VCCP
D
CC
B
AA
C4690
2 1
470PF_50V_2
8
7 6
5 4
CHANGE by
XXX
R4550
2 1
4.99K_1%_2
DATE
21-OCT-2002
23
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CPU-1/6
DOC.NUMBER
CODE
SIZE
1310xxxxx-0-0
CS
A3
SHEET
of
8023
1
REV
X01X01
8 7
6 5
4
3 2 1
U4500
35
IN
35
IN
35
IN
35
D
B
P1V05S_VCCP
R4502
24.9_1%_2
IN
35
IN
35
IN
35
IN
35
IN
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
OUT
35
IN
35
IN
35
IN
35
IN
35
IN
21
DMI_TX0_DN
DMI_TX1_DN
DMI_TX2_DN
DMI_TX3_DN
DMI_TX0_DP
DMI_TX1_DP
DMI_TX2_DP
DMI_TX3_DP
DMI_RX0_DN
DMI_RX1_DN
DMI_RX2_DN
DMI_RX3_DN
DMI_RX0_DP
DMI_RX1_DP
DMI_RX2_DP
DMI_RX3_DP
FDI_TX0_DN
FDI_TX1_DN
FDI_TX2_DN
FDI_TX3_DN
FDI_TX4_DN
FDI_TX5_DN
FDI_TX6_DN
FDI_TX7_DN
FDI_TX0_DP
FDI_TX1_DP
FDI_TX2_DP
FDI_TX3_DP
FDI_TX4_DP
FDI_TX5_DP
FDI_TX6_DP
FDI_TX7_DP
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
CPU_EDP_COMPIO
M2
DMI_RX#[0]
P6
DMI_RX#[1]
P1
DMI_RX#[2]
P10
DMI_RX#[3]
N3
DMI_RX[0]
P7
DMI_RX[1]
P3
DMI_RX[2]
P11
DMI_RX[3]
K1
DMI_TX#[0]
M8
DMI_TX#[1]
N4
DMI_TX#[2]
R2
DMI_TX#[3]
K3
DMI_TX[0]
M7
DMI_TX[1]
P4
DMI_TX[2]
T3
DMI_TX[3]
U7
FDI0_TX#[0]
W11
FDI0_TX#[1]
W1
FDI0_TX#[2]
AA6
FDI0_TX#[3]
W6
FDI1_TX#[0]
V4
FDI1_TX#[1]
Y2
FDI1_TX#[2]
AC9
FDI1_TX#[3]
U6
FDI0_TX[0]
W10
FDI0_TX[1]
W3
FDI0_TX[2]
AA7
FDI0_TX[3]
W7
FDI1_TX[0]
T4
FDI1_TX[1]
AA3
FDI1_TX[2]
AC8
FDI1_TX[3]
AA11
FDI0_FSYNC
AC12
FDI1_FSYNC
U11
FDI_INT
AA10
FDI0_LSYNC
AG8
FDI1_LSYNC
AF3
eDP_COMPIO
AD2
eDP_ICOMPO
AG11
eDP_HPD
AG4
eDP_AUX#
AF4
eDP_AUX
AC3
eDP_TX#[0]
AC4
eDP_TX#[1]
AE11
eDP_TX#[2]
AE7
eDP_TX#[3]
AC1
eDP_TX[0]
AA4
eDP_TX[1]
AE10
eDP_TX[2]
AE6
eDP_TX[3]
ITL_IVY_BRIDGE_BGA1023_2C_GT1_1023P
Intel(R) FDIDMI
DP
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PCI EXPRESS -- GRAPHICS
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
G3
G1
G4
H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7
K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6
G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4
F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4
CPU_PEG_ICOMPI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PEG_TX0_DN
PEG_TX1_DN
PEG_TX2_DN
PEG_TX3_DN
PEG_TX4_DN
PEG_TX5_DN
PEG_TX6_DN
PEG_TX7_DN
PEG_TX0_DP
PEG_TX1_DP
PEG_TX2_DP
PEG_TX3_DP
PEG_TX4_DP
PEG_TX5_DP
PEG_TX6_DP
PEG_TX7_DP
24.9_1%_2
72
PEG_RX0_C_DN
72
PEG_RX1_C_DN
72
PEG_RX2_C_DN
72
PEG_RX3_C_DN
72
PEG_RX4_C_DN
72
PEG_RX5_C_DN
72
PEG_RX6_C_DN
72
PEG_RX7_C_DN
72
PEG_RX0_C_DP
72
PEG_RX1_C_DP
72
PEG_RX2_C_DP
72
PEG_RX3_C_DP
72
PEG_RX4_C_DP
72
PEG_RX5_C_DP
72
PEG_RX6_C_DP
72
PEG_RX7_C_DP
C4837
C4838
C4839
C4840
C4841
C4842
C4843
C4844
C4853
C4854
C4855
C4856
C4857
C4858
C4859
C4860
R4503
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
P1V05S_VCCP
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
72
PEG_TX0_C_DN
72
PEG_TX1_C_DN
72
PEG_TX2_C_DN
72
PEG_TX3_C_DN
72
PEG_TX4_C_DN
72
PEG_TX5_C_DN
72
PEG_TX6_C_DN
72
PEG_TX7_C_DN
72
PEG_TX0_C_DP
72
PEG_TX1_C_DP
72
PEG_TX2_C_DP
72
PEG_TX3_C_DP
72
PEG_TX4_C_DP
72
PEG_TX5_C_DP
72
PEG_TX6_C_DP
72
PEG_TX7_C_DP
D
CC
B
AA
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CPU-2/6
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
1310xxxxx-0-0
CS
A3
SHEET
of
24
1
DOC.NUMBER
CODE
REV
X01X01
80
8 7
6 5
4
3 2 1
U4500
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
M_B_DQ<0>
M_B_DQ<1>
M_B_DQ<2>
M_B_DQ<3>
M_B_DQ<4>
M_B_DQ<5>
M_B_DQ<6>
M_B_DQ<7>
M_B_DQ<8>
M_B_DQ<9>
M_B_DQ<10>
M_B_DQ<11>
M_B_DQ<12>
M_B_DQ<13>
M_B_DQ<14>
M_B_DQ<15>
M_B_DQ<16>
M_B_DQ<17>
M_B_DQ<18>
M_B_DQ<19>
M_B_DQ<20>
M_B_DQ<21>
M_B_DQ<22>
M_B_DQ<23>
M_B_DQ<24>
M_B_DQ<25>
M_B_DQ<26>
M_B_DQ<27>
M_B_DQ<28>
M_B_DQ<29>
M_B_DQ<30>
M_B_DQ<31>
M_B_DQ<32>
M_B_DQ<33>
M_B_DQ<34>
M_B_DQ<35>
M_B_DQ<36>
M_B_DQ<37>
M_B_DQ<38>
M_B_DQ<39>
M_B_DQ<40>
M_B_DQ<41>
M_B_DQ<42>
M_B_DQ<43>
M_B_DQ<44>
M_B_DQ<45>
M_B_DQ<46>
M_B_DQ<47>
M_B_DQ<48>
M_B_DQ<49>
M_B_DQ<50>
M_B_DQ<51>
M_B_DQ<52>
M_B_DQ<53>
M_B_DQ<54>
M_B_DQ<55>
M_B_DQ<56>
M_B_DQ<57>
M_B_DQ<58>
M_B_DQ<59>
M_B_DQ<60>
M_B_DQ<61>
M_B_DQ<62>
M_B_DQ<63>
M_B_BS0
M_B_BS1
M_B_BS2
M_B_CAS#
M_B_RAS#
M_B_WE#
30
30
30
U4500
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
M_A_DQ<0>
M_A_DQ<1>
M_A_DQ<2>
M_A_DQ<3>
M_A_DQ<4>
M_A_DQ<5>
M_A_DQ<6>
M_A_DQ<7>
M_A_DQ<8>
M_A_DQ<9>
M_A_DQ<10>
M_A_DQ<11>
M_A_DQ<12>
M_A_DQ<13>
M_A_DQ<14>
M_A_DQ<15>
M_A_DQ<16>
M_A_DQ<17>
M_A_DQ<18>
M_A_DQ<19>
M_A_DQ<20>
M_A_DQ<21>
M_A_DQ<22>
M_A_DQ<23>
M_A_DQ<24>
M_A_DQ<25>
M_A_DQ<26>
M_A_DQ<27>
M_A_DQ<28>
M_A_DQ<29>
M_A_DQ<30>
M_A_DQ<31>
M_A_DQ<32>
M_A_DQ<33>
M_A_DQ<34>
M_A_DQ<35>
M_A_DQ<36>
M_A_DQ<37>
M_A_DQ<38>
M_A_DQ<39>
M_A_DQ<40>
M_A_DQ<41>
M_A_DQ<42>
M_A_DQ<43>
M_A_DQ<44>
M_A_DQ<45>
M_A_DQ<46>
M_A_DQ<47>
M_A_DQ<48>
M_A_DQ<49>
M_A_DQ<50>
M_A_DQ<51>
M_A_DQ<52>
M_A_DQ<53>
M_A_DQ<54>
M_A_DQ<55>
M_A_DQ<56>
M_A_DQ<57>
M_A_DQ<58>
M_A_DQ<59>
M_A_DQ<60>
M_A_DQ<61>
M_A_DQ<62>
M_A_DQ<63>
M_A_BS0
M_A_BS1
M_A_BS2
M_A_CAS#
M_A_RAS#
M_A_WE#
29
29
D
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
B
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
AG6
AP11
AJ10
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56
BD37
BF36
BA28
BE39
BD39
AT41
SA_DQ[0]
AJ6
SA_DQ[1]
SA_DQ[2]
AL6
SA_DQ[3]
SA_DQ[4]
AJ8
SA_DQ[5]
AL8
SA_DQ[6]
AL7
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
DDR SYSTEM MEMORY A
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AU36
M_CLK_DDR0_DP
AV36
M_CLK_DDR0_DN
M_CKE0
AY26
AT40
M_CLK_DDR1_DP
AU40
M_CLK_DDR1_DN
M_CKE1
BB26
M_CS#0
BB40
M_CS#1
BC41
M_ODT0
AY40
M_ODT1
BA41
AL11
M_A_DQS0_DN
AR8
M_A_DQS1_DN
AV11
M_A_DQS2_DN
AT17
M_A_DQS3_DN
AV45
M_A_DQS4_DN
AY51
M_A_DQS5_DN
AT55
M_A_DQS6_DN
AK55
M_A_DQS7_DN
AJ11
M_A_DQS0_DP
AR10
M_A_DQS1_DP
AY11
M_A_DQS2_DP
AU17
M_A_DQS3_DP
AW45
M_A_DQS4_DP
AV51
M_A_DQS5_DP
AT56
M_A_DQS6_DP
AK54
M_A_DQS7_DP
M_A_A<0>
BG35
M_A_A<1>
BB34
M_A_A<2>
BE35
M_A_A<3>
BD35
M_A_A<4>
AT34
M_A_A<5>
AU34
M_A_A<6>
BB32
M_A_A<7>
AT32
M_A_A<8>
AY32
M_A_A<9>
AV32
M_A_A<10>
BE37
M_A_A<11>
BA30
M_A_A<12>
BC30
M_A_A<13>
AW41
M_A_A<14>
AY28
M_A_A<15>
AU26
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
30
30
30
30
30
29
30
29
30
29
30
30
30
30
30
30
29
30
29
30
29
30
30
30
30
30
30
29
30
29
30
30
30
30
30
30
29
30
29
31
31
31
31
31
31
29
31
29
31
29
31
29
31
29
31
29
31
29
31
29
31
31
31
31
31
31
31
29
31
29
31
29
31
29
31
29
31
29
31
29
31
29
31
31
31
31
31
29
31
32
30
29
31
32
30
29
31
32
30
29
29
29
29
31
32
30
29
31
32
30
29
31
32
30
29
29
29
29
29
29
29
AL4
SB_DQ[0]
AL1
SB_DQ[1]
AN3
SB_DQ[2]
AR4
SB_DQ[3]
AK4
SB_DQ[4]
AK3
SB_DQ[5]
AN4
SB_DQ[6]
AR1
SB_DQ[7]
AU4
SB_DQ[8]
AT2
SB_DQ[9]
AV4
SB_DQ[10]
BA4
SB_DQ[11]
AU3
SB_DQ[12]
AR3
SB_DQ[13]
AY2
SB_DQ[14]
BA3
SB_DQ[15]
BE9
SB_DQ[16]
BD9
SB_DQ[17]
BD13
SB_DQ[18]
BF12
SB_DQ[19]
BF8
SB_DQ[20]
BD10
SB_DQ[21]
BD14
SB_DQ[22]
BE13
SB_DQ[23]
BF16
SB_DQ[24]
BE17
SB_DQ[25]
BE18
SB_DQ[26]
BE21
SB_DQ[27]
BE14
SB_DQ[28]
BG14
SB_DQ[29]
BG18
SB_DQ[30]
BF19
SB_DQ[31]
BD50
SB_DQ[32]
BF48
SB_DQ[33]
BD53
SB_DQ[34]
BF52
SB_DQ[35]
BD49
SB_DQ[36]
BE49
SB_DQ[37]
BD54
SB_DQ[38]
BE53
SB_DQ[39]
BF56
SB_DQ[40]
BE57
SB_DQ[41]
BC59
SB_DQ[42]
AY60
SB_DQ[43]
BE54
SB_DQ[44]
BG54
SB_DQ[45]
BA58
AW59
AW58
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
AU58
SB_DQ[49]
AN61
SB_DQ[50]
AN59
SB_DQ[51]
AU59
SB_DQ[52]
AU61
SB_DQ[53]
AN58
SB_DQ[54]
AR58
SB_DQ[55]
AK58
SB_DQ[56]
AL58
SB_DQ[57]
AG58
SB_DQ[58]
AG59
SB_DQ[59]
AM60
SB_DQ[60]
AL59
SB_DQ[61]
AF61
SB_DQ[62]
AH60
SB_DQ[63]
BG39
SB_BS[0]
BD42
SB_BS[1]
AT22
SB_BS[2]
AV43
SB_CAS#
BF40
SB_RAS#
BD45
SB_WE#
ITL_IVY_BRIDGE_BGA1023_2C_GT1_1023P
BA34
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_ODT[0]
SB_ODT[1]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
DDR SYSTEM MEMORY B
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
M_CLK_DDR2_DP
AY34
M_CLK_DDR2_DN
M_CKE2
AR22
1
BA36
1
BB36
1
BF27
M_CS#2
BE41
1
BE47
M_ODT2
AT43
M_ODT3
BG47
1
AL3
AV3
M_B_DQS1_DN
BG11
BD17
BG51
BA59
AT60
AK59
AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61
M_B_A<0>
BF32
M_B_A<1>
BE33
M_B_A<2>
BD33
M_B_A<3>
AU30
M_B_A<4>
BD30
M_B_A<5>
AV30
M_B_A<6>
BG30
M_B_A<7>
BD29
M_B_A<8>
BE30
M_B_A<9>
BE28
M_B_A<10>
BD43
M_B_A<11>
AT28
M_B_A<12>
AV28
M_B_A<13>
BD46
M_B_A<14>
AT26
M_B_A<15>
AU22
TP24
TP24
TP24
TP24
TP4508
TP24
TP4509
M_B_DQS0_DN
M_B_DQS2_DN
M_B_DQS3_DN
M_B_DQS4_DN
M_B_DQS5_DN
M_B_DQS6_DN
M_B_DQS7_DN
M_B_DQS0_DP
M_B_DQS1_DP
M_B_DQS2_DP
M_B_DQS3_DP
M_B_DQS4_DP
M_B_DQS5_DP
M_B_DQS6_DP
M_B_DQS7_DP
TP4505
TP4506
TP4507
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
31
32
30
31
32
30
31
32
30
D
30
31
32
30
31
32
30
30
30
30
31
31
31
31
30
30
30
30
31
31
31
31
31
32
30
BI
31
32
30
BI
31
32
30
BI
31
32
30
BI
31
32
30
BI
31
32
30
BI
31
32
30
BI
31
32
30
BI
31
32
30
BI
31
32
30
BI
31
32
30
BI
31
32
30
BI
31
32
30
BI
31
32
30
BI
31
32
30
BI
31
32
30
BI
CC
B
AA
ITL_IVY_BRIDGE_BGA1023_2C_GT1_1023P
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CPU-3/6
SIZE
8
7 6
5 4
CHANGE by
XXX
DATE
21-OCT-2002
23
A3
CS
1310xxxxx-0-0
SHEET
of
1
DOC.NUMBER
CODE
REV
X01X01
8025
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