intersil X95820 DATA SHEET

®

www.BDTIC.com/Intersil

X95820

Dual Digital Controlled Potentiometers (XDCP™)

Data Sheet July 18, 2006

Low Noise/Low Power/I2C® Bus/256 Taps

The X95820 integrates two digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.

The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the

2

I

C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR), that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power up the device recalls the contents of the two
DCP’s IVR to the corresponding WRs.

The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.

Ordering Information

FN8212.2

Features

• Two potentiometers in one package

• 256 resistor taps-0.4% resolution

•I2C serial interface

- Three address pins, up to eight devices/bus

• Wiper resistance: 70Ω typical @ 3.3V

• Non-volatile storage of wiper position

• Standby current < 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ, 10kΩ total resistance

• High reliability

- Endurance: 150,000 data changes per bit per register

- Register data retention: 50 years @ T ≤ 75°C

• 14 Ld TSSOP

• Pb-free plus anneal available (RoHS compliant)

PART

PART NUMBER

X95820WV14I-2.7* X95820WV G 10kΩ 14 Ld TSSOP
X95820WV14IZ-2.7*

(Note)
X95820UV14I-2.7* X95820UV G 50kΩ 14 Ld TSSOP
X95820UV14IZ-2.7*

(Note)

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

MARKING

X95820WV Z G 10kΩ 14 Ld TSSOP

X95820UV Z G 50kΩ 14 Ld TSSOP

RESISTANCE

OPTION PACKAGE

(Pb-free)

(Pb-free)

Pinouts

V

CC

WP

RH0

RL0

RW0

A2

SCL

X95820

(14 LD TSSOP)

TOP VIEW

1

2

3

4

5

6

7

14

A1

A0

13

RH1

12

11

RL1

RW1

10

GND

9

SDA

8

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

www.BDTIC.com/Intersil

X95820

V

CC

PiN Descriptions

PIN SYMBOL DESCRIPTION

1V
2WP
3 RH0 “High” terminal of DCP0
4 RL0 “Low” terminal of DCP0
5 RW0 “Wiper” terminal of DCP0
6 A2 Device address for the I
7SCLI
8 SDA Serial data I/O for the I

9 GND Ground
10 RW1 “Wiper” terminal of DCP1
11 RL1 “Low” terminal of DCP1
12 RH1 “High” terminal of DCP1
13 A0 Device address for the I
14 A1 Device address for the I

SDA

SCL

A2

A1

A0

CC

I2C

INTERFACE

POWER-UP,

INTERFACE,
CONTROL AND
STATUS LOGIC

NON-VOLATILE

REGISTERS

WP

WR1

WR0

GND

R

H1

R

W1

R

L1

R

H0

R

W0

R

L0

Power supply pin
Hardware write protection pin. Active low. Prevents any “Write” operation of the I2C interface.

2

C interface

2

C interface clock

2

C interface

2

C interface

2

C interface

2

FN8212.2

July 18, 2006

X95820

www.BDTIC.com/Intersil

Absolute Maximum Ratings Recommended Operating Conditions

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at Any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . . .-0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V

CC

Voltage at Any DCP Pin with Respect to GND . . . . . . -0.3V to V

Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300°C

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

CC

+0.3

CC

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

R

W

C

H/CL/CW

I

LkgDCP

VOLTAGE DIVIDER MODE (0V @ RL

INL (Note 6) Integral Non-linearity -1 1 LSB

DNL (Note 5) Differential Non-linearity Monotonic over all tap positions -0.5 0.5 LSB

ZSerror
(Note 3)

FSerror
(Note 4)

V

MATCH

(Note 7)

(Note 8) Ratiometric Temperature Coefficient DCP Register set to 80 hex ±4 ppm/°C

TC

V

RESISTOR MODE (Measurements between RW
connected. i = 0 or 1)

RINL

(Note 12)

RDNL

(Note 11)

Roffset

(Note 10)

R

MATCH

(Note 13)

TC

(Note 14)

RH to RL Resistance W, U versions respectively 10, 50 kΩ
RH to RL Resistance Tolerance -20 +20 %
Wiper Resistance VCC = 3.3V @ 25°C

Wiper current = V
Potentiometer Capacitance (Note 15) 10/10/25 pF
Leakage on DCP Pins (Note 15) Voltage at pin from GND to V

; VCC @ RHi; measured at RWi, unloaded; i = 0 or 1)

i

Zero-scale Error U option 0 1 7 LSB

W option 0 0.5 2
Full-scale Error U option -7 -1 0 LSB

W option -2 -1 0
DCP to DCP Matching Any two DCPs at same tap position, same

voltage at all RH terminals, and same

voltage at all RL terminals

and RLi with RHi not connected, or between RWi and RHi with RLi not

i

Integral Non-linearity DCP register set between 20 hex and

FF hex. Monotonic over all tap positions
Differential Non-linearity -0.5 0.5 MI

Offset DCP Register set to 00 hex, U option 0 1 7 MI

DCP Register set to 00 hex, W option 0 0.5 2 MI

DCP to DCP Matching Any two DCPs at the same tap position with

the same terminal voltages.
Resistance Temperature Coefficient DCP register set between 20 hex and FF

R

hex

Temperature Range (Industrial). . . . . . . . . . . . . . . . . .-40°C to 85°C

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

Power Rating of Each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper Current of Each DCP. . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

TYP

(Note 1) MAX UNIT

70 200 Ω

CC/RTOTAL

CC

-2 2 LSB

-1 1 MI

-2 2 MI

0.1 1 µA

±45 ppm/°C

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 9)

(Note 9)

(Note 9)

(Note 9)

(Note 9)

3

FN8212.2

July 18, 2006

X95820

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

CC2

I

SB

I

LkgDig

t

DCP

(Note 15)

Vpor Power-on Recall Voltage Minimum V

VccRamp VCC Ramp Rate 0.2 V/ms

(Note 15) Power-up Delay VCC above Vpor, to DCP Initial V alue Register recall

t

D

EEPROM SPECS

SERIAL INTERFACE SPECS

V

IL

V

IH

Hysterisis

(Note 15)

V

OL

(Note 15)

Cpin

(Note 15)

f

SCL

t

IN

(Note 15)

t

AA

(Note 15)

t

BUF

(Note 15)

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

VCC Supply Current
(Volatile write/read)

VCC Supply Current
(nonvolatile write)

VCC Current (standby) V

Leakage Current, at Pins A0,
A1, A2, SDA, SCL, and WP
Pins

DCP Wiper Response Time SCL falling edge of last bit of DCP Data Byte to

EEPROM Endurance 150,000 Cycles
EEPROM Retention Temperature ≤ 75°C 50 Years

WP, A2, A1, A0, SDA, and
SCL input buffer LOW
voltage

WP, A2, A1, A0, SDA, and
SCL Input Buffer HIGH
Voltage

SDA and SCL input buffer
hysterisis

SDA Output Buffer LOW
Voltage, Sinking 4mA

, A2, A1, A0, SDA, and

WP
SCL Pin Capacitance

SCL Frequency 400 kHz
Pulse Width Suppression

Time at SDA and SCL Inputs
SCL Falling Edge to SDA

Output Data Valid
Time the Bus Must be Free

Before the Start of a New
Transmission

Clock LOW Time Measured at the 30% of VCC crossing. 1300 ns
Clock HIGH Time Measured at the 70% of VCC crossing. 600 ns
START Condition Setup

Time
STAR T Condition Hold Time From SDA falling edge crossing 30% of VCC to SCL

f

= 400kHz;SDA = Open; (for I2C,

SCL

Active, Read and Volatile Write States only)
f

= 400kHz; SDA = Open; (for I2C,

SCL

Active, Nonvolatile Write State only)

= +5.5V, I

CC

= +3.6V, I

V

CC

Voltage at pin from GND to V

wiper change

completed, and

Any pulse narrower than the max spec is
suppressed.

SCL falling edge crossing 30% of V
exits the 30% to 70% of V

SDA crossing 70% of V
to SDA crossing 70% of V
START condition.

SCL rising edge to SDA falling edge. Both crossing
70% of V

falling edge crossing 70% of V

2

C Interface in Standby State 5 µA

2

C Interface in Standby State 2 µA

CC

at which memory recall occurs 1.8 2.6 V

CC

I2C Interface in standby state

, until SDA

CC

window.

CC

during a STOP condition,

CC

during the following

CC

.

CC

.

CC

-10 10 µA

-0.3 0.3*Vcc V

0.7*Vcc Vcc+0.3 V

0.05*
Vcc

1300 ns

600 ns

600 ns

(Note 1) MAX UNITS

1mA

3mA

1µs

3ms

00.4V

10 pF

50 ns

900 ns

V

4

FN8212.2

July 18, 2006