• Three Digitally Controlled Potentiometers (DCPs)
—64 Tap - 10kΩ
—100 Tap - 10kΩ
—256 Tap - 100kΩ
—Nonvolatile
—Write Protect Function
• 2-Wire industry standard Serial Interface
• Dual Voltage Monitors
—Programmable Threshold Voltages
• Single Supply Operation
—2.7V to 5.5V
• Hot Pluggable
• 20 Pin package
—TSSOP
BLOCK DIAGRAM
8
WP
PROTECT LOGIC
DESCRIPTION
The X9522 combines three Digitally Controlled Potentiometers (DCPs), and two programmable voltage monitor
inputs with software and hardware indicators. All functions of the X9522 are accessed by an industry standard
2-Wire serial interface.
Two of the DCPs of the X9522 may be utilized to control
the bias and modulation currents of the laser diode in a
Fiber Optic module. The third DCP may be used to set
other various reference quantities, or as a coarse trim for
one of the other two DCPs.The programmable voltage
monitors may be used for monitoring various module
alarm levels.
The features of the X9522 are ideally suited to simplifying
the design of fiber optic modules. The integration of
these functions into one package significantly reduces
board area, cost and increases reliability of laser diode
modules.
R
WIPER
COUNTER
REGISTER
6 - BIT
NONVOLATILE
MEMORY
H0
R
W0
R
L0
SDA
SCL
V3
V2
Vcc / V1
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
THRESHOLD
RESET LOGIC
VTRIP
VTRIP
R
WIPER
COUNTER
REGISTER
7 - BIT
CONSTAT
REGISTER
2
-
+
3
-
+
2
NONVOLATILE
MEMORY
WIPER
COUNTER
REGISTER
8 - BIT
NONVOLATILE
MEMORY
H1
R
W1
R
L1
R
H2
R
W2
R
L2
V3RO
V2RO
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Ordering Information
www.BDTIC.com/Intersil
X9522
PRESET (FACTORY SHIPPED) V
PART NUMBERPART MARKING
X9522V20I-AX9522VIAOptimized for 3.3V system monitoring-40 to +8520 Ld TSSOP
X9522V20I-BX9522VIBOptimized for 5V system monitoring-40 to +8520 Ld TSSOP
X9522V20IZ-A (Note)X9522VZIAOptimized for 3.3V system monitoring-40 to +8520 Ld TSSOP (Pb-free)
X9522V20IZ-B (Note)X9522VZIBOptimized for 5V system monitoring-40 to +8520 Ld TSSOP (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
THRESHOLD LEVELS (x = 2, 3)TEMP RANGE (°C)PACKAGE
TRIPx
PIN CONFIGURATION
20 Pin TSSOP
R
H2
R
W22
R
V3
V3RO
NC
WP
SCL
SDA
V
SS
1
3
L2
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Vcc / V1
NC
V2RO
V2
R
L0
R
W0
R
H0
R
H1
R
W1
R
L1
NOT TO SCALE
DETAILED DEVICE DESCRIPTION
The X9522 combines three Intersil Digitally Controlled
Potentiometer (DCP) devices, and two voltage monitors,
in one package. These functions are suited to the control,
support, and monitoring of various system parameters in
fiber optic modules. The combination of the X9522 functionality lowers system cost, increases reliability, and
reduces board space requirements.
Two high resolution DCPs allow for the “set-and-forget”
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents. One lower resolution DCP may be used for setting sundry system parameters such as maximum laser output power (for eye
safety requirements).
The dual Voltage Monitor circuits continuously compare
their inputs to individual trip voltages. If an input voltage
exceeds it’s associated trip level, a hardware output
(V3RO, V2RO) are allowed to go HIGH. If the input voltage becomes lower than it’s associated trip level, the corresponding output is driven LOW. A corresponding
binary representation of the two monitor circuit outputs
(V2RO and V3RO) are also stored in latched, volatile
(CONSTAT) register bits. The status of these two monitor outputs can be read out via the 2-wire serial port.
Intersil’s unique circuits allow for all internal trip voltages to be individually programmed with high accuracy. This gives the designer great flexibility in
changing system parameters, either at the time of
manufacture, or in the field.
The device features a 2-Wire interface and software pro-
2
tocol allowing operation on an I
C™ compatible serial
bus.
2
FN8208.1
January 3, 2006
X9522
www.BDTIC.com/Intersil
PIN ASSIGNMENT
PinNameFunction
1
2
3
4V3
5V3RO
7WP
8SCL
9SDA
10VssGround.
11
12
13
14
15
16
17V2
18V2RO
20Vcc / V1Supply Voltage.
6, 19NCNo Connect.
R
H2
R
w2
R
L2
R
L1
R
w1
R
H1
R
H0
R
W0
R
L0
Connection to end of resistor array for (the 256 Tap) DCP 2.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP 2.
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3
input is higher than the
V3 to VSS when not used.
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than
V
and goes LOW when V3 is less than V
TRIP3
pin requires the use of an external “pull-up” resistor.
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is
enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write
Protection is enabled, and the DCP Write Lock feature is active (i.e. the DCP Write Lock bit is set to
“1”), then no “write” (volatile or nonvolatile) operations can be performed in the device (including the
wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an
internal “pull-down” resistor, thus if left floating the write protection feature is disabled.
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input
and output.
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the
device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor.
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
Connection to end of resistor array for (the 100 Tap) DCP 1.
Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.
Connection to the other end of resistor array for (the 64 Tap) DCP 0.
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2
input is greater than the
V2 to VSS when not used.
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than
V
, and goes LOW when V2 is less than V
TRIP2
pin. The V2RO pin requires the use of an external “pull-up” resistor.
V
threshold voltage, V3RO makes a transition to a HIGH level. Connect
TRIP3
V
threshold voltage, V2RO makes a transition to a HIGH level. Connect
TRIP2
. There is no delay circuitry on this pin. The V3RO
TRIP3
. There is no power-up reset delay circuitry on this
TRIP2
3
FN8208.1
January 3, 2006
SCL
www.BDTIC.com/Intersil
SDA
X9522
Data StableData ChangeData Stable
Figure 1.Valid Data Changes on the SDA Bus
PRINCIPLES OF OPERATION
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the
slave. The master always initiates data transfers, and
provides the clock for both transmit and receive operations. Therefore, the X9522 operates as a slave in all
applications.
Serial Clock and Data
Data states on the SDA line can change only while SCL
is LOW. SDA state changes while SCL is HIGH are
reserved for indicating START and STOP conditions.
See Figure 1. On power-up of the X9522, the SDA pin is
in the input mode.
Serial Start Condition
All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not respond
to any command until this condition has been met. See
Figure 2.
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. The STOP condition is also used to
place the device into the Standby power mode after a
read sequence. A STOP condition can only be issued
after the transmitting device has released the bus. See
Figure 2.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention
used to indicate a successful data transfer. The transmitting device, either master or slave, will release the
bus after transmitting eight bits. During the ninth clock
cycle, the receiver will pull the SDA line LOW to
ACKNOWLEDGE that it received the eight bits of data.
Refer to Figure 3.
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If
a write operation is selected, the device will respond with
an ACKNOWLEDGE after the receipt of each subsequent eight bit word.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected
and no STOP condition is generated by the master, the
device will continue to transmit data. The device will terminate further data transmissions if an ACKNOWLEDGE
is not detected. The master must then issue a STOP
condition to place the device into a known state.
SCL
SDA
StartStop
Figure 2.Valid Start and Stop Conditions
4
FN8208.1
January 3, 2006
SCL
www.BDTIC.com/Intersil
SCL
from
from
Master
Master
Data Output
from
Transmitter
Data Output
from
Receiver
X9522
819
StartAcknowledge
Figure 3.Acknowledge Response From Receiver
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the X9522
can be split up into two main parts:
—Three Digitally Controlled Potentiometers (DCPs)
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on
each of these individual parts, a 1, 2 or 3 Byte protocol is used. All operations however must begin with
the Slave Address Byte being issued on the SDA pin.
The Slave address selects the part of the X9522 to
be addressed, and specifies if a Read or Write operation is to be performed.
It should be noted that in order to perform a write operation to a DCP, the Write Enable Latch (WEL) bit must first
be set.
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte consists of three parts:
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9522.
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 111 internally
selects the DCP structures in the X9522. The CONSTAT Register may be selected using the Internal
Device Address 010.All other bit combinations are
RESERVED.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W
bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W
bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
SA6SA7
SA5
1010
DEVICE TYPE
IDENTIFIER
Internal Address
(SA3 - SA1)
010
111
Others
Bit SA0Operation
0WRITE
1READ
SA3 SA2
SA4
INTERNAL
DEVICE
ADDRESS
Internally Addressed
Device
CONSTAT Register
DCP
RESERVED
SA1
SA0
R/W
READ /
WRITE
Figure 4.Slave Address Format
5
FN8208.1
January 3, 2006
Nonvolatile Write Acknowledge Polling
www.BDTIC.com/Intersil
After a nonvolatile write command sequence (for either
the Non Volatile Memory of a DCP (NVM), or the CONSTAT Register) has been correctly issued (including the
final STOP condition), the X9522 initiates an internal high
voltage write cycle. This cycle typically requires 5 ms.
During this time, no further Read or Write commands can
be issued to the device. Write Acknowledge Polling is
used to determine when this high voltage write cycle has
been completed.
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal
Device Address. The LSB of the Slave Address (R/W
can be set to either 1 or 0 in this case. If the device is still
busy with the high voltage cycle then no ACKNOWLEDGE will be returned. If the device has completed the
write operation, an ACKNOWLEDGE will be returned
and the host can then proceed with a read or write operation. (Refer to Figure 5.)
X9522
)
N
WIPER
COUNTER
REGISTER
(WCR)
NON
VOLATILE
MEMORY
(NVM)
DECODER
“WIPER”
FET
SWITCHES
2
1
0
Figure 6.DCP Internal Structure
RESISTOR
ARRAY
R
Hx
R
Lx
R
Wx
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
ACK
returned?
YES
High Voltage Cycle
complete. Continue
command sequence?
YES
Continue normal
Read or Write
command sequence
PROCEED
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
The X9522 includes three independent resistor arrays.
These arrays respectively contain 63, 99 and 255
discrete resistive segments that are connected in series.
The physical ends of each array are equivalent to the
Issue STOP
fixed terminals of a mechanical potentiometer (R
inputs - where x = 0,1,2).
R
Lx
At both ends of each array and between each resistor
NO
segment there is a CMOS switch connected to the wiper
) output. Within each individual array, only one
(R
x
w
switch may be turned on at any one time. These
switches are controlled by the Wiper Counter Register
(WCR) (See Figure 6). The WCR is a volatile register.
NO
Issue STOP
On power-up of the X9522, wiper position data is automatically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below
shows the Initial Values of the DCP WCR’s before the
contents of the NVM is loaded into the WCR.
DCPInitial Values Before Recall
/ 64 TAPVH / TAP = 63
R
0
/ 100 TAPVL / TAP = 0
R
1
R
/ 256 TAPVH / TAP = 255
2
Hx
and
Figure 5. Acknowledge Polling Sequence
6
FN8208.1
January 3, 2006
Vcc
www.BDTIC.com/Intersil
X9522
Vcc (Max.)
V
TRIP
t
trans
0
Figure 7.DCP Power-up
The data in the WCR is then decoded to select and
enable one of the respective FET switches. A “make
before break” sequence is used internally for the FET
switches when the wiper is moved from one tap position
to another.
t
pu
Hot Pluggability
Figure 7 shows a typical waveform that the X9522 might
experience in a Hot Pluggable situation. On power-up,
Vcc / V1 applied to the X9522 may exhibit some amount
of ringing, before it settles to the required value.
The device is designed such that the wiper terminal
) is recalled to the correct position (as per the last
(R
Wx
stored in the DCP NVM), when the voltage applied to
Vcc / V1 exceeds V
Therefore, if t
V1 to settle above V
wiper terminal position is recalled by (a maximum) time:
t
+ tpu. It should be noted that t
trans
system hot plug conditions.
trans
for a time exceeding t
TRIP
is defined as the time taken for Vcc /
(Figure 7): then the desired
TRIP
trans
pu.
is determined by
DCP Operations
In total there are three operations that can be performed
on any internal DCP structure:
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
A nonvolatile write to a DCP will change the “wiper
position” by simultaneously writing new data to the
associated WCR and NVM. Therefore, the new “wiper
position” setting is recalled into the WCR after Vcc / V1 of
the X9522 is powered down and then powered back up.
A volatile write operation to a DCP however, changes the
“wiper position” by writing new data to the associated
WCR only. The contents of the associated NVM register
t
Maximum Wiper Recall time
remains unchanged. Therefore, when Vcc / V1 to the
device is powered down then back up, the “wiper
position” reverts to that last position written to the DCP
using a nonvolatile write operation.
Both volatile and nonvolatile write operations are
executed using a three byte command sequence: (DCP)
Slave Address Byte, Instruction Byte, followed by a Data
Byte (See Figure 9).
A DCP Read operation allows the user to “read out” the
current “wiper position” of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consisting
of the (DCP) Slave Address Byte followed by an
Instruction Byte and the Slave Address Byte again (Refer
to Figure 10.).
Instruction Byte
While the Slave Address Byte is used to select the DCP
devices, an Instruction Byte is used to determine which
DCP is being addressed.
The Instruction Byte (Figure 8) is valid only when the
Device Type Identifier and the Internal Device
Address bits of the Slave Address are set to
1010111. In this case, the two Least Significant Bit’s
(I1 - I0) of the Instruction Byte are used to select the
particular DCP (0 - 2). In the case of a Write to any of
the DCPs (i.e. the LSB of the Slave Address is 0), the
Most Significant Bit of the Instruction Byte (I7), determines the Write Type (WT) performed.
If WT is “1”, then a Nonvolatile Write to the DCP
In this case, the “wiper position” of the DCP is changed
by simultaneously writing new data to the associated
WCR and NVM. Therefore, the new “wiper position” setting is recalled into the WCR after Vcc / V1 of the X9522
has been powered down then powered back up.
occurs.
7
FN8208.1
January 3, 2006
X9522
www.BDTIC.com/Intersil
I5I6I7I4I3I2I1I0
00WT000P1P0
WRITE TYPE
†
WT
Select a Volatile Write operation to be performed
0
on the DCP pointed to by bits P1 and P0
Select a Nonvolatile Write operation to be per-
1
formed on the DCP pointed to by bits P1 and P0
†
This bit has no effect when a Read operation is being performed.
Description
DCP SELECT
Figure 8.Instruction Byte Format
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only. The contents of
the associated NVM register remains unchanged. Therefore, when Vcc / V1 to the device is powered down then
back up, the “wiper position” reverts to that last written to
the DCP using a nonvolatile write operation.
DCP Write Operation
A write to DCPx (x=0,1,2) can be performed using the
three byte command sequence shown in Figure 9.
In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Register must first be set (See “WEL: Write Enable Latch
(Volatile)” on page 10.)
The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
returned by the X9522 after the Slave Address, if it has
been received correctly.
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be
volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9522.
Following the Instruction Byte, a Data Byte is issued to
the X9522 over SDA. The Data Byte contents is latched
into the WCR of the DCP on the first rising edge of the
clock signal, after the LSB of the Data Byte (D0) has
been issued on SDA (See Figure 25).
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).
P1- P0DCPx# TapsMax. Data Byte
00 x = 0643Fh
01x = 1100Refer to Appendix 1
10x = 2256FFh
11Reserved
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
For DCP0 (64 Tap) and DCP2 (256 Tap), the Data Byte
maps one to one to the “wiper position” of the DCP
“wiper terminal”. Therefore, the Data Byte 00001111
) corresponds to setting the “wiper terminal” to tap
(15
10
position 15. Similarly, the Data Byte 00011100 (28
10
corresponds to setting the “wiper terminal” to tap position
28. The mapping of the Data Byte to “wiper position” data
for DCP1 (100 Tap), is shown in “APPENDIX 1”. An
example of a simple C language function which “translates” between the tap position (decimal) and the Data
Byte (binary) for DCP1, is given in “APPENDIX 2”.
)
10101110
S
T
A
R
T
SLAVE ADDRESS BYTE
A
WT00000P1 P0 A
C
K
INSTRUCTION BYTE
C
K
Figure 9.DCP Write Command Sequence
8
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
A
T
C
O
K
P
FN8208.1
January 3, 2006
X9522
www.BDTIC.com/Intersil
S
WRITE Operation
Signals from
the Master
t
a
r
Slave
Address
Instruction
Byte
t
SDA Bus
Signals from
the Slave
101 11100
“Dummy” write
W
00 000
T
A
C
K
Figure 10. DCP Read Sequence
It should be noted that all writes to any DCP of the X9522
are random in nature. Therefore, the Data Byte of consecutive write operations to any DCP can differ by an
arbitrary number of bits. Also, setting the bits P1=1, P0=1
is a reserved sequence, and will result in no ACKNOWLEDGE after sending an Instruction Byte on SDA.
The factory default setting of all “wiper position” settings
is with 00h stored in the NVM of the DCPs. This corre-
R
sponds to having the “wiper teminal”
(x = 0,1,2) at
WX
the “lowest” tap position, Therefore, the resistance
R
between
Wiper Resistance,
and RLX is a minimum (essentially only the
WX
R
).
W
DCP Read Operation
A read of DCPx (x = 0,1,2) can be performed using the
three byte random read command sequence shown in
Figure 10.
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read
operation). An ACKNOWLEDGE is returned by the
X9522 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1-P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9522.
S
READ Operation
t
Slave
a
r
Address
Data Byte
t
P
P
1
101 11110
0
A
C
K
A
C
K
MSB
S
t
o
p
--
-
“-” = DON’T CARE
LSB
DCPx
x = 0
x = 1
x = 2
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W
bit set to 1. Then the X9522
issues an ACKNOWLEDGE followed by Data Byte, and
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the “wiper
position” (value of the WCR) of the DCP pointed to by
bits P1 and P0.
It should be noted that when reading out the data byte
for DCP0 (64 Tap), the upper two most significant bits
are “unknown” bits. For DCP1 (100 Tap), the upper
most significant bit is an “unknown”. For DCP2 (256
Tap) however, all bits of the data byte are relevant (See
Figure 10).
CONTROL AND STATUS REGISTER
The Control and Status (CONSTAT) Register provides the user with a mechanism for changing and
reading the status of various parameters of the
X9522 (See Figure 11).
The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CONSTAT register retain their stored values even when Vcc /
V1 is powered down, then powered back up. The volatile
bits however, will always power-up to a known logic state
“0” (irrespective of their value at power-down).
9
FN8208.1
January 3, 2006
CS6CS7CS4
www.BDTIC.com/Intersil
CS5
0
Bit(s)Description
V2OSV2 Output Status flag
V3OSV3 Output Status flag
DWLKSets the DCP Write Lock
RWELRegister Write Enable Latch bit
WELWrite Enable Latch bit
NOTE: Bits belled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
V3OS
V2OS
CS7Always set to “0” (RESERVED)
CS4Always set to “0” (RESERVED)
CS0Always set to “0” (RESERVED)
CS3
CS2CS1CS0
0
DWLK
RWEL
WEL
0
NV
Figure 11. CONSTAT Register Format
A detailed description of the function of each of the
CONSTAT register bits follows:
X9522
It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT
Register Write Operation").
The RWEL bit will reset itself to the default “0” state,
in one of two cases:
—After a successful write operation to any bits of
the CONSTAT register has been completed (See
Figure 12).
—When the X9522 is powered down.
DWLK: DCP Write Lock bit - (Nonvolatile)
The DCP Write Lock bit (DWLK) is used to inhibit a DCP
write operation (changing the “wiper position”).
When the DCP Write Lock bit of the CONSTAT register
is set to “1”, then the “wiper position” of the DCPs cannot be changed - i.e. DCP write operations cannot be
conducted:
DWLKDCP Write Operation Permissible
0YES (Default)
1NO
The factory default setting for this bit is DWLK = 0.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the
entire X9522 device. This bit must first be enabled before
ANY write operation (to DCPs, or the CONSTAT register). If the WEL bit is not first enabled, then ANY proceeding (volatile or nonvolatile) write operation to DCPs,
or the CONSTAT register, is aborted and no ACKNOWLEDGE is issued after a Data Byte.
The WEL bit is a volatile latch that powers up in the disabled, LOW (0) state. The WEL bit is enabled / set by
writing 00000010 to the CONSTAT register. Once
enabled, the WEL bit remains set to “1” until either it is
reset to “0” (by writing 00000000 to the CONSTAT register) or until the X9522 powers down, and then up again.
Writes to the WEL bit do not cause an internal high voltage write cycle. Therefore, the device is ready for
another operation immediately after a STOP condition is
executed in the CONSTAT Write command sequence
(See Figure 12).
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9522. Therefore, in order to write
to any of the bits of the CONSTAT Register (except
WEL), the RWEL bit must first be set to “1”. The RWEL
bit is a volatile bit that powers up in the disabled, LOW
(“0”) state.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9522 is active (HIGH), then nonvolatile write operations
to the DCPs are inhibited, irrespective of the DCP Write
Lock bit setting (See "WP: Write Protection Pin").
V2OS, V3OS: Voltage Monitor Status Bits (Volatile)
Bits V2OS and V3OS of the CONSTAT register are
latched, volatile flag bits which indicate the status of the
Voltage Monitor reset output pins V2RO and V3RO.
At power-up the VxOS (x=2,3) bits default to the value
“0”. These bits can be set to a “1” by writing the appropriate value to the CONSTAT register. To provide consistency between the VxRO and VxOS however, the status
of the VxOS bits can only be set to a “1” when the corresponding VxRO output is HIGH.
Once the VxOS bits have been set to “1”, they will be
reset to “0” if:
—The device is powered down, then back up,
—The corresponding VxRO output becomes LOW.
10
FN8208.1
January 3, 2006
SCL
www.BDTIC.com/Intersil
SDA
X9522
S
1 010010R/WA
T
A
R
T
SLAVE ADDRESS BYTE
11111111 A
C
K
ADDRESS BYTE
Figure 12. CONSTAT Register Write Command Sequence
CONSTAT Register Write Operation
The CONSTAT register is accessed using the Slave
Address set to 1010010 (Refer to Figure 4.). Following
the Slave Address Byte, access to the CONSTAT register requires an Address Byte which must be set to FFh.
Only one data byte is allowed to be written for each
CONSTAT register Write operation. The user must issue
a STOP, after sending this byte to the register, to initiate
the nonvolatile cycle that stores the DWLK bit. The
X9522 will not ACKNOWLEDGE any data bytes written
after the first byte is entered (Refer to Figure 12.).
When writing to the CONSTAT register, the bits CS7,
CS4 and CS0 must all be set to “0”. Writing any other bit
sequence to bits CS7, CS4 and CS0 of the CONSTAT
register is reserved.
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps:
—Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a START and ended with a STOP).
CS7 CS6
C
K
CONSTAT REGISTER DATA IN
CS5 CS4 CS3
CS2 CS1
CS0
A
S
C
T
K
O
P
—Write a 06H to the CONSTAT Register to set the
Register Write Enable Latch (RWEL) AND the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceded by a START
and ended with a STOP).
—Write a one byte value to the CONSTAT Register that
has all the bits set to the desired state. The CONSTAT
register can be represented as 0xy0t010 in binary,
where xy are the Voltage Monitor Output Status
(V2OS and V3OS) bits, and t is the DCP Write Lock
(DWLK) bit. This operation is proceeded by a START
and ended with a STOP bit. Since this is a nonvolatile
write cycle, it will typically take 5ms to complete. The
RWEL bit is reset by this cycle and the sequence must
be repeated to change the nonvolatile bits again. If bit
2 is set to ‘1’ in this third step (0xy0 t110) then the
RWEL bit is set, but the DWLK bit will remain
unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation
and the X9522 does not return an ACKNOWLEDGE.
For example, a sequence of writes to the device CONSTAT register consisting of [02H, 06H, 02H] will reset the
nonvolatile (DWLK) bit in the CONSTAT Register to “0”.
WRITE Operation
Address
0
A
C
K
“Dummy” Write
Byte
S
t
a
r
t
A
C
K
Slave
Address
0 1 0 0 1 0
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
Slave
a
Address
r
t
0 1 0 0 1 011
Figure 13. CONSTAT Register Read Command Sequence
11
READ Operation
CS7 … CS0
1
A
C
Data
K
S
t
o
p
FN8208.1
January 3, 2006
It should be noted that a write to nonvolatile bit (DWLK)
www.BDTIC.com/Intersil
of CONSTAT register will be ignored if the Write Protect
pin of the X9522 is active (HIGH) (See "WP: Write Protection Pin").
X9522
Vx
V
TRIPx
0V
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at
any time by performing a random read (See Figure 13).
Using the Slave Address Byte set to 10100101, and an
Address Byte of FFh. Only one byte is read by each register read operation. The X9522 resets itself after the first
byte is read. The master should supply a STOP condition
to be consistent with the bus protocol.
After setting the WEL and / or the RWEL bit(s) to a “1”,
a CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write
operation.
When reading the contents of the CONSTAT register,
the bits CS7, CS4 and CS0 will always return “0”.
DATA PROTECTION
There are a number of levels of data protection features
designed into the X9522. Any write to the device first
requires setting of the WEL bit in the CONSTAT register.
A write to the CONSTAT register itself, further requires
the setting of the RWEL bit. The DCP Write Lock of the
device enables the user to inhibit writes to all DCPs. One
further level of data protection in the X9522, is incorporated in the form of the Write Protection pin.
WP: Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X9522.
The table below (X9522 Write Permission Status) summarizes the effect of the WP pin (and DCP Write Lock),
on the write permission status of the device.
VxRO
Vcc / V1
0 Volts
(x = 2,3)
V
0V
TRIP
Figure 14. Voltage Monitor Response
Additional Data Protection Features
In addition to the preceding features, the X9522 also
incorporates the following data protection functionality:
—The proper clock count and data bit sequence is
required prior to the STOP bit in order to start a nonvolatile write cycle.
VOLTAGE MONITORING FUNCTIONS
V2 monitoring
The X9522 asserts the V2RO output HIGH if the voltage V2 exceeds the corresponding V
(See Figure 14). The bit V2OS in the CONSTAT register is then set to a “0” (assuming that it has been set to
“1” after system initilization).
The V2RO output may remain active HIGH with Vcc
down to 1V.
TRIP2
threshold
X9522 Write Permission Status
DWLK
(DCP Write Lock
bit status)
11NONONONO
01YESNONONO
1
0
(Write Protect pin
WP
status)
0
0
12
DCP Volatile Write
Permitted
NONOYESYES
YESYESYESYES
DCP Nonvolatile
Write Permitted
Write to CONSTAT Register
Volatile BitsNonvolatile Bits
Permitted
FN8208.1
January 3, 2006
V2, V3
www.BDTIC.com/Intersil
WP
V
TRIPx
X9522
V
P
SCL
SDA
01234567
†
S
T
A
R
T
A0h
Figure 15. Setting V
01234567
09h† sets V
0Dh† sets V
TRIPx
V3 monitoring
The X9522 asserts the V3RO output HIGH if the voltage V3 exceeds the corresponding V
(See Figure 14). The bit V3OS in the CONSTAT register is then set to a “0” (assuming that it has been set to
“1” after system initilization).
The V3RO output may remain active HIGH with Vcc
down to 1V.
V
THRESHOLDS (X = 2,3)
TRIPX
The X9522 is shipped with pre-programmed threshold
(V
) voltages. In applications where the required
TRIPx
thresholds are different from the default values, or if a
TRIP3
threshold
01234567
00h
†
†
All others Reserved.
TRIP1
TRIP2
Data Byte
to a higher level (x = 1,2).
higher precision / tolerance is required, the X9522 trip
points may be adjusted by the user, using the steps
detailed below.
Setting a V
Voltage (x = 2,3)
TRIPx
There are two procedures used to set the threshold
voltages (V
), depending if the threshold voltage
TRIPx
to be stored is higher or lower than the present value.
For example, if the present V
new V
directly into the V
is 3.2 V, the new voltage can be stored
TRIPx
cell. If however, the new setting
TRIPx
is 2.9 V and the
TRIPx
is to be lower than the present setting, then it is necessary to “reset” the V
voltage before setting the
TRIPx
new value.
V
P
WP
01234567
00h
Data Byte
Level (x = 2,3)
SCL
SDA
01234567
†
S
T
A
R
T
A0h
13
01234567
0Bh† Resets
0Fh† Resets
VTRIP2
VTRIP3
Figure 16. Resetting the V
TRIPx
†
†
All others Reserved.
FN8208.1
January 3, 2006
X9522
www.BDTIC.com/Intersil
Setting a Higher V
To set a V
threshold to a new voltage which is
TRIPx
Voltage (x = 2,3)
TRIPx
higher than the present threshold, the user must apply
the desired V
threshold voltage to the corre-
TRIPx
sponding input pin (V2 or V3). Then, a programming
voltage (Vp) must be applied to the WP pin before a
START condition is set up on SDA. Next, issue on the
SDA pin the Slave Address A0h, followed by the Byte
Address 09h for V
, and 0Dh for V
TRIP3
Data Byte in order to program V
TRIPx
, and a 00h
TRIP3
. The STOP bit
following a valid write operation initiates the programming sequence. Pin WP must then be brought LOW to
complete the operation (See Figure 16). The user
does not have to set the WEL bit in the CONSTAT register before performing this write sequence.
Setting a Lower V
In order to set V
present value, then V
ing to the procedure described below. Once V
has been “reset”, then V
Voltage (x = 2,3)
TRIPx
to a lower voltage than the
TRIPx
must first be “reset” accord-
TRIPx
can be set to the desired
TRIPx
TRIPx
voltage using the procedure described in “Setting a
Higher V
Resetting the V
To reset a V
TRIPx
Voltage”.
Voltage
TRIPx
voltage, apply the programming volt-
TRIPx
age (Vp) to the WP pin before a START condition is set
up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 0Bh for
, and 0Fh for V
V
TRIP2
Data Byte in order to reset V
, followed by 00h for the
TRIP3
. The STOP bit fol-
TRIPx
lowing a valid write operation initiates the programming sequence. Pin WP must then be brought LOW to
complete the operation (See Figure 16).The user does
not have to set the WEL bit in the CONSTAT register
before performing this write sequence.
After being reset, the value of V
becomes a nomi-
TRIPx
nal value of 1.7V.
Once the desired V
threshold has been set, the
TRIPx
error between the desired and (new) actual set threshold
can be determined. This is achieved by applying Vcc / V1
to the device, and then applying a test voltage higher
than the desired threshold voltage, to the input pin of the
voltage monitor circuit whose V
For example, if V
was set to a desired level of 3.0 V,
TRIP2
was programmed.
TRIPx
then a test voltage of 3.4 V may be applied to the voltage
monitor input pin V2. In all cases, care should be taken
not to exceed the maximum input voltage limits.
After applying the test voltage to the voltage monitor
input pin, the test voltage can be decreased (either in discrete steps, or continuously) until the output of the voltage monitor circuit changes state. At this point, the error
between the actual / measured, and desired threshold
levels is calculated.
For example, the desired threshold for V
TRIP2
is set to
3.0 V, and a test voltage of 3.4 V was applied to the input
pin V2 (after applying power to Vcc / V1). The input voltage is decreased, and found to trip the associated output
level of pin V2RO from a LOW to a HIGH, when V2
reaches 3.09 V. From this, it can be calculated that the
programming error is 3.09 - 3.0 = 0.09 V.
If the error between the desired and measured V
TRIPx
less than the maximum desired error, then the programming process may be terminated. If however, the error is
greater than the maximum desired error, then another
iteration of the V
programming sequence can be
TRIPx
performed (using the calculated error) in order to further
increase the accuracy of the threshold voltage.
If the calculated error is greater than zero, then the
V
a value equal to the previously set V
must first be “reset”, and then programmed to the
TRIPx
minus the cal-
TRIPx
culated error. If it is the case that the error is less than
zero, then the V
equal to the previously set V
must be programmed to a value
TRIPx
plus the absolute value
TRIPx
of the calculated error.
is
V
The accuracy with which the V
Accuracy (x = 2,3)
TRIPx
thresholds are set,
TRIPx
can be controlled using the iterative process shown in
Figure 17.
If the desired threshold is less that the present threshold
voltage, then it must first be “reset” (See "Resetting the
VTRIPx Voltage").
The desired threshold voltage is then applied to the
appropriate input pin (V2 or V3) and the procedure
described in Section “Setting a Higher V
TRIPx
Voltage“
Continuing the previous example, we see that the calculated error was 0.09V. Since this is greater than zero, we
must first “reset” the V
age equal to the last previously programmed voltage,
minus the last previously calculated error. Therefore, we
must apply V
programming sequence (See "Setting a Higher VTRIPx
Voltage (x = 2,3)" ) .
Using this process, the desired accuracy for a particular V
threshold may be attained using a succes-
TRIPx
sive number of iterations.
must be followed.
14
threshold, then apply a volt-
TRIP2
= 2.91 V to pin V2 and execute the
TRIP1
FN8208.1
January 3, 2006
X9522
www.BDTIC.com/Intersil
New Vx applied =
Old Vx applied
+ | Error |
V
NO
Set Vx = desired
Apply Vcc & Voltage
> Desired V
NO
Programming
TRIPx
Desired V
present value?
Execute
V
TRIPx
Sequence
Execute
Set Higher
Sequence
Decrease Vx
Output
switches?
TRIPx
YES
Reset
V
TRIPx
TRIPx
<
V
TRIPx
to Vx
Desired Value
New Vx applied =
Old Vx applied
Execute
Reset
Sequence
Note: X = 1,2,3.
Let: MDE = Maximum Desired Error
+
MDE
Acceptable
Error Range
–
MDE
Error = Actual – Desired
- | Error |
V
TRIPx
Error < MDE
Figure 17. V
YES
–
Actual V
- Desired V
= Error
TRIPx
TRIPx
Error >MDE
| Error | < | MDE |
DONE
Setting / Reset Sequence (x = 1,2,3)
TRIPx
+
15
FN8208.1
January 3, 2006
X9522
www.BDTIC.com/Intersil
ABSOLUTE MAXIMUM RATINGS
ParameterMin.Max.Units
Temperature under Bias-65+135°C
Storage Temperature-65+150 °C
Voltage on WP pin (With respect to Vss)-1.0+15V
Voltage on other pins (With respect to Vss)-1.0+7V
| Voltage on R
- Voltage on R
Hx
D.C. Output Current (SDA,V2RO,V3RO)
| (x = 0,1,2. Referenced to Vss)
Lx
0
Lead Temperature (Soldering, 10 seconds)300°C
Supply Voltage Limits (Applied Vcc / V1 voltage, referenced to Vss)2.75.5V
RECOMMENDED OPERATING CONDITIONS
TemperatureMin.Max.Units
Industrial-40+85
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
Vcc / V1V
5mA
°C
Figure 18. Equivalent A.C. Circuit
Figure 19. DCP SPICE Macromodel
SDA
V2RO
V3RO
R
Hx
10pF
Vcc / V1 = 5V
R
TOTAL
C
H
R
Wx
2300Ω
100pF
R
W
C
25pF
R
Lx
C
L
10pF
W
(x = 0,1,2)
16
FN8208.1
January 3, 2006
TIMING DIAGRAMS
www.BDTIC.com/Intersil
Figure 20. Bus Timing
X9522
SCL
t
SU:SA
SDA IN
t
HD:STA
SDA OUT
Figure 21. WP Pin Timing
START
SCL
SDA IN
WP
t
F
t
SU:DAT
t
SU:WP
t
HIGH
t
LOW
t
HD:DAT
t
R
t
AA
Clk 1Clk 9
t
HD:WP
t
DH
t
BUF
t
SU:STO
Figure 22. Write Cycle Timing
SCL
SDA
8th bit of last byteACK
Stop
Condition
t
WC
Start
Condition
17
FN8208.1
January 3, 2006
Figure 23. V2, V3 Timing Diagram
www.BDTIC.com/Intersil
X9522
Vx
VxRO
Vcc / V1
Note : x = 2,3.
Figure 24. V
V2, V3
t
Rx
t
RPDx
Programming Timing Diagram (x = 2,3)
TRIPX
t
RPDx
V
TRIPx
t
RPDx
t
Fx
V
RVALID
t
RPDx
V
TRIPx
0 Volts
0 Volts
V
TRIP
0 Volts
V
WP
SCL
SDA
t
TSU
P
t
VPS
t
wc
00h
t
VPH
t
THD
t
VPO
NOTE : Vcc / V1 must be greater than V2, V3 when programming.
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 2)
unsigned DCP100_TAP_Position(int tap_pos)
{
/* optional range checking
*/ if (tap_pos < 0) return ((unsigned)0); /* set to min val */
else if (tap_pos >99) return ((unsigned) 96); /* set to max val */
/* 100 Tap DCP encoding formula */
if (tap_pos > 74)
return ((unsigned) (195 - tap_pos));
else if (tap_pos > 49)
return ((unsigned) (14 + tap_pos));
else if (tap_pos > 24)
return ((unsigned) (81 - tap_pos));
else return (tap_pos);
}
26
FN8208.1
January 3, 2006
X9522
www.BDTIC.com/Intersil
20-LEAD PLASTIC, TSSOPPACKAGE TYPE V
.025 (.65) BSC
0° - 8 °
.0075 (.19)
.0118 (.30)
.252 (6.4)
.260 (6.6)
.019 (.50)
.029 (.75)
Detail A (20X)
.169 (4.3)
.177 (4.5)
.047 (1.20)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
Seating Plane
.252 (6.4) BSC
(1.78)
(0.42)
(0.65)
(4.16)
(7.72)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
27
ALL MEASUREMENTS ARE TYPICAL
FN8208.1
January 3, 2006
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.