intersil X9522 DATA SHEET

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Data Sheet January 3, 2006
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Laser Diode Control for Fiber Optic Modules
FN8208.1
Triple DCP, Dual Voltage Monitors
FEATURES
• Three Digitally Controlled Potentiometers (DCPs) —64 Tap - 10kΩ —100 Tap - 10kΩ —256 Tap - 100kΩ —Nonvolatile —Write Protect Function
• 2-Wire industry standard Serial Interface
• Dual Voltage Monitors —Programmable Threshold Voltages
• Single Supply Operation —2.7V to 5.5V
• Hot Pluggable
• 20 Pin package —TSSOP
BLOCK DIAGRAM
8
WP
PROTECT LOGIC
DESCRIPTION
The X9522 combines three Digitally Controlled Potenti­ometers (DCPs), and two programmable voltage monitor inputs with software and hardware indicators. All func­tions of the X9522 are accessed by an industry standard 2-Wire serial interface.
Two of the DCPs of the X9522 may be utilized to control the bias and modulation currents of the laser diode in a Fiber Optic module. The third DCP may be used to set other various reference quantities, or as a coarse trim for one of the other two DCPs.The programmable voltage monitors may be used for monitoring various module alarm levels.
The features of the X9522 are ideally suited to simplifying the design of fiber optic modules. The integration of these functions into one package significantly reduces board area, cost and increases reliability of laser diode modules.
R
WIPER COUNTER REGISTER
6 - BIT
NONVOLATILE
MEMORY
H0
R
W0
R
L0
SDA
SCL
V3
V2
Vcc / V1
DATA
REGISTER
COMMAND DECODE & CONTROL
LOGIC
THRESHOLD
RESET LOGIC
VTRIP
VTRIP
R
WIPER COUNTER REGISTER
7 - BIT
CONSTAT
REGISTER
2
-
+
3
-
+
2
NONVOLATILE
MEMORY
WIPER COUNTER REGISTER
8 - BIT
NONVOLATILE
MEMORY
H1
R
W1
R
L1
R
H2
R
W2
R
L2
V3RO
V2RO
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
©2000 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2006. All Rights Reserved
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Ordering Information
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X9522
PRESET (FACTORY SHIPPED) V
PART NUMBER PART MARKING
X9522V20I-A X9522VIA Optimized for 3.3V system monitoring -40 to +85 20 Ld TSSOP X9522V20I-B X9522VIB Optimized for 5V system monitoring -40 to +85 20 Ld TSSOP X9522V20IZ-A (Note) X9522VZIA Optimized for 3.3V system monitoring -40 to +85 20 Ld TSSOP (Pb-free) X9522V20IZ-B (Note) X9522VZIB Optimized for 5V system monitoring -40 to +85 20 Ld TSSOP (Pb-free)
*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
THRESHOLD LEVELS (x = 2, 3) TEMP RANGE (°C) PACKAGE
TRIPx
PIN CONFIGURATION
20 Pin TSSOP
R
H2
R
W2 2
R
V3
V3RO
NC
WP
SCL
SDA
V
SS
1
3
L2
4 5 6
7 8
9
10
20 19 18 17
16 15 14 13 12 11
Vcc / V1
NC
V2RO V2 R
L0
R
W0
R
H0
R
H1
R
W1
R
L1
NOT TO SCALE
DETAILED DEVICE DESCRIPTION
The X9522 combines three Intersil Digitally Controlled Potentiometer (DCP) devices, and two voltage monitors, in one package. These functions are suited to the control, support, and monitoring of various system parameters in fiber optic modules. The combination of the X9522 func­tionality lowers system cost, increases reliability, and reduces board space requirements.
Two high resolution DCPs allow for the “set-and-forget” adjustment of Laser Driver IC parameters such as Laser Diode Bias and Modulation Currents. One lower resolu­tion DCP may be used for setting sundry system param­eters such as maximum laser output power (for eye safety requirements).
The dual Voltage Monitor circuits continuously compare their inputs to individual trip voltages. If an input voltage exceeds it’s associated trip level, a hardware output (V3RO, V2RO) are allowed to go HIGH. If the input volt­age becomes lower than it’s associated trip level, the cor­responding output is driven LOW. A corresponding binary representation of the two monitor circuit outputs (V2RO and V3RO) are also stored in latched, volatile (CONSTAT) register bits. The status of these two moni­tor outputs can be read out via the 2-wire serial port.
Intersil’s unique circuits allow for all internal trip volt­ages to be individually programmed with high accu­racy. This gives the designer great flexibility in changing system parameters, either at the time of manufacture, or in the field.
The device features a 2-Wire interface and software pro-
2
tocol allowing operation on an I
C™ compatible serial
bus.
2
FN8208.1
January 3, 2006
X9522
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PIN ASSIGNMENT
Pin Name Function
1
2
3
4V3
5V3RO
7WP
8SCL
9SDA
10 Vss Ground.
11
12
13
14
15
16
17 V2
18 V2RO
20 Vcc / V1 Supply Voltage.
6, 19 NC No Connect.
R
H2
R
w2
R
L2
R
L1
R
w1
R
H1
R
H0
R
W0
R
L0
Connection to end of resistor array for (the 256 Tap) DCP 2.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP 2.
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3 input is higher than the V3 to VSS when not used.
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than
V
and goes LOW when V3 is less than V
TRIP3
pin requires the use of an external “pull-up” resistor.
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the DCP Write Lock feature is active (i.e. the DCP Write Lock bit is set to “1”), then no “write” (volatile or nonvolatile) operations can be performed in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled.
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up re­sistor.
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
Connection to end of resistor array for (the 100 Tap) DCP 1.
Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.
Connection to the other end of resistor array for (the 64 Tap) DCP 0.
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2 input is greater than the V2 to VSS when not used.
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than
V
, and goes LOW when V2 is less than V
TRIP2
pin. The V2RO pin requires the use of an external “pull-up” resistor.
V
threshold voltage, V3RO makes a transition to a HIGH level. Connect
TRIP3
V
threshold voltage, V2RO makes a transition to a HIGH level. Connect
TRIP2
. There is no delay circuitry on this pin. The V3RO
TRIP3
. There is no power-up reset delay circuitry on this
TRIP2
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FN8208.1
January 3, 2006
SCL
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SDA
X9522
Data Stable Data Change Data Stable
Figure 1. Valid Data Changes on the SDA Bus
PRINCIPLES OF OPERATION
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive opera­tions. Therefore, the X9522 operates as a slave in all applications.
Serial Clock and Data
Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions. See Figure 1. On power-up of the X9522, the SDA pin is in the input mode.
Serial Start Condition
All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met. See Figure 2.
Serial Stop Condition
All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. The STOP condition is also used to place the device into the Standby power mode after a read sequence. A STOP condition can only be issued after the transmitting device has released the bus. See Figure 2.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention used to indicate a successful data transfer. The trans­mitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to ACKNOWLEDGE that it received the eight bits of data. Refer to Figure 3.
The device will respond with an ACKNOWLEDGE after recognition of a START condition if the correct Device Identifier bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an ACKNOWLEDGE after the receipt of each subse­quent eight bit word.
In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an ACKNOWLEDGE. If an ACKNOWLEDGE is detected and no STOP condition is generated by the master, the device will continue to transmit data. The device will ter­minate further data transmissions if an ACKNOWLEDGE is not detected. The master must then issue a STOP condition to place the device into a known state.
SCL
SDA
Start Stop
Figure 2. Valid Start and Stop Conditions
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January 3, 2006
SCL
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SCL
from
from
Master
Master
Data Output
from
Transmitter
Data Output
from
Receiver
X9522
81 9
Start Acknowledge
Figure 3. Acknowledge Response From Receiver
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the X9522 can be split up into two main parts:
—Three Digitally Controlled Potentiometers (DCPs)
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on each of these individual parts, a 1, 2 or 3 Byte proto­col is used. All operations however must begin with the Slave Address Byte being issued on the SDA pin. The Slave address selects the part of the X9522 to be addressed, and specifies if a Read or Write opera­tion is to be performed.
It should be noted that in order to perform a write opera­tion to a DCP, the Write Enable Latch (WEL) bit must first be set.
Slave Address Byte
Following a START condition, the master must output a Slave Address Byte (Refer to Figure 4.). This byte con­sists of three parts:
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4). The Device Type Identifier must always be set to 1010 in order to select the X9522.
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 111 internally selects the DCP structures in the X9522. The CON­STAT Register may be selected using the Internal Device Address 010.All other bit combinations are RESERVED.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W
bit. This bit defines the operation to be performed on the device being addressed (as defined in the bits SA3 - SA1). When the R/W
bit is “1”, then a READ operation is selected. A “0” selects a WRITE operation (Refer to Figure 4.)
SA6SA7
SA5
1010
DEVICE TYPE
IDENTIFIER
Internal Address
(SA3 - SA1)
010
111
Others
Bit SA0 Operation
0WRITE
1 READ
SA3 SA2
SA4
INTERNAL
DEVICE
ADDRESS
Internally Addressed
Device
CONSTAT Register
DCP
RESERVED
SA1
SA0
R/W
READ / WRITE
Figure 4. Slave Address Format
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Nonvolatile Write Acknowledge Polling
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After a nonvolatile write command sequence (for either the Non Volatile Memory of a DCP (NVM), or the CON­STAT Register) has been correctly issued (including the final STOP condition), the X9522 initiates an internal high voltage write cycle. This cycle typically requires 5 ms. During this time, no further Read or Write commands can be issued to the device. Write Acknowledge Polling is used to determine when this high voltage write cycle has been completed.
To perform acknowledge polling, the master issues a START condition followed by a Slave Address Byte. The Slave Address issued must contain a valid Internal Device Address. The LSB of the Slave Address (R/W can be set to either 1 or 0 in this case. If the device is still busy with the high voltage cycle then no ACKNOWL­EDGE will be returned. If the device has completed the write operation, an ACKNOWLEDGE will be returned and the host can then proceed with a read or write opera­tion. (Refer to Figure 5.)
X9522
)
N
WIPER COUNTER REGISTER
(WCR)
NON
VOLATILE
MEMORY
(NVM)
DECODER
“WIPER”
FET
SWITCHES
2
1
0
Figure 6. DCP Internal Structure
RESISTOR
ARRAY
R
Hx
R
Lx
R
Wx
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address Byte (Read or Write)
ACK
returned?
YES
High Voltage Cycle
complete. Continue
command sequence?
YES
Continue normal
Read or Write
command sequence
PROCEED
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
The X9522 includes three independent resistor arrays. These arrays respectively contain 63, 99 and 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the
Issue STOP
fixed terminals of a mechanical potentiometer (R
inputs - where x = 0,1,2).
R
Lx
At both ends of each array and between each resistor
NO
segment there is a CMOS switch connected to the wiper
) output. Within each individual array, only one
(R
x
w
switch may be turned on at any one time. These switches are controlled by the Wiper Counter Register (WCR) (See Figure 6). The WCR is a volatile register.
NO
Issue STOP
On power-up of the X9522, wiper position data is auto­matically loaded into the WCR from its associated Non Volatile Memory (NVM) Register. The Table below shows the Initial Values of the DCP WCR’s before the contents of the NVM is loaded into the WCR.
DCP Initial Values Before Recall
/ 64 TAP VH / TAP = 63
R
0
/ 100 TAP VL / TAP = 0
R
1
R
/ 256 TAP VH / TAP = 255
2
Hx
and
Figure 5. Acknowledge Polling Sequence
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January 3, 2006
Vcc
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X9522
Vcc (Max.)
V
TRIP
t
trans
0
Figure 7. DCP Power-up
The data in the WCR is then decoded to select and enable one of the respective FET switches. A “make before break” sequence is used internally for the FET switches when the wiper is moved from one tap position to another.
t
pu
Hot Pluggability
Figure 7 shows a typical waveform that the X9522 might experience in a Hot Pluggable situation. On power-up, Vcc / V1 applied to the X9522 may exhibit some amount of ringing, before it settles to the required value.
The device is designed such that the wiper terminal
) is recalled to the correct position (as per the last
(R
Wx
stored in the DCP NVM), when the voltage applied to Vcc / V1 exceeds V
Therefore, if t V1 to settle above V wiper terminal position is recalled by (a maximum) time:
t
+ tpu. It should be noted that t
trans
system hot plug conditions.
trans
for a time exceeding t
TRIP
is defined as the time taken for Vcc /
(Figure 7): then the desired
TRIP
trans
pu.
is determined by
DCP Operations
In total there are three operations that can be performed on any internal DCP structure:
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
A nonvolatile write to a DCP will change the “wiper position” by simultaneously writing new data to the associated WCR and NVM. Therefore, the new “wiper position” setting is recalled into the WCR after Vcc / V1 of the X9522 is powered down and then powered back up.
A volatile write operation to a DCP however, changes the “wiper position” by writing new data to the associated WCR only. The contents of the associated NVM register
t
Maximum Wiper Recall time
remains unchanged. Therefore, when Vcc / V1 to the device is powered down then back up, the “wiper position” reverts to that last position written to the DCP using a nonvolatile write operation.
Both volatile and nonvolatile write operations are executed using a three byte command sequence: (DCP) Slave Address Byte, Instruction Byte, followed by a Data Byte (See Figure 9).
A DCP Read operation allows the user to “read out” the current “wiper position” of the DCP, as stored in the associated WCR. This operation is executed using the Random Address Read command sequence, consisting of the (DCP) Slave Address Byte followed by an Instruction Byte and the Slave Address Byte again (Refer to Figure 10.).
Instruction Byte
While the Slave Address Byte is used to select the DCP devices, an Instruction Byte is used to determine which DCP is being addressed.
The Instruction Byte (Figure 8) is valid only when the Device Type Identifier and the Internal Device Address bits of the Slave Address are set to
1010111. In this case, the two Least Significant Bit’s (I1 - I0) of the Instruction Byte are used to select the particular DCP (0 - 2). In the case of a Write to any of the DCPs (i.e. the LSB of the Slave Address is 0), the Most Significant Bit of the Instruction Byte (I7), deter­mines the Write Type (WT) performed.
If WT is “1”, then a Nonvolatile Write to the DCP In this case, the “wiper position” of the DCP is changed by simultaneously writing new data to the associated WCR and NVM. Therefore, the new “wiper position” set­ting is recalled into the WCR after Vcc / V1 of the X9522 has been powered down then powered back up.
occurs.
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FN8208.1
January 3, 2006
X9522
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I5I6I7 I4 I3 I2 I1 I0
00WT 0 0 0 P1 P0
WRITE TYPE
WT
Select a Volatile Write operation to be performed
0
on the DCP pointed to by bits P1 and P0
Select a Nonvolatile Write operation to be per-
1
formed on the DCP pointed to by bits P1 and P0
This bit has no effect when a Read operation is being performed.
Description
DCP SELECT
Figure 8. Instruction Byte Format
If WT is “0” then a DCP Volatile Write is performed. This operation changes the DCP “wiper position” by writing new data to the associated WCR only. The contents of the associated NVM register remains unchanged. There­fore, when Vcc / V1 to the device is powered down then back up, the “wiper position” reverts to that last written to the DCP using a nonvolatile write operation.
DCP Write Operation
A write to DCPx (x=0,1,2) can be performed using the three byte command sequence shown in Figure 9.
In order to perform a write operation on a particular DCP, the Write Enable Latch (WEL) bit of the CONSTAT Reg­ister must first be set (See “WEL: Write Enable Latch (Volatile)” on page 10.)
The Slave Address Byte 10101110 specifies that a Write to a DCP is to be conducted. An ACKNOWLEDGE is returned by the X9522 after the Slave Address, if it has been received correctly.
Next, an Instruction Byte is issued on SDA. Bits P1 and P0 of the Instruction Byte determine which WCR is to be written, while the WT bit determines if the Write is to be volatile or nonvolatile. If the Instruction Byte format is valid, another ACKNOWLEDGE is then returned by the X9522.
Following the Instruction Byte, a Data Byte is issued to the X9522 over SDA. The Data Byte contents is latched into the WCR of the DCP on the first rising edge of the clock signal, after the LSB of the Data Byte (D0) has been issued on SDA (See Figure 25).
The Data Byte determines the “wiper position” (which FET switch of the DCP resistive array is switched ON) of the DCP. The maximum value for the Data Byte depends upon which DCP is being addressed (see Table below).
P1- P0 DCPx # Taps Max. Data Byte
00 x = 0 64 3Fh
0 1 x = 1 100 Refer to Appendix 1
1 0 x = 2 256 FFh
1 1 Reserved
Using a Data Byte larger than the values specified above results in the “wiper terminal” being set to the highest tap position. The “wiper position” does NOT roll-over to the lowest tap position.
For DCP0 (64 Tap) and DCP2 (256 Tap), the Data Byte maps one to one to the “wiper position” of the DCP “wiper terminal”. Therefore, the Data Byte 00001111
) corresponds to setting the “wiper terminal” to tap
(15
10
position 15. Similarly, the Data Byte 00011100 (28
10
corresponds to setting the “wiper terminal” to tap position
28. The mapping of the Data Byte to “wiper position” data for DCP1 (100 Tap), is shown in “APPENDIX 1”. An example of a simple C language function which “trans­lates” between the tap position (decimal) and the Data Byte (binary) for DCP1, is given in “APPENDIX 2”.
)
10101110
S T A R T
SLAVE ADDRESS BYTE
A
WT 0 0 0 0 0 P1 P0 A C K
INSTRUCTION BYTE
C K
Figure 9. DCP Write Command Sequence
8
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
A
T
C
O
K
P
FN8208.1
January 3, 2006
X9522
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S
WRITE Operation
Signals from the Master
t
a
r
Slave
Address
Instruction
Byte
t
SDA Bus
Signals from the Slave
101 11100
“Dummy” write
W
00 000
T
A C K
Figure 10. DCP Read Sequence
It should be noted that all writes to any DCP of the X9522 are random in nature. Therefore, the Data Byte of con­secutive write operations to any DCP can differ by an arbitrary number of bits. Also, setting the bits P1=1, P0=1 is a reserved sequence, and will result in no ACKNOWL­EDGE after sending an Instruction Byte on SDA.
The factory default setting of all “wiper position” settings is with 00h stored in the NVM of the DCPs. This corre-
R
sponds to having the “wiper teminal”
(x = 0,1,2) at
WX
the “lowest” tap position, Therefore, the resistance
R
between Wiper Resistance,
and RLX is a minimum (essentially only the
WX
R
).
W
DCP Read Operation
A read of DCPx (x = 0,1,2) can be performed using the three byte random read command sequence shown in Figure 10.
The master issues the START condition and the Slave Address Byte 10101110 which specifies that a “dummy” write” is to be conducted. This “dummy” write operation sets which DCP is to be read (in the preceding Read operation). An ACKNOWLEDGE is returned by the X9522 after the Slave Address if received correctly. Next, an Instruction Byte is issued on SDA. Bits P1-P0 of the Instruction Byte determine which DCP “wiper position” is to be read. In this case, the state of the WT bit is “don’t care”. If the Instruction Byte format is valid, then another ACKNOWLEDGE is returned by the X9522.
S
READ Operation
t
Slave
a
r
Address
Data Byte
t
P
P 1
101 11110
0
A C K
A C K
MSB
S
t o p
--
-
“-” = DON’T CARE
LSB
DCPx
x = 0
x = 1
x = 2
Following this ACKNOWLEDGE, the master immediately issues another START condition and a valid Slave address byte with the R/W
bit set to 1. Then the X9522 issues an ACKNOWLEDGE followed by Data Byte, and finally, the master issues a STOP condition. The Data Byte read in this operation, corresponds to the “wiper position” (value of the WCR) of the DCP pointed to by bits P1 and P0.
It should be noted that when reading out the data byte for DCP0 (64 Tap), the upper two most significant bits are “unknown” bits. For DCP1 (100 Tap), the upper most significant bit is an “unknown”. For DCP2 (256 Tap) however, all bits of the data byte are relevant (See Figure 10).
CONTROL AND STATUS REGISTER
The Control and Status (CONSTAT) Register pro­vides the user with a mechanism for changing and reading the status of various parameters of the X9522 (See Figure 11).
The CONSTAT register is a combination of both volatile and nonvolatile bits. The nonvolatile bits of the CON­STAT register retain their stored values even when Vcc / V1 is powered down, then powered back up. The volatile bits however, will always power-up to a known logic state “0” (irrespective of their value at power-down).
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CS6CS7 CS4
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CS5
0
Bit(s) Description
V2OS V2 Output Status flag
V3OS V3 Output Status flag
DWLK Sets the DCP Write Lock
RWEL Register Write Enable Latch bit
WEL Write Enable Latch bit
NOTE: Bits belled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
V3OS
V2OS
CS7 Always set to “0” (RESERVED)
CS4 Always set to “0” (RESERVED)
CS0 Always set to “0” (RESERVED)
CS3
CS2 CS1 CS0
0
DWLK
RWEL
WEL
0
NV
Figure 11. CONSTAT Register Format
A detailed description of the function of each of the CONSTAT register bits follows:
X9522
It must be noted that the RWEL bit can only be set, once the WEL bit has first been enabled (See "CONSTAT Register Write Operation").
The RWEL bit will reset itself to the default “0” state, in one of two cases:
—After a successful write operation to any bits of
the CONSTAT register has been completed (See Figure 12).
—When the X9522 is powered down.
DWLK: DCP Write Lock bit - (Nonvolatile)
The DCP Write Lock bit (DWLK) is used to inhibit a DCP write operation (changing the “wiper position”).
When the DCP Write Lock bit of the CONSTAT register is set to “1”, then the “wiper position” of the DCPs can­not be changed - i.e. DCP write operations cannot be conducted:
DWLK DCP Write Operation Permissible
0 YES (Default)
1NO
The factory default setting for this bit is DWLK = 0.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the entire X9522 device. This bit must first be enabled before ANY write operation (to DCPs, or the CONSTAT regis­ter). If the WEL bit is not first enabled, then ANY pro­ceeding (volatile or nonvolatile) write operation to DCPs, or the CONSTAT register, is aborted and no ACKNOWL­EDGE is issued after a Data Byte.
The WEL bit is a volatile latch that powers up in the dis­abled, LOW (0) state. The WEL bit is enabled / set by writing 00000010 to the CONSTAT register. Once enabled, the WEL bit remains set to “1” until either it is reset to “0” (by writing 00000000 to the CONSTAT regis­ter) or until the X9522 powers down, and then up again.
Writes to the WEL bit do not cause an internal high volt­age write cycle. Therefore, the device is ready for another operation immediately after a STOP condition is executed in the CONSTAT Write command sequence (See Figure 12).
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CONSTAT) Register Write Enable status of the X9522. Therefore, in order to write to any of the bits of the CONSTAT Register (except WEL), the RWEL bit must first be set to “1”. The RWEL bit is a volatile bit that powers up in the disabled, LOW (“0”) state.
IMPORTANT NOTE: If the Write Protect (WP) pin of the X9522 is active (HIGH), then nonvolatile write operations to the DCPs are inhibited, irrespective of the DCP Write Lock bit setting (See "WP: Write Protection Pin").
V2OS, V3OS: Voltage Monitor Status Bits (Volatile)
Bits V2OS and V3OS of the CONSTAT register are latched, volatile flag bits which indicate the status of the Voltage Monitor reset output pins V2RO and V3RO.
At power-up the VxOS (x=2,3) bits default to the value “0”. These bits can be set to a “1” by writing the appropri­ate value to the CONSTAT register. To provide consis­tency between the VxRO and VxOS however, the status of the VxOS bits can only be set to a “1” when the corre­sponding VxRO output is HIGH.
Once the VxOS bits have been set to “1”, they will be reset to “0” if:
—The device is powered down, then back up,
—The corresponding VxRO output becomes LOW.
10
FN8208.1
January 3, 2006
SCL
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SDA
X9522
S
1 010010R/WA T A R T
SLAVE ADDRESS BYTE
11111111 A C K
ADDRESS BYTE
Figure 12. CONSTAT Register Write Command Sequence
CONSTAT Register Write Operation
The CONSTAT register is accessed using the Slave Address set to 1010010 (Refer to Figure 4.). Following the Slave Address Byte, access to the CONSTAT regis­ter requires an Address Byte which must be set to FFh. Only one data byte is allowed to be written for each CONSTAT register Write operation. The user must issue a STOP, after sending this byte to the register, to initiate the nonvolatile cycle that stores the DWLK bit. The X9522 will not ACKNOWLEDGE any data bytes written after the first byte is entered (Refer to Figure 12.).
When writing to the CONSTAT register, the bits CS7, CS4 and CS0 must all be set to “0”. Writing any other bit sequence to bits CS7, CS4 and CS0 of the CONSTAT register is reserved.
Prior to writing to the CONSTAT register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps:
—Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a START and ended with a STOP).
CS7 CS6 C K
CONSTAT REGISTER DATA IN
CS5 CS4 CS3
CS2 CS1
CS0
A
S
C
T
K
O P
—Write a 06H to the CONSTAT Register to set the
Register Write Enable Latch (RWEL) AND the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceded by a START and ended with a STOP).
—Write a one byte value to the CONSTAT Register that
has all the bits set to the desired state. The CONSTAT register can be represented as 0xy0t010 in binary, where xy are the Voltage Monitor Output Status (V2OS and V3OS) bits, and t is the DCP Write Lock (DWLK) bit. This operation is proceeded by a START and ended with a STOP bit. Since this is a nonvolatile write cycle, it will typically take 5ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (0xy0 t110) then the RWEL bit is set, but the DWLK bit will remain unchanged. Writing a second byte to the control regis­ter is not allowed. Doing so aborts the write operation and the X9522 does not return an ACKNOWLEDGE.
For example, a sequence of writes to the device CON­STAT register consisting of [02H, 06H, 02H] will reset the nonvolatile (DWLK) bit in the CONSTAT Register to “0”.
WRITE Operation
Address
0
A C K
“Dummy” Write
Byte
S
t
a
r t
A C K
Slave
Address
0 1 0 0 1 0
Signals from the Master
SDA Bus
Signals from the Slave
S
t
Slave
a
Address
r
t
0 1 0 0 1 011
Figure 13. CONSTAT Register Read Command Sequence
11
READ Operation
CS7 … CS0
1
A C
Data
K
S
t o p
FN8208.1
January 3, 2006
It should be noted that a write to nonvolatile bit (DWLK)
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of CONSTAT register will be ignored if the Write Protect pin of the X9522 is active (HIGH) (See "WP: Write Pro­tection Pin").
X9522
Vx
V
TRIPx
0V
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at any time by performing a random read (See Figure 13). Using the Slave Address Byte set to 10100101, and an Address Byte of FFh. Only one byte is read by each reg­ister read operation. The X9522 resets itself after the first byte is read. The master should supply a STOP condition to be consistent with the bus protocol.
After setting the WEL and / or the RWEL bit(s) to a “1”, a CONSTAT register read operation may occur, without interrupting a proceeding CONSTAT register write operation.
When reading the contents of the CONSTAT register, the bits CS7, CS4 and CS0 will always return “0”.
DATA PROTECTION
There are a number of levels of data protection features designed into the X9522. Any write to the device first requires setting of the WEL bit in the CONSTAT register. A write to the CONSTAT register itself, further requires the setting of the RWEL bit. The DCP Write Lock of the device enables the user to inhibit writes to all DCPs. One further level of data protection in the X9522, is incorpo­rated in the form of the Write Protection pin.
WP: Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it disables nonvolatile write operations to the X9522.
The table below (X9522 Write Permission Status) sum­marizes the effect of the WP pin (and DCP Write Lock), on the write permission status of the device.
VxRO
Vcc / V1
0 Volts
(x = 2,3)
V
0V
TRIP
Figure 14. Voltage Monitor Response
Additional Data Protection Features
In addition to the preceding features, the X9522 also incorporates the following data protection functionality:
—The proper clock count and data bit sequence is
required prior to the STOP bit in order to start a nonvol­atile write cycle.
VOLTAGE MONITORING FUNCTIONS
V2 monitoring
The X9522 asserts the V2RO output HIGH if the volt­age V2 exceeds the corresponding V (See Figure 14). The bit V2OS in the CONSTAT regis­ter is then set to a “0” (assuming that it has been set to “1” after system initilization).
The V2RO output may remain active HIGH with Vcc down to 1V.
TRIP2
threshold
X9522 Write Permission Status
DWLK
(DCP Write Lock
bit status)
1 1 NO NO NO NO
01YESNONONO
1
0
(Write Protect pin
WP
status)
0
0
12
DCP Volatile Write
Permitted
NO NO YES YES
YES YES YES YES
DCP Nonvolatile
Write Permitted
Write to CONSTAT Register
Volatile Bits Nonvolatile Bits
Permitted
FN8208.1
January 3, 2006
V2, V3
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WP
V
TRIPx
X9522
V
P
SCL
SDA
01234567
S T A R
T
A0h
Figure 15. Setting V
01234567
09h† sets V 0Dh† sets V
TRIPx
V3 monitoring
The X9522 asserts the V3RO output HIGH if the volt­age V3 exceeds the corresponding V (See Figure 14). The bit V3OS in the CONSTAT regis­ter is then set to a “0” (assuming that it has been set to “1” after system initilization).
The V3RO output may remain active HIGH with Vcc down to 1V.
V
THRESHOLDS (X = 2,3)
TRIPX
The X9522 is shipped with pre-programmed threshold (V
) voltages. In applications where the required
TRIPx
thresholds are different from the default values, or if a
TRIP3
threshold
01234567
00h
All others Reserved.
TRIP1
TRIP2
Data Byte
to a higher level (x = 1,2).
higher precision / tolerance is required, the X9522 trip points may be adjusted by the user, using the steps detailed below.
Setting a V
Voltage (x = 2,3)
TRIPx
There are two procedures used to set the threshold voltages (V
), depending if the threshold voltage
TRIPx
to be stored is higher or lower than the present value. For example, if the present V new V directly into the V
is 3.2 V, the new voltage can be stored
TRIPx
cell. If however, the new setting
TRIPx
is 2.9 V and the
TRIPx
is to be lower than the present setting, then it is neces­sary to “reset” the V
voltage before setting the
TRIPx
new value.
V
P
WP
01234567
00h
Data Byte
Level (x = 2,3)
SCL
SDA
01234567
S T A R
T
A0h
13
01234567
0Bh† Resets
0Fh† Resets
VTRIP2
VTRIP3
Figure 16. Resetting the V
TRIPx
All others Reserved.
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January 3, 2006
X9522
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Setting a Higher V
To set a V
threshold to a new voltage which is
TRIPx
Voltage (x = 2,3)
TRIPx
higher than the present threshold, the user must apply the desired V
threshold voltage to the corre-
TRIPx
sponding input pin (V2 or V3). Then, a programming voltage (Vp) must be applied to the WP pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h, followed by the Byte Address 09h for V
, and 0Dh for V
TRIP3
Data Byte in order to program V
TRIPx
, and a 00h
TRIP3
. The STOP bit following a valid write operation initiates the program­ming sequence. Pin WP must then be brought LOW to complete the operation (See Figure 16). The user does not have to set the WEL bit in the CONSTAT reg­ister before performing this write sequence.
Setting a Lower V
In order to set V present value, then V ing to the procedure described below. Once V has been “reset”, then V
Voltage (x = 2,3)
TRIPx
to a lower voltage than the
TRIPx
must first be “reset” accord-
TRIPx
can be set to the desired
TRIPx
TRIPx
voltage using the procedure described in “Setting a Higher V
Resetting the V
To reset a V
TRIPx
Voltage”.
Voltage
TRIPx
voltage, apply the programming volt-
TRIPx
age (Vp) to the WP pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h followed by the Byte Address 0Bh for
, and 0Fh for V
V
TRIP2
Data Byte in order to reset V
, followed by 00h for the
TRIP3
. The STOP bit fol-
TRIPx
lowing a valid write operation initiates the program­ming sequence. Pin WP must then be brought LOW to complete the operation (See Figure 16).The user does not have to set the WEL bit in the CONSTAT register before performing this write sequence.
After being reset, the value of V
becomes a nomi-
TRIPx
nal value of 1.7V.
Once the desired V
threshold has been set, the
TRIPx
error between the desired and (new) actual set threshold can be determined. This is achieved by applying Vcc / V1 to the device, and then applying a test voltage higher than the desired threshold voltage, to the input pin of the voltage monitor circuit whose V For example, if V
was set to a desired level of 3.0 V,
TRIP2
was programmed.
TRIPx
then a test voltage of 3.4 V may be applied to the voltage monitor input pin V2. In all cases, care should be taken not to exceed the maximum input voltage limits.
After applying the test voltage to the voltage monitor input pin, the test voltage can be decreased (either in dis­crete steps, or continuously) until the output of the volt­age monitor circuit changes state. At this point, the error between the actual / measured, and desired threshold levels is calculated.
For example, the desired threshold for V
TRIP2
is set to
3.0 V, and a test voltage of 3.4 V was applied to the input pin V2 (after applying power to Vcc / V1). The input volt­age is decreased, and found to trip the associated output level of pin V2RO from a LOW to a HIGH, when V2 reaches 3.09 V. From this, it can be calculated that the programming error is 3.09 - 3.0 = 0.09 V.
If the error between the desired and measured V
TRIPx
less than the maximum desired error, then the program­ming process may be terminated. If however, the error is greater than the maximum desired error, then another iteration of the V
programming sequence can be
TRIPx
performed (using the calculated error) in order to further increase the accuracy of the threshold voltage.
If the calculated error is greater than zero, then the V a value equal to the previously set V
must first be “reset”, and then programmed to the
TRIPx
minus the cal-
TRIPx
culated error. If it is the case that the error is less than zero, then the V equal to the previously set V
must be programmed to a value
TRIPx
plus the absolute value
TRIPx
of the calculated error.
is
V
The accuracy with which the V
Accuracy (x = 2,3)
TRIPx
thresholds are set,
TRIPx
can be controlled using the iterative process shown in Figure 17.
If the desired threshold is less that the present threshold voltage, then it must first be “reset” (See "Resetting the VTRIPx Voltage").
The desired threshold voltage is then applied to the appropriate input pin (V2 or V3) and the procedure described in Section “Setting a Higher V
TRIPx
Voltage“
Continuing the previous example, we see that the calcu­lated error was 0.09V. Since this is greater than zero, we must first “reset” the V age equal to the last previously programmed voltage, minus the last previously calculated error. Therefore, we must apply V programming sequence (See "Setting a Higher VTRIPx Voltage (x = 2,3)" ) .
Using this process, the desired accuracy for a particu­lar V
threshold may be attained using a succes-
TRIPx
sive number of iterations.
must be followed.
14
threshold, then apply a volt-
TRIP2
= 2.91 V to pin V2 and execute the
TRIP1
FN8208.1
January 3, 2006
X9522
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New Vx applied =
Old Vx applied
+ | Error |
V
NO
Set Vx = desired
Apply Vcc & Voltage
> Desired V
NO
Programming
TRIPx
Desired V
present value?
Execute
V
TRIPx
Sequence
Execute
Set Higher
Sequence
Decrease Vx
Output
switches?
TRIPx
YES
Reset
V
TRIPx
TRIPx
<
V
TRIPx
to Vx
Desired Value
New Vx applied =
Old Vx applied
Execute
Reset
Sequence
Note: X = 1,2,3.
Let: MDE = Maximum Desired Error
+
MDE
Acceptable
Error Range
MDE
Error = Actual – Desired
- | Error |
V
TRIPx
Error < MDE
Figure 17. V
YES
Actual V
- Desired V
= Error
TRIPx
TRIPx
Error >MDE
| Error | < | MDE |
DONE
Setting / Reset Sequence (x = 1,2,3)
TRIPx
+
15
FN8208.1
January 3, 2006
X9522
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ABSOLUTE MAXIMUM RATINGS
Parameter Min. Max. Units
Temperature under Bias -65 +135 °C Storage Temperature -65 +150 °C Voltage on WP pin (With respect to Vss) -1.0 +15 V Voltage on other pins (With respect to Vss) -1.0 +7 V
| Voltage on R
- Voltage on R
Hx
D.C. Output Current (SDA,V2RO,V3RO)
| (x = 0,1,2. Referenced to Vss)
Lx
0
Lead Temperature (Soldering, 10 seconds) 300 °C Supply Voltage Limits (Applied Vcc / V1 voltage, referenced to Vss) 2.7 5.5 V
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max. Units
Industrial -40 +85
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended peri­ods may affect device reliability
Vcc / V1 V
5mA
°C
Figure 18. Equivalent A.C. Circuit
Figure 19. DCP SPICE Macromodel
SDA
V2RO V3RO
R
Hx
10pF
Vcc / V1 = 5V
R
TOTAL
C
H
R
Wx
2300Ω
100pF
R
W
C
25pF
R
Lx
C
L
10pF
W
(x = 0,1,2)
16
FN8208.1
January 3, 2006
TIMING DIAGRAMS
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Figure 20. Bus Timing
X9522
SCL
t
SU:SA
SDA IN
t
HD:STA
SDA OUT
Figure 21. WP Pin Timing
START
SCL
SDA IN
WP
t
F
t
SU:DAT
t
SU:WP
t
HIGH
t
LOW
t
HD:DAT
t
R
t
AA
Clk 1 Clk 9
t
HD:WP
t
DH
t
BUF
t
SU:STO
Figure 22. Write Cycle Timing
SCL
SDA
8th bit of last byte ACK
Stop
Condition
t
WC
Start
Condition
17
FN8208.1
January 3, 2006
Figure 23. V2, V3 Timing Diagram
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X9522
Vx
VxRO
Vcc / V1
Note : x = 2,3.
Figure 24. V
V2, V3
t
Rx
t
RPDx
Programming Timing Diagram (x = 2,3)
TRIPX
t
RPDx
V
TRIPx
t
RPDx
t
Fx
V
RVALID
t
RPDx
V
TRIPx
0 Volts
0 Volts
V
TRIP
0 Volts
V
WP
SCL
SDA
t
TSU
P
t
VPS
t
wc
00h
t
VPH
t
THD
t
VPO
NOTE : Vcc / V1 must be greater than V2, V3 when programming.
18
FN8208.1
January 3, 2006
Figure 25. DCP “Wiper Position” Timing
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Rwx (x = 0,1,2)
R
wx(n)
X9522
t
wr
R
wx(n + 1)
R
wx(n - 1)
SCL
SDA
n = tap position
10101110
S T A R
T
SLAVE ADDRESS BYTE
A
WT 0 0 0 0 0 P1 P0 A C K
INSTRUCTION BYTE
D7 D6 D5 D4 D3 D2 D1 D0
C K
DATA BYTE
Time
S
A
T
C
O
K
P
19
FN8208.1
January 3, 2006
X9522
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D.C. OPERATING CHARACTERISTICS
Symbol Parameter Min Typ Max Unit Test Conditions / Notes
I
CC1
I
CC2
I
LI
I
ai
I
LO
V
TRIPxPR
V
TRIP1
V
TRIP2
I
Vx
(7)
V
IL
VIH
V
OLx
(2)
(7)
(1)
(6)
(6)
Current into Vcc / V1 Pin
Write nonvolatile memory
Current into Vcc / V1 Pin
With 2-Wire bus activity
Input Leakage Current (SCL, SDA)
Input Leakage Current (WP)
Analog Input Leakage 1 10 µA
Output Leakage Current (SDA, V2RO,
V3RO)
V
Programming Range (x = 1,2)
TRIPx
Pre - programmed V
Pre - programmed V
V2 Input leakage current V3 Input leakage current
Input LOW Voltage (SCL, SDA, WP) -0.5 0.8 V
Input HIGH Voltage (SCL,SDA, WP) 2.0
V2RO, V3RO, SDA Output Low Voltage 0.4 V
(X9522: Active)
Read memory array
(X9522:Standby)
No 2-Wire bus activity
threshold
TRIP1
threshold
TRIP2
(3)
(3)
0.1 10 μA
0.1 10 μA
1.8 4.70 V
1.65
2.85
1.65
2.85
1.8
3.0
1.8
3.0
0.4
1.5
50 50
10 μA
1.85
3.05
1.85
3.05
1 1
Vcc / V1
+0.5
f
= 400kHz
mA
μA
SCL
= Vcc / V1
V
SDA
WP = Vss or Open/Floating V
= Vcc / V1 (when no bus ac-
SCL
tivity else f
(4)
V
= GND to Vcc / V1
IN
= VSS to VCC with all other an-
V
IN
= 400kHz)
SCL
alog pins floating
(5)
V X9522 is in Standby
Factory shipped default option A
V
Factory shipped default option B
Factory shipped default option A
V
Factory shipped default option B
V
μA
Others = GND or Vcc / V1
V
I
= GND to Vcc / V1
OUT
= V
SDA
SINK
SCL
= 2.0mA
(2)
= Vcc / V1
.
.
Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200nS after a STOP ending a read operation; or t
Notes: 2. The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; t
a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address Byte.
Notes: 3. Current through external pull up resistor not included.
Notes: 4. V
Notes: 5. V
Notes: 6. See Ordering Information on page 2.
Notes: 7. V
= Voltage applied to input pin.
IN
= Voltage applied to output pin.
OUT
Min. and VIH Max. are for reference only and are not tested.
IL
after a STOP ending a write operation.
WC
after a STOP that initiates
WC
20
FN8208.1
January 3, 2006
X9522
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A.C. CHARACTERISTICS (See Figure 20, Figure 21, Figure 22)
Symbol Parameter
f
SCL
(5)
t
IN
(5)
t
AA
t
BUF
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
(5)
t
DH
(5)
t
R
(5)
t
F
t
SU:WP
t
HD:WP
(5)
Cb
(5)
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
WP Hold Time
Capacitive load for each bus line
400kHz
Min Max Units
0 400 kHz
50 ns
0.1 0.9
1.3
1.3
0.6
0.6
0.6
100 ns
0
0.6
50 ns
20 +.1Cb
20 +.1Cb
0.6
0
(2)
(2)
300 ns
300 ns
400 pF
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
A.C. TEST CONDITIONS
Input Pulse Levels 0.1Vcc to 0.9Vcc
Input Rise and Fall Times 10ns
Input and Output Timing Levels 0.5Vcc
Output Load See Figure 18
NONVOLATILE WRITE CYCLE TIMING
Symbol Parameter Min. Typ.(1) Max. Units
(4)
t
WC
CAPACITANCE (T
Symbol Parameter Max Units Test Conditions
(5)
C
OUT
(5)
CIN
Notes: 1. Typical values are for TA = 25°C and Vcc / V1 = 5.0V Notes: 2. Cb = total capacitance of one bus line in pF.
Notes: 3. Over recommended operating conditions, unless otherwise specified
Notes: 4. t
Notes: 5. This parameter is not 100% tested.
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
WC
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Nonvolatile Write Cycle Time 5 10 ms
= 25°C, F = 1.0 MHZ, VCC / V1 = 5V)
A
Output Capacitance (SDA, V2RO, V3RO) 8 pF
Input Capacitance (SCL, WP) 6 pF
V
OUT
V
IN
= 0V
= 0V
21
FN8208.1
January 3, 2006
POTENTIOMETER CHARACTERISTICS
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Symbol Parameter
R
V
V
P
R
I
TOL
RHx
RLx
R
W
W
End to End Resistance Tolerance -20 +20 %
RH Terminal Voltage (x = 0,1,2)
RL Terminal Voltage (x = 0,1,2)
Power Rating
(1)(6
)
DCP Wiper Resistance
Wiper Current
(6)
Noise
(2)
(3)
C
H/CL/CW
Absolute Linearity
Relative Linearity
R
Temperature Coefficient
TOTAL
Potentiometer Capacitances
X9522
Limits
Vss
Vss
200 400 Ω
400 1200 Ω
-1 +1
-1 +1
±300 ppm/°C
±300 ppm/°C
10/10/25
Vcc /
Vcc /
V1
V1
V
V
10 mW
5mW
4.4 mA
mV/
sqt(Hz)
mV/
sqt(Hz)
(4)
MI
(4)
MI
pF
Test Conditions/NotesMin. Typ. Max. Units
R
= 10kΩ (DCP0,
TOTAL
DCP1)
R
I V
= 100kΩ (DCP2)
TOTAL
= 1mA, Vcc / V1 = 5 V,
W
= Vcc / V1, V
RHx
RLx
(x = 0,1,2).
= 1mA, Vcc / V1 = 2.7 V,
I
W
V
= Vcc / V1, V
RHx
RLx
(x = 0,1,2)
R
= 10kΩ (DCP0,
TOTAL
DCP1)
R
R
R
R
= 100kΩ (DCP2)
TOTAL
w(n)(actual)
- [R
w(n+1)
= 10kΩ (DCP0,
TOTAL
- R
w(n)(expected)
w(n) + MI
]
DCP1)
R
= 100kΩ (DCP2)
TOTAL
See Figure 19.
= Vss
= Vss
t
wr
V
TRIP
t
PU
Notes: 1. Power Rating between the wiper terminal R
Notes: 2. Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (R
Notes: 3. Relative Linearity is a measure of the error in step size between taps = R
Notes: 4. 1 Ml = Minimum Increment = R
Notes: 5. Typical values are for T
Notes: 6. This parameter is periodically sampled and not 100% tested.
Wiper Response time
Vcc / V1 power-up DCP recall threshold
Vcc / V1 power-up DCP recall delay
(6)
time
Ml Maximum (x = 0,1,2).
= 25°C and nominal supply voltage.
A
(6)
and the end terminals RHX or RLX - for ANY tap position n, (x = 0,1,2).
WX(n)
/ (Number of taps in DCP - 1).
TOT
200
25 50 75
- [R
Wx(n+1)
μs
V
ms
+ Ml] = ±1 Ml (x = 0,1,2)
wx(n)
22
See Figure 25.
(actual) - R
wx(n)
(expected)) = ±1
wx(n)
January 3, 2006
FN8208.1
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V
(X = 1,2) PROGRAMMING PARAMETERS (See Figure 24)
TRIPX
Parameter Description Min Typ Max Units
V
t
VPS
t
VPH
t
TSU
t
THD
t
VPO
t
wc
V
P
V
ta
V
tv
Notes: These parameters are not 100% tested.
Program Enable Voltage Setup time
TRIPx
V
Program Enable Voltage Hold time
TRIPx
V
Setup time
TRIPx
V
Hold (stable) time
TRIPx
V
Program Enable Voltage Off time
TRIPx
(Between successive adjustments)
V
Write Cycle time
TRIPx
10 μs
10 μs
10 μs
10 μs
1ms
510 ms
Programming Voltage 10 15 V
V
Program Voltage accuracy
TRIPx
(Programmed at 25
V
Program variation after programming (-40 - 85°C).
TRIP
°
C.)
(Programmed at 25°C.)
-100 +100 mV
-25 +10 +25 mV
V2RO, V3RO OUTPUT TIMING. (See Figure 23)
Symbol Description Condition Min. Typ. Max. Units
t
RPDx
(4)
t
Fx
t
(4)
Rx
V
RVALID
(4)
(4)
V2, V3 to V2RO, V3RO propagation delay (respectively)
20 μs
V2, V3 Fall Time 20 mV/μs
V2, V3 Rise Time 20 mV/μs
Vcc / V1 for V2RO, V3RO Valid
(3)
.
1V
Notes: 1. See Figure 23 for timing diagram.
Notes: 2. See Figure 18 for equivalent load.
Notes: 3. This parameter describes the lowest possible Vcc / V1 level for which the outputs V2RO, and V3RO will be correct with respect to their
inputs ( V2, V3).
Notes: 4. The above parameters are not 100% tested.
23
FN8208.1
January 3, 2006
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APPENDIX 1
DCP1 (100 Tap) Tap position to Data Byte translation Table
Tap
Position
0 0 0000 0000
1 1 0000 0001
. .
23 23 0001 0111
24 24 0001 1000
25 56 0011 1000
26 55 0011 0111
. .
48 33 0010 0001
49 32 0010 0000
50 64 0100 0000
51 65 0100 0001
. .
73 87 0101 0111
74 88 0101 1000
75 120 0111 1000
76 119 0111 0111
. .
98 97 0110 0001
99 96 0110 0000
Decimal Binary
. .
. .
. .
. .
Data Byte
. .
. .
. .
. .
24
FN8208.1
January 3, 2006
X9522
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APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1)
unsigned DCP1_TAP_Position(int tap_pos) {
int block; int i; int offset; int wcr_val;
offset= 0; block = tap_pos / 25;
if (block < 0) return ((unsigned)0);
else if (block <= 3) { switch(block)
{ case (0): return ((unsigned)tap_pos) ;
}
case (1): {
wcr_val = 56; offset = tap_pos - 25; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val);
}
case (2): {
wcr_val = 64; offset = tap_pos - 50; for (i=0; i<= offset; i++) wcr_val++ ; return ((unsigned)--wcr_val);
}
case (3): {
wcr_val = 120; offset = tap_pos - 75; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val);
}
} } return((unsigned)01100000);
25
FN8208.1
January 3, 2006
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APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 2)
unsigned DCP100_TAP_Position(int tap_pos) { /* optional range checking */ if (tap_pos < 0) return ((unsigned)0); /* set to min val */ else if (tap_pos >99) return ((unsigned) 96); /* set to max val */
/* 100 Tap DCP encoding formula */ if (tap_pos > 74) return ((unsigned) (195 - tap_pos)); else if (tap_pos > 49) return ((unsigned) (14 + tap_pos)); else if (tap_pos > 24) return ((unsigned) (81 - tap_pos)); else return (tap_pos); }
26
FN8208.1
January 3, 2006
X9522
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20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
0° - 8 °
.0075 (.19) .0118 (.30)
.252 (6.4) .260 (6.6)
.019 (.50) .029 (.75)
Detail A (20X)
.169 (4.3) .177 (4.5)
.047 (1.20)
.002 (.05) .006 (.15)
.010 (.25)
Gage Plane
Seating Plane
.252 (6.4) BSC
(1.78)
(0.42)
(0.65)
(4.16)
(7.72)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
27
ALL MEASUREMENTS ARE TYPICAL
FN8208.1
January 3, 2006
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