intersil X9521 DATA SHEET

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Data Sheet January 3, 2006

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Dual DCP, EEPROM Memory

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X9521

FN8207.1

Fiber Channel/Gigabit Ethernet Laser
Diode Control for Fiber Optic Modules

FEATURES

• Two Digitally Controlled Potentiometers (DCP’s)
—100 Tap - 10kΩ
—256 Tap - 100kΩ
—Non-Volatile
—Write Protect Function

• 2kbit EEPROM Memory with Write Protect & Block

• 2-Wire industry standard Serial Interface

• Single Supply Operation

• Hot Pluggable

• 20 Ld TSSOP

BLOCK DIAGRAM

TM

Lock

—Complies to the Gigabit Interface Converter

(GBIC) specification

—2.7V to 5.5V

8

WP

PROTECT LOGIC

DESCRIPTION

The X9521 combines two Digitally Controlled Potentiom­eters (DCP’s), and integrated EEPROM with Block

TM

Lock

protection. All functions of the X9521 are

accessed by an industry standard 2-Wire serial interface.

The DCP’s of the X9521 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber
Optic module. The 2kbit integrated EEPROM may be
used to store module definition data.

The features of the X9521 are ideally suited to simplifying
the design of fiber optic modules which comply to the Gi­gabit Interface Converter (GBIC) specification. The inte­gration of these functions into one package significantly
reduces board area, cost and increases reliability of laser
diode modules.

R

WIPER
COUNTER
REGISTER

7 - BIT

NONVOLATILE

MEMORY

H1

R

W1

R

L1

CONSTAT

REGISTER

2kbit

EEPROM

ARRAY

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

©2000 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

SDA

SCL

DATA

REGISTER

COMMAND
DECODE &

CONTROL

LOGIC

THRESHOLD

RESET LOGIC

1

4

WIPER
COUNTER
REGISTER

8 - BIT

NONVOLATILE

MEMORY

R

H2

R

W2

R

L2

Ordering Information

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X9521

PRESET (FACTORY SHIPPED) V

PART NUMBER PART MARKING

X9521V20I-A X9521VIA Optimized for 3.3V system monitoring -40 to +85 20 Ld TSSOP
X9521V20I-B X9521VIB Optimized for 5V system monitoring -40 to +85 20 Ld TSSOP
X9521V20IZ-A (Note) X9521VZIA Optimized for 3.3V system monitoring -40 to +85 20 Ld TSSOP (Pb-free)
X9521V20IZ-B (Note) X9521VZIB Optimized for 5V system monitoring -40 to +85 20 Ld TSSOP (Pb-free)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

THRESHOLD LEVELS (x = 2, 3) TEMP RANGE (°C) PACKAGE

TRIPx

PIN CONFIGURATION

20 Pin TSSOP

R

H2

R

W2 2

R

L2

NC
NC

NC

WP

SCL

SDA

V

SS

10

20

1

19

3

18

4

17

5

16

6

15

7

14

8

13

9

12
11

Vcc

NC

NC
NC
NC

NC

NC
R

H1

R

W1

R

L1

PIN ASSIGNMENT

Pin Name Function

1

2

3

7WP

8SCL

9SDA

10 Vss Ground.

11

12

13

20 Vcc Supply Voltage.

4, 5, 6,
14, 15,
16, 17,

18, 19

R

H2

R

w2

R

L2

R

L1

R

w1

R

H1

NC No connect.

Connection to end of resistor array for (the 256 Tap) DCP 2.

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.

Connection to other end of resistor array for (the 256 Tap) DCP2.

Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is
enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write Pro­tection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then
no “write” (volatile or nonvolatile) operations can be performed in the device (including the wiper position
of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull­down” resistor, thus if left floating the write protection feature is disabled.

Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input
and output.

Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the de­vice. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor.

Connection to other end of resistor for (the 100 Tap) DCP 1.

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1

Connection to end of resistor array for (the 100 Tap) DCP 1.

2

FN8207.1

January 3, 2006

SCL

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SDA

SCL

SDA

X9521

Start Stop

Figure 2. Valid Start and Stop Conditions

Data Stable Data Change Data Stable

Figure 1. Valid Data Changes on the SDA Bus

PRINCIPLES OF OPERATION

SERIAL INTERFACE

Serial Interface Conventions

The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the
slave. The master always initiates data transfers, and
provides the clock for both transmit and receive opera­tions. Therefore, the X9521 operates as a slave in all
applications.

Serial Clock and Data

Data states on the SDA line can change only while SCL
is LOW. SDA state changes while SCL is HIGH are
reserved for indicating START and STOP conditions.
See Figure 1. On power-up of the X9521, the SDA pin is
in the input mode.

Serial Start Condition

All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not respond
to any command until this condition has been met. See
Figure 2.

Serial Stop Condition

All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. The STOP condition is also used to
place the device into the Standby power mode after a
read sequence. A STOP condition can only be issued
after the transmitting device has released the bus. See
Figure 2.

Serial Acknowledge

An ACKNOWLEDGE (ACK) is a software convention
used to indicate a successful data transfer. The transmit­ting device, either master or slave, will release the bus
after transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to ACKNOWL­EDGE that it received the eight bits of data. Refer to
Figure 3.

The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If
a write operation is selected, the device will respond with
an ACKNOWLEDGE after the receipt of each subse­quent eight bit word.

In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected
and no STOP condition is generated by the master, the
device will continue to transmit data. The device will ter­minate further data transmissions if an ACKNOWLEDGE
is not detected. The master must then issue a STOP
condition to place the device into a known state.

3

FN8207.1

January 3, 2006

SCL

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SCL

from

from

Master

Master

Data Output

from

Transmitter

Data Output

from

Receiver

Start Acknowledge

Figure 3. Acknowledge Response From Receiver

DEVICE INTERNAL ADDRESSING

Addressing Protocol Overview

The user addressable internal components of the X9521
can be split up into three main parts:

—Two Digitally Controlled Potentiometers (DCPs)

—EEPROM array

—Control and Status (CONSTAT) Register

Depending upon the operation to be performed on each
of these individual parts, a 1, 2 or 3 Byte protocol is used.
All operations however must begin with the Slave
Address Byte being issued on the SDA pin. The Slave
address selects the part of the X9521 to be addressed,
and specifies if a Read or Write operation is to be per­formed.

X9521

81 9

—The next three bits (SA3 - SA1) are the Internal Device

Address bits. Setting these bits to 000 internally
selects the EEPROM array, while setting these bits to
111 selects the DCP structures in the X9521. The
CONSTAT Register may be selected using the Inter­nal Device Address 010.

—The Least Significant Bit of the Slave Address (SA0)

Byte is the R/W

bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W

bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)

SA6SA7

SA5

1010

SA4

SA3 SA2

SA1

SA0

R/W

It should be noted that in order to perform a write opera­tion to either a DCP or the EEPROM array, the Write
Enable Latch (WEL) bit must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 12.)

Slave Address Byte

Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con­sists of three parts:

—The Device Type Identifier which consists of the most

significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9521.

DEVICE TYPE

IDENTIFIER

Internal Address

(SA3 - SA1)

000

010

111

Bit SA0 Operation

0WRITE

1 READ

INTERNAL

DEVICE

ADDRESS

Internally Addressed

Device

EEPROM Array

CONSTAT Register

DCP

Figure 4. Slave Address Format

READ /
WRITE

4

FN8207.1

January 3, 2006

Nonvolatile Write Acknowledge Polling

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After a nonvolatile write command sequence (for either
the EEPROM array, the Non Volatile Memory of a DCP
(NVM), or the CONSTAT Register) has been correctly
issued (including the final STOP condition), the X9521
initiates an internal high voltage write cycle. This cycle
typically requires 5 ms. During this time, no further Read
or Write commands can be issued to the device. Write
Acknowledge Polling is used to determine when this high
voltage write cycle has been completed.

To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal
Device Address. The LSB of the Slave Address (R/W
can be set to either 1 or 0 in this case. If the device is still
busy with the high voltage cycle then no ACKNOWL­EDGE will be returned. If the device has completed the
write operation, an ACKNOWLEDGE will be returned
and the host can then proceed with a read or write opera­tion. (Refer to Figure 5.).

X9521

)

N

WIPER
COUNTER
REGISTER

(WCR)

NON

VOLATILE

MEMORY

(NVM)

DECODER

“WIPER”

FET

SWITCHES

2

1

0

RESISTOR

ARRAY

Figure 6. DCP Internal Structure

DIGITALLY CONTROLLED POTENTIOMETERS

R

Hx

R

Lx

R

Wx

Byte load completed

by issuing STOP.

Enter ACK Polling

Issue START

Issue Slave Address
Byte (Read or Write)

ACK

returned?

YES

High Voltage Cycle

complete. Continue

command sequence?

YES

Continue normal

Read or Write

command sequence

DCP Functionality

The X9521 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
inputs - where x = 1,2).

At both ends of each array and between each resistor

Issue STOP

segment there is a CMOS switch connected to the wiper

) output. Within each individual array, only one

(R

x

w

switch may be turned on at any one time. These

NO

switches are controlled by the Wiper Counter Register
(WCR) (See Figure 6). The WCR is a volatile register.

On power-up of the X9521, wiper position data is auto­matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below

NO

Issue STOP

shows the Initial Values of the DCP WCR’s before the
contents of the NVM is loaded into the WCR.

DCP Initial Values Before Recall

/ 100 TAP VL / TAP = 0

R

1

R2 / 256 TAP VH / TAP = 255

and R

Hx

Lx

PROCEED

Figure 5. Acknowledge Polling Sequence

5

FN8207.1

January 3, 2006

Vcc

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X9521

Vcc (Max.)

V

TRIP

t

trans

0

Figure 7. DCP Power-up

The data in the WCR is then decoded to select and
enable one of the respective FET switches. A “make
before break” sequence is used internally for the FET
switches when the wiper is moved from one tap position
to another.

t

pu

Hot Pluggability

Figure 7 shows a typical waveform that the X9521 might
experience in a Hot Pluggable situation. On power-up,
Vcc applied to the X9521 may exhibit some amount of
ringing, before it settles to the required value.

The device is designed such that the wiper terminal

) is recalled to the correct position (as per the last

(R

Wx

stored in the DCP NVM), when the voltage applied to
Vcc exceeds V

Therefore, if
settle above V
minal position is recalled by (a maximum) time:

t

. It should be noted that t

pu

tem hot plug conditions.

t

trans

for a time exceeding tpu.

TRIP

is defined as the time taken for Vcc to

(Figure 7): then the desired wiper ter-

TRIP

is determined by sys-

trans

t

trans

DCP Operations

In total there are three operations that can be performed
on any internal DCP structure:

—DCP Nonvolatile Write

—DCP Volatile Write

—DCP Read

A nonvolatile write to a DCP will change the “wiper
position” by simultaneously writing new data to the
associated WCR and NVM. Therefore, the new “wiper
position” setting is recalled into the WCR after Vcc of the
X9521 is powered down and then powered back up.

A volatile write operation to a DCP however, changes the
“wiper position” by writing new data to the associated
WCR only. The contents of the associated NVM register

t

Maximum Wiper Recall time

remains unchanged. Therefore, when Vcc to the device
is powered down then back up, the “wiper position”
reverts to that last position written to the DCP using a
nonvolatile write operation.

Both volatile and nonvolatile write operations are
executed using a three byte command sequence: (DCP)
Slave Address Byte, Instruction Byte, followed by a Data
Byte (See Figure 9).

A DCP Read operation allows the user to “read out” the
current “wiper position” of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consisting
of the (DCP) Slave Address Byte followed by an
Instruction Byte and the Slave Address Byte again (Refer
to Figure 11.).

Instruction Byte

+

While the Slave Address Byte is used to select the DCP
devices, an Instruction Byte is used to determine which
DCP is being addressed.

The Instruction Byte (Figure 8) is valid only when the
Device Type Identifier and the Internal Device
Address bits of the Slave Address are set to

1010111. In this case, the two Least Significant Bit’s
(I1 - I0) of the Instruction Byte are used to select the
particular DCP (0 - 2). In the case of a Write to any of
the DCPs (i.e. the LSB of the Slave Address is 0), the
Most Significant Bit of the Instruction Byte (I7), deter­mines the Write Type (WT) performed.

If WT is “1”, then a Nonvolatile Write to the DCP
In this case, the “wiper position” of the DCP is changed
by simultaneously writing new data to the associated
WCR and NVM. Therefore, the new “wiper position” set­ting is recalled into the WCR after Vcc of the X9521 has
been powered down then powered back up

occurs.

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FN8207.1

January 3, 2006

X9521

www.BDTIC.com/Intersil

I5I6I7 I4 I3 I2 I1 I0

00WT 0 0 0 P1 P0

WRITE TYPE

†

WT

Select a Volatile Write operation to be performed

0

on the DCP pointed to by bits P1 and P0

Select a Nonvolatile Write operation to be per-

1

formed on the DCP pointed to by bits P1 and P0

†

This bit has no effect when a Read operation is being performed.

Description

DCP SELECT

Figure 8. Instruction Byte Format

If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only. The contents of
the associated NVM register remains unchanged. There­fore, when Vcc to the device is powered down then back
up, the “wiper position” reverts to that last written to the
DCP using a nonvolatile write operation.

DCP Write Operation

A write to DCPx (x = 1,2) can be performed using the
three byte command sequence shown in Figure 9.

In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Reg­ister must first be set (See “BL1, BL0: Block Lock protec­tion bits - (Nonvolatile)” on page 12.)

The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
returned by the X9521 after the Slave Address, if it has
been received correctly.

Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be

volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9521.

Following the Instruction Byte, a Data Byte is issued to
the X9521 over SDA. The Data Byte contents is latched
into the WCR of the DCP on the first rising edge of the
clock signal, after the LSB of the Data Byte (D0) has
been issued on SDA (See Figure 25).

The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).

P1 - P0 DCPx # Taps Max. Data Byte

00 Reserved

0 1 x = 1 100 Refer to Appendix 1

1 0 x = 2 256 FFh

11 Reserved

Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.

For DCP2 (256 Tap), the Data Byte maps one to one to
the “wiper position” of the DCP “wiper terminal”. There­fore, the Data Byte 00001111 (15

) corresponds to set-

10

ting the “wiper terminal” to tap position 15. Similarly, the
Data Byte 00011100 (28

) corresponds to setting the

10

“wiper terminal” to tap position 28. The mapping of the
Data Byte to “wiper position” data for DCP1 (100 Tap), is
shown in “APPENDIX 1” . An example of a simple C lan­guage function which “translates” between the tap posi­tion (decimal) and the Data Byte (binary) for DCP1, is
given in “APPENDIX 2” .

It should be noted that all writes to any DCP of the X9521
are random in nature. Therefore, the Data Byte of con­secutive write operations to any DCP can differ by an
arbitrary number of bits. Also, setting the bits (P1 = 0,

10101110

S
T
A
R
T

SLAVE ADDRESS BYTE

A

WT 0 0 0 0 0 P1 P0 A
C
K

INSTRUCTION BYTE

C
K

Figure 9. DCP Write Command Sequence

7

D7 D6 D5 D4 D3 D2 D1 D0

DATA BYTE

S

A

T

C

O

K

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FN8207.1

January 3, 2006

Signals from

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the Master

S

t

a

r
t

Slave

Address

X9521

Address

Byte

Data

(1)

(2 < n < 16)

Data

(n)

S

t
o
p

SDA Bus

Signals from
the Slave

01

1

0

0

0

0

0

A
C
K

Figure 10. EEPROM Page Write Operation

P0 = 0) or (P1 = 1, P0 = 1) are reserved sequences, and
will result in no ACKNOWLEDGE after sending an
Instruction Byte on SDA.

The factory default setting of all “wiper position” settings
is with 00h stored in the NVM of the DCPs. This corre-

R

sponds to having the “wiper teminal”

(x=1,2) at the

WX

“lowest” tap position, Therefore, the resistance between

R

and RLX is a minimum (essentially only the Wiper

WX

Resistance,

R

).

W

DCP Read Operation

A read of DCPx (x = 1,2) can be performed using the
three byte random read command sequence shown in
Figure 11.

The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read
operation). An ACKNOWLEDGE is returned by the
X9521 after the Slave Address if received correctly. Next,

A
C
K

A
C
K

A
C
K

an Instruction Byte is issued on SDA. Bits P1 - P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9521.

Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W

bit set to 1. Then the X9521
issues an ACKNOWLEDGE followed by Data Byte, and
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the “wiper
position” (value of the WCR) of the DCP pointed to by
bits P1 and P0.

It should be noted that when reading out the data byte for
DCP1 (100 Tap), the upper most significant bit is an
“unknown”. For DCP2 (256 Tap) however, all bits of the
data byte are relevant (See Figure 11).

Signals from
the Master

SDA Bus

Signals from
the Slave

S

t

a

r

t

101 11100

Slave

Address

“Dummy” write

WRITE Operation

Instruction

Byte

W

00 000

T

A
C
K

S

t

Slave

a

Address

r
t

P

P
1

101 11110

0

A
C
K

READ Operation

Figure 11. DCP Read Sequence

8

Data Byte

A
C
K

-

MSB

“-” = DON’T CARE

S

t
o
p

DCPx

x = 1

x = 2

LSB

FN8207.1

January 3, 2006