intersil X9520 DATA SHEET

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X9520

Fiber Channel/Gigabit Ethernet Laser Diode Control for Fiber Optic Modules

Data Sheet August 20, 2007

Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

The X9520 combines three Digitally Controlled Potentiometers (DCPs), V1/VCC Powe r-on R eset ( POR) circuitry , tw o programma ble volt ag e monitor inputs with software and hardware indicators, and integrated EEPROM with Block Lock™ protection. All functions of the X9520 are accessed by an industry standard 2-Wire serial interface.

Two of the DCPs of the X9520 may be utilized to control the bias and modulation currents of the laser diode in a Fiber Optic module. The third DCP may be used to set other various reference quantities, or as a coarse trim for one of the other two DCPs. The 2kbit integrated EEPROM may be used to store module definition data. The programmable POR circuit may be used to ensure that V1/VCC is stable before power is applied to the laser diode/module. The programmable voltage monitors may be used for monitoring various module alarm levels.

The features of the X9520 are ideally suited to simplifying the design of fiber optic modules which comply to the Gigabit Interface Converter (GBIC) specification. The integration of these functions into one package significantly reduces board area, cost and increases reliability of laser diode modules.

Features

• Three Digitally Controlled Potentiometers (DCPs)

- 64 Tap - 10kΩ

- 100 Tap - 10kΩ

- 256 Tap - 100kΩ

- Nonvolatile

- Write Protect Function

• 2kbit EEPROM Memory with Write Protect & Block Lock

• 2-Wire Industry Standard Serial Interface

- Complies to the Gigabit Interface Converter (GBIC) specification

• Power-on Reset (POR) Circuitry

- Programmable Threshold Voltage

- Software Selectable Reset Timeout

- Manual Reset

• Two Supplementary Voltage Monitors

- Programmable Threshold Voltages

• Single Supply Operation

- 2.7V to 5.5V

• Hot Pluggable

• 20 Ld Package

-TSSOP

• Pb-free available (RoHS compliant)

FN8206.2

Ordering Information

PART

PART NUMBER

X9520V20I-A X9520V IA Optimized for 3.3V system monitoring** -40 to +85 20 Ld TSSOP MDP0044 X9520V20I-AT1* X9520V IA Optimized for 3.3V system monitoring** -40 to +85 20 Ld TSSOP MDP0044 X9520V20I-AT2* X9520V IA Optimized for 3.3V system monitoring** -40 to +85 20 Ld TSSOP MDP0044 X9520V20I-B X9520V IB Optimized for 5V system monitoring** -40 to +85 20 Ld TSSOP MDP0044 X9520V20I-BT1* X9520V IB Optimized for 5V system monitoring** -40 to +85 20 Ld TSSOP MDP0044 X9520V20IZ-A (Note) X9520V ZIA Optimized for 3.3V system monitoring** -40 to +85 20 Ld TSSOP (Pb-free) MDP0044 X9520V20IZ-AT1* (Note) X9520V ZIA Optimized for 3.3V system monitoring** -40 to +85 20 Ld TSSOP (Pb-free) MDP0044 X9520V20IZ-AT2* (Note) X9520V ZIA Optimized for 3.3V system monitoring** -40 to +85 20 Ld TSSOP (Pb-free) MDP0044 X9520V20IZ-B (Note) X9520V ZIB Optimized for 5V system monitoring** -40 to +85 20 Ld TSSOP (Pb-free) MDP0044 X9520V20IZ-BT1* (Note) X9520V ZIB Optimized for 5V system monitoring** -40 to +85 20 Ld TSSOP (Pb-free) MDP0044 * Please refer to TB347 for details on reel specifications.

** For details, see DC Operating characteristics NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING

PRESET (FACTOR Y SHIPPED) TRIPx

THRESHOLD LEVELS (x = 2, 3)

TEMP. RANGE

(°C) PACKAGE

PKG.

DWG. #

™

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

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SDA

SCL

V1/VCC

DATA

COMMAND DECODE & CONTROL

LOGIC

THRESHOLD

RESET LOGIC

VTRIP

X9520

WIPER COUNTER REGISTER

6 - BIT

NONVOLATILE

PROTECT LOGIC

CONSTAT

2kbit

EEPROM

ARRAY

POWER-ON /

LOW VOLTAGE

RESET

GENERATION

MEMORY

WIPER COUNTER REGISTER

7 - BIT

NONVOLATILE

MEMORY

WIPER COUNTER REGISTER

8 - BIT

NONVOLATILE

MEMORY

V3RO

V2RO

V1RO

Detailed Device Description

The X9520 combines three Intersil Digitally Controlled Potentiometer (DCP) devices, V1/VCC power-on reset control, V1/VCC low voltage reset control, two supplementary voltage monitors, and integrated EEPROM with Block Lock™ protection, in one package. These functions are suited to the control, support, and monitoring of various system parameters in Fiber Channel/Gigabit Ethernet fiber optic modules, such as in Gigabit Interface Converter (GBIC) applications. The combination of the X9520 fucntionality lowers system cost, increases reliability, and reduces board space requirements using Intersil’s unique XBGA™ packaging.

Two high resolution DCPs allow for the “set-and-forget” adjustment of Laser Driver IC parameters such as Laser Diode Bias and Modulation Currents. One lower resolution DCP may be used for setting sundry system parameters such as maximum laser output power (for eye safety requirements).

Applying voltage to V which allows the V1RO output to go HIGH, until the supply the supply voltage stabilizes for a period of time (selectable via software). The V1RO output then goes LOW. The Low Voltage Reset circuitry allows the V1RO output to go HIGH when V

falls below the minimum VCC trip point. V1RO

remains HIGH until V Manual Reset (MR) input allows the user to externally trigger the V1RO output (HIGH).

activates the Power-on Reset circuit

returns to proper operating level. A

Two supplementary Voltage Monitor circuits continuously compare their inputs to individual trip voltages. If an input voltage exceeds it’s associated trip level, a hardware output (V3RO, V2RO) are allowed to go HIGH. If the input voltage becomes lower than it’s associated trip level, the corresponding output is driven LOW. A corresponding binary representation of the two monitor circuit outputs (V2RO and V3RO) are also stored in latched, volatile (CONSTAT) register bits. The status of these two monitor outputs can be read out via the 2-wire serial port.

An application of the V1RO output may be to drive the “ENABLE

” input of a Laser Driver IC, with MR as a “TX_DISABLE” input. V2RO and V3RO may be used to monitor “TX_FAULT” and “RX_LOS” conditions respectively.

Intersil’s unique circuits allow for all internal trip voltages to be individually programmed with high accuracy. This gives the designer great flexibility in changing system parameters, either at the time of manufacture, or in the field.

The memory portion of the device is a CMOS serial EEPROM array with Intersil’s Block Lock™ protection. This memory may be used to store fiber optic module manufacturing data, serial numbers, or various other system parameters. The EEPROM array is internally organized as x 8, and utilizes Intersil’s proprietary Direct Write™ cells, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years.

The device features a 2-Wire interface and software protocol allowing operation on an I

C™ compatible serial bus.

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Pinout

X9520

(20 LD TSSOP)

TOP VIEW

V3RO

WP SCL SDA

1 2 3

4 5 6

7 8

V1/VCC

V1RO

19 18

V2RO

V2 R

16 15 14 13 12 11

NOT TO SCALE

Pin Descriptions

TSSOP NAME FUNCTION

1R 2R 3RL2Connection to other end of resistor array for (the 256 Tap) DCP 2. 4 V3 V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3 input is higher than the

5 V3RO V3 RESE T Output. This open drain output makes a transition to a HIGH level when V3 is greater than V

6 MR Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the V1RO pin

7 WP Write Protect Control Pin. WP pin is a TTL level comp atible input. When held HIGH, Write Protection is enabled. In the enabled

8 SCL Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output. 9 SDA Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input

10 Vss Ground. 11 R 12 R 13 R 14 R 15 R 16 R 17 V2 V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2 input is greater than the

18 V2RO V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than V

Connection to end of resistor array for (the 256 Tap) DCP 2.

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.

threshold voltage, V3RO makes a transition to a HIGH level. Connect V3 to VSS when not used.

TRIP3

and goes LOW

when V3 is less than VTRIP3. There is no delay circuitry on this pin. The V3RO pin requires the use of an external “pull-up”

TRIP3

resistor.

(V1/VCC RESET Output pin). V1RO will remain HIGH for time t reset time can be selected using bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use of an external

after MR has returned to it’s normally LOW state. The

purst

“pull-down” resistor.

state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations can be performed in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled.

buffer is always active (not gated). This pin requires an external pull up resistor.

Connection to other end of resistor for (the 100 Tap) DCP 1.

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.

Connection to end of resistor array for (the 100 Tap) DCP 1.

Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0.

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.

Connection to the other end of resistor array for (the 64 Tap) DCP 0.

threshold voltage, V2RO makes a transition to a HIGH level. Connect V2 to VSS when not used.

TRIP2

, and goes LOW when V2 is less than V external “pull-up” resistor.

TRIP2

. There is no power-up reset delay circuitry on this pin. The V2RO pin requires the use of an

TRIP2

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Pin Descriptions (Continued)

TSSOP NAME FUNCTION

19 V1RO V1/VCC RESET Output. This is an active HIGH, open drain output which becomes active whenever V1/VCC falls below

20 V1/VCC Supply Voltage.

. V1RO becomes active on power-up and remains active for a time t

TRIP1

be changed by varying the POR0 and POR1 bits of the internal control register). The V1RO pin requires the use of an external “pull-up” resistor. The V1RO pin can be forced active (HIGH) using the manual reset (MR) input pin.

after the power supply stabilizes (t

purst

can

Principles of Operation

Serial Interface

SERIAL INTERFACE CONVENTIONS

The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the X9520 operates as a slave in all applications.

SERIAL CLOCK AND DATA

Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions. See Figure 1. On power-up of the X9520, the SDA pin is in the input mode.

SERIAL START CONDITION

All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The device continuously monitors the SDA and SCL lines for the

START condition and does not respond to any command until this condition has been met. See Figure 2.

SERIAL STOP CONDITION

All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. The STOP condition is also used to place the device into the Standby pow er mode after a read sequence. A STOP condition can only be issued after the transmitting device has released th e bu s . See Figure 2.

SCL

SDA

SCL

SDA

DATA STABLE DATA CHANGE DATA STABLE

FIGURE 1. VALID DATA CHANGES ON THE SDA BUS

START STOP

FIGURE 2. VALID START AND STOP CONDITIONS

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SCL

Master

from

Master

Data Output from

Transmitter

Data Output from

Receiver

X9520

81 9

START ACKNOWLEDGE

FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER

SERIAL ACKNOWLEDGE

An ACKNOWLEDGE (ACK) is a software convention used to indicate a successful data transfer . The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to ACKNOWLEDGE that it received the eight bits of data. Refer to Figure 3.

The device will respond with an ACKNOWLEDGE after recognition of a START condition if the correct Device Identifier bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an ACKNOWLEDGE after the receipt of each subsequent eight bit word.

In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an ACKNOWLEDGE. If an ACKNOWLEDGE is detected and no STOP condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an ACKNOWLEDGE is not detected. The master must then issue a STOP condition to place the device into a known state.

Device Internal Addressing

Addressing Protocol Overview

The user addressable internal components of the X9520 can be split up into three main parts:

• Three Digitally Controlled Potentiometers (DCPs)

• EEPROM array

• Control and Status (CONSTAT) Register Depending upon the operation to be performed on each of

these individual parts, a 1, 2 or 3 Byte protocol is used. All operations however must begin with the Slave Address Byte being issued on the SDA pin. The Slave address selects the part of the X9520 to be addressed, and specifies if a Read or Write operation is to be performed.

It should be noted that in order to perform a write operation to either a DCP or the EEPROM array, the Write Enable Latch (WEL) bit must first be set (See “BL1, BL0: Block Lock protection bits - (Nonvolatile)” on page 13.)

Slave Address Byte

Following a START condition, the master must output a Slave Address Byte (Refer to Figure 4). This byte consists of three parts:

• The Device Type Identifier which consists of the most significant four bits of the Slave Addre ss (SA7 - SA4). The Device Type Identifier must always be set to 1010 in order to select the X9520.

• The next three bits (SA3 - SA1) are the Internal Device Address bits. Setting these bits to 000 internally selects the EEPROM array, while setting these bits to 111 selects the DCP structures in the X9520. The CONSTAT Register may be selected using the Internal Device Address 010.

• The Least Significant Bit of the Slave Address (SA0) Byte is the R/W performed on the device being addressed (as defined in the bits SA3 - SA1). When the R/W operation is selected. A “0” selects a WRITE operation (Refer to Figure 4.)

bit. This bit defines the operation to be

bit is “1”, then a READ

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SA6SA7

SA5

1010

DEVICE TYPE

IDENTIFIER

INTERNAL ADDRESS

(SA3 - SA1)

000 EEPROM Array 010 CONSTAT Register 111 DCP

BIT SA0 OPERATION

0WRITE 1 READ

FIGURE 4. SLAVE ADDRESS FORMAT

SA3 SA2

SA4

INTERNAL

DEVICE

ADDRESS

INTERNALL Y ADDRESSED

SA1

DEVICE

SA0

R/W

READ/ WRITE

Nonvolatile Write Acknowledge Polling

After a nonvolatile write command sequence (for either the EEPROM array, the Non Volatile Memory of a DCP (NVM), or the CONSTAT Register) has been correctly is sued (including the final STOP condition), the X9520 initiates an internal high voltage write cycle. This cycle typically requires 5 ms. During this time, no further Read or Write commands can be issued to the device. Write Acknowledge Polling is used to determine when this high voltage write cycle has been completed.

Byte load completed

by issuing STOP.

Enter ACK Polling

Issue START

Issue Slave Address Byte (Read or Write)

ACK

returned?

YES

High Voltage Cycle

complete. Continue

command sequence?

YES

Continue normal

Read or Write

command sequence

PROCEED

FIGURE 5. ACKNOWLEDGE POLLING SEQUENCE

ssue STOP

Issue STOP

T o perform acknowledge polling, the master issues a ST AR T condition followed by a Slave Address Byte. The Slave Address issued must contain a valid Internal Device Address. The LSB of the Slave Address (R/W

) can be set to either 1 or 0 in this case. If the device is still busy with the high voltage cycle then no ACKNOWLEDGE will be returned. If the device has completed the write operation, an ACKNOWLEDGE will be returned and the host can then proceed with a read or write operation (Refer to Figure 5.).

Digitally Controlled Potentiometers

DCP Functionality

The X9520 includes three independent resistor arrays. These arrays respectively contain 63, 99 and 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R inputs - where x = 0,1,2).

and RLx

WIPER COUNTER REGISTER

(WCR)

NON

VOLATILE

MEMORY

(NVM)

DECODER

FIGURE 6. DCP INTERNAL STRUCTURE

“WIPER”

FET

SWITCHES

RESISTOR

ARRAY

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trans

X9520

purst

FIGURE 7. DCP POWER

V1/VCC (Max)

TRIP1

MAXIMUM WIPER RECALL TIME

At both ends of each array and between each resistor segment there is a CMOS switch connected to the wiper (R

) output. Within each individual array, only one switch

may be turned on at any one time. These switches are controlled by the Wiper Counter Register (WCR) (See Figure

6). The WCR is a volatile register. On power-up of the X9520, wiper position data is

automatically loaded into the WCR from its associated Non Volatile Memory (NVM) Register. The table below shows the Initial Values of the DCP WCR’s before the contents of the NVM is loaded into the WCR.

DCP INITIAL VALUES BEFORE RECALL

R0/64 TAP VH/TAP = 63

100 TAP VL/TAP = 0

256 TAP VH/TAP = 255

The data in the WCR is then decoded to select and enable one of the respective FET switches. A “make before break” sequence is used internally for the FET switches when the wiper is moved from one tap position to another.

Hot Pluggability

Figure 7 shows a typical waveform that the X9520 might experience in a Hot Pluggable situation. On power-up, V1/VCC applied to the X9520 may exhibit some amount of ringing, before it settles to the required value.

The device is designed such that the wiper terminal (R recalled to the correct position (as per the last stored in the DCP NVM), when the voltage applied to V1/VCC exceeds V time, set in the CONSTAT Register - See “Control and Status Register” on page 12.).

Therefore, if to settle above V terminal position is recalled by (a maximum) time:

for a time exceeding t

TRIP1

trans

(the Power-on Reset

purst

is defined as the time taken for V1/VCC

(Figure 7): then the desired wiper

TRIP1

trans

) is

. It should be noted that t

purst

system hot plug conditions.

is determined by

trans

DCP Operations

In total there are three operations that can be performed on any internal DCP structure:

• DCP Nonvolatile Write

• DCP Volatile Write

• DCP Read A nonvolatile write to a DCP will change the “wiper position”

by simultaneously writing new data to the associated WCR and NVM. Therefore, the new “wiper position” setting is recalled into the WCR after V1/VCC of the X9520 is powered down and then powered back up.

A volatile write operation to a DCP however, changes the “wiper position” by writing new data to the associated WCR only. The contents of the associated NVM register remains unchanged. Therefore, when V1/VCC to the device is powered down then back up, the “wiper position” reverts to that last position written to the DCP using a nonvolatile write operation.

Both volatile and nonvolatile write operations are executed using a three byte command sequence: (DCP) Slave Address Byte, Instruction Byte, followed by a Data Byte (See Figure 9).

A DCP Read operation allows the user to “read out” the current “wiper position” of the DCP, as stored in the associated WCR. This operation is ex ecu ted using the Random Address Read command sequence, consisting of the (DCP) Slave Address Byte followed by an Instruction Byte and the Slave Address Byte again (Refer to Figure 10.).

Instruction Byte

While the Slave Address Byte is used to select the DCP devices, an Instruction Byte is used to determine which DCP is being addressed.

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I5I6I7 I4 I3 I2 I1 I0

00WT 0 0 0 P1 P0

WRITE TYPE

†

0 Select a Volatile Write operation to be performed on the

DCP pointed to by bits P1 and P0

1 Select a Nonvolatile Write operation to be performed on

the DCP pointed to by bits P1 and P0

†

This bit has no effect when a Read operation is being performed.

FIGURE 8. INSTRUCTION BYTE FORMAT

DESCRIPTION

DCP SELECT

The Instruction Byte (Figure 8) is valid only when the Device Type Identifier and the Internal Device Address bits of the Slave Address are set to 1010111. In this case, the two Least Significant Bit’s (I1 - I0) of the Instruction Byte are used to select the particular DCP (0 - 2). In the case of a Write to any of the DCPs (i.e. the LSB of the Slave Address is 0), the Most Significant Bit of the Instruction Byte (I7), determines the Write Type (WT) performed.

If WT is “1”, then a Nonvolatile Write to the DCP occurs. In this case, the “wiper position” of the DCP is changed by simultaneously writing new data to the associated WCR and NVM. Therefore, the new “wiper position” setting is recalled into the WCR after V1/VCC of the X9520 has been powered down then powered back up

If WT is “0” then a DCP Volatile Write is performed. This operation changes the DCP “wiper position” by writing new data to the associated WCR only. The contents of the associated NVM register remains unchanged. Therefore, when V1/VCC to the device is powered down then back up, the “wiper position” reverts to that last written to the DCP using a nonvolatile write operation.

DCP Write Operation

A write to DCPx (x = 0,1,2) can be performed u sing the three byte command sequence shown in Figure 9.

In order to perform a write operation on a particular DCP, the Write Enable Latch (WEL) bit of the CONSTA T Re gi ster must first be set (See “BL1, BL0: Block Lock protection bits (Nonvolatile)” on page 13.)

The Slave Address Byte 10101110 specifies that a Write to a DCP is to be conducted. An ACKNOWLEDGE is returned by the X9520 after the Slave Address, if it has been received correctly.

Next, an Instruction Byte is issued on SDA. Bits P1 and P0 of the Instruction Byte determine which WCR is to be written, while the WT bit determines if the Write is to be volatile or nonvolatile. If the Instruction Byte format is valid, another ACKNOWLEDGE is then returned by the X9520.

Following the Instruction Byte, a Data Byte is issued to the X9520 over SDA. The Data Byte contents is latched into the WCR of the DCP on the first rising edge of the clock signal, after the LSB of the Data Byte (D0) has been issued on SDA (See Figure 34).

The Data Byte determines the “wiper position” (which FET switch of the DCP resistive array is switched ON) of the DCP. The maximum value for the Data Byte depends upon which DCP is being addressed (see Table below).

P1 - P0 DCPX # TAPS MAX DATA BYTE

00 x = 0 64 3Fh 0 1 x = 1 100 Refer to Appendix 1 1 0 x = 2 256 FFh 11 Reserved

Using a Data Byte larger than the values specified above results in the “wiper terminal” being set to the highest tap position. The “wiper position” does NOT roll-over to th e lowest tap position.

For DCP0 (64 Tap) and DCP2 (256 Tap), the Data Byte maps one to one to the “wiper position” of the DCP “wiper

10101110

S T A R T

SLAVE ADDRESS BYTE

WT 0 0 0 0 0 P1 P0 A C K

INSTRUCTION BYTE

FIGURE 9. DCP WRITE COMMAND SEQUENCE

C K

D7 D6 D5 D4 D3 D2 D1 D0

DATA BYTE

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terminal”. Therefore, the Data Byte 00001111 (1510) corresponds to setting the “wiper terminal” to tap position 15. Similarly, the Data Byte 00011100 (28

) corresponds to

setting the “wiper terminal” to tap position 28. The mapping of the Data Byte to “wiper position” data for DCP1 (100 Tap), is shown in “Appendix 1” . An example of a simple C language function which “translates” between the tap position (decimal) and the Data Byte (binary) for DCP1, is given in “Appendix 2” .

It should be noted that all writes to any DCP of the X9520 are random in nature. Therefore, the Data Byte of consecutive write operations to any DCP can differ by an arbitrary number of bits. Also, setting the bits P1 = 1, P0 = 1 is a reserved sequence, and will result in no ACKNOWLEDGE after sending an Instruction Byte on SDA.

The factory default setting of all “wiper position” settings is with 00h stored in the NVM of the DCPs. This corresponds to having the “wiper teminal” tap position, Therefore, the resistance between

is a minimum (essentially only the Wiper Resistance,

(x = 0,1,2) at the “lowest”

and

DCP Read Operation

A read of DCPx (x = 0,1,2) can be performed using the three byte random read command sequence shown in Figure 10.

The master issues the START condition and the Slave Address Byte 10101110 which specifies that a “dummy” write” is to be conducted. This “dummy” write operation sets which DCP is to be read (in the preceding Read operation). An ACKNOWLEDGE is returned by the X9520 after the Slave Address if received correctly. Next, an Instruction Byte is issued on SDA. Bits P1-P0 of the Instruction Byte determine which DCP “wiper position” is to be read. In this case, the state of the WT bit is “don’t care”. If the Instruction Byte format is valid, then another ACKNOWLEDGE is returned by the X9520.

Following this ACKNOWLEDGE, the master immediately issues another START condition and a valid Slave address byte with the R/W ACKNOWLEDGE followed by Data Byte, and finally, the master issues a STOP condition. The Data Byte read in this operation, corresponds to the “wiper position” (value of the WCR) of the DCP pointed to by bits P1 and P0.

bit set to 1. Then the X9520 issues an

Signals from the Master

SDA Bus

Signals from the Slave

t a r

101 11100

Signals from the Master

SDA Bus

Signals from the Slave

Slave

Address

WRITE Operation

Instruction

Byte

Slave

Address

r t

00 000

A C K

“Dummy” write

FIGURE 10. DCP READ SEQUENCE

Slave

Address

10100000

Internal

Device

Address

FIGURE 11. EEPROM BYTE WRITE SEQUENCE

P 1

WRITE Operation

A C K

Address

Byte

101 11110

A C K

READ Operation

Data Byte

A C K

Data

Byte

t o p

MSB

“-” = DON’T CARE

t o p

A C K

LSB

DCPx

x = 0

x = 1

x = 2

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