intersil X9460 DATA SHEET

®

www.BDTIC.com/Intersil

X9460

Low Noise, Low Cost, High End Features, Dual Audio Log Potentiometer

Data Sheet October 17, 2005

Dual Audio Control Digitally Controlled
Potentiometer (XDCP™)

The X9460 integrates two digitally controlled potentiometer
(XDCP) on a monolithic CMOS integrated circuit. The two
XDCPs can be used as stereo gain controls in audio
applications. Read/Write operations can directly access
each channel independently or both channels
simultaneously. Increment/Decrement can adjust each
channel independently or both channels simultaneously.

The X9460 contains a zero amplitude wiper switching circuit
that delays wiper changes until the next zero crossing of the
audio signal.

The digitally controlled potentiometer is implemented using
31 polysilicon resistors in a log array. Between each of the
resistors are tap points connected to the wiper terminal
through switches. The XDCPs are designed to minimize
wiper noise to avoid pops and clicks during audio volume
transitions. The position of the wiper on the array is
controlled by the user through the 2-wire serial bus interface.

Power-up reset the wiper to the mute position.

FN8203.2

Features

• Dual Audio Control – Two 32 Taps Log Pots

• Zero Amplitude Wiper Switching

• 2-Wire Serial Interface
4 Slave Byte Addresses for Writes[A1,A0]

• Total Resistance: 33kΩ Each XDCP (Typical)

• Dual Voltage Operation
V+/V- = ±2.7 to ±5.5V

• Temp Range = -40°C to +85°C

• Package Options
14 L d TSSOP

• Zero Amplitude Wiper Switching

• Pb-Free Plus Anneal Available (RoHS Compliant)

Audio Performance

• 0 to - 62dB Volume Control

• -92dB Mute

- Power-Up to Mute Position

Pinout

SDA

SCL

V

CC

V+

V

SS

A0
A1

X9460

(14 LD TSSOP)

TOP VIEW

X9460

14
13
12
11
10

9
8

1
2
3
4
5
6
7

V­R

H-right

R

L-right

R

W-right

R

H-left

R

L-left

R

W-left

• SNR -96dB

• THD+N: -95dB @1kHz

• Crosstalk Rejection: -102dB @ 1kHz

• Channel-to-Channel Variation: ± 0.1dB

• 3dB-Cutoff: 100kHz

Applications

• Set Top Boxes

• Stereo Amplifiers

• DVD Players

• Portable Audio Products

Ordering Information

PART NUMBER PART MARKING VCC LIMITS (V) TEMP RANGE (°C) PACKAGE

X9460KV14I* X9460KV I 5V ± 10% -40 to +85 14 Ld TSSOP

X9460KV14IZ* (Note) X9460KV Z I -40 to +85 14 Ld TSSOP (Pb-free)

X9460KV14I-2.7* X9460KV G 2.7 to 5.5 -40 to +85 14 Ld TSSOP

X9460KV14IZ-2.7* (Note) X9460KV Z G -40 to +85 14 Ld TSSOP (Pb-free)

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Simplified Functional Diagram

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X9460

V

CC

Power-on
Recall

data
address

I2C
bus

BUS

INTERFACE
CONTROL &
REGISTER

V

SS

Detailed Functional Diagram

V

CC

SCL

SDA

A0

A1

INTERFACE

AND

CONTROL

CIRCUITRY

mute

select
inc/dec

Power-on

Recall

R

mute

DATA

W-Left

8

R

R

H-Left

L-Left

POT
Left

WIPER
COUNTER
REGISTER

(WCR)

POT Left

WIPER

COUNTER
REGISTER

(WCR)

R

W-Right

V+

R

H-Right

R

POT
Right

L-Right

V+

62dB total

# OF

STEP SIZE

STEPS

-1dB 11

-2dB 10

-3dB 5

-4dB 4

Mute 1

V-

R

H-Left

R

L-Left

R

W-Left

R

W-Right

R

H-Right

R

L-Right

POT Right

SS

V-V

2

FN8203.2

October 17, 2005

Typical Application

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Gain / Volume Control

Left Channel Control
Right Channel Control
Simultaneous Left and Right Channel

Control

Power-up in Mute

X9460

Audio

DAC

Audio => R
RWL, R

WR

HL, RHR

=> Amplifier

X9460

2 XDCP

Audio

Amplifier

Left

Audio

Amplifier

Right

µController

EEPROM

Serial Bus

Pin Assignments

PIN

(TSSOP) SYMBOL FUNCTION

1SDASerial Data

2 SCL Serial Clock

3V

CC

4 V+ Positive Analog Supply

5V

SS

6 A0 Device Address

7 A1 Device Address

8R

9R

10 R

11 R

12 R

13 R

W-left

L-left

H-left

W-right

L-right

H-right

14 V- Negative Analog Supply

System Supply Voltage

System Ground

Wiper terminal of the Left Potentiometer

Negative terminal of the Left Potentiometer

Positive terminal of the Left Potentiometer

Wiper terminal of the Right Potentiometer

Negative terminal of the Right Potentiometer

Positive terminal of the Right Potentiometer

3

FN8203.2

October 17, 2005

X9460

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Detailed Pin Description

Host Interface Pins

SERIAL CLOCK (SCL)

The SCL input clocks data into and out of the X9460.

SERIAL DATA (SDA)

SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wire­ORed with any number of open drain or open collector
outputs. An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the guidelines
for calculating typical values on the bus pull-up resistors
graph.

DEVICE ADDRESS (A

The Address inputs are used to set the least significant 2 bits
of the 8-bit Slave Byte Address. A match in the slave
address serial data stream must be made with the Address
input in order to initiate communication with the X9460. Up to
4 X9460s may be connected to a single I
written to (NOTE: you cannot read from more than one
device on the same 2-wire bus). If left floating, these pins are
internally pulled to ground.

Slave Byte (bits, MSB-LSB) = 0101 0 A

Potentiometer Pins

R

The R
connections on either end of a mechanical potentiometer.

R

The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.

, R

H-LEFT

and RL inputs are equivalent to the terminal

H

, R

W-LEFT

L-LEFT

W-RIGHT

, R

Supply Pins

ANALOG SUPPLY V- AND V+

The positive power supply for the DCP analog control
section is connected to V+. The negative power supply for
the DCP analog control section is connected to V-.

DIGITAL SUPPLIES V

The power supplies for the digital control sections.

Power-up and Down Recommendations

There are no restrictions on the power-up condition of VCC,
V+ and V- and the voltages applied to the potentiometer pins
provided that the V
the voltage at R
all times, the voltages on the potentiometer pins must be
less than V+ and more than V-.

, RL, and RW, ie. VCC, V+ > RH, RL, RW. At

H

- A0)

1

2

C serial bus and

R/W

1 A0

, R

H-RIGHT

, V

CC

SS

and V+ are more positive or equal to

CC

L-RIGHT

The V
ground. V

pin is always connected to the system common or

SS

, VL, VW are the voltages on the RH, RL, and RW

H

potentiometer pins.

X9460 Principles of Operation

The X9460 is a highly integrated microcircuit incorporating
two resistor arrays with their associated registers, counters
and the serial interface logic providing direct communication
between the host and the DCP potentiometers. This section
provides detailed description as following:

- Resistor Array Description

- Serial Interface Description

- Command Set and Register Information Description

Resistor Array Description

The X9460 is comprised of two resistor arrays. Each array
contains 31 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (R
R

inputs). Tables 1 and 2 provide a description of the step

L

size and tap positions.

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (R
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The five bits of the WCR are
decoded to select, and enable, one of thirty-two switches.

TABLE 1. TOTAL -62dB RANGE PLUS MUTE POSITION

STEP SIZE # OF STEPS

-1dB 11 steps

- 2dB 10 steps

- 3dB 5 steps

- 4dB 4 steps

Mute 1 step

TABLE 2. WIPER TAP POSITION vs dB

TAP POSITION, n dB MIN/MAX dB

for n = 20 to 31 n - 31 -11/0

for n = 10 to 19 2n-51 -31/-13

for n = 5 to 9 3n-61 -46/-34

for n = 1 to 4 4n-66 -62/-50

n = 0 -92 -92

and

H

W

)

The following V

ramp rate spec is always in effect.

CC

0.2 V/ms < VCC ramp < 50 V/ms

4

FN8203.2

October 17, 2005

X9460

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Serial Interface Description

Serial Interface

The X9460 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. The X9460 is a slave device in all
applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions.

Start Condition

All commands to the X9460 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X9460 continuously monitors the SDA
and SCL lines for the start condition and will not respond to
any command until this condition is met.

Stop Condition

All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH.

Acknowledge

Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.

The X9460 will respond with an acknowledge: 1) after
recognition of a start condition and after an identification and
slave address byte, and 2) again after each successful
receipt of the instruction or databyte. See Figure 1.

Invalid Commands

For any invalid commands or unrecognizable addresses, the
X9460 will NOT acknowledge and return the X9460 to the
idle state.

SCL FROM

MASTER

DATA

OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

1

FIGURE 1. ACKNOWLEDGE RESPONSE FROM RECEIVER

89

ACKNOWLEDGE

5

FN8203.2

October 17, 2005

X9460

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Command Set and Register Description

Device Addressing

Following a start condition the master must output the Slave
Byte Address of the slave it is accessing. The most
significant four bits of the slave address are the device type
identifier (refer to Figure 2). For the X9460 this is fixed as

0101.

DEVICE TYPE

IDENTIFIER

100

FIGURE 2. SLAVE BYTE ADDRESS

The next three bits of the Slave Byte Address are the device
address. The device address is defined by the A
The X9460 compares the serial data stream with the Slave
Byte Address; a successful compare is required for the
X9460 to respond with an acknowledge. The A
can be actively driven by CMOS input signals or tied to V
or V

. The R/W bit sets the device for read or write

SS

operations. Note that the X9460 supports reads and writes to
a single device on the 2-wire bus. If more than one X9460 is
used on the same 2-wire bus, those devices must have
unique device addresses and only writes are supported. You
may not read from multiple devices or contention will result
and the data is not valid.

Command Set

After a Slave Byte Address match, the next byte sent
contains the Command and register pointer information. The
four most significant bits are the Command. The next bit is a
“X” (don’t care) set to zero.

1

0A1A0

DEVICE ADDRESS

this bit not used, set to 0

R/W

- A0 inputs.

1

- A0 inputs

1

CC

Several instructions require a three-byte sequence to
complete. These instructions transfer data between the host
and the X9460. These instructions are: Read Wiper Counter
Register, Write Wiper Counter Register. The sequence of
operations is shown in Figure 4 and 5. The four-byte
command is used for write command for both right and left
pots (Figure 6).

Special Commands

Increment/Decrement Instruction. The Increment/Decrement
command is different from the other commands. Once the
command is issued and the X9460 has responded with an
acknowledge, the master can clock the selected wiper up
and/or down. For each SCL clock pulse (t

) while SDA is

HIGH

HIGH, the selected wiper will move one resistor segment
towards the R

terminal. Similarly, for each SCL clock pulse

H

while SDA is LOW, the selected wiper will move one resistor
segment towards the R

terminal. A detailed illustration of

L

the sequence and timing for this operation are shown in
Figures 7 and 8 respectively.

Wiper Counter Register

The X9460 contains two Wiper Counter Registers. The
Wiper Counter Register output is decoded to select one of
thirty-two switches along its resistor array. The Write Wiper
Counter Register command directly sets the WCR to a
value. The Increment/Decrement instruction steps the
register value up or down one to multiple times.

The WCR is a volatile register (Table 3) and is reset to the
mute position (tap 0, “zero”) at power-up.

TABLE 3. WIPER COUNTER REGISTERS, 5-bit - VOLATILE:

WCR4 WCR3 WCR2 WCR1 WCR0

(MSB) (LSB)

The X9460 contains one 5-bit Wiper Counter Register for
each DCP. (Two 5-bit registers in total.)

I1I2I3 I0 0 ZDRT LT

INSTRUCTIONS

FIGURE 3. COMMAND BYTE FORMAT

The Z

bit enables and disables the Zero Amplitude Wiper

D

Switching circuit. When Z

=1, the wiper switches will turn on

D

WIPER COUNTER

SELECT

when close-to-zero amplitude is detected across the
potentiometer pins. When Z

=0, this circuit is disabled. The

D

last two bits, LT (left POT enable) and RT (right POT
enable), select which of the two potentiometers is affected
by the instruction.

6

FN8203.2

October 17, 2005

X9460

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TABLE 4. COMMAND SET

INSTRUCTION SET

I

INSTRUCTION

3I2I1

Read Wiper LSB of Slave Byte=1, no command required

Write Left Wiper Counter 1 0 1 0 0 1/0 0 1 Write new value to the Wiper Counter Register

Write Right Wiper Counter 1 0 1 0 0 1/0 1 0 Write new value to the Wiper Counter Register

Write Both Wiper Counters 1 0 1 0 0 1/0 1 1 Write new value to the Wiper Counter Register

Inc/Dec Left Wiper Counter 0 0 1 0 0 1/0 0 1 Enable Increment/decrement of the Control Latch

Inc/Dec Right Wiper Counter 0 0 1 0 0 1/0 1 0 Enable Increment/decrement of the Control Latch

Inc/Dec Both Wiper Counters 0 0 1 0 0 1/0 1 1 Enable Increment/decrement of the Control Latch

Notes: “1/0” = data is one or zero

SCL

XZDRT LT

0

OPERATIONI

Slave will return Left then Right Data( not to be used with more
than one device on the 2-wire bus)

SDA

SCL

SDA

S

01010A1A0R/W
T
A
R

DEVICE TYPE

T

IDENTIFIER

FIGURE 4. THREE-BYTE COMMAND SEQUENCE (READ, SINGLE DEVICE ON THE 2-WIRE BUS ONLY)

S

01010A1A0R/W
T
A
R

DEVICE TYPE
T

IDENTIFIER

1000

A

00 0

C
K

0

10100

A

I3 I2 I1 I0 0 ZD RT LT
C
K

W
C

R
4

LEFT POT

DATA BYTE

INSTRUCTION BYTE

W

W

W

C

C

R

R

3

2

W

C

C

R

R

1

0

00 0

A

000

C
K

000

A

000
C
K

FIGURE 5. THREE-BYTE COMMAND SEQUENCE (WRITE)

W

W

C
R
4

RIGHT POT

DATA BYTE

RIGHT or LEFT POT

DATA BYTE

W

C

C

R

R

3

2

W

W

C
R
4

W

C

C

R

R

3

2

W

W

C

C

R

R

1

0

W

W

C

C

R

R

1

0

S

A

T

C

O

K

P

S

A

T

C

O

K

P

7

FN8203.2

October 17, 2005

SCL

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X9460

SDA

SCL

SDA

0

S

01010A1A0R/WA
T
A
R

DEVICE TYPE

T

IDENTIFIER

S

01 0 10 A1A0R/WA

T
A

R

DEVICE TYPE

T

IDENTIFIER

FIGURE 7. INCREMENT/DECREMENT COMMAND SEQUENCE (WRITE)

10100

I3 I2 I1 I0 0 ZD RT LT A
C
K

INSTRUCTION BYTE

1

00 0 000

1

W

W

W

00 0 A

C
K

C
R
4

LEFT POT

DATA BYTE

W

C

C

C

R

R

R

3

2

1

FIGURE 6. FOUR-BYTE COMMAND SEQUENCE (WRITE)

000

C
K

I3 I2 I1 I0 ZD RT LT A

INSTRUCTION BYTE

0

01

0

W

W

W

W

W
C

000

R

C

0

K

I

C
K

I

N

N

C

C

1

2

INC and DEC ACTIVE

C

C

R

R

4

3

RIGHT POT

DATA BYTE

I
N
C
n

W

C

C

C

S

R
2

D
E

C
1

A

R

R

T

C

1

0

O

K

P

S

D

T

E

O

C

P

n

INC/DEC

CMD

ISSUED

SCL

SDA

R

t

WRID

W

Wiper can move within 10µs after the falling edge of SCL

VOLTAGE OUT

FIGURE 8. INCREMENT/DECREMENT TIMING LIMITS

8

FN8203.2

October 17, 2005

X9460

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Instruction Formats

Read Wiper Counter Register (Single device on 2-wire bus only)

device type

S

identifier

T
A

R

01010

T

device

addresses

A1A

0

S
A
C
K

R / W = 1

(sent by slave on SDA)

000LD

Write Wiper Counter Register

device type

S

identifier

T
A

R

01010

T

device

addresses

A1A

0

instruction

S

opcode

A
C
K

10100

R / W = 0

Write Both Wiper Counter Registers

device type

S

identifier

T
A

R

01010

T

device

addresses

A1A

0

instruction

S

opcode

A
C
K

10100

R / W = 0

Left wiper position

L

L

D

D

4

3

2

wiper

addresses

ZDRTL

wiper

addresses

Z

11 000LD

D

Right wiper position

M

(sent by slave on SDA)

A

L

L

C

D

D

000RD

K

1

0

Left or Right wiper

S

(sent by master on SDA)

A
C
K

000

T

Left wiper position

(sent by master on

S
A
C
K

SDA)

4

R

R

D

D

4

3

2

position

D4D3D2D1D

L

L

L

L

D

D

D

D

3

2

1

0

R
D

1

0

S
A

C

K

S

M

T

A

R

O

C

D

P

K

0

S

S

T

A

O

C

P

K

Right wiper position

(sent by master on

SDA)

R

R

000RD

D

D

4

3

2

S

S

T

A

O

C

R

R

P

K

D

D

1

0

Increment/Decrement Wiper Counter Register

device type

S

identifier

T
A
R

0101 0A1A0

T

Definitions:

1. “MACK”/“SACK”: stands for the acknowledge sent by the master/slave.

2. “A1 ~ A0”: stands for the device addresses sent by the master.

3. “I”: stands for the increment operation, SDA held high during active SCL phase (high).

4. “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

device

addresses

instruction

S

opcode

A

C

00100ZDRTLT I/DI/D ....I/DI/D

K

R / W = 0

wiper

addresses

S
A
C
K

increment/decrement

(sent by master on SDA)

S
T

O

P

9

FN8203.2

October 17, 2005

X9460

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Absolute Maximum Ratings Recommended Operating Conditions

Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on SDA, SCL or any Address Input

with Respect to V
Voltage on V+ (referenced to V
Voltage on V- (referenced to V

(V+) - (V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+

Any R

H

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-

Any R

L

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C

max (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA

I

W

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation
of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +6V

SS

). . . . . . . . . . . . . . . . . . . . . . . .+6V

SS

) . . . . . . . . . . . . . . . . . . . . . . . . -6V

SS

Analog Specifications Over the recommended operating conditions unless otherwise specified (Note 1)

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DYNAMIC PERFORMANCE (Notes 2, 3)

Control Range -62 0 dB

Mute Mode @1V rms -92 dB

SNR Signal Noise Ratios (Unweighted) @1V rms @ 1kHz, Tap = -6dB -96 dB

THD + N Total Harmonic Distortion + Noise @1V rms @ 1kHz, Tap = -6dB -95 dB

XTalk DCP Isolation @1kHz, tap = -6dB -102 dB

Digital Feedthrough
(Peak Component)

-3db Cutoff Frequency 100 kHz

DC ACCURACY

Step Size Steps of -1, -2, -3, -4 dB -1 -4 dB

Step Size Error For -1dB steps -0.2 +0.2 dB

Step Size Error For -2dB steps -0.4 +0.4 dB

Step Size Error For -3dB steps -0.6 +0.6 dB

Step Size Error For -4dB steps -0.8 +0.8 dB

DCP to DCP Matching -0.1 0.1 dB

NOTES:

1. V

= | V- |

CC

Ramp up timing 0.2V/ms < Vcc Ramp Rate < 50V/ms

V

CC

2. This parameter is guaranteed by design and characterization

= 25oC, VCC = 5.0V; 2 Hz to 20kHz Measurement Bandwidth with 80kHz filter, input signal 1Vrms, 1kHz Sine Wave.

3. T

A

tap = -6dB -105 dB

Temperature Range (Industrial) . . . . . . . . . . . . . . . . . .-40°C to 85°C

X9460V14-2.7

Supply Voltage (V

V- Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -2.7V

V+ Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7V to +5.5V

) . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

Analog Specifications Over the recommended operating conditions unless otherwise specified (Note 1)

ANALOG INPUTS

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

TERM

R

TOTAL

Cin (Note 4) Input Capacitance RL, RH, RW T

(NOte 2) Wiper Current -3 +3 mA

I

W

R

V- Voltage on V- pin -5.5 -2.7 V

Voltage on RL, RW, and RH pins V- V+ V

End to End Resistance Typical 33kΩ -20 +20 %

= 25oC25pF

A

Wiper Resistance Wiper Current = ±3mA 100 200 Ω

W

10

FN8203.2

October 17, 2005

X9460

www.BDTIC.com/Intersil

Analog Specifications Over the recommended operating conditions unless otherwise specified (Note 1) (Continued)

ANALOG INPUTS

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V+ Voltage on V+ pin +2.7 +5.5 V

Noise 20Hz to 20kHz, Grounded Input @ -6dB tap 2 µVrm s

(Note 2) Temperature Coefficient of resistance -300 PPM/°C

TC

R

DC Electrical Specifications Over the recommended operating conditions unless otherwise specified. (Note 1)

LIMITS

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

SB

I

Iai Analog Input Leakage V

I

LO

V

V

V

VCC Supply Current (Move Wiper,
Write, Read)

VCC Current (Standby) SCL = SDA = VCC, Addr. = V

Input Leakage Current VIN = VSS to V

LI

Output Leakage Current V

Input HIGH Voltage VCC x 0.7 VCC + 0.5 V

IH

Input LOW Voltage -0.5 VCC x 0.1 V

IL

Output LOW Voltage IOL = 3mA 0.4 V

OL

f

= 400kHz, SDA = Open,

SCL

Other Inputs = V

= V- to V+ with all other

IN

analog inputs floating

= VSS to V

OUT

SS

CC

CC

SS

MIN TYP MAX UNITS

200 300 µA

3 µA

110µA

0.1 µA

10 µA

Capacitance

SYMBOL TEST TEST CONDITIONS MAX UNITS

(Note 4) Input/Output Capacitance (SDA) V

C

I/O

(NOte 4) Input Capacitance (A0, A1, A2 and SCL) VIN = 0V 6 pF

C

IN

NOTE:

4. This parameter is not 100% tested.

= 0V 8 pF

I/O

11

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X9460

www.BDTIC.com/Intersil

A.C. Test Conditions

Input Pulse Levels VCC x 0.1 to VCC x 0.9

Input Rise and Fall Times 10ns

Input and Output Timing Level V

CC

x 0.5

Equivalent A.C. Load Circuit

5V

1533Ω

SDA OUTPUT

100pF

AC TIMING Over recommended operating conditions

SYMBOL PARAMETER MIN MAX UNITS

f

SCL

t

CYC

t

HIGH

t

LOW

t

SU:STA

t

HD:STA

t

SU:STO

t

SU:DAT

t

HD:DAT

(Note 2) SCL and SDA Rise Time 300 ns

t

R

tF (Note 2) SCL and SDA Fall Time 300 ns

(Note 2) SCL Low to SDA Data Output Valid Time 900 ns

t

AA

(Note 2) SDA Data Output Hold Time 50 ns

t

DH

TI (Note 2) Noise Suppression Time Constant at SCL and SDA inputs 50 ns

(Note 2) Bus Free Time (Prior to Any Transmission) 1300 ns

t

BUF

t

SU:WPA

t

HD:WPA

Clock Frequency 400 kHz

Clock Cycle Time 2500 ns

Clock High Time 600 ns

Clock Low Time 1300 ns

Start Setup Time 600 ns

Start Hold Time 600 ns

Stop Setup Time 600 ns

SDA Data Input Setup Time 500 ns

SDA Data Input Hold Time 50 ns

A0, A1 (Note 2) 0ns

A0, A1 (Note 2) 0ns

DC Timing (Note 2)

SYMBOL PARAMETER MIN MAX UNITS

t

WRPO

t

WRL

t

WRID

Wiper Response Time After The Third (Last) Power Supply Is Stable 10 µs

Wiper Response Time After Instruction Issued (All Load Instructions) 10 µs

Wiper Response Time From An Active SCL Edge (Increment/Decrement Instruction) 10 µs

12

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October 17, 2005

Timing Diagrams

www.BDTIC.com/Intersil

SCL

t

SU:STA

SDA

X9460

(START) (STOP)

t

R

t

HD:STA

t

R

FIGURE 9. START AND STOP TIMING

t

F

t

SU:STO

t

F

SCL

SDA

SCL

SDA

t

CYC

t

SU:DAT

FIGURE 10. INPUT TIMING

t

AA

FIGURE 11. OUTPUT TIMING

t

HIGH

t

HD:DAT

t

DH

t

LOW

t

BUF

SCL

SDA

VWx

LSB

t

WRL

FIGURE 12. DCP TIMING (FOR ALL LOAD INSTRUCTIONS)

13

(STOP)

FN8203.2

October 17, 2005

Typical Performance Characteristics

www.BDTIC.com/Intersil

(Vcc, V+ = 5.0V, V- = -5.0V, TA = + 25 °C, unless otherwise noted)

+0

-10

-20

-30

-40

-50

-60

-70

-80

d

-90

B
V

-10 0

-11 0

-12 0

-13 0

-14 0

-15 0

-16 0

-17 0

-18 0

20 20k50 100 200 500 1k 2k 5k 10k

(with 1kHz 1Vrms input, tap = -6dB)

X9460

FF T Spectrum

Hz

FIGURE 13. SINGLE TONE FREQUENCY RESPONSE

THD+N vs Frequency

-60

-65

-70

-75

-80

-85

d

-90

B

-95

-100

-105

-110

-115

-120
20 20k50 100 200 500 1k 2k 5k 10k

(with 80kHz low-pass filter, tap = -6dB)

Hz

FIGURE 14. THD + N

14

FN8203.2

October 17, 2005

k

X9460

www.BDTIC.com/Intersil

Typical Performance Characteristics

(Vcc, V+ = 5.0V, V- = -5.0V, TA = + 25 °C, unless otherwise noted)

Mute Mod e

+0

-10

-20

-30

-40

-50

-60

d

-70

B
V

-80

-90

-100

-110

-120

-130

-140
20 20

50 100 200 500 1k 2k 5k 10k

Hz

FIGURE 15. MUTE

15

FN8203.2

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Packaging Information

www.BDTIC.com/Intersil

X9460

14-Lead Plastic, TSSOP, Package Type V

.025 (.65) BSC

0° - 8°

.0075 (.19)

.0118 (.30)

.193 (4.9)
.200 (5.1)

.019 (.50)
.029 (.75)

Detail A (20X)

.169 (4.3)
.177 (4.5)

.047 (1.20)

.002 (.05)
.006 (.15)

.010 (.25)

Gage Plane

Seating Plane

.252 (6.4) BSC

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

16

FN8203.2

October 17, 2005