intersil X9460 DATA SHEET

www.BDTIC.com/Intersil

X9460

Low Noise, Low Cost, High End Features, Dual Audio Log Potentiometer

Data Sheet October 17, 2005

Dual Audio Control Digitally Controlled Potentiometer (XDCP™)

The X9460 integrates two digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The two XDCPs can be used as stereo gain controls in audio applications. Read/Write operations can directly access each channel independently or both channels simultaneously. Increment/Decrement can adjust each channel independently or both channels simultaneously.

The X9460 contains a zero amplitude wiper switching circuit that delays wiper changes until the next zero crossing of the audio signal.

The digitally controlled potentiometer is implemented using 31 polysilicon resistors in a log array. Between each of the resistors are tap points connected to the wiper terminal through switches. The XDCPs are designed to minimize wiper noise to avoid pops and clicks during audio volume transitions. The position of the wiper on the array is controlled by the user through the 2-wire serial bus interface.

Power-up reset the wiper to the mute position.

FN8203.2

Features

• Dual Audio Control – Two 32 Taps Log Pots

• Zero Amplitude Wiper Switching

• 2-Wire Serial Interface 4 Slave Byte Addresses for Writes[A1,A0]

• Total Resistance: 33kΩ Each XDCP (Typical)

• Dual Voltage Operation V+/V- = ±2.7 to ±5.5V

• Temp Range = -40°C to +85°C

• Package Options 14 L d TSSOP

• Zero Amplitude Wiper Switching

• Pb-Free Plus Anneal Available (RoHS Compliant)

Audio Performance

• 0 to - 62dB Volume Control

• -92dB Mute

- Power-Up to Mute Position

Pinout

SDA

SCL

V+

A0 A1

X9460

(14 LD TSSOP)

TOP VIEW

X9460

14 13 12 11 10

9 8

1 2 3 4 5 6 7

H-right

L-right

W-right

H-left

L-left

W-left

• SNR -96dB

• THD+N: -95dB @1kHz

• Crosstalk Rejection: -102dB @ 1kHz

• Channel-to-Channel Variation: ± 0.1dB

• 3dB-Cutoff: 100kHz

Applications

• Set Top Boxes

• Stereo Amplifiers

• DVD Players

• Portable Audio Products

Ordering Information

PART NUMBER PART MARKING VCC LIMITS (V) TEMP RANGE (°C) PACKAGE

X9460KV14I* X9460KV I 5V ± 10% -40 to +85 14 Ld TSSOP

X9460KV14IZ* (Note) X9460KV Z I -40 to +85 14 Ld TSSOP (Pb-free)

X9460KV14I-2.7* X9460KV G 2.7 to 5.5 -40 to +85 14 Ld TSSOP

X9460KV14IZ-2.7* (Note) X9460KV Z G -40 to +85 14 Ld TSSOP (Pb-free)

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Simplified Functional Diagram

www.BDTIC.com/Intersil

X9460

Power-on Recall

data address

I2C bus

BUS

INTERFACE CONTROL & REGISTER

Detailed Functional Diagram

SCL

SDA

INTERFACE

AND

CONTROL

CIRCUITRY

mute

select inc/dec

Power-on

Recall

mute

DATA

W-Left

H-Left

L-Left

POT Left

WIPER COUNTER REGISTER

(WCR)

POT Left

WIPER

COUNTER REGISTER

(WCR)

W-Right

V+

H-Right

POT Right

L-Right

V+

62dB total

# OF

STEP SIZE

STEPS

-1dB 11

-2dB 10

-3dB 5

-4dB 4

Mute 1

V-

H-Left

L-Left

W-Left

W-Right

H-Right

L-Right

POT Right

V-V

FN8203.2

October 17, 2005

Typical Application

www.BDTIC.com/Intersil

Gain / Volume Control

Left Channel Control Right Channel Control Simultaneous Left and Right Channel

Control

Power-up in Mute

X9460

Audio

DAC

Audio => R RWL, R

HL, RHR

=> Amplifier

X9460

2 XDCP

Audio

Amplifier

Left

Audio

Amplifier

Right

µController

EEPROM

Serial Bus

Pin Assignments

(TSSOP) SYMBOL FUNCTION

1SDASerial Data

2 SCL Serial Clock

4 V+ Positive Analog Supply

6 A0 Device Address

7 A1 Device Address

10 R

11 R

12 R

13 R

W-left

L-left

H-left

W-right

L-right

H-right

14 V- Negative Analog Supply

System Supply Voltage

System Ground

Wiper terminal of the Left Potentiometer

Negative terminal of the Left Potentiometer

Positive terminal of the Left Potentiometer

Wiper terminal of the Right Potentiometer

Negative terminal of the Right Potentiometer

Positive terminal of the Right Potentiometer

FN8203.2

October 17, 2005

X9460

www.BDTIC.com/Intersil

Detailed Pin Description

Host Interface Pins

SERIAL CLOCK (SCL)

The SCL input clocks data into and out of the X9460.

SERIAL DATA (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wireORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph.

DEVICE ADDRESS (A

The Address inputs are used to set the least significant 2 bits of the 8-bit Slave Byte Address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9460. Up to 4 X9460s may be connected to a single I written to (NOTE: you cannot read from more than one device on the same 2-wire bus). If left floating, these pins are internally pulled to ground.

Slave Byte (bits, MSB-LSB) = 0101 0 A

Potentiometer Pins

The R connections on either end of a mechanical potentiometer.

The wiper outputs are equivalent to the wiper output of a mechanical potentiometer.

, R

H-LEFT

and RL inputs are equivalent to the terminal

, R

W-LEFT

L-LEFT

W-RIGHT

, R

Supply Pins

ANALOG SUPPLY V- AND V+

The positive power supply for the DCP analog control section is connected to V+. The negative power supply for the DCP analog control section is connected to V-.

DIGITAL SUPPLIES V

The power supplies for the digital control sections.

Power-up and Down Recommendations

There are no restrictions on the power-up condition of VCC, V+ and V- and the voltages applied to the potentiometer pins provided that the V the voltage at R all times, the voltages on the potentiometer pins must be less than V+ and more than V-.

, RL, and RW, ie. VCC, V+ > RH, RL, RW. At

- A0)

C serial bus and

R/W

1 A0

, R

H-RIGHT

, V

and V+ are more positive or equal to

L-RIGHT

The V ground. V

pin is always connected to the system common or

, VL, VW are the voltages on the RH, RL, and RW

potentiometer pins.

X9460 Principles of Operation

The X9460 is a highly integrated microcircuit incorporating two resistor arrays with their associated registers, counters and the serial interface logic providing direct communication between the host and the DCP potentiometers. This section provides detailed description as following:

- Resistor Array Description

- Serial Interface Description

- Command Set and Register Information Description

Resistor Array Description

The X9460 is comprised of two resistor arrays. Each array contains 31 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R R

inputs). Tables 1 and 2 provide a description of the step

size and tap positions.

At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (R output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The five bits of the WCR are decoded to select, and enable, one of thirty-two switches.

TABLE 1. TOTAL -62dB RANGE PLUS MUTE POSITION

STEP SIZE # OF STEPS

-1dB 11 steps

- 2dB 10 steps

- 3dB 5 steps

- 4dB 4 steps

Mute 1 step

TABLE 2. WIPER TAP POSITION vs dB

TAP POSITION, n dB MIN/MAX dB

for n = 20 to 31 n - 31 -11/0

for n = 10 to 19 2n-51 -31/-13

for n = 5 to 9 3n-61 -46/-34

for n = 1 to 4 4n-66 -62/-50

n = 0 -92 -92

and

)

The following V

ramp rate spec is always in effect.

0.2 V/ms < VCC ramp < 50 V/ms

FN8203.2

October 17, 2005

X9460

www.BDTIC.com/Intersil

Serial Interface Description

Serial Interface

The X9460 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. The X9460 is a slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions.

Start Condition

All commands to the X9460 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9460 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met.

Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data.

The X9460 will respond with an acknowledge: 1) after recognition of a start condition and after an identification and slave address byte, and 2) again after each successful receipt of the instruction or databyte. See Figure 1.

Invalid Commands

For any invalid commands or unrecognizable addresses, the X9460 will NOT acknowledge and return the X9460 to the idle state.

SCL FROM

MASTER

DATA

OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

FIGURE 1. ACKNOWLEDGE RESPONSE FROM RECEIVER

ACKNOWLEDGE

FN8203.2

October 17, 2005

+ 11 hidden pages