intersil X9455 DATA SHEET

®

www.BDTIC.com/Intersil

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Data Sheet July 28, 2006

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X9455

FN8202.1

Dual Two-wiper Digitally-Controlled
(XDCP™) Potentiometer

The X9455 integrates 2 digitally controlled potentiometers
(XDCP), each one with dual wipers, on a monolithic CMOS
integrated circuit.

The digitally controlled potentiometer is implemented using
255 resistive elements in a series array. Between each
element are tap points connected to wiper terminals through
switches. The position of each wiper on the array is
controlled by the user through the U/D or 2-wire bus
interface. Each potentiometer wiper has associated with it
two volatile Wiper Counter Register (WCR) and each WCR
has associated with it four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. The contents of the default data
registers (DR0A0, DR0B0, DR1A0, DR1B0) are loaded into
the WCR on power up.

The DCP can be used as a four-terminal potentiometer in a
wide variety of applications including the programming of
bias voltages, window comparators, and three resistor
programmable networks.

Features

• Dual two-wiper solid state potentiometer

• 256 resistor tap points-0.4% resolution

• 2-wire serial interface for write, read, and transfer
operations of the potentiometer

• Up/Down interface for individual potentiometer wipers

• Wiper resistance, 40Ω typical

• Non-volatile storage of wiper positions

• Power on recall loads saved wiper position on power-up.

• Standby current < 20µA Max

• Maximum wiper current: 3mA

: 2.7V to 5.5V operation

•V

CC

•2.8kΩ,10kΩ, 50kΩ, 100kΩ version of total pot resistance

• Endurance: 100,000 data changes per bit per register

• 100 yr. data retention

• 24 Ld TSSOP

• Pb-free plus anneal available (RoHS compliant)

Pinout

DS0

A0

RW0B

NC

U/D

Vcc

RL0

RH0

RW0A

A2

WP

X9455

(24 LD TSSOP)

TOP VIEW

1

2

3

4

5

6

X9455

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

DS1

SCL

RL1

RH1NC

RW1A

CS

Vss

RW1B

NC

NC

A1

SDA

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Ordering Information

www.BDTIC.com/Intersil

X9455

PART NUMBER

PART

MARKING

V

LIMITS

CC

(V) R

(kΩ) TEMP RANGE (°C) PACKAGE PKG. DWG. #

TOTAL

X9455TV24I-2.7 X9455TV G 2.7 to 5.5 100 -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9455TV24IZ-2.7 (Note) X9455TV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9455UV24I-2.7 X9455UV G 50 -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9455UV24IZ-2.7 (Note) X9455UV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9455WV24I-2.7 X9455WV G 10 -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9455WV24IZ-2.7 (Note) X9455WV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9455YV24I-2.7 X9455YV G 2.8 -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9455YV24IZ-2.7 (Note) X9455YV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Functional Diagram

A2

A1

A0

SDA

SCL

DS0

DS1

CS

U/D

V

CC

2-wire

Interface

Up/Down
Interface

V

SS

POWERUP,

INTERFACE

CONTROL AND

STATUS

WP

WCR0A
DR0A0

DR0A1
DR0A2
DR0A3

WCR0B

DR0B0
DR0B1
DR0B2
DR0B3

R

W0A

DCP0

R

W0B

R

H0

WCR1A

WCR1B

DR1B0

DR1A0
DR1A1

DR1B1

DR1A2

DR1B2

DR1A3

DR1B3

R

L0

R

W1A

DCP1

R

W1B

R

H1

R

L1

2

FN8202.1

July 28, 2006

Pin Descriptions

www.BDTIC.com/Intersil

TSSOP PIN SYMBOL BRIEF DESCRIPTION

1 DS0 Wiper Selection input for Up/Down interface
2 A0 Device Address for 2-wire interface
3 RW0B Second Wiper Terminal of DCP0
4 NC No Connect
5 NC No Connect
6U/D
7 VCC System Supply Voltage
8 RL0 Low Terminal of DCP0

9 RH0 High Terminal of DCP0
10 RW0A First Wiper Terminal of the DCP0
11 A2 Device Address for 2-wire interface
12 WP
13 SDA Serial Data Input/Output for 2-wire interface
14 A1 Device Address for 2-wire interface
15 NC No Connect
16 NC No Connect
17 RW1B Second Wiper Terminal of DCP1
18 VSS System Ground
19 CS
20 RW1A First Wiper Terminal of DCP1
21 RH1 High Terminal of DCP1
22 RL1 Low Terminal of DCP1
23 SCL Serial Clock for 2-wire interface
24 DS1 Wiper selection input for Up/Down interface

X9455

Increment/Decrement for Up/Down interface

Hardware Write Protect (Active low)

Chip select for Up/Down interface

3

FN8202.1

July 28, 2006

X9455

www.BDTIC.com/Intersil

Absolute Maximum Ratings Recommended Operating Conditions

Junction Temperature under bias. . . . . . . . . . . . . . .-65°C to +135°C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any digital interface pin
with respect to V
V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

CC

Voltage at any DCP pin with
respect to V

Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . .300°C

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation
of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating
conditions for extended periods may aff ect devi ce re lia bil ity.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

R

TOTAL

Matching

I

(Note 5) Wiper current See test circuit -3.0 +3.0 mA

W

R

W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

SS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to V

SS

End to end resistance Y, W, U, T versions respectively 2.8, 10, 50,

End to end resistance tolerance -20 +20 %
Power rating 25C, each DCP 50 mW
DCP to DCP resistance matching 0.75 2.0 %

Wiper resistance

Wiper current =

CC

Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage (V

V

CC

R

TOTAL

) (Note 4) Limits . . . . . . . . . . . . . . 2.7V to 5.5V

CC

TYP

(Note 4) MAX UNIT

100

50 150 Ω

kΩ

V

TERM

C

H/CL/CW

I

OL

Voltage on any DCP pin Vss Vcc V
Noise (Note 5) Ref: 1kHz -120 dBV
Resolution 0.4 %
Absolute linearity (Note 1) V(R
Relative linearity
Temperature coefficient of resistance

(Note 5)
Ratiometric Temperature (Note 5)

Coefficient
Potentiometer Capacitance (Note 5) See equivalent circuit 10/10/25 pF
Leakage on DCP pins Voltage at pin from VSS to V

(Note 2) -0.3 +0.3 MI (Note 3)

)=V(RH1)=V

H0

V(RL0)=V(RL1)=V

CC

SS

CC

-1 +1 MI (Note 3)

±300 ppm/°C

-20 +20 ppm/C

0.1 10 µA

DC Electrical Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNITS

I

CC1

I

CC2

I

CC3

I

SB

I

VCC supply current (Volatile write/read) f

VCC supply current (active) f

VCC supply current (nonvolatile write) f

VCC current (standby) V

Leakage current, bus interface pins Voltage at pin from VSS to V

L

= 400kHz; SDA = Open; (for 2-Wire, Active,

SCL

Read and Volatile Write States only)

= 200kHz; (for U/D interface, increment,

SCL

decrement)

= 400kHz; SDA = Open;

SCL

(for 2-Wire, Active, Nonvolatile Write State only)

= +5.5V; VIN = VSS or VCC; SDA = VCC;

CC

(for 2-Wire, Standby State only)

CC

3mA

3mA

5mA

20 µA

-10 10 µA

4

FN8202.1

July 28, 2006

X9455

www.BDTIC.com/Intersil

DC Electrical Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNITS

V
V

V

Endurance and Data Retention

Capacitance

SYMBOL TEST TEST CONDITIONS MAX UNITS

C

IN/OUT

CIN (Note 5) Input capacitance (DS0, DS1, CS, U/D, SCL, WP, A2, A1

Power-Up Timing

SYMBOL PARAMETER MAX UNITS

(Notes 5, 9) Power Up Delay from VCC power up (VCC above 2.7V) to wiper position recall

t

D

Input HIGH voltage VCC x 0.7 VCC + 1 V

IH

Input LOW voltage -1 VCC x 0.3 V

IL

SDA pin output LOW voltage IOL = 3mA 0.4 V

OL

PARAMETER MIN UNITS

Minimum endurance 100,000 Data changes per bit

Data retention 100 Years

(Note 5) Input / Output capacitance (SDA) V

and A0

)

completed, and communication interfaces ready for operation.

= 0V 8 pF

OUT

V

= 0V 6 pF

IN

2ms

A.C. Test Conditions

Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing threshold level V
External load at pin SDA 2.3kΩ to V

x 0.5

CC

and 100 pF to V

CC

SS

2-Wire Interface Timing (s)

SYMBOL PARAMETER MIN MAX UNITS

f

SCL

t

HIGH

t

LOW

t

SU:STA

t

HD:STA

t

SU:STO

t

SU:DAT

t

HD:DAT

(Note 5) SCL and SDA Rise Time 300 ns

t

R

(Note 5) SCL and SDA Fall Time 300 ns

t

F

(Note 5) SCL Low to SDA Data Output Valid Time 0.9 µs

t

AA

t

DH

t

(Note 5) Pulse Width Suppression Time at SCL and SDA inputs 50 ns

IN

(Note 5) Bus Free Time (Prior to Any Transmission) 1200 ns

t

BUF

Clock Frequency 400 kHz
Clock High Time 600 ns
Clock Low Time 1300 ns
Start Condition Setup Time 600 ns
Start Condition Hold Time 600 ns
Stop Condition Setup Time 600 ns
SDA Data Input Setup Time 100 ns
SDA Data Input Hold Time 30 ns

SDA Data Output Hold Time 0 ns

5

FN8202.1

July 28, 2006

X9455

www.BDTIC.com/Intersil

2-Wire Interface Timing (s) (Continued)

SYMBOL PARAMETER MIN MAX UNITS

t

SU:WPA

(Note 5)

t

HD:WPA

(Note 5)

SDA vs. SCL Timing

A0, A1, A2 and WP Setup Time 600 ns

A0, A1, A2 and WP Hold Time 600 ns

SCL

t

SU:STA

(Input Timing)

(Output Timing)

, A0, A1, and A2 Pin Timing

WP

SDA

SDA

SCL

SDA IN

WP, A0, A1, or A2

t

HD:STA

START

t

F

t

SU:DAT

t

SU:WP

Clk 1

t

HIGH

t

LOW

t

HD:DAT

t

HD:WP

t

R

t

SU:STO

t

AA

STOP

t

DH

t

BUF

Increment/Decrement Timing

SYMBOL PARAMETER MIN TYP (Note 4) MAX UNITS

t

CI

(Note 5) SCL HIGH to U/D, DS0 or DS1 change 600 ns

t

ID

(Note 5) U/D, DS0 or DS1 to SCL setup 600 ns

t

DI

t

IL

t

IH

t

IC

t

CPHS

t

CPHNS

(Note 5)

(Note 5) SCL to RW change 100 500 µs

t

IW

t

CYC

, tF (Note 5) SCL input rise and fall time 500 µs

t

R

CS to SCL Setup 600 ns

SCL LOW period 2.5 µs
SCL HIGH period 2.5 µs
SCL inactive to CS inactive (Nonvolatile Store Setup Time) 1 µs
CS deselect time (STORE) 10 ms
CS deselect time (NO STORE) 1 µs

SCL cycle time 5 µs

6

FN8202.1

July 28, 2006