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Data Sheet March 11, 2005
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Programmable Analog
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X9438
FN8199.0
Dual Digitally Controlled Potentiometer
(XDCP™) with Operational Amplifier
FEATURES
• Two CMOS voltage operational amplifiers
• Two digitally controlled potentiometers
• Can be combined or used separately
•Amplifiers:
—Low voltage operation
—V+/V- = ±2.7V to ±5.5V
—Rail-to-rail CMOS performance
—1MHz gain bandwidth product
• Digitally controlled potentiometers
—Dual 64 tap potentiometers
—R
—2-wire serial interface
—V
= 10kΩ
total
= 2.7V to 5.5V
CC
DESCRIPTION
The X9438 is a monolithic CMOS IC that incorporates
two operational amplifiers and two nonvolatile digitally
controlled potentiometers. The amplifiers are CMOS
differential input voltage operational amplifiers with
near rail-to-rail outputs. All pins for the two amplifiers
are brought out of the package to allow combining
them with the potentiometers, or using them as complete stand-alone amplifiers.
The digitally controlled potentiometers consist of a
series string of 63 polycrystalline resistors that behave
as standard integrated circuit resistors. The two-wire
serial port, common to both pots, allows the user to
program the connection of the wiper output to any of
the resistor nodes in the series string. The wiper position is saved in the on board E2 memory to allow for
nonvolatile restoration of the wiper position.
A wide variety of applications can be implemented
using the potentiometers and the amplifiers. A typical
application is to implement the amplifier as a wiper
buffer in circuits that use the potentiometer as a voltage
reference. The potentiometer can also be combined
with the amplifier yielding a digitally programmable gain
amplifier or programmable current source.
BLOCK DIAGRAM
SCL
SDA
A3
A2
A1
A0
WP
V
CC
Control and
Memory
WCR0
WCR1
V
SS
RH0R
R
W0
RW1RL1R
L0
H1
V+
V
NI0
+
–
+
–
V-
V
V
V
V
V
OUT0
INV0
NI1
OUT1
INV1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
X9438
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9438.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor.
Device Address (A
- A3)
0
The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9438. A maximum of 16 devices may share the
same 2-wire serial bus.
Potentiometer Pins
(1)
Analog Supplies V+, V-
The analog supplies V+, V- are the supply voltages for
the XDCP analog section and the operational amplifiers.
System Supply V
The system supply V
and Ground VSS.
CC
and its reference VSS is used
CC
to bias the interface and control circuits.
PIN CONFIGURATION
TSSOP
1
0
2
3
4
5
6
X9438
7
8
9
10
11
2
12
24
23
22
21
20
19
18
17
16
15
14
13
A
3
SCL
V
INV1
V
NI1
V
OUT1
VV
SS
R
W1
R
H1
R
L1
A
1
SDA
V
CC
R
R
H0
R
W0
A
WP
SDA
A1
R
R
H1
R
W1
V
L0
L1
SS
SOIC
1
2
3
4
5
2
6
X9438
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V+
V
OUT0
V
NI0
V
INV0
A0
NC
A
3
SCL
V
INV1
V
NI1
V
OUT1
V-
V
V
NC
A
INV0
V
NI0
OUT0
V+
V
R
R
R
WR
CC
L0
H0
W0
A
RH (R
The R
- RH1), RL (R
H0
and RL inputs are equivalent to the terminal con-
H
L0
- RL1)
nections on either end of a mechanical potentiometer.
R
(R
W0
- RW1)
W
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
Amplifier and Device Pins
Amplifier Input Voltage V
V
and V
NI
are inputs to the noninverting (+) and
INV
(0,1) and V
NI
INV
(0,1)
inverting (-) inputs of the operational amplifiers.
Amplifier Output Voltage V
V
is the voltage output pin of the operational
OUT
OUT
(0,1)
amplifier.
Hardware Write Protect Input WP
The WP pin, when low, prevents non-volatile writes to
the wiper counter registers.
Note: (1) Alternate designations for RH, RL, RW are VH, VL, V
W
PIN NAMES
Symbol Description
SCL Serial Clock
SDA Serial Data
A0 - A3 Device Address
R
- RH1,
H0
- R
R
L0
L1
R
- R
W0
W1
V
V
V
,
NI(0,1)
INV(0,1)
OUT0, VOUT1
Potentiometers (terminal equivalent)
Potentiometers (wiper equivalent)
Amplifier Input Voltages
Amplifier Outputs
WP Hardware Write Protection
V+,V- Analog and Voltage Amplifier Supplies
V
CC
V
SS
System/Digital Supply Voltage
System Ground
NC No Connection
2
FN8199.0
March 11, 2005
X9438
PRINCIPLES OF OPERATION
The X9438 is an integrated microcircuit incorporating
two resistor arrays, two operational amplifiers and
their associated registers and counters; and the serial
interface logic providing direct communication
between the host and the digitally controlled potentiometers and operational amplifiers.
Serial Interface
The X9438 supports a bidirectional bus oriented proto col. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and provide the clock for both transmit and receive operation s.
Therefore, the X9438 will be considered a slave
device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t
). SDA state changes during
LOW
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9438 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
). The X9438 continuously
HIGH
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condition is met.
Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data.
The X9438 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the command byte. If the command is followed by a data byte
the X9438 will respond with a final acknowledge.
Operational Amplifier
The voltage operational amplifiers are CMOS rail-torail output general purpose amplifiers. They are
designed to operate from dual (±) power supplies. The
amplifiers may be configured like any standard amplifier. All pins are externally available to allow connections with the potentiometers or as stand alone
amplifiers.
Potentiometer/Array Description
The X9438 is comprised of two resistor arrays and two
operational amplifiers. Each array contains 63 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R
) output. Within each individual array only one
W
switch may be turned on at a time. These switches are
controlled by a volatile wiper counter register (WCR).
The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
INSTRUCTIONS AND PROGRAMMING
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant four bits of the slave address are the device type
identifier (refer to Figure 1). For the X9438 this is fixed
as 0101[B].
Figure 1. Address/Identification Byte Format
Device Type
Identifier
100
A3 A2 A1 A0
1
Device Address
3
FN8199.0
March 11, 2005
X9438
The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A
- A3 inputs. The X9438 compares
0
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9438 to respond with an acknowledge. The
A
signals or tied to V
inputs can be actively driven by CMOS input
0-A3
or VSS.
CC
Acknowledge Polling
The disabling of the inputs, during the internal non-volatile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the
stop condition is issued to indicate the end of the nonvolatile write command the X9438 initiates the internal
write cycle. ACK polling (Flow 1) can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9438 is
still busy with the write operation no ACK will be
returned. If the X9438 has completed the write operation an ACK will be returned and the master can then
proceed with the next operation.
Flow 1. ACK Polling Sequence
Nonvolatile Write
Command Completed
Enter Ack Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Yes
Further
Operation?
Yes
Issue
Instruction
Prooceed
No
No
Issue STOP
Issue STOP
Prooceed
Instruction Structure
The byte following the address contains the instruction
and register pointer information. The four most significant bits are the instruction. The ne xt four bit s point to
one of the two pots and when applicable they point to
one of the four WCRs associated data registers. The
format is shown below in Figure 2.
Figure 2. Instruction Byte Format
Register
Select
I1I2I3 I0 R1 R0 0 P0
Instructions
WCR Select
The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the two registers that is to be acted upon when a register oriented
instruction is issued. The last bit (P0) selects which
one of the two potentiometers is to be affected by the
instruction.
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions
exchange data between the wiper counter register and
one of the data registers. A transfer from a data register to a wiper counter register is essentially a write to a
static RAM. The response of the wiper to this action
will be delayed t
. A transfer from the wiper counter
WRL
register (current wiper position) to a data register is a
write to non-volatile memory and takes a minimum of
t
to complete. The transfer can occur between one
WR
of the two potentiometers and one of its associated
registers; or it may occur globally, wherein the transfer
occurs between all of the potentiometers and one of
their associated registers.
Four instructions require a three-byte sequence to
complete. The basic sequence is illustrated in Figure
4. These instructions transfer data between the host
and the X9438; either between the host and one of the
data registers or directly between the host and the
wiper counter and analog control registers. These
instructions are: 1) Read Wiper Counter Register or
read the current wiper position of the selected pot, 2)
Write Wiper Counter Register, i.e. change current
wiper position of the selected pot; 3) Read Data Register, read the contents of the selected non-volatile register; 4) Write Data Register, write a new value to the
selected data register. The bit structures of the instructions are shown in Figure 6.
4
FN8199.0
March 11, 2005
Figure 3. Two-Byte Command Sequence
SCL
SDA
S
0101A3A2A1A0A
T
A
R
T
Figure 4. Three-Byte Command Sequence
SCL
SDA
S
0 1 0 1 A3 A2 A1 A0 A
T
A
R
T
C
K
X9438
I3 I2 I1 I0 R1 R0 0 P0 A
C
K
I3 I2 I1 I0 0 P0 R1 R0 A
S
C
T
K
O
P
C
K
D5 D4 D3 D2 D1 D0
A
S
C
T
K
O
P
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9438 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; th ereby, providing a fine
tuning capability to the host. For each SCL clock pulse
Figure 5. Increment/Decrement Command Sequence
SCL
SDA
S
0 1 0 1 A3 A2 A1 A0 A
T
A
R
T
I3 I2 I1 I0 P1 P0 R1 R0 A
C
K
(t
) while SDA is HIGH, the selected wiper will
HIGH
move one resistor segment towards the V
terminal.
H
Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the V
terminal. A detailed illustration of the
L
sequence for this operation is shown in Figure 5.
XX
I
C
K
I
N
N
C
C
1
2
D
I
E
N
C
C
1
n
S
D
T
E
O
C
P
n
5
FN8199.0
March 11, 2005
Figure 6. Instruction Set
Read Wiper Counter Register (WCR)
Read the contents of the Wiper Counter Register P
S
device type
T
identifier
A
R
0101
T
device
addresses
A3A2A1A
instruction
S
opcode
A
C
1001000
K
0
WCR
addresses
Write Wiper Counter Register (WCR)
Write new value to the Wiper Counter Register P
S
device type
T
identifier
A
R
0101
T
device
addresses
A3A2A1A
instruction
S
opcode
A
C
1010000
K
0
.
0
WCR
addresses
X9438
.
0
S
A
C
P
K
0
P0: 0 - WCR0, 1 - WCR1
S
A
C
P
K
0
P0: 0 - WCR0, 1 - WCR1
register data
(sent by slave on SDA)
D5D4D3D2D1D
00
register data
(sent by master on SDA)
D5D4D3D2D1D
00
M
S
A
T
C
O
K
P
0
S
S
A
T
C
O
K
P
0
Read Data Register (DR)
Read the contents of the Register pointed to by P
S
device type
T
identifier
A
R
0101
T
device
addresses
A3A2A1A
S
A
C
K
0
instruction
opcode
1011
and R1 - R0.
0
WCR/DR
addresses
R1R
0
0
S
A
C
P
K
0
register data
(sent by master on SDA)
D5D4D3D2D1D
00
M
S
A
T
C
O
K
P
0
R1 R0: 00 - R0, 10 - R1
01 - R2, 11 - R3
Write Data Register (DR)
Write new value to the Register pointed to by P
S
device type
T
identifier
A
R
0101
T
device
addresses
A3A2A1A
S
A
C
K
0
instruction
opcode
1100
and R1 - R0.
0
WCR/DR
addresses
R1R
0
0
S
A
C
P
K
0
register data
(sent by master on SDA)
D5D4D3D2D1D
00
S
S
A
C
K
0
HIGH-VOLTAGE
T
WRITE CYCLE
O
P
Definitions:
SACK - Slave acknowledge, MACK - Master acknowledge, I/D - Increment/De crement (1/0), R - Register,
P - Potentiometer
6
FN8199.0
March 11, 2005
X9438
Figure 6. Instruction Set (continued)
Transfer Data Register to Wiper Counter Register
Transfer the contents of the Register pointed to by R
S
device type
T
identifier
A
R
0101
T
device
addresses
A3A2A1A
S
A
C
K
0
instruction
opcode
1101
Transfer Wiper Counter Register to Data Register
Transfer the contents of the WCR pointed to by P
S
device type
T
identifier
A
R
0101
T
device
addresses
A3A2A1A
S
A
C
K
0
instruction
opcode
1110
Global Transfer Data Register to Wiper Counter Register
Transfer the contents of all four Data Registers pointed to by R
S
device type
T
identifier
A
R
0101
T
device
addresses
A3A2A1A
S
A
C
K
0
instruction
opcode
0001
- R0 to the WCR pointed to by P0.
1
WCR/DR
addresses
R1R
to the Register pointed to by R1 - R0.
0
P
0
0
0
WCR/DR
addresses
R1R
P
0
0
0
DR
addresses
R1R
0
00
S
S
A
T
C
O
K
P
S
S
A
C
K
1
S
A
C
K
HIGH-VOLTAGE
T
WRITE CYCLE
O
P
- R0 to their respective WCR.
S
T
O
P
Global Transfer Wiper Counter Register to Data Register
Transfer the contents of all WCRs to their respective data Registers pointed to by R
S
device type
T
identifier
A
R
0101
T
device
addresses
A3A2A1A
S
A
C
K
0
instruction
opcode
1000
DR
addresses
R1R
0
00
S
S
A
C
K
HIGH-VOLTAGE
T
WRITE CYCLE
O
P
Increment/Decrement Wiper Counter Register
WCR
.
0
increment/decrement
S
(sent by master on SDA)
A
C
P
I/DI/
K
0
....
D
Enable Increment/decrement of the WCR pointed to by P
S
device type
T
identifier
A
R
0101
T
device
addresses
A3A2A1A
instruction
S
opcode
A
C
0010000
K
0
addresses
P0: 0 or 1 only.
1
- R0.
I/DI/
S
T
O
P
D
7
FN8199.0
March 11, 2005
X9438
REGISTER OPERATION
Both digitally controlled potentiometers share the
serial interface and share a common architecture.
Each potentiometer is associated with a Wiper
Counter Register (WCR), and four Data Registers.
Figure 7 illustrates the control, registers, and system
features of the device.
Figure 7. System Block Diagram
V
H (0,1)
WP
SCL
SDA
A0
A1
A2
A3
Interface
and
Control
Circuitry
(DR0-DR3)
0,1
WCR
0,1
V
L (0,1)
V
W (0,1)
V
INV (0,1)
V
NI (0,1)
+
–
V
OUT (0,1)
Wiper Counter (WCR) and Analog Control Registers
(ACR)
The X9438 contains two wiper counter registers, one
for each XDCP. The wiper counter register is equivalent to a serial-in, parallel-out counter, with its outputs
decoded to select one of sixty-four switches along its
resistor array. The contents of the wiper counter register can be altered in four ways: it may be written
directly by the host via the write WCR Instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated data registers
(DR) via the XFR data register instruction (parallel
load); it can be modified one step at a time by the
increment/decrement instruction (WCR only). Finally,
it is loaded with the contents of its data register zero
(R0) upon power-up.
The wiper counter register is a volatile register; that is,
its contents are lost when the X9438 is powered-down.
Although the registers are automatically loaded with the
value in R0 upon power-up, it should be noted this may
be different from the value present at power-down.
Data Registers (DR)
Each potentiometer has four non-volatile data registers
(DR). These can be read or written directly by the host
and data can be transferred between any of the four
data registers and the WCR. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could store system parameters or user preference data.
REGISTER DESCRIPTIONS AND MEMORY MAP
Memory Map
WCRO WCR1
DR0 DR0
DR1 DR1
DR2 DR2
DR3 DR3
Wiper Counter Register (WCR)
0 0 WP5 WP4 WP3 WP2 WP1 WP0
(volatile) (LSB)
WP0-WP5 identify wiper position.
Data Registers (DR, R0 - R3)
Wiper Position or User Data
(Nonvolatile)
8
FN8199.0
March 11, 2005
X9438
ABSOLUTE MAXIMUM RATINGS
Temperature under bias....................-65°C to +135°C
Storage temperature .........................-65°C to +150°C
Voltage on SDA, SCL or any address
input with respect to V
Voltage on any V+ (referenced to V
Voltage on any V- (referenced to V
......................... -1V to +7V
SS
) ................ +7V
SS
) .................. -7V
SS
(V+) - (V-) .............................................................10V
Any R
Any R
....................................................................V+
H
......................................................................V-
L
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C+70°C
Industrial -40
°C+85°C
Device Supply Voltage (VCC) Limits
X9438 5V ±10%
X9438-2.7 2.7V to 5.5V
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol Parameter
R
TOTAL
End to end resistance -20 +20 %
Test ConditionsMin. Typ. Max. Unit
Power rating 50 mW 25°C, each pot
I
R
Wiper current -3 +3 mA
W
Wiper resistance 40 100 Ω VCC = 5V, Wiper Current = 3mA
W
100 250 Ω V
= 2.7, Wiper Current = 1mA
CC
Vv+ Voltage on V+ pin X9438 +4.5 +5.5 V
X9438-2.7 +2.7 +5.5
Vv- Voltage on V- pin X9438 -5.5 -4.5 V
X9438-2.7 -5.5 -2.7
V
TERM
Voltage on any RH or RL pin V- V+ V
Noise -100 dBv Ref: 1V
Resolution
Absolute linearity
Relative linearity
(4)
(1)
(2)
Temperature coefficient of R
-1 +1 MI
-0.2 +0.2 MI
TOTAL
1.6 %
(3)
(3)
±300 ppm/°C
V
w(n)(actual)
V
w(n + 1)
- [V
- V
w(n) + MI
w(n)(expected)
]
Ratiometric temperature coefficient ±20 ppm/°C
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-
eter. It is a measure of the error in step size.
(3) MI = RTOT/63 or (R
(4) Individual array resolutions
- RL)/63, single pot ( = LSB)
H
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X9438
AMPLIFIER ELECTRICAL CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Industrial Commercial
Symbol Parameter Condition
V
OS
TC
VOS
I
B
I
OS
CMRR Common mode
PSRR Power supply
V
CM
A
V
V
O
I
O
I
S
GB Gain-bandwidth prod R
SR Slew rate R
Φ
M
Input offset voltage V+/V- ±3V to ±5V 1 3 1 2 mV
Input offset voltage temp.
V+/V- ±3V to ±5V -10 -10 µV/°C
coefficient
Input bias current V+/V- ±3V to ±5V 50 50 pA
Input offset current V+/V- ±3V to ±5V 25 25 pA
V
= -1V to +1V 70 70 dB
CM
rejection ratio
V+/V- ±3V to ±5V 70 70 dB
rejection ratio
Input common mode voltage
Tj = 25°C V- V+ V- V+ V
range
Large signal voltage gain VO = -1V to + 1V 30 50 30 50 V/mV
Output voltage swing V-
+0.1
V+
Output current V+/V- = ±5.5V
V+/V- = ±3.3V
50
30
Supply current V+/V- = ±5.0V 3 3 mA
V+/V- = ±3.0V 1.5 1.5 mA
= 100k, CL = 50pf 1.0 1.0 MHz
L
= 100k, CL = 50pf 1.5 1.5 V/µsec
L
Phase margin RL = 100k, CL = 50pf 80 80 Deg.
-.15
+0.1
50
30
-.15
UnitMin. Typ. Max. Min. Typ. Max.
V
V
mA
mA
V+ and V- (±5V to ±3V) are the amplifier power supplies. The amplifiers are specified with dual power supplies. V
and VSS
CC
is the logic supply. All ratings are over the temperature range for the Industrial (-40 to + 85°C) and Commercial (0 to 70°C)
versions of the part unless specified differently.
SYSTEM/DIGITAL D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol Parameter
I
I
I
I
V
V
V
CC
SB
LI
LO
IH
IL
OL
VCC supply current (active) 400 µA f
VCC current (standby) 1 µA SCL = SDA = VCC, Addr. = V
Input leakage current 10 µA VIN = VSS to V
Output leakage current 10 µA V
Input HIGH voltage VCC x 0.7 VCC + 0.5 V
Input LOW voltage -0.5 VCC x 0.1 V
Output LOW voltage 0.4 V IOL = 3mA
SCL
Other Inputs = V
Test ConditionsMin. Typ. Max. Unit
= 400kHz, SDA = Open,
SS
CC
= VSS to V
OUT
CC
SS
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X9438
ENDURANCE AND DATA RETENTION
Parameter Min. Unit
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 Years
CAPACITANCE
Symbol Test Typical Unit Test Conditions
C
I/O
C
IN
| CH | C
C
L
W
POWER-UP TIMING AND SEQUENCE
Power-up sequence
Power-down sequence: no limitation
A.C. TEST CONDITIONS
Input pulse levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level V
Note: (1) Applicable to recall and power consumption applications
Input/output capacitance (SDA) 8 pF V
Input capacitance (A0, A1, A2, A3, and SCL) 6 pF VIN = 0V
Potentiometer capacitance 10/10/25 pF See SPICE Model
(1)
: (1) VCC (2) V+ and V-
x 0.5
CC
I/O
= 0V
EQUIVALENT A.C. LOAD CIRCUIT SPICE Macro Model
5V
1533Ω
SDA Output
100pF
2.7V
100pF
R
H
R
TOTAL
C
H
C
W
R
W
R
L
C
L
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TIMING DIAGRAMS
START and STOP Timing
(START) (STOP)
SCL
t
SU:STA
SDA
Input Timing
t
HD:STA
X9438
t
R
t
R
t
F
t
SU:STO
t
F
t
CYC
SCL
SDA
t
SU:DAT
Output Timing
SCL
SDA
DCP Timing (for All Load Instructions)
SCL
t
HIGH
t
LOW
t
HD:DAT
t
AA
t
DH
t
BUF
(STOP)
SDA
VWx
12
LSB
t
WRL
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DCP Timing (for Increment/Decrement Instruction)
SCL
X9438
SDA
VWx
Wiper Register Address Inc/Dec Inc/Dec
Write Protect and Device Address Pins Timing
(START) (STOP)
SCL
SDA
t
SU:WPA
WP
A0, A1
A2, A3
...
(Any Instruction)
...
...
t
HD:WPA
t
WRID
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X9438
AC TIMING
Symbol Parameter Min. Max. Unit
f
SCL
t
CYC
t
HIGH
t
LOW
t
SU:STA
t
HD:STA
t
SU:STO
t
SU:DAT
HD:DAT
t
R
t
F
t
AA
t
DH
T
I
t
BUF
t
SU:WPA
t
HD:WPA
(4)
t
Note: (4) VCC = 5V/2.7V
Clock frequency 400 kHz
Clock cycle time 2500 ns
Clock high time 600 ns
Clock low time 1300 ns
Start setup time 600 ns
Start hold time 600 ns
Stop setup time 600 ns
SDA data input setup time 100 ns
SDA data input hold time 0/30 ns
SCL and SDA rise time 300 ns
SCL and SDA fall time 300 ns
SCL low to SDA data output valid time 100 900 ns
SDA data output hold time 50 ns
Noise suppression time constant at SCL and SDA inputs 50 ns
Bus free time (Prior to Any Transmission) 1300 ns
WP, A0, A1, A2 and A3 setup time 0 ns
WP, A0, A1, A2 and A3 hold time 0 ns
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol Parameter Typ. Max. Unit
t
WR
High-voltage write cycle time (store instructions) 5 10 ms
DCP TIMING
Symbol Parameter Min. Max. Unit
t
WRL
RAMP (sample tester)
V
CC
Wiper response time after instruction issued (All load instructions) 10 µs
Symbol Parameter Typ. Max. Unit
trV
CC
VCC Power-up rate .2 50 V/ms
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BASIC APPLICATIONS
X9438
1
3
R
4
VO = G V
Attenuator
–
+
R1 = R3 = R
R2 = 2R
S
R
2
V
O
4
1
I to V Converter
R
3
R
1
–
+
VO/IS = -R3(1 + R2/R1) + R
R
2
V
V
O
2
S
R
R
-1/2 ≤ G ≤ +1/2
Absolute Value Amplifier with Gain
Phase Shifter
2R
R
V
S
R
RR
–
+
A
1
R
VO = |VS|
1
R
R
1
–
V
+
A
2
O
V
S
1
C
VO/VS = 180° - 2tan-1wRC
R
1
–
V
+
O
R
15
Function Generator
R
–
2
R
1
+
R
}
A
R
}
B
C
–
+
frequency ∝ R1, R2, C
amplitude ∝ R
, R
A
B
FN8199.0
March 11, 2005
PACKAGING INFORMATION
24-Lead Plastic Small Outline Gull Wing Package Type S
X9438
0° - 8°
Pin 1 Index
(4X) 7°
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.015 (0.40)
0.050 (1.27)
Pin 1
X 45°
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
0.009 (0.22)
0.013 (0.33)
0.420"
0.290 (7.37)
0.299 (7.60)
0.003 (0.10)
0.012 (0.30)
0.050" Typical
0.393 (10.00)
0.420 (10.65)
0.092 (2.35)
0.105 (2.65)
0.050"
Typical
0.030" Typical
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
24 Places
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PACKAGING INFORMATION
.026 (.65) BSC
X9438
24-Lead Plastic, TSSOP Package Type V
0 - 8°
.0075 (.19)
.0118 (.30)
.303 (7.70)
.311 (7.90)
.020 (.50)
.030 (.75)
Detail A (20X)
.169 (4.3)
.177 (4.5)
.047 (1.20)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
Seating Plane
.252 (6.4) BSC
(1.78)
(0.42)
(0.65)
(4.16)
(7.72)
See Detail “A”
.031 (.80)
.041 (1.05)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
ALL MEASUREMENTS ARE TYPICAL
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Ordering Information
X9438
Device
X9438 P T V
Y
VCC Limits
Blank = 5V ±10%
-2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Package
P24 = 24-Lead Plastic DIP
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
Potentiometer Organization
Pot 0 Pot 1
W = 10kΩ 10kΩ
Y = 2.5kΩ 2.5kΩ
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
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