intersil X9429 DATA SHEET

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X9429

Low Noise/Low Power/2-Wire Bus

Data Sheet October 19, 2005

Single Digitally Controlled Potentiometer (XDCP™)

FEATURES

• Single Voltage Potentiometer

• 64 Resistor Taps

• 2-wire Serial Interface for Write, Read, and Transfer Operations of the Potentiometer

• Wiper Resistance, 150Ω Typical at 5V

• Non-Volatile Storage of Multiple Wiper Positions

• Power-on Recall. Loads Saved Wiper Position on Power-up.

• Standby Current < 5µA Max

: 2.7V to 5.5V Operation

•V

• 2.5kΩ, 10kΩ Total Pot Resistance

• Endurance: 100, 000 Data Changes per Bit per Register

• 100 yr. Data Retention

• 14 Ld TSSOP, 16 Ld SOIC

• Low Power CMOS

• Pb-Free Plus Anneal Available (RoHS Compliant)

FN8248.2

DESCRIPTION

The X9429 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit.

The digital controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user th rough the 2-wire bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the re sistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR.

The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

BLOCK DIAGRAM

address

status

2-wire bus interface

data

Bus

Interface &

Control

write

read transfer inc / dec

control

Power-on Recall

Wiper Counter

Data Registers

4 Bytes

VL/R

wiper

VH/R

VW/R

10kΩ

64-taps

POT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

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Ordering Information

POTENTIOMETER

PART NUMBER PART MARKING VCC LIMITS (V)

X9429WS16* X9429WS 5 ±10% 10 0 to 70 16 Ld SOIC (300 mil)

X9429WS16Z* (Note) X9429WS Z 0 to 70 16 Ld SOIC (300 mil) (Pb-free)

X9429WS16I* X9429WS I -40 to 85 16 Ld SOIC (300 mil)

X9429WS16IZ* (Note) X9429WS Z I -40 to 85 16 Ld SOIC (300 mil) (Pb-free)

X9429WV14* X9429WV 0 to 70 14 Ld TSSOP (4.4mm)

X9429WV14Z* (Note) X9429WV Z 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)

X9429WV14IZ* (Note) X9429WV Z I -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9429WV14I* X9429WV I -40 to 85 14 Ld TSSOP (4.4mm)

X9429YS16* X9429YS 2.5 0 to 70 16 Ld SOIC (300 mil)

X9429YS16Z* (Note) X9429YS Z 0 to 70 16 Ld SOIC (300 mil) (Pb-free)

X9429YS16I* X9429YS I -40 to 85 16 Ld SOIC (300 mil)

X9429YS16IZ* (Note) X9429YS Z I -40 to 85 16 Ld SOIC (300 mil) (Pb-free)

X9429YV14* X9429YV 0 to 70 14 Ld TSSOP (4.4mm)

X9429YV14Z* (Note) X9429YV Z 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)

X9429YV14I* X9429YV I -40 to 85 14 Ld TSSOP (4.4mm)

X9429YV14IZ* (Note) X9429YV Z I -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9429WS16-2.7* X9429WS F 2.7 to 5.5 10 0 to 70 16 Ld SOIC (300 mil)

X9429WS16Z-2.7* (Note) X9429WS Z F 0 to 70 16 Ld SOIC (300 mil) (Pb-free)

X9429WS16I-2.7* X9429WS G -40 to 85 16 Ld SOIC (300 mil)

X9429WS16IZ-2.7* (Note) X9429WS Z G -40 to 85 16 Ld SOIC (300 mil) (Pb-free)

X9429WV14-2.7* X9429WV F 0 to 70 14 Ld TSSOP (4.4mm)

X9429WV14Z-2.7* (Note) X9429WV Z F 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)

X9429WV14I-2.7* X9429WV G -40 to 85 14 Ld TSSOP (4.4mm)

X9429WV14IZ-2.7* (Note) X9429WV Z G -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9429YS16-2.7* X9429YS F 2.5 0 to 70 16 Ld SOIC (300 mil)

X9429YS16Z-2.7* (Note) X9429YS Z F 0 to 70 16 Ld SOIC (300 mil) (Pb-free)

X9429YS16I-2.7* X9429YS G -40 to 85 16 Ld SOIC (300 mil)

X9429YS16IZ-2.7* (Note) X9429YS Z G -40 to 85 16 Ld SOIC (300 mil) (Pb-free)

X9429YV14-2.7* X9429YV F 0 to 70 14 Ld TSSOP (4.4mm)

X9429YV14Z-2.7* (Note) X9429YV Z F 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)

X9429YV14I-2.7* X9429YV G -40 to 85 14 Ld TSSOP (4.4mm)

X9429YV14IZ-2.7* (Note) X9429YV Z G -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE

FN8248.2

October 19, 2005

DETAILED FUNCTIONAL DIAGRAM

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X9429

SCL

SDA

INTERFACE

AND

CONTROL

CIRCUITRY

Control

DATA

CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF circuits

• Provide a control variable (I, V, or R) in feedback circuits

DR1

DR0

DR2 DR3

Power-on Recall

WIPER

COUNTER REGISTER

(WCR)

10kΩ

64--taps

RH/V

SYSTEM LEVEL APPLICATIONS

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in communication systems

• Set and regulate the DC biasing point in an RF power amplifier in wireless systems

• Control the gain in audio and home entertainment systems

• Provide the variable DC bias for tuners in RF wireless systems

• Set the operating points in temperature control systems

• Control the operating point for sensors in industrial systems

• Trim offset and gain errors in artificial intelligent systems

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PIN CONFIGURATION

1 2 3 4 5 6 7 8

SOIC

X9429

16 15 14 13 12 11 10 9

TSSOP

NC NC

NC A2

SCL

SDA

VSS

1 2

3 4

5 6

X9429

14 13

12 11

RL/V

RH/V

W/VW

9 8

NC NC NC

SCL

SDA

VSS

PIN ASSIGNMENTS

TSSOP pin SOIC pin Symbol Brief Description

1 1 NC No Connect 2 2 NC No Connect 3 3 NC No Connect 4 4 A2 Device Address for 2-wire bus. 5 5 SCL Serial Clock for 2-wire bus. 6 6 SDA Serial Data Input/Output for 2-wire bus. 78V

89WP

System Ground Hardware Write Protect

9 10 A0 Device Address for 2-wire bus. 10 11 A3 Device Address for 2-wire bus. 11 12 R 12 13 R 13 14 R 14 16 V

/ V

Wiper Terminal of the Potentiometer. High Terminal of the Potentiometer. Low Terminal of the Potentiometer. System Supply Voltage

15 NC No Connect

7 NC No Connect

RL/V RH/V RW/V

L H

PIN DESCRIPTIONS

Device Address (A

The Address inputs are used to set the least

Host Interface Pins

significant 3 bits of the 8-bit slav e addre ss. A matc h in the slave address serial data stream must be made

Serial Clock (SCL)

The SCL input is used to clock data into and out of the X9429.

Serial Data (SDA)

with the Address input in order to initiate communication with the X9429. A maximum of 8 devices may occupy the 2-wire serial bus.

Potentiometer Pins

SDA is a bidirectional pin used to transfer data into

, RL/V

and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical

H/VH

The RH/VH and RL/VL inputs are equivalent to the terminal connections on either end of a mechanical

potentiometer. values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph.

, A2, A3)

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RW/V

The wiper outputs are equivalent to the wiper output of a mechanical potentiometer.

Hardware Write Protect Input WP

The WP pin when low prevents nonvolatile writes to the Data Registers.

PRINCIPLES OF OPERATION

The X9429 is a highly integrated microcircuit incorporating a resistor array and its associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers.

Serial Interface

The X9429 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9429 will be considered a slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW periods (t

). SDA state changes during

LOW

SCL HIGH are reserved for indicating start and stop conditions.

Start Condition

All commands to the X9429 are preceded by the start condition, which is a HIGH to LOW transit ion of SDA while SCL is HIGH (t

). The X9429 continuously

HIGH

monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met.

during this period the receiver pulls the SDA line LOW

to acknowledge that it successfully received the eight

bits of data.

The X9429 will respond with an acknowledge after

recognition of a start condition and its slave address

and once again after successful receipt of the

command byte. If the command is followed by a data

byte the X9429 will respond with a final acknowledge.

Array Description

The X9429 is comprised of a resistor array. The array

contains 63 discrete resistive segments that are

connected in series. The physical ends of the array

are equivalent to the fixed terminals of a mechanical

potentiometer (V

and VL/RL inputs).

H/RH

At both ends of the array and between each resistor

segment is a CMOS switch connected to the wiper

) output. Within each individual array only one

W/RW

switch may be turned on at a time. These switches are

controlled by the Wiper Counter Register (WCR). The

six bits of the WCR are decoded to select, and enable,

one of sixty-four switches.

The WCR may be written directly, or it can be changed

by transferring the contents of one of four associated

Data Registers into the WCR. These Data Registers

and the WCR can be read and written by the host

system.

Device Addressing

Following a start condition the master must output the

address of the slave it is accessing. The most

significant four bits of the slave address are the device

type identifier (refer to Figure 1). For the X9429 this is

fixed as 0101[B].

Figure 1. Slave Address

Device Type

Identifier

Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transit ion of SDA while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and

The next four bits of the slave address are the device

address. The physical device address is defined by the

state of the A

the serial data stream with the address input state; a

successful compare of all three address bits is required

for the X9429 to respond with an acknowledge. The A

, and A3 inputs can be actively driven by CMOS input

signals or tied to V

100

, A2, and A3 inputs. The X9429 compares

or VSS.

A3 A2 0 A0

Device Address

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Acknowledge Polling

The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9429 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9429 is still busy with the write operation no ACK will be returned. If the X9429 has completed the write operation an ACK will be returned, and the master can then proceed with the next operation.

Instruction Structure

The next byte sent to the X9429 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of four associated registers. The format is shown below in Figure 2.

Figure 2. Instruction Byte Format

Select

Flow 1. ACK Polling Sequence

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

YES

Further

Operation?

YES

Issue

Instruction

Issue STOP

I1I2I3 I0 R1 R0 0 0

Instructions

Proceed

The four high order bits define the instruction. The

next two bits (R1 and R0) select one of the four

registers that is to be acted upon when a register

oriented instruction is issued. Bits 0 and 1 are defin ed

to be 0.

Four of the seven instructions end with the

transmission of the instruction byte. The basic

sequence is illustrated in Figure 3. These two-byte

instructions exchange data between the Wiper

Counter Register and one of the Data Registers. A

transfer from a Data Register to a Wiper Counter

response of the wiper to this action will be delayed

. A transfer from the Wiper Counter Register

WRL

(current wiper position), to a Data Register is a write to

nonvolatile memory and takes a minimum of t

complete.

Four instructions require a three-byte sequence to

complete. These instructions transfer data between the

host and the X9429; either between the host and one of

the Data Registers or directly between the host and the

Wiper Counter Register. These instructions are:

FN8248.2

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Figure 3. Two-Byte Instruction Sequence

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SCL

SDA

0101A3A20A0A T A R T

Read Wiper Counter Register (read the current wiper position of the selected pot), write Wiper Counter Register (change current wiper position of the selected pot), read Data Register (read the contents of the selected nonvolatile register) and write Data Register (write a new value to the selected Data Register). The sequence of operations is shown in Figure 4.

The Increment/Decrement command is different from the other commands. Once the command is issued and the X9429 has responded with an acknowledge,

X9429

I3 I2 I1 I0 R1 R0 0 0 A C K

the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse

) while SDA is HIGH, the selected wiper will

HIGH

move one resistor segment towards the V terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the V illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively.

O P

terminal. A detailed

L/RL

H/RH

Table 1. Instruction Set

Instruction Set

Instruction

Read Wiper Counter Register

Write Wiper Counter Register

1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register

1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register

Read Data Register 1 0 1 1 1/0 1/0 0 0

Write Data Register 1 1 0 0 1/0 1/0 0 0 XFR Data Register to

Wiper Counter Register

11011/01/00 0

XFR Wiper Counter Register to Data Regis-

11101/01/00 0

ter Increment/Decrement

Wiper Counter Register

Note: (1) 1/0 = data is one or zero

001000 0 0

OperationI3I2I1I0R1R0X1X

Read the contents of the Data Register pointed to

- R

by R

Write new value to the Data Register pointed to by

- R

Transfer the contents of the Data Register pointed to by R

- R0 to its Wiper Counter Register

Transfer the contents of the Wiper Counter Register to the Data Register pointed to by R

- R

Enable Increment/decrement of the Wiper Counter Register

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Figure 4. Three-Byte Instruction Sequence

SCL

SDA

0 1 0 1 A3 A2 0 A0 A T A R

Figure 5. Increment/Decrement Instruction Sequence

SCL

SDA

I3 I2 I1 I0 R1 R0 0 0 A C K

0 0 D5 D4 D3 D2 D1 D0 C K

O P

0101A3A20A0 T A R T

A C K

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

Issued

SCL

SDA

VW/R

Voltage Out

I3 I2 I1 I0 R0 0 0 A

I N C 1

WRID

I N C 2

C K

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Figure 7. Acknowledge Response from Receiver

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X9429

SCL from

Master

Data Output

from Transmitter

Data Output

from Receiver

START

Figure 8. Detailed Potentiometer Block Diagram

Serial Data Path From Interface

Circuitry

8 6

If WCR = 00[H] then VW/RW = VL/R If WCR = 3F[H] then VW/RW = VH/R

UP/DN

Modified SCL

Serial Bus

Input

Parallel Bus

Input

UP/DN CLK

Acknowledge

o u

Wiper

Counter

(WCR)

INC/DEC

Logic

D e

c o d e

VH/R

VL/R

VW/R

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DETAILED OPERATION

The potentiometer has a Wiper Counter Register and four Data Registers. A detailed discussion of the register organization and array operation follows.

Wiper Counter Register

The X9429 contains a Wiper Counter Register. The Wiper Counter Register can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up.

The WCR is a volatile register; that is, its contents are lost when the X9429 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, it should be noted this may be different from the value present at power-do wn.

Data Registers

The potentiometer has four nonvolatile Data Registers. These can be read or written directly by the host and data can be transferred bet ween any of the four Data Registers and the Wiper Counter Register. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms.

Data Registers, (6-Bit), Nonvolatile

D5 D4 D3 D2 D1 D0

NV NV NV NV NV NV

(MSB) (LSB)

Four 6-bit Data Registers for each XDCP. – {D5~D0}: These bits are for general purpose not

volatile data storage or for storage of up to four different wiper values. The contents of Data Register 0 are automatically moved to the Wiper Counter Register on power-up.

Wiper Counter Register, (6-Bit), Volatile

WP5 WP4 WP3 WP2 WP1 WP0

VVVVVV

(MSB) (LSB)

One 6-bit wiper counter register for each XDCP. – {D5~D0}: These bits specify the wiper position of the

respective XDCP. The Wiper Counter Register is loaded on power-up by the value in Data Register 0. The contents of the WCR can be loaded from any of the other Data Register or directly. The contents of the WCR can be saved in a DR.

If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory loca tions that could possibly store system parameters or user preference data.

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Instruction Format

Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.

(2) “A3 ~ A0”: stands for the device addresses sent by the master. (3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition. (4) “I”: stands for the increment operation, SDA held high during active SCL phase (high). (5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

Read Wiper Counter Register (WCR)

device type

identifier A R

0101

Write Wiper Counter Register (WCR)

device type

identifier

T A R

0101

device

addresses

A3A

device

addresses

A3A

instruction

opcode

A C

10010000 00WP

instruction

opcode

A C

10100000 00WP

(sent by slave on SDA)

A C K

(sent by master on SDA)

A C K

wiper position

Read Data Register (DR)

device type

identifier

T A R

0101

device

addresses

A3A

S A

instruction

opcode

1011

addresses

R1R

00 00WP

S A

Write Data Register (DR)

device type

identifier

T A R

0101

device

addresses

A3A

S A C

instruction

opcode

1100

addresses

R1R

00 00WP

S A C K

XFR Data Register (DR) to Wiper Counter Register (WCR)

device type

identifier A R

0101

device

addresses

A3A

S A

instruction

opcode

1101

addresses

R1R

S A C K

wiper position/data

(sent by slave on SDA)

wiper position/data

(sent by master on SDA)

S T O P

HIGH-VOLTAGE

WRITE CYCLE

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XFR Wiper Counter Register (WCR) to Data Register (DR)

device type

identifier

T A R

0101

device

addresses

A3A

A 0

instruction

opcode

1110

Increment/Decrement Wiper Counter Register (WCR)

device type

identifier

T A R

0101

device

addresses

A3A

A 0

instruction

opcode

A C

00100000

SYMBOL TABLE Guidelines for Calculating Typical Values of Bus

WAVEFORM INPUTS OUTPUTS

Must be steady

May change from Low to High

May change from High to Low

Don’t Care: Changes Allowed

N/A Center Line

Will be steady

Will change from Low to High

Will change from High to Low

Changing: State Not Known

is High Impedance

addresses

R1R

A C K

HIGH-VOLTAGE

WRITE CYCLE

increment/decrement

(sent by master on SDA)

A C

I/DI/

....

Pull-Up Resistors

Resistance (K)

I/DI/

120 100

80 60

40 20

Min. Resistance

20 40 60 80 100 120

Bus Capacitance (pF)

T O P

CC MAX

MIN

OL MIN

MAX

Max. Resistance

BUS

=1.8kΩ

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ABSOLUTE MAXIMUM RATINGS

Temperature under bias: ........................-65°C to +135°C

Storage temperature: .............................-65°C to +150°C

Voltage on SCL, SDA any address input

with respect to V

∆V = | (V

- VL) |.............................................................5V

:...................................-1V to +7V

Lead temperature (soldering, 10 seconds)..............300°C

(10 seconds)...................................................±6mA

COMMENT

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature Min. Max.

Commercial 0°C+70°C

Industrial -40°C+85°C

Device Supply Voltage (VCC) Limits

X9429 5V ±10%

X9429-2.7 2.7V to 5.5V

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Limits

Symbol Parameter

Test ConditionsMin. Typ. Max. Unit

End to End Resistance Tolerance ±20 % Power rating 50 mW 25°C, each pot

Wiper current ±3 mA Wiper resistance 150 250 Ω Wiper current = ± 1mA, VCC = 5V

400 1000 Ω Wiper current = ± 1mA, V

TERM

Voltage on any VH/RH or VL/RL pin V

= 0V

Noise -120 dBV Ref: 1kHz Resolution Absolute Linearity Relative Linearity Temperature Coefficient of R

(4)

(1)

(2)

TOTAL

1.6 % ±1 MI

±0.2 MI

(3) (3)

±300 ppm/°C

w(n)(actual)

w(n + 1)

- [V

- V

w(n) + MI

Ratiometric Temperature Coefficient ±20 ppm/°C

H/CL/CW

Potentiometer Capacitances 10/10/25 pF See Circuit #3,

Spice Macromodel

w(n)(expected)

]

= 3V

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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter

CC1

CC2

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as

VCC supply current (nonvolatile write)

VCC supply current (mov e w iper , write, read)

1mAf

Other Inputs = V

100 µA f

Other Inputs = V VCC current (standby) 5 µA SCL = SDA = VCC, Addr. = V Input leakage current 10 µA VIN = VSS to V Output leakage current 10 µA V Input HIGH voltage VCC x 0.7 VCC x 0.5 V Input LOW voltage -0.5 VCC x 0.1 V Output LOW voltage 0.4 V IOL = 3mA

a potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-

ometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (R (4) Typical = individual array resolutions.

- RL)/63, single pot

Test ConditionsMin. Typ. Max. Unit

= 400kHz, SDA = Open,

SCL

= 400kHz, SDA = Open,

SCL

= VSS to V

OUT

ENDURANCE AND DATA RETENTION

Parameter Min. Unit

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 Years

CAPACITANCE

Symbol Test Max. Unit Test Conditions

(5)

I/O

(5)

Input/output capacitance (SDA) 8 pF V

I/O

= 0V

Input capacitance (A0, A2,and A3 and SCL) 6 pF VIN = 0V

POWER-UP TIMING

Symbol Parameter Min. Typ. Max. Unit

(6)

tRV

VCC Power-up ramp rate 0.2 50 V/msec

POWER-UP AND POWER-DOWN REQUIREMENTS

There are no restrictions on the power-up or power-down conditions of V potentiometer pins provided that V The V

Notes: (5) This parameter is periodically sampled and not 100% tested

ramp rate spec is alway in effect.

(6) Sample tested only.

is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW.

and the voltage applied to the

FN8248.2

October 19, 2005

X9429

www.BDTIC.com/Intersil

A.C. TEST CONDITIONS

nput pulse levels VCC x 0.1 to VCC x 0.9

Input rise and fall times 10ns Input and output timing level V

x 0.5

Circuit #3 SPICE Macro Model

TOTAL

10pF

EQUIVALENT A.C. LOAD CIRCUIT

SDA Output

1533Ω

100pF

10pF

2.7V

100pF

25pF

AC TIMING (Over recommended operating conditions)

Symbol Parameter Min. Max. Unit

SCL

CYC

HIGH

LOW

SU:STA

HD:STA

SU:STO

SU:DAT

HD:DAT

BUF

SU:WPA

HD:WPA

Clock frequency 100 400 kHz Clock cycle time 2500 ns Clock high time 600 ns Clock low time 1300 ns Start setup time 600 ns Start hold time 600 ns Stop setup time 600 ns SDA data input setup time 100 ns SDA data input hold time 30 ns SCL and SDA rise time 300 ns SCL and SDA fall time 300 ns SCL low to SDA data output valid time 900 ns SDA data output hold time 50 ns Noise suppression time constant at SCL and SDA inputs 50 ns Bus free time (prior to any transmission) 1300 ns WP, A0, A2, A3 setup time 0 ns WP, A0, A2, A3 hold time 0 ns

FN8248.2

October 19, 2005

X9429

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HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Typ. Max. Unit

XDCP TIMING

Symbol Parameter Min. Max. Unit

WRPO

WRL

WRID

Note: (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling

edge of SCL.

TIMING DIAGRAMS

START and STOP Timing

SCL

SDA

High-voltage write cycle time (store instructions) 5 10 ms

Wiper response time after the third (last) power supply is stable 10 µs Wiper response time after instruction issued (all load instructions) 10 µs Wiper response time from an active SCL/SCK edge (increment/decreme nt instruction) 10 µs

(START) (STOP)

SU:STO

SU:STA

HD:STA

Input Timing

SCL

SDA

Output Timing

SCL

SDA

CYC

SU:DAT

HIGH

LOW

HD:DAT

BUF

FN8248.2

October 19, 2005

XDCP Timing (for All Load Instructions)

www.BDTIC.com/Intersil

SCL

X9429

(STOP)

SDA

W/RW

XDCP Timing (for Increment/Decrement Instruction)

SCL

Wiper Register Address Inc/Dec Inc/Dec

W/RW

SDA

Write Protect and Device Address Pins Timing

(START) (STOP)

SCL

SDA

LSB

WRL

...

(Any Instruction)

... ...

WRID

A0, A2

SU:WPA

HD:WPA

FN8248.2

October 19, 2005

APPLICATIONS INFORMATION

www.BDTIC.com/Intersil

Basic Configurations of Electronic Potentiometers

VW/R

Three terminal Potentiometer; Variable voltage divider

Application Circuits

Noninverting Amplifier Voltage Regulator

X9429

Two terminal Variable Resistor; Variable current

VO = (1+R2/R1)V

Offset Voltage Adjustment Comparator with Hysteresis

10kΩ

+5V

100kΩ

+ –

– +

TL072

10kΩ10kΩ

VO (REG) = 1.25V (1+R2/R1)+I

VUL = {R1/(R1+R2)} VO(max) V

= {R1/(R1+R2)} VO(min)

317

adj

}

VO (REG)V

adj R2

– +

FN8248.2

October 19, 2005

Application Circuits (continued)

www.BDTIC.com/Intersil

Attenuator Filter

VO = G V

-1/2 ≤ G ≤ +1/2

Inverting Amplifier Equivalent L-R Circuit

}

All RS = 10kΩ

}

– +

X9429

= 1 + R2/R

fc = 1/(2πRC)

+ –

VO = G V G = - R2/R

Function Generator

– +

}

frequency ∝ R1, R2, C amplitude ∝ R

, R

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R

– +

+ R3) >> R

FN8248.2

October 19, 2005

PACKAGING INFORMATION

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X9429

14-Lead Plastic, TSSOP, Package Type V

.025 (.65) BSC

0° - 8°

.0075 (.19) .0118 (.30)

.193 (4.9) .200 (5.1)

.019 (.50) .029 (.75)

Detail A (20X)

.169 (4.3) .177 (4.5)

.047 (1.20)

.002 (.05) .006 (.15)

.010 (.25)

Gage Plane

Seating Plane

.252 (6.4) BSC

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

FN8248.2

October 19, 2005

PACKAGING INFORMATION

www.BDTIC.com/Intersil

X9429

16-Lead Plastic SOIC (300 Mil Body) Package Type S

PIN 1 INDEX

(4X) 7°

0.050 (1.27)

PIN 1

0.010 (0.25)

0.020 (0.50)

X 45°

0.014 (0.35)

0.020 (0.51)

0.403 (10.2 )

0.413 ( 10.5)

0.290 (7.37)

0.299 (7.60)

0.003 (0.10)

0.012 (0.30)

0.050" Typical

0.393 (10.00)

0.420 (10.65)

0.092 (2.35)

0.105 (2.65)

0° - 8 °

0.015 (0.40)

0.050 (1.27)

0.0075 (0.19)

0.010 (0.25)

0.420"

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

0.030" Typical 16 Places

0.050"

Typical

FN8248.2

October 19, 2005

intersil X9429 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual