intersil X9429 DATA SHEET

®

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X9429

Low Noise/Low Power/2-Wire Bus

Data Sheet October 19, 2005

Single Digitally Controlled Potentiometer
(XDCP™)

FEATURES

• Single Voltage Potentiometer

• 64 Resistor Taps

• 2-wire Serial Interface for Write, Read, and
Transfer Operations of the Potentiometer

• Wiper Resistance, 150Ω Typical at 5V

• Non-Volatile Storage of Multiple Wiper Positions

• Power-on Recall. Loads Saved Wiper Position
on Power-up.

• Standby Current < 5µA Max

: 2.7V to 5.5V Operation

•V

CC

• 2.5kΩ, 10kΩ Total Pot Resistance

• Endurance: 100, 000 Data Changes per Bit per
Register

• 100 yr. Data Retention

• 14 Ld TSSOP, 16 Ld SOIC

• Low Power CMOS

• Pb-Free Plus Anneal Available (RoHS Compliant)

FN8248.2

DESCRIPTION

The X9429 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user th rough the 2-wire
bus interface. The potentiometer has associated with it
a volatile Wiper Counter Register (WCR) and a four
non-volatile Data Registers that can be directly written
to and read by the user. The contents of the WCR
controls the position of the wiper on the re sistor array
though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

BLOCK DIAGRAM

address

status

2-wire
bus
interface

data

V

CC

Bus

Interface &

Control

V

SS

write

read
transfer
inc / dec

control

Power-on Recall

Wiper Counter

Register (WCR)

Data Registers

4 Bytes

VL/R

wiper

L

VH/R

VW/R

H

10kΩ

64-taps

POT

W

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9429

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Ordering Information

POTENTIOMETER

PART NUMBER PART MARKING VCC LIMITS (V)

X9429WS16* X9429WS 5 ±10% 10 0 to 70 16 Ld SOIC (300 mil)

X9429WS16Z* (Note) X9429WS Z 0 to 70 16 Ld SOIC (300 mil) (Pb-free)

X9429WS16I* X9429WS I -40 to 85 16 Ld SOIC (300 mil)

X9429WS16IZ* (Note) X9429WS Z I -40 to 85 16 Ld SOIC (300 mil) (Pb-free)

X9429WV14* X9429WV 0 to 70 14 Ld TSSOP (4.4mm)

X9429WV14Z* (Note) X9429WV Z 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)

X9429WV14IZ* (Note) X9429WV Z I -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9429WV14I* X9429WV I -40 to 85 14 Ld TSSOP (4.4mm)

X9429YS16* X9429YS 2.5 0 to 70 16 Ld SOIC (300 mil)

X9429YS16Z* (Note) X9429YS Z 0 to 70 16 Ld SOIC (300 mil) (Pb-free)

X9429YS16I* X9429YS I -40 to 85 16 Ld SOIC (300 mil)

X9429YS16IZ* (Note) X9429YS Z I -40 to 85 16 Ld SOIC (300 mil) (Pb-free)

X9429YV14* X9429YV 0 to 70 14 Ld TSSOP (4.4mm)

X9429YV14Z* (Note) X9429YV Z 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)

X9429YV14I* X9429YV I -40 to 85 14 Ld TSSOP (4.4mm)

X9429YV14IZ* (Note) X9429YV Z I -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9429WS16-2.7* X9429WS F 2.7 to 5.5 10 0 to 70 16 Ld SOIC (300 mil)

X9429WS16Z-2.7* (Note) X9429WS Z F 0 to 70 16 Ld SOIC (300 mil) (Pb-free)

X9429WS16I-2.7* X9429WS G -40 to 85 16 Ld SOIC (300 mil)

X9429WS16IZ-2.7* (Note) X9429WS Z G -40 to 85 16 Ld SOIC (300 mil) (Pb-free)

X9429WV14-2.7* X9429WV F 0 to 70 14 Ld TSSOP (4.4mm)

X9429WV14Z-2.7* (Note) X9429WV Z F 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)

X9429WV14I-2.7* X9429WV G -40 to 85 14 Ld TSSOP (4.4mm)

X9429WV14IZ-2.7* (Note) X9429WV Z G -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9429YS16-2.7* X9429YS F 2.5 0 to 70 16 Ld SOIC (300 mil)

X9429YS16Z-2.7* (Note) X9429YS Z F 0 to 70 16 Ld SOIC (300 mil) (Pb-free)

X9429YS16I-2.7* X9429YS G -40 to 85 16 Ld SOIC (300 mil)

X9429YS16IZ-2.7* (Note) X9429YS Z G -40 to 85 16 Ld SOIC (300 mil) (Pb-free)

X9429YV14-2.7* X9429YV F 0 to 70 14 Ld TSSOP (4.4mm)

X9429YV14Z-2.7* (Note) X9429YV Z F 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)

X9429YV14I-2.7* X9429YV G -40 to 85 14 Ld TSSOP (4.4mm)

X9429YV14IZ-2.7* (Note) X9429YV Z G -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE

2

FN8248.2

October 19, 2005

DETAILED FUNCTIONAL DIAGRAM

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V

CC

X9429

SCL

SDA

A3

A2

A0

WP

INTERFACE

AND

CONTROL

CIRCUITRY

V

SS

Control

DATA

CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage
amplifier circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and
Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF
circuits

• Provide a control variable (I, V, or R) in feedback
circuits

DR1

DR0

DR2 DR3

Power-on Recall

WIPER

COUNTER
REGISTER

(WCR)

10kΩ

64--taps

RH/V

R

L

R

W

H

/V

L

/V

W

SYSTEM LEVEL APPLICATIONS

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems

• Control the gain in audio and home entertainment
systems

• Provide the variable DC bias for tuners in RF
wireless systems

• Set the operating points in temperature control
systems

• Control the operating point for sensors in industrial
systems

• Trim offset and gain errors in artificial intelligent
systems

3

FN8248.2

October 19, 2005

X9429

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PIN CONFIGURATION

1
2
3
4
5
6
7
8

SOIC

X9429

16
15
14
13
12
11
10
9

TSSOP

NC
NC

NC
A2

SCL

SDA

VSS

1
2

3
4

5
6

7

X9429

14
13

12
11

10

V

CC

RL/V

L

RH/V

H

R

W/VW

A3

9
8

A0

WP

NC
NC
NC

A2

SCL

SDA

NC

VSS

PIN ASSIGNMENTS

TSSOP pin SOIC pin Symbol Brief Description

1 1 NC No Connect
2 2 NC No Connect
3 3 NC No Connect
4 4 A2 Device Address for 2-wire bus.
5 5 SCL Serial Clock for 2-wire bus.
6 6 SDA Serial Data Input/Output for 2-wire bus.
78V

SS

89WP

System Ground
Hardware Write Protect

9 10 A0 Device Address for 2-wire bus.
10 11 A3 Device Address for 2-wire bus.
11 12 R
12 13 R
13 14 R
14 16 V

W

/ V

W

/ V

H

H

/ V

L

L

CC

Wiper Terminal of the Potentiometer.
High Terminal of the Potentiometer.
Low Terminal of the Potentiometer.
System Supply Voltage

15 NC No Connect

7 NC No Connect

V

CC

NC

RL/V
RH/V
RW/V

A3

A0

WP

L
H

W

PIN DESCRIPTIONS

Device Address (A

The Address inputs are used to set the least

Host Interface Pins

significant 3 bits of the 8-bit slav e addre ss. A matc h in
the slave address serial data stream must be made

Serial Clock (SCL)

The SCL input is used to clock data into and out of the
X9429.

Serial Data (SDA)

with the Address input in order to initiate
communication with the X9429. A maximum of 8
devices may occupy the 2-wire serial bus.

Potentiometer Pins

SDA is a bidirectional pin used to transfer data into

, RL/V

R

and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical

H/VH

The RH/VH and RL/VL inputs are equivalent to the
terminal connections on either end of a mechanical

potentiometer.
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.

4

, A2, A3)

0

L

FN8248.2

October 19, 2005

X9429

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RW/V

W

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

Hardware Write Protect Input WP

The WP pin when low prevents nonvolatile writes to the
Data Registers.

PRINCIPLES OF OPERATION

The X9429 is a highly integrated microcircuit
incorporating a resistor array and its associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.

Serial Interface

The X9429 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9429 will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods (t

). SDA state changes during

LOW

SCL HIGH are reserved for indicating start and stop
conditions.

Start Condition

All commands to the X9429 are preceded by the start
condition, which is a HIGH to LOW transit ion of SDA
while SCL is HIGH (t

). The X9429 continuously

HIGH

monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.

during this period the receiver pulls the SDA line LOW

to acknowledge that it successfully received the eight

bits of data.

The X9429 will respond with an acknowledge after

recognition of a start condition and its slave address

and once again after successful receipt of the

command byte. If the command is followed by a data

byte the X9429 will respond with a final acknowledge.

Array Description

The X9429 is comprised of a resistor array. The array

contains 63 discrete resistive segments that are

connected in series. The physical ends of the array

are equivalent to the fixed terminals of a mechanical

potentiometer (V

and VL/RL inputs).

H/RH

At both ends of the array and between each resistor

segment is a CMOS switch connected to the wiper

(V

) output. Within each individual array only one

W/RW

switch may be turned on at a time. These switches are

controlled by the Wiper Counter Register (WCR). The

six bits of the WCR are decoded to select, and enable,

one of sixty-four switches.

The WCR may be written directly, or it can be changed

by transferring the contents of one of four associated

Data Registers into the WCR. These Data Registers

and the WCR can be read and written by the host

system.

Device Addressing

Following a start condition the master must output the

address of the slave it is accessing. The most

significant four bits of the slave address are the device

type identifier (refer to Figure 1). For the X9429 this is

fixed as 0101[B].

Figure 1. Slave Address

Device Type

Identifier

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transit ion of SDA
while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and

5

The next four bits of the slave address are the device

address. The physical device address is defined by the

state of the A

the serial data stream with the address input state; a

successful compare of all three address bits is required

for the X9429 to respond with an acknowledge. The A

, and A3 inputs can be actively driven by CMOS input

A

2

signals or tied to V

100

, A2, and A3 inputs. The X9429 compares

0

or VSS.

CC

1

A3 A2 0 A0

Device Address

FN8248.2

October 19, 2005

,

0

X9429

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Acknowledge Polling

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9429
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9429 is still busy with the write operation no ACK will
be returned. If the X9429 has completed the write
operation an ACK will be returned, and the master can
then proceed with the next operation.

Instruction Structure

The next byte sent to the X9429 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of four associated registers. The format is
shown below in Figure 2.

Figure 2. Instruction Byte Format

Register

Select

Flow 1. ACK Polling Sequence

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

YES

Further

Operation?

YES

Issue

Instruction

NO

NO

Issue STOP

Issue STOP

I1I2I3 I0 R1 R0 0 0

Instructions

Proceed

Proceed

The four high order bits define the instruction. The

next two bits (R1 and R0) select one of the four

registers that is to be acted upon when a register

oriented instruction is issued. Bits 0 and 1 are defin ed

to be 0.

Four of the seven instructions end with the

transmission of the instruction byte. The basic

sequence is illustrated in Figure 3. These two-byte

instructions exchange data between the Wiper

Counter Register and one of the Data Registers. A

transfer from a Data Register to a Wiper Counter

Register is essentially a write to a static RAM. The

response of the wiper to this action will be delayed

. A transfer from the Wiper Counter Register

t

WRL

(current wiper position), to a Data Register is a write to

nonvolatile memory and takes a minimum of t

WR

to

complete.

Four instructions require a three-byte sequence to

complete. These instructions transfer data between the

host and the X9429; either between the host and one of

the Data Registers or directly between the host and the

Wiper Counter Register. These instructions are:

6

FN8248.2

October 19, 2005

Figure 3. Two-Byte Instruction Sequence

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SCL

SDA

S

0101A3A20A0A
T
A
R
T

Read Wiper Counter Register (read the current wiper
position of the selected pot), write Wiper Counter
Register (change current wiper position of the selected
pot), read Data Register (read the contents of the
selected nonvolatile register) and write Data Register
(write a new value to the selected Data Register). The
sequence of operations is shown in Figure 4.

The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9429 has responded with an acknowledge,

X9429

I3 I2 I1 I0 R1 R0 0 0 A
C
K

the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse

) while SDA is HIGH, the selected wiper will

(t

HIGH

move one resistor segment towards the V
terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the V
illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.

S

C

T

K

O
P

terminal. A detailed

L/RL

H/RH

Table 1. Instruction Set

Instruction Set

Instruction

Read Wiper Counter
Register

Write Wiper Counter
Register

1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register

1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register

Read Data Register 1 0 1 1 1/0 1/0 0 0

Write Data Register 1 1 0 0 1/0 1/0 0 0
XFR Data Register to

Wiper Counter Register

11011/01/00 0

XFR Wiper Counter
Register to Data Regis-

11101/01/00 0

ter
Increment/Decrement

Wiper Counter Register

Note: (1) 1/0 = data is one or zero

001000 0 0

0

OperationI3I2I1I0R1R0X1X

Read the contents of the Data Register pointed to

- R

by R

1

0

Write new value to the Data Register pointed to by

- R

R

1

0

Transfer the contents of the Data Register pointed
to by R

- R0 to its Wiper Counter Register

1

Transfer the contents of the Wiper Counter Register
to the Data Register pointed to by R

- R

1

0

Enable Increment/decrement of the Wiper Counter
Register

7

FN8248.2

October 19, 2005