intersil X9428 DATA SHEET

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X9428

Low Noise/Low Power/2-Wire Bus

Data Sheet March 8, 2005

Single Digitally Controlled Potentiometer
(XDCP™)

FEATURES

• Solid state potentiometer

• 2-wire serial interface

• Register oriented format
—Direct Read/Write/Transfer Wiper Position
—Store as many as Four Positions per

Potentiometer

• Power supplies
—V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V

• Low power CMOS
—Standby current < 1µA
—Ideal for Battery Operated Applications

• High reliability
—Endurance–100,000 Data Changes per Bit per

—Register Data Retention–100 years

• 4-bytes of nonvolatile memory

•10kΩ resistor array

• Resolution: 64 taps each potentiometer

• SOIC and TSSOP packages

= 2.7V to 5.5V

CC

Register

FN8197.0

DESCRIPTION

The X9428 integrates a digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.

The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user th rough the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Pow er-up recalls
the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two-term inal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

BLOCK DIAGRAM

V
V

SCL
SDA

WP

CC
SS

V+
V–

A0
A2
A3

Interface

and

Control

Circuitry

Data

R0 R1

8

R2 R3

Wiper

Counter
Register

(WCR)

VH/R

VL/R

VW/R

H

L

W

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9428

PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)

The SCL input is used to clock data into and out of the
X9428.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.

Device Address (A

, A2, A3)

0

The Address inputs are used to set the least
significant 3 bits of the 8-bit slav e addres s. A matc h in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9428. A maximum of 8
devices may occupy the 2-wire serial bus.

Potentiometer Pins

PIN CONFIGURATION

V

R

L/VL

RH/V

RW/V

SDA

CC

A2

W

WP

V

SS

A2
R

R

R

SDA

WP

V

H

SS

1
2

3
4

5
6

7
8

1

L

2
3

H

4

W

5
6
7

DIP/SOIC

X9428

TSSOP

X9428

16
15

14
13

12
11

10
9

14
13
12
11
10

V+
NC
A0
NC
A3
SCL
NC
V-

V

CC

V+
A0
NC
A3
SCL

9

V-

8

R

, RL/V

H/VH

L

The RH/VH and RL/VL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.

R

W/VW

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

Hardware Write Protect Input WP

The WP pin when low prevents nonvolatile writes to
the Data Registers.

Analog Supply V+, V-

The Analog Supply V+, V- are the supply voltages for
the XDCP analog section.

PIN NAMES

Symbol Description

SCL Serial clock

SDA Serial data

A0, A2, A3 Device address

R

, VL/RHPotentiometer Pins

H/VH

(terminal equivalent)

R

W/VW

WP

Potentiometer Pin (wiper equivalent)
Hardware write protection

V+,V- Analog and voltage follower

V

CC

V

SS

System supply voltage
System ground

NC No connection

2

FN8197.0

March 8, 2005

X9428

PRINCIPLES OF OPERATION

The X9428 is a highly integrated microcircuit
incorporating a resistor array and its associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.

Serial Interface

The X9428 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9428 will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods (tLOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.

The X9428 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9428 will respond with a final acknowledge.

Array Description

The X9428 is comprised of a resistor array. The array
contains 63 discrete resistive segments that are
connected in series. The physical ends of the array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

and VL/RL inputs).

H/RH

At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(V

) output. Within each individual array only one

W/RW

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers and
the WCR can be read and written by the host system.

Start Condition

All commands to the X9428 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t

). The X9428 continuously

HIGH

monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9428
this is fixed as 0101[B].

Figure 1. Slave Address

Device Type

Identifier

100

1

A3 A2 0 A0

Device Address

The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A

, A2, A3 inputs. The X9428

0

compares the serial data stream with the address
input state; a successful compa re of all four address
bits is required for the X9428 to respond with an
acknowledge. The A
driven by CMOS input signals or tied to V

, A2, A3 inputs can be actively

0

or VSS.

CC

3

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March 8, 2005

X9428

Acknowledge Polling

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9428
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9428 is still busy with the write operation no ACK will
be returned. If the X9428 has completed the write
operation an ACK will be returned, and the master can
then proceed with the next operation.

Flow 1. ACK Polling Sequence

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

YES

Further

Operation?

YES

Issue

Instruction

NO

NO

Issue STOP

Issue STOP

Figure 2. Instruction Byte Format

Register

Select

I1I2I3 I0 R1 R0 0 0

Instructions

The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers that
is to be acted upon when a register oriented instruction
is issued. Bits 0 and 1 are defined to be 0.

Four of the seven instructions end with the transmission
of the instruction byte. The basic sequence is illustrated
in Figure 3. These two-byte instructions exchange data
between the Wiper Counter Register and one of the
Data Registers. A transfer from a Data Register to a
Wiper Counter Register is essentially a write to a static
RAM. The response of the wiper to this action will be
delayed t

. A transfer from the Wiper Counter

WRL

Register (current wiper position), to a Data Register is a
write to nonvolatile memory and takes a minimum of
t

to complete.

WR

Four instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9428; either between the host and one of
the Data Registers or directly between the host and the
Wiper Counter Register. These instructions are: Read
Wiper Counter Register (read the current wiper position
of the selected pot), write Wiper Counter Register
(change current wiper position of the selected pot), read
Data Register (read the contents of the selected
nonvolatile register) and write Data Register (write a
new value to the selected Data Register). The
sequence of operations is shown in Figure 4.

Proceed

Proceed

Instruction Structure

The next byte sent to the X9428 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of four associated registers. The format is
shown below in Figure 2.

4

FN8197.0

March 8, 2005

Figure 3. Two-Byte Instruction Sequence

SCL

SDA

S

0101A3A20A0A
T
A
R
T

X9428

I3 I2 I1 I0 R1 R0 0 0 A
C
K

S

C

T

K

O
P

The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9428 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; th ereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(t

) while SDA is HIGH, the selected wiper will

HIGH

move one resistor segment towards the V

H/RH

terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the V

terminal. A detailed

L/RL

illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.

Table 1. Instruction Set

Instruction Set

Instruction

Read Wiper Counter

0

1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register

OperationI3I2I1I0R1R0X1X

Register
Write Wiper Counter

1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register

Register
Read Data Register 1 0 1 1 1/0 1/0 0 0 Read the contents of the Data Register pointed to by

R

- R

1

0

Write Data Register 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register pointed to by

- R

R

1

0

XFR Data Register to
Wiper Counter Register

XFR Wiper Counter
Register to Data Register

Increment/Decrement
Wiper Counter Register

Note: (7) 1/0 = data is one or zero

1 1 0 1 1/0 1/0 0 0 Transfer the contents of the Data Register pointed to

- R0 to its Wiper Counter Register

by R

1

1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter Register

to the Data Register pointed to by R

- R

1

0

0 0 1 0 0 0 0 1/0 Enable Increment/decrement of the Wiper Counter

Register

5

FN8197.0

March 8, 2005

X9428

Figure 4. Three-Byte Instruction Sequence

SCL

SDA

S

0 1 0 1 A3 A2 0 A0 A
T
A
R
T

Figure 5. Increment/Decrement Instruction Sequence

SCL

I3 I2 I1 I0 R1 R0 0 0 A
C
K

0 0 D5 D4 D3 D2 D1 D0
C
K

A

S

C

T

K

O
P

SDA

S

0101A3A20A0A
T
A
R
T

C
K

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

Issued

SCL

SDA

VW/R

W

Voltage Out

XX

I3 I2 I1 I0 R0 0 0 A

R1

I
N
C
1

t

WRID

I
N
C
2

C
K

D

I

E

N

C

C

1

n

S

D

T

E

O

C

P

n

6

FN8197.0

March 8, 2005

Figure 7. Acknowledge Response from Receiver

X9428

SCL from

Master

Data Output

from Transmitter

Data Output

from Receiver

START

1

Figure 8. Detailed Potentiometer Block Diagram

Serial Data Path
From Interface

Circuitry

Register 0 Register 1

8 6

Register 2 Register 3

If WCR = 00[H] then VW/RW = VL/R
If WCR = 3F[H] then VW/RW = VH/R

L

H

UP/DN

Modified SCL

Serial
Bus

Input

Parallel
Bus

Input

Register

UP/DN
CLK

89

Acknowledge

C
o

u
n

t

e

r

Wiper

Counter

(WCR)

INC/DEC

Logic

D

e
c
o
d

e

VH/R

VL/R

H

L

VW/R

W

7

FN8197.0

March 8, 2005