• Register oriented format
—Direct Read/Write/Transfer Wiper Position
—Store as many as Four Positions per
Potentiometer
• Power supplies
—V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• Low power CMOS
—Standby current < 1µA
—Ideal for Battery Operated Applications
• High reliability
—Endurance–100,000 Data Changes per Bit per
—Register Data Retention–100 years
• 4-bytes of nonvolatile memory
•10kΩ resistor array
• Resolution: 64 taps each potentiometer
• SOIC and TSSOP packages
= 2.7V to 5.5V
CC
Register
FN8197.0
DESCRIPTION
The X9428 integrates a digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user th rough the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Pow er-up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-term inal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
V
V
SCL
SDA
WP
CC
SS
V+
V–
A0
A2
A3
Interface
and
Control
Circuitry
Data
R0 R1
8
R2 R3
Wiper
Counter
Register
(WCR)
VH/R
VL/R
VW/R
H
L
W
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
X9428
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9428.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
Device Address (A
, A2, A3)
0
The Address inputs are used to set the least
significant 3 bits of the 8-bit slav e addres s. A matc h in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9428. A maximum of 8
devices may occupy the 2-wire serial bus.
Potentiometer Pins
PIN CONFIGURATION
V
R
L/VL
RH/V
RW/V
SDA
CC
A2
W
WP
V
SS
A2
R
R
R
SDA
WP
V
H
SS
1
2
3
4
5
6
7
8
1
L
2
3
H
4
W
5
6
7
DIP/SOIC
X9428
TSSOP
X9428
16
15
14
13
12
11
10
9
14
13
12
11
10
V+
NC
A0
NC
A3
SCL
NC
V-
V
CC
V+
A0
NC
A3
SCL
9
V-
8
R
, RL/V
H/VH
L
The RH/VH and RL/VL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
R
W/VW
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input WP
The WP pin when low prevents nonvolatile writes to
the Data Registers.
Analog Supply V+, V-
The Analog Supply V+, V- are the supply voltages for
the XDCP analog section.
The X9428 is a highly integrated microcircuit
incorporating a resistor array and its associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9428 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9428 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (tLOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
The X9428 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9428 will respond with a final acknowledge.
Array Description
The X9428 is comprised of a resistor array. The array
contains 63 discrete resistive segments that are
connected in series. The physical ends of the array
are equivalent to the fixed terminals of a mechanical
potentiometer (V
and VL/RL inputs).
H/RH
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(V
) output. Within each individual array only one
W/RW
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers and
the WCR can be read and written by the host system.
Start Condition
All commands to the X9428 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
). The X9428 continuously
HIGH
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9428
this is fixed as 0101[B].
Figure 1. Slave Address
Device Type
Identifier
100
1
A3A20A0
Device Address
The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A
, A2, A3 inputs. The X9428
0
compares the serial data stream with the address
input state; a successful compa re of all four address
bits is required for the X9428 to respond with an
acknowledge. The A
driven by CMOS input signals or tied to V
, A2, A3 inputs can be actively
0
or VSS.
CC
3
FN8197.0
March 8, 2005
X9428
Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9428
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9428 is still busy with the write operation no ACK will
be returned. If the X9428 has completed the write
operation an ACK will be returned, and the master can
then proceed with the next operation.
Flow 1. ACK Polling Sequence
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
YES
Further
Operation?
YES
Issue
Instruction
NO
NO
Issue STOP
Issue STOP
Figure 2. Instruction Byte Format
Register
Select
I1I2I3I0R1R000
Instructions
The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers that
is to be acted upon when a register oriented instruction
is issued. Bits 0 and 1 are defined to be 0.
Four of the seven instructions end with the transmission
of the instruction byte. The basic sequence is illustrated
in Figure 3. These two-byte instructions exchange data
between the Wiper Counter Register and one of the
Data Registers. A transfer from a Data Register to a
Wiper Counter Register is essentially a write to a static
RAM. The response of the wiper to this action will be
delayed t
. A transfer from the Wiper Counter
WRL
Register (current wiper position), to a Data Register is a
write to nonvolatile memory and takes a minimum of
t
to complete.
WR
Four instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9428; either between the host and one of
the Data Registers or directly between the host and the
Wiper Counter Register. These instructions are: Read
Wiper Counter Register (read the current wiper position
of the selected pot), write Wiper Counter Register
(change current wiper position of the selected pot), read
Data Register (read the contents of the selected
nonvolatile register) and write Data Register (write a
new value to the selected Data Register). The
sequence of operations is shown in Figure 4.
Proceed
Proceed
Instruction Structure
The next byte sent to the X9428 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of four associated registers. The format is
shown below in Figure 2.
4
FN8197.0
March 8, 2005
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
S
0101A3A20A0A
T
A
R
T
X9428
I3I2I1 I0R1 R0 00A
C
K
S
C
T
K
O
P
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9428 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; th ereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(t
) while SDA is HIGH, the selected wiper will
HIGH
move one resistor segment towards the V
H/RH
terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the V
terminal. A detailed
L/RL
illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.
Table 1. Instruction Set
Instruction Set
Instruction
Read Wiper Counter
0
10010000Read the contents of the Wiper Counter Register
OperationI3I2I1I0R1R0X1X
Register
Write Wiper Counter
10100000Write new value to the Wiper Counter Register
Register
Read Data Register10111/0 1/000Read the contents of the Data Register pointed to by
R
- R
1
0
Write Data Register11001/0 1/000Write new value to the Data Register pointed to by
- R
R
1
0
XFR Data Register to
Wiper Counter Register
XFR Wiper Counter
Register to Data Register
Increment/Decrement
Wiper Counter Register
Note: (7) 1/0 = data is one or zero
11011/0 1/000Transfer the contents of the Data Register pointed to
- R0 to its Wiper Counter Register
by R
1
11101/0 1/000Transfer the contents of the Wiper Counter Register
to the Data Register pointed to by R
- R
1
0
00100001/0 Enable Increment/decrement of the Wiper Counter
If WCR = 00[H] then VW/RW = VL/R
If WCR = 3F[H] then VW/RW = VH/R
L
H
UP/DN
Modified SCL
Serial
Bus
Input
Parallel
Bus
Input
Register
UP/DN
CLK
89
Acknowledge
C
o
u
n
t
e
r
Wiper
Counter
(WCR)
INC/DEC
Logic
D
e
c
o
d
e
VH/R
VL/R
H
L
VW/R
W
7
FN8197.0
March 8, 2005
X9428
DETAILED OPERATION
The potentiometer has a Wiper Co unter Register and
four Data Registers. A detailed discussion of the
register organization and array operation follows.
Wiper Counter Register
The X9428 contains a Wiper Counter Register. The
Wiper Counter Register can be envisioned as a 6-bit
parallel and serial load counter with its outputs
decoded to select one of sixty-four switches along its
resistor array. The contents of the WCR can be altered
in four ways: it may be written directly by the host via
the write Wiper Counter Register instruction (serial
load); it may be written indirectly by transferring the
contents of one of four associated Da ta Registers via
the XFR Data Register instruction (parallel load); it can
be modified one step at a time by the
Increment/Decrement instruction. Finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.
The WCR is a volatile register; that is, its contents are
lost when the X9428 is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be
different from the value present at power-do wn.
Data Registers
The potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred b etween any of the
four Data Registers and the Wiper Counter Register. It
should be noted all operations changing data in one of
these registers is a nonvolatile operation and will take
a maximum of 10ms.
Register Descriptions
Data Registers, (6-Bit), Nonvolatile
D5D4D3D2D1D0
NVNVNVNVNVNV
(MSB)(LSB)
Four 6-bit Data Registers for each XD CP. (eight 6-bit
registers in total).
– {D5~D0}: These bits are for general purpose not
volatile data storage or for storage of up to four
different wiper values. The contents of Data Register
0 are automatically moved to the Wiper Counter
Register on power-up.
Wiper Counter Register, (6-Bit), Volatile
WP5WP4WP3WP2WP1WP0
VVVVVV
(MSB)(LSB)
One 6-bit wiper counter register for each XDCP. (Four
6-bit registers in total.)
– {D5~D0}: These bits specify the wiper position of the
respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register 0.
The contents of the WCR can be loaded from any of
the other Data Register or directly. The contents of
the WCR can be saved in a DR.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory loca tions that could possibly
store system parameters or user preference data.
8
FN8197.0
March 8, 2005
X9428
Instruction Format
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
S
device type
T
identifier
A
R
0101
T
Write Wiper Counter Register (WCR)
S
device type
T
identifier
A
R
0101
T
device
addresses
A3A
0
2
device
addresses
A3A
0
2
instruction
S
opcode
A
C
A
1001000000WP
K
0
instruction
S
opcode
A
C
A
1010000000WP
K
0
S
(sent by slave on SDA)
A
C
K
S
(sent by master on SDA)
A
C
K
wiper position
W
W
W
P
P
P
5
4
3
2
wiper position
W
W
W
P
P
P
5
4
3
2
W
W
M
S
A
W
P
1
W
P
1
T
C
O
P
K
P
0
S
S
A
T
C
O
P
K
P
0
Read Data Register (DR)
S
device type
T
identifier
A
R
0101
T
device
addresses
A3A
0
2
S
A
C
A
K
0
instruction
opcode
1011
register
addresses
R1R
0000WP
0
S
A
C
K
Write Data Register (DR)
S
device type
T
identifier
A
R
0101
T
device
addresses
A3A
0
2
S
A
C
A
K
0
instruction
opcode
1100
register
addresses
R1R
0000WP
0
S
A
C
K
XFR Data Register (DR) to Wiper Counter Register (WCR)
S
device type
T
identifier
A
R
0101
T
device
addresses
A3A
0
2
S
A
C
A
K
0
instruction
opcode
1101
register
addresses
R1R
00
0
S
A
C
K
wiper position/data
(sent by slave on SDA)
W
W
W
W
P
P
P
P
5
4
3
2
1
wiper position/data
(sent by master on SDA)
W
W
W
W
P
P
P
P
5
4
3
2
1
S
T
O
P
W
P
0
W
P
0
M
S
A
T
C
O
K
P
S
S
HIGH-VOLTAGE
A
T
C
K
WRITE CYCLE
O
P
9
FN8197.0
March 8, 2005
X9428
XFR Wiper Counter Register (WCR) to Data Register (DR)
S
device type
T
identifier
A
R
0101
T
Increment/Decrement Wiper Counter Register (WCR)
S
device type
T
identifier
A
R
0101
T
SYMBOL TABLEGuidelines for Calculating Typical Values of Bus
device
addresses
A3A
0
2
device
addresses
A3A
2
instruction
S
opcode
A
C
A
1110
K
0
instruction
S
opcode
A
C
A
0
00100000
K
0
register
addresses
R1R
00
0
S
S
A
C
K
HIGH-VOLTAGE
T
WRITE CYCLE
O
P
increment/decrement
S
(sent by master on SDA)
A
C
I/DI/
K
....
D
I/DI/
S
T
O
P
D
Pull-Up Resistors
WAVEFORMINPUTSOUTPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/ACenter Line
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
is High
Impedance
Resistance (K)
120
R
100
80
60
40
20
0
MIN
R
MAX
Max.
Resistance
Min.
Resistance
20 40 60 80 100 120
0
Bus Capacitance (pF)
=
=
V
CC MAX
I
OL MIN
t
R
C
BUS
=1.8kΩ
10
FN8197.0
March 8, 2005
X9428
ABSOLUTE MAXIMUM RATINGS
Temperature under bias....................-65°C to +135°C
Storage temperature .........................-65°C to +150°C
Voltage on SDA, SCL or any address
input with respect to V
Voltage on V+ (referenced to V
Voltage on V- (referenced to V
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Lead temperature (soldering, 10 seconds)........ 300°C
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
VCC supply current
(nonvolatile write)
VCC supply current
(mov e w i p e r , write, read)
1mAf
Other Inputs = V
100µAf
Other Inputs = V
VCC current (standby)1µASCL = SDA = VCC, Addr. = V
Input leakage current10µAVIN = VSS to V
Output leakage current10µAV
Input HIGH voltageVCC x 0.7VCC x 0.5V
Input LOW voltage-0.5VCC x 0.1V
Output LOW voltage0.4VIOL = 3mA
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-
eter. It is a measure of the error in step size.
(3) MI = RTOT/63 or (R
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
- RL)/63, single pot
H
Test ConditionsMin.Typ.Max.Unit
= 400kHz, SDA = Open,
SCL
SS
= 400kHz, SDA = Open,
SCL
SS
CC
= VSS to V
OUT
CC
SS
ENDURANCE AND DATA RETENTION
ParameterMin.Unit
Minimum endurance100,000Data changes per bit per register
Data retention100Years
CAPACITANCE
SymbolTestMax.UnitTest Conditions
(5)
C
I/O
(5)
C
IN
Input/output capacitance (SDA)8pFV
I/O
= 0V
Input capacitance (A0, A1, A2, A3, and SCL)6pFVIN = 0V
POWER-UP TIMING
SymbolParameter Min.Typ.Max.Unit
(6)
t
PUR
t
PUW
t
RVCC
(6)
(7)
Power-up to initiation of read operation1ms
Power-up to initiation of write operation5ms
VCC Power-up ramp rate0.250V/msec
POWER-UP AND POWER-DOWN
There are no restrictions on the power-up or power-down sequencing of the bias supplies V
, V+, and V- provided
CC
that all three supplies reach their final value s within 1msec of each other. However, at all times, the voltages on the
potentiometer pins must be less than V+ and more than V-. The recall of the wiper position from nonvolatile memory
is not in effect until all supplies reach their final value.
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) t
(7) Sample tested only.
and t
PUR
instruction can be issued. These parameters are periodically sampled and not 100% tested.
are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific
PUW
12
FN8197.0
March 8, 2005
X9428
A.C. TEST CONDITIONS
I
nput pulse levelsVCC x 0.1 to VCC x 0.9
Input rise and fall times10ns
Input and output timing levelV
CC
x 0.5
Circuit #3 SPICE Macro Model
R
R
H
TOTAL
C
H
C
C
L
W
10pF
EQUIVALENT A.C. LOAD CIRCUIT
SDA Output
5V
1533Ω
100pF
10pF
2.7V
100pF
25pF
R
W
AC TIMING (over recommended operating conditions)
SymbolParameterMin.Max.Unit
f
SCL
t
CYC
t
HIGH
t
LOW
t
SU:STA
t
HD:STA
t
SU:STO
t
SU:DAT
t
HD:DAT
t
R
t
F
t
AA
t
DH
T
I
t
BUF
t
SU:WPA
t
HD:WPA
Clock frequency100400kHz
Clock cycle time2500ns
Clock high time600ns
Clock low time1300ns
Start setup time600ns
Start hold time600ns
Stop setup time600ns
SDA data input setup time100ns
SDA data input hold time30ns
SCL and SDA rise time300ns
SCL and SDA fall time300ns
SCL low to SDA data output valid time900ns
SDA data output hold time50ns
Noise suppression time constant at SCL and SDA inputs50ns
Bus free time (prior to any transmission)1300ns
WP, A0, A1, A2 and A3 setup time0ns
WP, A0, A1, A2 and A3 hold time0ns
R
L
13
FN8197.0
March 8, 2005
X9428
HIGH-VOLTAGE WRITE CYCLE TIMING
SymbolParameterTyp.Max.Unit
t
WR
XDCP TIMING
SymbolParameterMin.Max.Unit
t
WRPO
t
WRL
t
WRID
Note: (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling
edge of SCL.
TIMING DIAGRAMS
START and STOP Timing
SCL
SDA
High-voltage write cycle time (store instructions)510ms
Wiper response time after the third (last) power supply is stable10µs
Wiper response time after instruction issued (all load instructions)10µs
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)10µs
(START)(STOP)
t
F
t
SU:STO
t
F
t
SU:STA
t
HD:STA
t
R
t
R
Input Timing
SCL
SDA
Output Timing
SCL
SDA
t
CYC
t
SU:DAT
t
HIGH
t
LOW
t
HD:DAT
t
AA
t
DH
t
BUF
14
FN8197.0
March 8, 2005
XDCP Timing (for All Load Instructions)
SCL
X9428
(STOP)
SDA
V
W/RW
XDCP Timing (for Increment/Decrement Instruction)
SCL
Wiper Register AddressInc/DecInc/Dec
V
W/RW
SDA
Write Protect and Device Address Pins Timing
LSB
t
WRL
t
WRID
SCL
SDA
WP
A0, A2, A3
15
(START)(STOP)
...
(Any Instruction)
...
...
t
SU:WPA
t
HD:WPA
FN8197.0
March 8, 2005
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
V
R
VW/R
W
Three terminal Potentiometer;
Variable voltage divider
Application Circuits
Noninverting AmplifierVoltage Regulator
X9428
+V
R
I
Two terminal Variable Resistor;
Variable current
V
S
VO = (1+R2/R1)V
Offset Voltage AdjustmentComparator with Hysteresis
V
S
10kΩ
R
R
1
100kΩ
-12V+12V
+
–
R
1
S
–
+
TL072
10kΩ10kΩ
V
O
2
R
2
V
O
IN
VO (REG) = 1.25V (1+R2/R1)+I
V
S
VUL = {R1/(R1+R2)} VO(max)
V
= {R1/(R1+R2)} VO(min)
LL
317
I
adj
R
2
–
+
}
}
R
R
2
1
R
1
adj R2
VO (REG)V
V
O
16
FN8197.0
March 8, 2005
Application Circuits (continued)
AttenuatorFilter
R
1
V
S
V
R
3
R
VO = G V
-1/2 ≤ G ≤ +1/2
Inverting AmplifierEquivalent L-R Circuit
R
R
1
S
}
4
All RS = 10kΩ
S
2
}
–
+
–
+
X9428
C
V
R
2
V
O
V
O
S
R
G
O
fc = 1/(2πRC)
C
1
V
S
R
1
= 1 + R2/R
+
–
R
1
R
2
+
–
V
O
2
VO = G V
G = - R2/R
R
Z
S
1
Function Generator
R
–
+
R
}
A
R
}
B
frequency ∝ R1, R2, C
amplitude ∝ R
2
, R
A
IN
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R
R
1
B
1
–
+
1
R
3
+ R3) >> R
C
2
17
FN8197.0
March 8, 2005
PACKAGING INFORMATION
X9428
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
0° - 8°
.0075 (.19)
.0118 (.30)
.193 (4.9)
.200 (5.1)
.019 (.50)
.029 (.75)
Detail A (20X)
.169 (4.3)
.177 (4.5)
.047 (1.20)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
Seating Plane
.252 (6.4) BSC
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
18
FN8197.0
March 8, 2005
PACKAGING INFORMATION
16-Lead Plastic SOIC (300 Mil Body) Package Type S
X9428
PIN 1 INDEX
(4X) 7°
0.050 (1.27)
PIN 1
0.010 (0.25)
0.020 (0.50)
X 45°
0.014 (0.35)
0.020 (0.51)
0.403 (10.2 )
0.413 ( 10.5)
0.290 (7.37)
0.299 (7.60)
0.003 (0.10)
0.012 (0.30)
0.050" Typical
0.393 (10.00)
0.420 (10.65)
0.092 (2.35)
0.105 (2.65)
0° - 8 °
0.0075 (0.19)
0.010 (0.25)
0.015 (0.40)
0.050 (1.27)
0.420"
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
19
0.030" Typical
16 Places
0.050"
Typical
FN8197.0
March 8, 2005
Ordering Information
X9428
X9428PTV
Device
Y
VCC Limits
Blank = 5V ±10%
-2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Package
P = 16-Lead Plastic DIP*
S = 16-Lead SOIC
V = 14-Lead TSSOP
Potentiometer Organization
Y = 2kΩ
W =10kΩ
*Note: P package only available as X9428WP16I-2.7 for prototyping. Other resistor values not available in package.
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