intersil X9428 DATA SHEET

®

www.BDTIC.com/Intersil

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Data Sheet April 26, 2006

9

1

3

2

2

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N

IG

S

Low Noise/Low Power/2-Wire Bus

X9428

FN8197.1

Single Digitally Controlled Potentiometer
(XDCP™)

FEATURES

• Solid state potentiometer

• 2-wire serial interface

• Register oriented format
—Direct Read/Write/Transfer wiper position
—Store as many as four positions per

potentiometer

• Power supplies
—V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V

• Low power CMOS
—Standby current < 1µA
—Ideal for battery operated applications

• High reliability
—Endurance–100,000 Data changes per bit per

—Register data retention–100 years

• 4-bytes of nonvolatile memory

•10kΩ resistor array

• Resolution: 64 taps each potentiometer

• 16 Ld SOIC, 14 Ld TSSOP packages

• Pb-free plus anneal available (RoHS compliant)

= 2.7V to 5.5V

CC

register

DESCRIPTION

The X9428 integrates a digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.

The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

BLOCK DIAGRAM

V

CC

V

SS

V+
V–

SCL

SDA

WP

A0

A2

A3

Interface

and

Control

Circuitry

1

8

Data

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

R0 R1

R2 R3

Wiper

Counter
Register

(WCR)

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

VH/R

VL/R

VW/R

H

L

W

Ordering Information

www.BDTIC.com/Intersil

X9428

PART

PART NUMBER

X9428WS16* X9428WS 5 to ±10% 10 0 to +70 16 Ld SOIC (300 mil) M16.3
X9428WS16Z* (Note) X9428WS Z 0 to +70 16 Ld SOIC (300 mil)

X9428WS16I* X9428WS I -40 to +85 16 Ld SOIC (300 mil) M16.3
X9428WS16IZ* (Note) X9428WS ZI -40 to +85 16 Ld SOIC (300 mil)

X9428WV14* X9428 W 0 to +70 14 Ld TSSOP

X9428WV14Z* (Note) X9428 Z 0 to +70 14 Ld TSSOP

X9428WV14I* X9428 WI -40 to +85 14 Ld TSSOP

X9428WV14IZ* (Note) X9428 ZI -40 to +85 14 Ld TSSOP

X9428YS16* X9428YS 2 0 to +70 16 Ld SOIC (300 mil) M16.3
X9428YS16Z* (Note) X9428YS Z 0 to +70 16 Ld SOIC (300 mil)

X9428YS16I* X9428YS I -40 to +85 16 Ld SOIC (300 mil) M16.3
X9428YS16IZ* (Note) X9428YS ZI -40 to +85 16 Ld SOIC (300 mil)

X9428YV14* X9428 Y 0 to +70 14 Ld TSSOP

X9428YV14Z* (Note) X9428 YZ 0 to +70 14 Ld TSSOP

X9428YV14I* X9428 YI -40 to +85 14 Ld TSSOP

X9428YV14IZ* (Note) X9428 YZI -40 to +85 14 Ld TSSOP

X9428WS16-2.7* X9428WS F 2.7 to 5.5 10 0 to +70 16 Ld SOIC (300 mil) M16.3
X9428WS16Z-2.7*

(Note)
X9428WS16I-2.7* X9428WS G -40 to +85 16 Ld SOIC (300 mil) M16.3
X9428WS16IZ-2.7*

(Note)
X9428WV14-2.7* X9428 WF 0 to +70 14 Ld TSSOP

X9428WV14Z-2.7*
(Note)

X9428WV14I-2.7* X9428 WG -40 to +85 14 Ld TSSOP

X9428WV14IZ-2.7*
(Note)

X9428YS16-2.7* X9428YS F 2 0 to +70 16 Ld SOIC (300 mil) M16.3
X9428YS16Z-2.7*

(Note)

MARKING VCC LIMITS (V)

X9428WS ZF 0 to +70 16 Ld SOIC (300 mil)

X9428WS ZG -40 to +85 16 Ld SOIC (300 mil)

X9428 ZF 0 to +70 14 Ld TSSOP

X9428 ZG -40 to +85 14 Ld TSSOP

X9428YS ZF 0 to +70 16 Ld SOIC (300 mil)

POTENTIOMETER

ORGANIZATION (kΩ)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

M16.3

(Pb-free)

M16.3

(Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

M16.3

(Pb-free)

M16.3

(Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

M16.3

(Pb-free)

M16.3

(Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

M16.3

(Pb-free)

2

FN8197.1

April 26, 2006

Ordering Information (Continued)

www.BDTIC.com/Intersil

X9428

PART

PART NUMBER

X9428YS16I-2.7* X9428YS G 2.7 to 5.5 2 -40 to +85 16 Ld SOIC (300 mil) M16.3
X9428YS16IZ-2.7*

(Note)
X9428YV14-2.7* X9428 YF 0 to +70 14 Ld TSSOP

X9428YV14Z-2.7*
(Note)

X9428YV14I-2.7* X9428 YG -40 to +85 14 Ld TSSOP

X9428YV14IZ-2.7*
(Note)

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING V

X9428YS ZG -40 to +85 16 Ld SOIC (300 mil)

X9428 YZF 0 to +70 14 Ld TSSOP

X9428 YZG -40 to +85 14 Ld TSSOP

LIMITS (V)

CC

POTENTIOMETER

ORGANIZATION (kΩ)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

M16.3

(Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

3

FN8197.1

April 26, 2006

X9428

www.BDTIC.com/Intersil

PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)

The SCL input is used to clock data into and out of the
X9428.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.

Device Address (A

, A2, A3)

0

The Address inputs are used to set the least
significant 3 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9428. A maximum of 8
devices may occupy the 2-wire serial bus.

Potentiometer Pins

PIN CONFIGURATION

V

R

L/VL

RH/V

RW/V

SDA

CC

A2

W

WP

V

SS

A2

R

R

R

SDA

WP

V

H

SS

1

2

3

4

5

6

7

8

1

L

2

3

H

4

W

5

6

7

DIP/SOIC

X9428

TSSOP

X9428

16

15

14

13

12

11

10

9

14

13

12

11

10

V+

NC

A0

NC

A3

SCL

NC

V-

V

CC

V+

A0

NC

A3

SCL

9

V-

8

, RL/V

R

H/VH

L

The RH/VH and RL/VL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.

R

W/VW

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

Hardware Write Protect Input WP

The WP pin when low prevents nonvolatile writes to
the Data Registers.

Analog Supply V+, V-

The Analog Supply V+, V- are the supply voltages for
the XDCP analog section.

PIN NAMES

Symbol Description

SCL Serial clock

SDA Serial data

A0, A2, A3 Device address

R

, VL/RHPotentiometer Pins

H/VH

(terminal equivalent)

R

W/VW

WP

Potentiometer Pin (wiper equivalent)

Hardware write protection

V+,V- Analog and voltage follower

V

CC

V

SS

System supply voltage

System ground

NC No connection

4

FN8197.1

April 26, 2006

X9428

www.BDTIC.com/Intersil

PRINCIPLES OF OPERATION

The X9428 is a highly integrated microcircuit
incorporating a resistor array and its associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.

Serial Interface

The X9428 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9428 will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods (tLOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.

The X9428 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9428 will respond with a final acknowledge.

Array Description

The X9428 is comprised of a resistor array. The array
contains 63 discrete resistive segments that are
connected in series. The physical ends of the array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(V
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers and
the WCR can be read and written by the host system.

) output. Within each individual array only one

W/RW

and VL/RL inputs).

H/RH

Start Condition

All commands to the X9428 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

). The X9428 continuously

HIGH

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9428
this is fixed as 0101[B].

Figure 1. Slave Address

Device Type

Identifier

100

The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A
compares the serial data stream with the address
input state; a successful compare of all four address
bits is required for the X9428 to respond with an
acknowledge. The A
driven by CMOS input signals or tied to V

1

A3 A2 0 A0

Device Address

, A2, A3 inputs. The X9428

0

, A2, A3 inputs can be actively

0

or VSS.

CC

5

FN8197.1

April 26, 2006

X9428

www.BDTIC.com/Intersil

Acknowledge Polling

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9428
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9428 is still busy with the write operation no ACK will
be returned. If the X9428 has completed the write
operation an ACK will be returned, and the master can
then proceed with the next operation.

Flow 1. ACK Polling Sequence

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

YES

Further

Operation?

YES

Issue

Instruction

NO

NO

Issue STOP

Issue STOP

Figure 2. Instruction Byte Format

Register

Select

I1I2I3 I0 R1 R0 0 0

Instructions

The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers that
is to be acted upon when a register oriented instruction
is issued. Bits 0 and 1 are defined to be 0.

Four of the seven instructions end with the transmission
of the instruction byte. The basic sequence is illustrated
in Figure 3. These two-byte instructions exchange data
between the Wiper Counter Register and one of the
Data Registers. A transfer from a Data Register to a
Wiper Counter Register is essentially a write to a static
RAM. The response of the wiper to this action will be
delayed t

. A transfer from the Wiper Counter

WRL

Register (current wiper position), to a Data Register is a
write to nonvolatile memory and takes a minimum of

to complete.

t

WR

Four instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9428; either between the host and one of
the Data Registers or directly between the host and the
Wiper Counter Register. These instructions are: Read
Wiper Counter Register (read the current wiper position
of the selected pot), write Wiper Counter Register
(change current wiper position of the selected pot), read
Data Register (read the contents of the selected
nonvolatile register) and write Data Register (write a
new value to the selected Data Register). The
sequence of operations is shown in Figure 4.

Proceed

Proceed

Instruction Structure

The next byte sent to the X9428 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of four associated registers. The format is
shown below in Figure 2.

6

FN8197.1

April 26, 2006

Figure 3. Two-Byte Instruction Sequence

www.BDTIC.com/Intersil

SCL

SDA

X9428

S

0101A3A20A0
T
A
R
T

The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9428 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse

) while SDA is HIGH, the selected wiper will

(t

HIGH

A

I3 I2 I1 I0 R1 R0 0 0 A
C
K

S

C

T

K

O
P

move one resistor segment towards the V
terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the V

terminal. A detailed

L/RL

illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.

H/RH

Table 1. Instruction Set

Instruction Set

Instruction

Read Wiper Counter

0

1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register

OperationI3I2I1I0R1R0X1X

Register
Write Wiper Counter

1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register

Register
Read Data Register 1 0 1 1 1/0 1/0 0 0 Read the contents of the Data Register pointed to by

- R

R

1

0

Write Data Register 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register pointed to by

- R

R

1

0

XFR Data Register to
Wiper Counter Register

XFR Wiper Counter
Register to Data Register

Increment/Decrement
Wiper Counter Register

Note: (7) 1/0 = data is one or zero

1 1 0 1 1/0 1/0 0 0 Transfer the contents of the Data Register pointed to

- R0 to its Wiper Counter Register

by R

1

1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter Register

to the Data Register pointed to by R

- R

1

0

0 0 1 0 0 0 0 1/0 Enable Increment/decrement of the Wiper Counter

Register

7

FN8197.1

April 26, 2006

Figure 4. Three-Byte Instruction Sequence

www.BDTIC.com/Intersil

SCL

SDA

X9428

S

0 1 0 1 A3 A2 0 A0
T
A
R
T

A

I3 I2 I1 I0 R1 R0 0 0
C
K

Figure 5. Increment/Decrement Instruction Sequence

SCL

SDA

S

0101A3A20A0
T
A
R
T

A

I3 I2 I1 I0 R0 0 0 A
C
K

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

Issued

SCL

R1

A

0 0 D5 D4 D3 D2 D1 D0
C
K

XX

I
N
C
1

t

WRID

I
N
C

2

C
K

D

I

E

N

C

C

1

n

A

S

C

T

K

O
P

S

D

T

E

O

C

P

n

SDA

VW/R

W

8

Voltage Out

FN8197.1

April 26, 2006

Figure 7. Acknowledge Response from Receiver

www.BDTIC.com/Intersil

X9428

SCL from

Master

Data Output

from Transmitter

Data Output

from Receiver

START

1

Figure 8. Detailed Potentiometer Block Diagram

Serial Data Path

From Interface

Circuitry

Register 0 Register 1

8 6

Register 2 Register 3

If WCR = 00[H] then VW/RW = VL/R

If WCR = 3F[H] then VW/RW = VH/R

L

H

UP/DN

Modified SCL

Serial
Bus

Input

Parallel
Bus

Input

Register

UP/DN

CLK

89

Acknowledge

C
o

u
n

t

e

r

Wiper

Counter

(WCR)

INC/DEC

Logic

D

e
c
o
d

e

VH/R

VL/R

H

L

9

VW/R

W

FN8197.1

April 26, 2006

X9428

www.BDTIC.com/Intersil

DETAILED OPERATION

The potentiometer has a Wiper Counter Register and
four Data Registers. A detailed discussion of the
register organization and array operation follows.

Wiper Counter Register

The X9428 contains a Wiper Counter Register. The
Wiper Counter Register can be envisioned as a 6-bit
parallel and serial load counter with its outputs
decoded to select one of sixty-four switches along its
resistor array. The contents of the WCR can be altered
in four ways: it may be written directly by the host via
the write Wiper Counter Register instruction (serial
load); it may be written indirectly by transferring the
contents of one of four associated Data Registers via
the XFR Data Register instruction (parallel load); it can
be modified one step at a time by the
Increment/Decrement instruction. Finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.

The WCR is a volatile register; that is, its contents are
lost when the X9428 is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be
different from the value present at power-down.

Data Registers

The potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the Wiper Counter Register. It
should be noted all operations changing data in one of
these registers is a nonvolatile operation and will take
a maximum of 10ms.

Register Descriptions

Data Registers, (6-Bit), Nonvolatile

D5 D4 D3 D2 D1 D0

NV NV NV NV NV NV

(MSB) (LSB)

Four 6-bit Data Registers for each XDCP. (eight 6-bit
registers in total).

– {D5~D0}: These bits are for general purpose not

volatile data storage or for storage of up to four
different wiper values. The contents of Data Register
0 are automatically moved to the Wiper Counter
Register on power-up.

Wiper Counter Register, (6-Bit), Volatile

WP5 WP4 WP3 WP2 WP1 WP0

VVVVVV

(MSB) (LSB)

One 6-bit wiper counter register for each XDCP. (Four
6-bit registers in total.)

– {D5~D0}: These bits specify the wiper position of the

respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register 0.
The contents of the WCR can be loaded from any of
the other Data Register or directly. The contents of
the WCR can be saved in a DR.

If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.

10

FN8197.1

April 26, 2006

X9428

www.BDTIC.com/Intersil

Instruction Format

Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.

(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

Read Wiper Counter Register (WCR)

S

device type

T

identifier
A
R

0101

T

Write Wiper Counter Register (WCR)

device

addresses

A3A

0

2

instruction

S

opcode

A
C

A

10010000 00WP

K

0

S

(sent by slave on SDA)

A
C
K

wiper position

W

W

W

P

P

P

5

4

3

2

W

S

M

T

A

W

O

C

P

P

P

K

1

0

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A

0

2

A

0

instruction

S

opcode

A
C

10100000 00WP

K

S
A
C
K

Read Data Register (DR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A

0

2

S
A
C

A

K

0

instruction

opcode

1011

register

address

R1R

es

00 00WP

0

S
A
C
K

Write Data Register (DR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A

0

2

S
A
C

A

K

0

instruction

opcode

1100

register

addresses

R1R

00 00WP

0

S
A
C
K

XFR Data Register (DR) to Wiper Counter Register (WCR)

wiper position

(sent by master on SDA)

W

W

W

W

P

P

P

P

5

3

4

2

1

wiper position/data

(sent by slave on SDA)

W

W

W

W

P

P

P

P

5

4

3

2

1

wiper position/data

(sent by master on SDA)

W

W

W

W

P

P

P

P

5

4

3

2

1

W
P

0

W

P

W
P

0

S

S

T

A

O

C

P

K

0

S

M

T

A

O

C

P

K

S

S

T

A

HIGH-VOLTAGE

O

C

K

WRITE CYCLE

P

S

device type

T

identifier
A
R

0101

T

device

addresses

A3A

0

2

A
0

11

S
A
C
K

instruction

opcode

1101

register

addresses

R1R

00

0

S

S

A

T

C

O

K

P

FN8197.1

April 26, 2006

X9428

www.BDTIC.com/Intersil

XFR Wiper Counter Register (WCR) to Data Register (DR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A

0

2

S
A
C

A

K

0

instruction

opcode

1110

register

addresses

R1R

00

0

S

S

T

A
C
K

HIGH-VOLTAGE

O

WRITE CYCLE

P

Increment/Decrement Wiper Counter Register (WCR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A

0

2

instruction

S

opcode

A
C

A

00100000

K

0

increment/decrement

S

(sent by master on SDA)

A
C

I/DI/

K

....

D

I/DI/

S
T
O
P

D

SYMBOL TABLE Guidelines for Calculating Typical Values of Bus

Pull-Up Resistors

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

Resistance (K)

120

R

100

80

60

40

20

0

MIN

R

MAX

Max.
Resistance

Min.
Resistance

20 40 60 80 100 120

0

Bus Capacitance (pF)

=

=

V

CC MAX

I

OL MIN

t

R

C

BUS

=1.8kΩ

12

FN8197.1

April 26, 2006

X9428

www.BDTIC.com/Intersil

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C

Storage temperature ......................... -65°C to +150°C

Voltage on SDA, SCL or any address

input with respect to V
Voltage on V+ (referenced to V
Voltage on V- (referenced to V

......................... -1V to +7V

SS

)........................ 10V

SS

)........................-10V

SS

(V+) - (V-) .............................................................. 12V

Any V
Any V

..............................................................V+

H/RH

.................................................................V-

L/RL

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Lead temperature (soldering, 10 seconds)........ 300°C

(10 seconds)................................................±12mA

I

W

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C+70°C

Industrial -40°C+85°C

Device Supply Voltage (VCC) Limits

X9428 5V ± 10%

X9428-2.7 2.7V to 5.5V

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Limits

Symbol Parameter

End to end resistance tolerance ±20 %

Power rating 50 mW 25°C, each pot

I

W

R

W

V+ Voltage on V+ pin X9428 +4.5 +5.5 V

V- Voltage on V- pin X9428 -5.5 -4.5 V

V

TERM

C

H/CL

Wiper current ±6 mA

Wiper resistance 150 250 Ω Wiper current = ± 1mA, VCC = 3V

40 100 Ω Wiper current = ± 1mA, V

X9428-2.7 +2.7 +5.5

X9428-2.7 -5.5 -2.7

Voltage on any VH/RH or VL/RL pin V- V+ V

Noise -140 dBV Ref: 1kHz

Resolution

Absolute linearity

Relative linearity

Temperature Coefficient of R

Ratiometric Temperature Coefficient ±20 ppm/°C

/CWPotentiometer Capacitances 10/10/25 pF See Circuit #3,

(4)

(1)

(2)

TOTAL

1.6 %

±1 MI

±0.2 MI

±300 ppm/°C

(3)

(3)

Test ConditionsMin. Typ. Max. Unit

V

w(n)(actual)

V

w(n + 1 )

Spice Macromodel

- [V

- V

w(n) + MI

= 5V

CC

w(n)(expected)

]

13

FN8197.1

April 26, 2006

X9428

www.BDTIC.com/Intersil

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter

I

CC1

I

CC2

I

SB

I

LI

I

LO

V

IH

V

IL

V

OL

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

VCC supply current
(nonvolatile write)

VCC supply current
(move wiper, write, read)

1mAf

SCL

Other Inputs = V

100 µA f

SCL

Other Inputs = V

VCC current (standby) 1 µA SCL = SDA = VCC, Addr. = V

Input leakage current 10 µA VIN = VSS to V

Output leakage current 10 µA V

Input HIGH voltage VCC x 0.7 VCC x 0.5 V

Input LOW voltage -0.5 VCC x 0.1 V

Output LOW voltage 0.4 V IOL = 3mA

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-

eter. It is a measure of the error in step size.
(3) MI = RTOT/63 or (R
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.

- RL)/63, single pot

H

Test ConditionsMin. Typ. Max. Unit

= 400kHz, SDA = Open,

SS

= 400kHz, SDA = Open,

SS

CC

= VSS to V

OUT

CC

SS

ENDURANCE AND DATA RETENTION

Parameter Min. Unit

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 Years

CAPACITANCE

Symbol Test Max. Unit Test Conditions

(5)

C

I/O

(5)

C

IN

Input/output capacitance (SDA) 8 pF V

I/O

= 0V

Input capacitance (A0, A1, A2, A3, and SCL) 6 pF VIN = 0V

POWER-UP TIMING

Symbol Parameter Min. Typ. Max. Unit

(6)

t

PUR

t

PUW

t

RVCC

(6)

(7)

Power-up to initiation of read operation 1 ms

Power-up to initiation of write operation 5 ms

VCC Power-up ramp rate 0.2 50 V/msec

POWER-UP AND POWER-DOWN

There are no restrictions on the power-up or power-down sequencing of the bias supplies V

, V+, and V- provided

CC

that all three supplies reach their final values within 1msec of each other. However, at all times, the voltages on the
potentiometer pins must be less than V+ and more than V-. The recall of the wiper position from nonvolatile memory
is not in effect until all supplies reach their final value.

Notes: (5) This parameter is periodically sampled and not 100% tested

(6) t

(7) Sample tested only.

and t

PUR

instruction can be issued. These parameters are periodically sampled and not 100% tested.

are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific

PUW

14

FN8197.1

April 26, 2006

X9428

www.BDTIC.com/Intersil

A.C. TEST CONDITIONS

nput pulse levels VCC x 0.1 to VCC x 0.9

I

Input rise and fall times 10ns

Input and output timing level V

CC

x 0.5

Circuit #3 SPICE Macro Model

R

R

H

TOTAL

C

H

C

C

L

W

10pF

EQUIVALENT A.C. LOAD CIRCUIT

SDA Output

5V

1533Ω

100pF

10pF

2.7V

100pF

25pF

R

W

AC TIMING (over recommended operating conditions)

Symbol Parameter Min. Max. Unit

f

SCL

t

CYC

t

HIGH

t

LOW

t

SU:STA

t

HD:STA

t

SU:STO

t

SU:DAT

t

HD:DAT

t

R

t

F

t

AA

t

DH

T

I

t

BUF

t

SU:WPA

t

HD:WPA

Clock frequency 100 400 kHz

Clock cycle time 2500 ns

Clock high time 600 ns

Clock low time 1300 ns

Start setup time 600 ns

Start hold time 600 ns

Stop setup time 600 ns

SDA data input setup time 100 ns

SDA data input hold time 30 ns

SCL and SDA rise time 300 ns

SCL and SDA fall time 300 ns

SCL low to SDA data output valid time 900 ns

SDA data output hold time 50 ns

Noise suppression time constant at SCL and SDA inputs 50 ns

Bus free time (prior to any transmission) 1300 ns

WP, A0, A1, A2 and A3 setup time 0 ns

WP, A0, A1, A2 and A3 hold time 0 ns

R

L

15

FN8197.1

April 26, 2006

X9428

www.BDTIC.com/Intersil

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Typ. Max. Unit

t

WR

XDCP TIMING

Symbol Parameter Min. Max. Unit

t

WRPO

t

WRL

t

WRID

Note: (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling

edge of SCL.

TIMING DIAGRAMS

START and STOP Timing

SCL

SDA

High-voltage write cycle time (store instructions) 5 10 ms

Wiper response time after the third (last) power supply is stable 10 µs

Wiper response time after instruction issued (all load instructions) 10 µs

Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 10 µs

(START) (STOP)

t

F

t

SU:STO

t

F

t

SU:STA

t

HD:STA

t

R

t

R

Input Timing

SCL

SDA

Output Timing

SCL

SDA

t

CYC

t

SU:DAT

t

HIGH

t

LOW

t

HD:DAT

t

AA

t

DH

t

BUF

16

FN8197.1

April 26, 2006

XDCP Timing (for All Load Instructions)

www.BDTIC.com/Intersil

SCL

X9428

(STOP)

SDA

V

W/RW

XDCP Timing (for Increment/Decrement Instruction)

SCL

Wiper Register Address Inc/Dec Inc/Dec

V

W/RW

SDA

Write Protect and Device Address Pins Timing

LSB

t

WRL

t

WRID

SCL

SDA

WP

A0, A2, A3

17

(START) (STOP)

...

(Any Instruction)

...

...

t

SU:WPA

t

HD:WPA

FN8197.1

April 26, 2006

APPLICATIONS INFORMATION

www.BDTIC.com/Intersil

Basic Configurations of Electronic Potentiometers

V

R

VW/R

W

Three terminal Potentiometer;
Variable voltage divider

Application Circuits

Noninverting Amplifier Voltage Regulator

X9428

+V

R

I

Two terminal Variable Resistor;
Variable current

V

S

VO = (1+R2/R1)V

Offset Voltage Adjustment Comparator with Hysteresis

V

S

10kΩ

R

R

100kΩ

-12V+12V

+

–

R

1

S

1

–

+

TL072

10kΩ10kΩ

V

O

2

R

2

V

O

IN

VO (REG) = 1.25V (1+R2/R1)+I

V

S

VUL = {R1/(R1+R2)} VO(max)
V

= {R1/(R1+R2)} VO(min)

LL

317

I

adj

R

2

–

+

}

}

R

R

2

1

R

1

adj R2

VO (REG)V

V

O

18

FN8197.1

April 26, 2006

Application Circuits (continued)

www.BDTIC.com/Intersil

Attenuator Filter

R

1

V

S

V

R

3

R

VO = G V

-1/2 ≤ G ≤ +1/2

Inverting Amplifier Equivalent L-R Circuit

R

R

1

S

}

4

All RS = 10kΩ

S

2

}

–

+

–

+

X9428

C

V

R

2

V

O

V

O

S

R

G

O

fc = 1/(2πRC)

C

1

V

S

R

1

= 1 + R2/R

+

–

R

1

R

2

+

–

V

O

2

VO = G V
G = - R2/R

R

Z

S

1

Function Generator

R

–

+

R

}

A

R

}

B

frequency ∝ R1, R2, C
amplitude ∝ R

2

, R

A

IN

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R

R

1

B

1

–

+

1

R

3

+ R3) >> R

C

2

19

FN8197.1

April 26, 2006

X9428

www.BDTIC.com/Intersil

Thin Shrink Small Outline Plastic Packages (TSSOP)

N

INDEX
AREA

123

0.05(0.002)

-A­D

e

b

0.10(0.004) C AM BS

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen­sion at maximum material condition. Minimum space between protru­sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)

E1

-B-

SEATING PLANE

A

-C-

M

0.25(0.010) BM M

E

α

A1

0.10(0.004)

GAUGE

PLANE

0.25

0.010

A2

L

c

M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.041 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.195 0.199 4.95 5.05 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N14 147

o

α

0

o

8

o

0

o

8

NOTESMIN MAX MIN MAX

-

Rev. 2 4/06

20

FN8197.1

April 26, 2006

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

X9428

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.

M

A1

C

0.10(0.004)

M16.3 (JEDEC MS-013-AA ISSUE C)

16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.3977 0.4133 10.10 10.50 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC ­H 0.394 0.419 10.00 10.65 ­h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N16 167

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

21

FN8197.1

April 26, 2006