intersil X9428 DATA SHEET

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Data Sheet April 26, 2006

Low Noise/Low Power/2-Wire Bus

X9428

FN8197.1

Single Digitally Controlled Potentiometer (XDCP™)

FEATURES

• Solid state potentiometer

• 2-wire serial interface

• Register oriented format —Direct Read/Write/Transfer wiper position —Store as many as four positions per

potentiometer

• Power supplies —V —V+ = 2.7V to 5.5V —V– = -2.7V to -5.5V

• Low power CMOS —Standby current < 1µA —Ideal for battery operated applications

• High reliability —Endurance–100,000 Data changes per bit per

—Register data retention–100 years

• 4-bytes of nonvolatile memory

•10kΩ resistor array

• Resolution: 64 taps each potentiometer

• 16 Ld SOIC, 14 Ld TSSOP packages

• Pb-free plus anneal available (RoHS compliant)

= 2.7V to 5.5V

DESCRIPTION

The X9428 integrates a digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit.

The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power-up recalls the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

BLOCK DIAGRAM

V+ V–

SCL

SDA

Interface

and

Control

Circuitry

Data

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

R0 R1

R2 R3

Wiper

Counter Register

(WCR)

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

VH/R

VL/R

VW/R

Ordering Information

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X9428

PART

PART NUMBER

X9428WS16* X9428WS 5 to ±10% 10 0 to +70 16 Ld SOIC (300 mil) M16.3 X9428WS16Z* (Note) X9428WS Z 0 to +70 16 Ld SOIC (300 mil)

X9428WS16I* X9428WS I -40 to +85 16 Ld SOIC (300 mil) M16.3 X9428WS16IZ* (Note) X9428WS ZI -40 to +85 16 Ld SOIC (300 mil)

X9428WV14* X9428 W 0 to +70 14 Ld TSSOP

X9428WV14Z* (Note) X9428 Z 0 to +70 14 Ld TSSOP

X9428WV14I* X9428 WI -40 to +85 14 Ld TSSOP

X9428WV14IZ* (Note) X9428 ZI -40 to +85 14 Ld TSSOP

X9428YS16* X9428YS 2 0 to +70 16 Ld SOIC (300 mil) M16.3 X9428YS16Z* (Note) X9428YS Z 0 to +70 16 Ld SOIC (300 mil)

X9428YS16I* X9428YS I -40 to +85 16 Ld SOIC (300 mil) M16.3 X9428YS16IZ* (Note) X9428YS ZI -40 to +85 16 Ld SOIC (300 mil)

X9428YV14* X9428 Y 0 to +70 14 Ld TSSOP

X9428YV14Z* (Note) X9428 YZ 0 to +70 14 Ld TSSOP

X9428YV14I* X9428 YI -40 to +85 14 Ld TSSOP

X9428YV14IZ* (Note) X9428 YZI -40 to +85 14 Ld TSSOP

X9428WS16-2.7* X9428WS F 2.7 to 5.5 10 0 to +70 16 Ld SOIC (300 mil) M16.3 X9428WS16Z-2.7*

(Note) X9428WS16I-2.7* X9428WS G -40 to +85 16 Ld SOIC (300 mil) M16.3 X9428WS16IZ-2.7*

(Note) X9428WV14-2.7* X9428 WF 0 to +70 14 Ld TSSOP

X9428WV14Z-2.7* (Note)

X9428WV14I-2.7* X9428 WG -40 to +85 14 Ld TSSOP

X9428WV14IZ-2.7* (Note)

X9428YS16-2.7* X9428YS F 2 0 to +70 16 Ld SOIC (300 mil) M16.3 X9428YS16Z-2.7*

(Note)

MARKING VCC LIMITS (V)

X9428WS ZF 0 to +70 16 Ld SOIC (300 mil)

X9428WS ZG -40 to +85 16 Ld SOIC (300 mil)

X9428 ZF 0 to +70 14 Ld TSSOP

X9428 ZG -40 to +85 14 Ld TSSOP

X9428YS ZF 0 to +70 16 Ld SOIC (300 mil)

POTENTIOMETER

ORGANIZATION (kΩ)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

M16.3

(Pb-free)

M16.3

(Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

M16.3

(Pb-free)

M16.3

(Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

M16.3

(Pb-free)

M16.3

(Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

M16.3

(Pb-free)

FN8197.1

April 26, 2006

Ordering Information (Continued)

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X9428

PART

PART NUMBER

X9428YS16I-2.7* X9428YS G 2.7 to 5.5 2 -40 to +85 16 Ld SOIC (300 mil) M16.3 X9428YS16IZ-2.7*

(Note) X9428YV14-2.7* X9428 YF 0 to +70 14 Ld TSSOP

X9428YV14Z-2.7* (Note)

X9428YV14I-2.7* X9428 YG -40 to +85 14 Ld TSSOP

X9428YV14IZ-2.7* (Note)

*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING V

X9428YS ZG -40 to +85 16 Ld SOIC (300 mil)

X9428 YZF 0 to +70 14 Ld TSSOP

X9428 YZG -40 to +85 14 Ld TSSOP

LIMITS (V)

POTENTIOMETER

ORGANIZATION (kΩ)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

M16.3

(Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

M14.173

(4.4mm)

M14.173

(4.4mm) (Pb-free)

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X9428

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PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)

The SCL input is used to clock data into and out of the X9428.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph.

Device Address (A

, A2, A3)

The Address inputs are used to set the least significant 3 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9428. A maximum of 8 devices may occupy the 2-wire serial bus.

Potentiometer Pins

PIN CONFIGURATION

L/VL

RH/V

RW/V

SDA

DIP/SOIC

X9428

TSSOP

X9428

V+

SCL

V-

V+

SCL

V-

, RL/V

H/VH

The RH/VH and RL/VL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer.

W/VW

The wiper outputs are equivalent to the wiper output of a mechanical potentiometer.

Hardware Write Protect Input WP

The WP pin when low prevents nonvolatile writes to the Data Registers.

Analog Supply V+, V-

The Analog Supply V+, V- are the supply voltages for the XDCP analog section.

PIN NAMES

Symbol Description

SCL Serial clock

SDA Serial data

A0, A2, A3 Device address

, VL/RHPotentiometer Pins

H/VH

(terminal equivalent)

W/VW

Potentiometer Pin (wiper equivalent)

Hardware write protection

V+,V- Analog and voltage follower

System supply voltage

System ground

NC No connection

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X9428

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PRINCIPLES OF OPERATION

The X9428 is a highly integrated microcircuit incorporating a resistor array and its associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers.

Serial Interface

The X9428 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9428 will be considered a slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions.

The X9428 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9428 will respond with a final acknowledge.

Array Description

The X9428 is comprised of a resistor array. The array contains 63 discrete resistive segments that are connected in series. The physical ends of the array are equivalent to the fixed terminals of a mechanical potentiometer (V

At both ends of the array and between each resistor segment is a CMOS switch connected to the wiper (V switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches.

The WCR may be written directly, or it can be changed by transferring the contents of one of four associated Data Registers into the WCR. These Data Registers and the WCR can be read and written by the host system.

) output. Within each individual array only one

W/RW

and VL/RL inputs).

H/RH

Start Condition

All commands to the X9428 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (t monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met.

Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data.

). The X9428 continuously

HIGH

Device Addressing

Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9428 this is fixed as 0101[B].

Figure 1. Slave Address

Device Type

Identifier

100

The next four bits of the slave address are the device address. The physical device address is defined by the state of the A compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9428 to respond with an acknowledge. The A driven by CMOS input signals or tied to V

A3 A2 0 A0

Device Address

, A2, A3 inputs. The X9428

, A2, A3 inputs can be actively

or VSS.

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X9428

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Acknowledge Polling

The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9428 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9428 is still busy with the write operation no ACK will be returned. If the X9428 has completed the write operation an ACK will be returned, and the master can then proceed with the next operation.

Flow 1. ACK Polling Sequence

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

YES

Further

Operation?

YES

Issue

Instruction

Issue STOP

Figure 2. Instruction Byte Format

Select

I1I2I3 I0 R1 R0 0 0

Instructions

The four high order bits define the instruction. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. Bits 0 and 1 are defined to be 0.

Four of the seven instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the Wiper Counter Register and one of the Data Registers. A transfer from a Data Register to a Wiper Counter Register is essentially a write to a static RAM. The response of the wiper to this action will be delayed t

. A transfer from the Wiper Counter

WRL

to complete.

Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9428; either between the host and one of the Data Registers or directly between the host and the Wiper Counter Register. These instructions are: Read Wiper Counter Register (read the current wiper position of the selected pot), write Wiper Counter Register (change current wiper position of the selected pot), read Data Register (read the contents of the selected nonvolatile register) and write Data Register (write a new value to the selected Data Register). The sequence of operations is shown in Figure 4.

Proceed

Instruction Structure

The next byte sent to the X9428 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of four associated registers. The format is shown below in Figure 2.

FN8197.1

April 26, 2006

Figure 3. Two-Byte Instruction Sequence

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SCL

SDA

X9428

0101A3A20A0 T A R T

The Increment/Decrement command is different from the other commands. Once the command is issued and the X9428 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse

) while SDA is HIGH, the selected wiper will

HIGH

I3 I2 I1 I0 R1 R0 0 0 A C K

O P

move one resistor segment towards the V terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the V

terminal. A detailed

L/RL

illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively.

H/RH

Table 1. Instruction Set

Instruction Set

Instruction

Read Wiper Counter

1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register

OperationI3I2I1I0R1R0X1X

1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register

- R

Write Data Register 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register pointed to by

- R

XFR Data Register to Wiper Counter Register

XFR Wiper Counter Register to Data Register

Increment/Decrement Wiper Counter Register

Note: (7) 1/0 = data is one or zero

1 1 0 1 1/0 1/0 0 0 Transfer the contents of the Data Register pointed to

- R0 to its Wiper Counter Register

by R

1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter Register

to the Data Register pointed to by R

- R

0 0 1 0 0 0 0 1/0 Enable Increment/decrement of the Wiper Counter

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