intersil X9420 DATA SHEET

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Data Sheet FN8195.1April 26, 2006

Single Digitally Controlled (XDCP™) Potentiometer

FEATURES

• Solid-State Potentiometer

• SPI Serial Interface

• Register Oriented Format —Direct read/write/transfer wiper positions —Store as many as four positions per

potentiometer

• Power Supplies —V —V+ = 2.7V to 5.5V —V– = -2.7V to -5.5V

• Low Power CMOS —Standby current < 1µA

• High Reliability —Endurance–100,000 data changes per bit per

—Register data retention–100 years

• 8-bytes of Nonvolatile EEPROM Memory

•10kΩ or 2.5kΩ Resistor Arrays

• Resolution: 64 Taps Each Pot

• 14 Ld TSSOP and 16 Ld SOIC Packages

• Pb-Free Plus Anneal Available (RoHS Compliant)

= 2.7V to 5.5V

X9420

Low Noise/Low Power/SPI Bus

DESCRIPTION

The X9420 integrates a single digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit.

The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power-up recalls the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

BLOCK DIAGRAM

HOLD

SCK

Interface

and

Control

Circuitry

Data

R0 R1

R2 R3

Wiper Counter Register

(WCR)

VH/R

VL/R

VW/R

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9420

Ordering Information

POTENTIOMETER

PART

PART NUMBER

X9420WS16* X9420WS 5 ±10% 10 0 to +70 16 Ld SOIC (300 mil) M16.3 X9420WS16Z* (Note) X9420WS Z 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3 X9420WS16I* X9420WS I -40 to +85 16 Ld SOIC (300 mil) M16.3 X9420WS16IZ* (Note) X9420WS ZI -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3 X9420WV14* X9420 W 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9420WV14Z* (Note) X9420 WZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9420WV14I* X9420 WI -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9420WV14IZ* (Note) X9420 WZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9420YS16* X9420YS 2.5 0 to +70 16 Ld SOIC (300 mil) M16.3 X9420YS16Z* (Note) X9420YS Z 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3 X9420YS16I* X9420YS I -40 to +85 16 Ld SOIC (300 mil) M16.3 X9420YS16IZ* (Note) X9420YS ZI -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3 X9420YV14* X9420 Y 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9420YV14Z* (Note) X9420 YZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9420YV14I* X9420 YI -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9420YV14IZ* (Note) X9420 YZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9420WS16-2.7* X9420WS F 2.7 to 5.5 10 0 to +70 16 Ld SOIC (300 mil) M16.3 X9420WS16Z-2.7* (Note) X9420WS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3 X9420WS16I-2.7* X9420WS G -40 to +85 16 Ld SOIC (300 mil) M16.3 X9420WS16IZ-2.7*

(Note) X9420WV14-2.7* X9420 WF 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9420WV14Z-2.7* (Note) X9420 WZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9420WV14I-2.7* X9420 WG -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9420WV14IZ-2.7*

(Note) X9420YS16-2.7* X9420YS F 2.7 to 5.5 2.5 0 to +70 16 Ld SOIC (300 mil) M16.3 X9420YS16Z-2.7* (Note) X9420YS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3 X9420YS16I-2.7* X9420YS G -40 to +85 16 Ld SOIC (300 mil) M16.3 X9420YS16IZ-2.7* (Note) X9420YS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3 X9420YV14-2.7* X9420 YF 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9420YV14Z-2.7* (Note) X9420 YZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9420YV14I-2.7* X9420 YG -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9420YV14IZ-2.7* (Note) X9420 YZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173

*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING VCC LIMITS (V)

X9420WS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3

X9420 WZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173

ORGANIZATION

(k)

TEMP. RANGE

(°C) PACKAGE

PKG.

DWG. #

FN8195.1

April 26, 2006

X9420

PIN DESCRIPTIONS

Host Interface Pins

Serial Output (SO)

SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.

Serial Input

SI is the serial data input pin. All opcodes, byte addresses and data to be written to the potentiometer and pot register are input on this pin. Data is latched by the rising edge of the serial clock.

Serial Clock (SCK)

The SCK input is used to clock data into and out of the X9420.

Chip Select (CS

When CS

is HIGH, the X9420 is deselected and the

)

SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS

LOW enables the X9420, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS

required prior to the start of any operation.

Hold (HOLD

HOLD

)

is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD

may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD

must be brought LOW while SCK is LOW. To resume communication, HOLD

is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times.

Device Address (A

)

The address inputs is used to set the least significant bit of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9420. A maximum of 2 devices may occupy the SPI serial bus.

Potentiometer Pins

, VL/R

H/RH

The VH/RH and VL/RL input are equivalent to the terminal connections on either end of a mechanical potentiometer.

W/RW

The wiper output is equivalent to the wiper output of a mechanical potentiometer.

Hardware Write Protect Input (WP

The WP

pin when LOW prevents nonvolatile writes to

)

the Data Registers. Writing to the Wiper Counter Register is not restricted.

Analog Supplies (V+, V-)

The analog supplies V+, V- are the supply voltages for the XDCP analog section.

System/Digital Supply (V

is the supply voltage for the system/digital

section. V

is the system ground.

)

PIN CONFIGURATION

DIP/SOIC

RL/V

RH/V

RW/V

RL/V

RH/V

RW/V

TSSOP

X9420

V+

HOLD

SCK

V-

V+

HOLD

SCK

V-

FN8195.1

April 26, 2006

X9420

PIN NAMES

Symbol Description

SCK Serial Clock

SI, SO Serial Data

A0 Device Address

H/RH

L/RL

W/RW

WP Hardware Write Protection

HOLD Serial Communication Pause

V+,V- Analog Supplies

NC No Connection

Potentiometer Pins (terminal equivalent)

Potentiometer Pins (wiper equivalent)

System Supply Voltage

System Ground

PRINCIPLES OF OPERATION

The X9420 is a highly integrated microcircuit incorporating a resistor array and associated registers and counter and the serial interface logic providing direct communication between the host and the XDCP potentiometer.

Serial Interface

The X9420 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS LOW and the HOLD

and WP pins must be HIGH

must be

during the entire operation.

Wiper Counter Register (WCR)

The X9420 contains a Wiper Counter Register. The WCR can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/ Decrement instruction. Finally, it is loaded with the contents of its data register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9420 is powereddown. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down.

Data Registers

The potentiometer has four 6-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the WCR. It should be noted all operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms.

If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data.

The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count.

Array Description

The X9420 is comprised of one resistor array containing 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (V

and VL/RL inputs).

H/RH

At both ends of the array and between each resistor segment is a CMOS switch connected to the wiper (V

) output. Within the individual array only one

W/RW

switch may be turned on at a time.

These switches are controlled by a Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. The block diagram of the potentiometer is shown in Figure 1.

Table 1. Data Registers, (6-bit), Nonvolatile

0 0 D5 D4 D3 D2 D1 D0

(MSB) (LSB)

There are four 6-bit Data Registers associated with the potentiometer.

– {D5~D0}: These bits are for general purpose Non-

volatile data storage or for storage of up to four different wiper values.

Table 2. Wiper Counter Register, (6-bit), Volatile

0 0 WP5 WP4 WP3 WP2 WP1 WP0

(MSB) (LSB)

– {WP5~WP0}: These bits specify the wiper position

of the potentiometer.

FN8195.1

April 26, 2006

Figure 1. Detailed Potentiometer Block Diagram

X9420

Serial Data Path

From Interface Circuitry

8 6

IF WCR = 00[H] THEN VW = V IF WCR = 3F[H] THEN VW = V

L H

Write in Process

The contents of the Data Registers are saved to nonvolatile memory when the CS

pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a Write In Process bit (WIP). The WIP bit is read with a Read Status command.

INSTRUCTIONS

UP/DN

Modified SCK

Figure 2. Address/Identification Byte Format

Serial Bus Input

Parallel Bus Input

Wiper Counter Register

(WCR)

INC/DEC

Logic

UP/DN

CLK

Device Type

Identifier

100

C O U N T E R

D E C O D E

11 0A0

Device Address

Address/Identification (ID) Byte

The first byte sent to the X9420 from the host, following a CS

going HIGH to LOW, is called the Address or Identification byte. The most significant four bits of the slave address are a device type identifier, for the X9420 this is fixed as 0101[B] (refer to Figure 2).

The least significant bit in the ID byte selects one of two devices on the bus. The physical device address is defined by the state of the A

input pin. The X9420

compares the serial data stream with the address input state; a successful compare of the address bit is required for the X9420 to successfully continue the command sequence. The A driven by a CMOS input signal or tied to V

input can be actively

or VSS.

The remaining three bits in the ID byte must be set to 110.

Instruction Byte

The next byte sent to the X9420 contains the instruction and register pointer information. The four most significant bits are the instruction. The next two bits point to one of four data registers. The format is shown below in Figure 3.

Figure 3. Instruction Byte Format

Select

I1I2I3 I0 R1 R0 0 0

Instructions

FN8195.1

April 26, 2006

X9420

The four high order bits of the instruction byte specify the operation. The next two bits (R

and R0) select

one of the four registers that is to be acted upon when a register oriented instruction is issued. The last two bits are defined as 0.

Two of the eight instructions are two bytes in length and end with the transmission of the instruction byte. These instructions are:

– XFR Data Register to Wiper Counter Register

— This instruction transfers the contents of one specified Data Register to the Wiper Counter Register.

– XFR Wiper Counter Register to Data Register

—This instruction transfers the contents of the Wiper Counter Register to the specified associated Data Register.

The basic sequence of the two byte instructions is illustrated in Figure 4. These two-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by t

. A transfer from

WRL

the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of t

to complete. The transfer can occur between the

potentiometer and one of its associated registers.

Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9420; either between the host and one of the Data Registers or directly between the host and the WCR. These instructions are:

– Read Wiper Counter Register

—read the current

wiper position of the pot,

– Write Wiper Counter Register

—change current

wiper position of the pot,

– Read Data Register

—read the contents of the

selected data register;

– Write Data Register

—write a new value to the

selected data register.

– Read Status

—This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress.

The sequence of these operations is shown in Figure 5 and Figure 6.

The final command is Increment/Decrement. It is different from the other commands, because it’s length is indeterminate. Once the command is issued, the master can clock the wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse (t

) while SI is HIGH, the selected wiper will move

HIGH

one resistor segment towards the V

H/RH

terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the V

terminal. A detailed illustration of

L/RL

the sequence and timing for this operation are shown in Figure 7 and Figure 8.

Figure 4. Two-Byte Instruction Sequence

SCK

0101110A0I3 I2 I1 I0 R1 R0 0 0

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