intersil X9420 DATA SHEET

查询X9420WV14供应商

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Data Sheet FN8195.1April 26, 2006

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Single Digitally Controlled (XDCP™)
Potentiometer

FEATURES

• Solid-State Potentiometer

• SPI Serial Interface

• Register Oriented Format
—Direct read/write/transfer wiper positions
—Store as many as four positions per

potentiometer

• Power Supplies
—V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V

• Low Power CMOS
—Standby current < 1µA

• High Reliability
—Endurance–100,000 data changes per bit per

—Register data retention–100 years

• 8-bytes of Nonvolatile EEPROM Memory

•10kΩ or 2.5kΩ Resistor Arrays

• Resolution: 64 Taps Each Pot

• 14 Ld TSSOP and 16 Ld SOIC Packages

• Pb-Free Plus Anneal Available (RoHS Compliant)

= 2.7V to 5.5V

CC

register

X9420

Low Noise/Low Power/SPI Bus

DESCRIPTION

The X9420 integrates a single digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.

The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

BLOCK DIAGRAM

HOLD

CS

SCK

S0

SI

A0

Interface

and

Control

Circuitry

Data

8

R0 R1

R2 R3

Wiper
Counter
Register

(WCR)

VH/R

VL/R

VW/R

H

L

W

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9420

Ordering Information

POTENTIOMETER

PART

PART NUMBER

X9420WS16* X9420WS 5 ±10% 10 0 to +70 16 Ld SOIC (300 mil) M16.3
X9420WS16Z* (Note) X9420WS Z 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420WS16I* X9420WS I -40 to +85 16 Ld SOIC (300 mil) M16.3
X9420WS16IZ* (Note) X9420WS ZI -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420WV14* X9420 W 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9420WV14Z* (Note) X9420 WZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420WV14I* X9420 WI -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9420WV14IZ* (Note) X9420 WZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420YS16* X9420YS 2.5 0 to +70 16 Ld SOIC (300 mil) M16.3
X9420YS16Z* (Note) X9420YS Z 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420YS16I* X9420YS I -40 to +85 16 Ld SOIC (300 mil) M16.3
X9420YS16IZ* (Note) X9420YS ZI -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420YV14* X9420 Y 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9420YV14Z* (Note) X9420 YZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420YV14I* X9420 YI -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9420YV14IZ* (Note) X9420 YZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420WS16-2.7* X9420WS F 2.7 to 5.5 10 0 to +70 16 Ld SOIC (300 mil) M16.3
X9420WS16Z-2.7* (Note) X9420WS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420WS16I-2.7* X9420WS G -40 to +85 16 Ld SOIC (300 mil) M16.3
X9420WS16IZ-2.7*

(Note)
X9420WV14-2.7* X9420 WF 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9420WV14Z-2.7* (Note) X9420 WZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420WV14I-2.7* X9420 WG -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9420WV14IZ-2.7*

(Note)
X9420YS16-2.7* X9420YS F 2.7 to 5.5 2.5 0 to +70 16 Ld SOIC (300 mil) M16.3
X9420YS16Z-2.7* (Note) X9420YS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420YS16I-2.7* X9420YS G -40 to +85 16 Ld SOIC (300 mil) M16.3
X9420YS16IZ-2.7* (Note) X9420YS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420YV14-2.7* X9420 YF 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9420YV14Z-2.7* (Note) X9420 YZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420YV14I-2.7* X9420 YG -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9420YV14IZ-2.7* (Note) X9420 YZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING VCC LIMITS (V)

X9420WS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3

X9420 WZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173

ORGANIZATION

(k)

TEMP. RANGE

(°C) PACKAGE

PKG.

DWG. #

2

FN8195.1

April 26, 2006

X9420

PIN DESCRIPTIONS

Host Interface Pins

Serial Output (SO)

SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.

Serial Input

SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the potentiometer
and pot register are input on this pin. Data is latched
by the rising edge of the serial clock.

Serial Clock (SCK)

The SCK input is used to clock data into and out of the
X9420.

Chip Select (CS

When CS

is HIGH, the X9420 is deselected and the

)

SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS

LOW enables the X9420, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS

is

required prior to the start of any operation.

Hold (HOLD

HOLD

)

is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD

may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD

must
be brought LOW while SCK is LOW. To resume
communication, HOLD

is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.

Device Address (A

)

0

The address inputs is used to set the least significant
bit of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9420. A maximum of 2 devices may occupy the
SPI serial bus.

Potentiometer Pins

V

, VL/R

H/RH

L

The VH/RH and VL/RL input are equivalent to the
terminal connections on either end of a mechanical
potentiometer.

V

W/RW

The wiper output is equivalent to the wiper output of a
mechanical potentiometer.

Hardware Write Protect Input (WP

The WP

pin when LOW prevents nonvolatile writes to

)

the Data Registers. Writing to the Wiper Counter
Register is not restricted.

Analog Supplies (V+, V-)

The analog supplies V+, V- are the supply voltages for
the XDCP analog section.

System/Digital Supply (V

V

is the supply voltage for the system/digital

CC

section. V

is the system ground.

SS

CC

)

PIN CONFIGURATION

DIP/SOIC

V

RL/V

RH/V

RW/V

RL/V

RH/V

RW/V

WP

V

V

CC

CS

W

SI

SS

CS

SI

WP

SS

1

2

3

L

4

H

5

6

7

8

TSSOP

1

2

L

3

H

4

W

5

6

7

X9420

X9420

16

15

14

13

12

11

10

14

13

12

11

10

V+

NC

A0

SO

HOLD

SCK

NC

V-

9

V

CC

V+

A0

SO

HOLD

SCK

9

V-

8

3

FN8195.1

April 26, 2006

X9420

PIN NAMES

Symbol Description

SCK Serial Clock

SI, SO Serial Data

A0 Device Address

V

,

H/RH

V

L/RL

V

W/RW

WP Hardware Write Protection

HOLD Serial Communication Pause

V+,V- Analog Supplies

V

CC

V

SS

NC No Connection

Potentiometer Pins (terminal equivalent)

Potentiometer Pins (wiper equivalent)

System Supply Voltage

System Ground

PRINCIPLES OF OPERATION

The X9420 is a highly integrated microcircuit
incorporating a resistor array and associated registers
and counter and the serial interface logic providing
direct communication between the host and the XDCP
potentiometer.

Serial Interface

The X9420 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS
LOW and the HOLD

and WP pins must be HIGH

must be

during the entire operation.

Wiper Counter Register (WCR)

The X9420 contains a Wiper Counter Register. The
WCR can be envisioned as a 6-bit parallel and serial
load counter with its outputs decoded to select one of
sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9420 is powered­down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.

Data Registers

The potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the WCR. It should be noted all
operations changing data in one of the Data Registers is
a nonvolatile operation and will take a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.

The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.

Array Description

The X9420 is comprised of one resistor array
containing 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

and VL/RL inputs).

H/RH

At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(V

) output. Within the individual array only one

W/RW

switch may be turned on at a time.

These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded to
select, and enable, one of sixty-four switches. The block
diagram of the potentiometer is shown in Figure 1.

4

Register Descriptions

Table 1. Data Registers, (6-bit), Nonvolatile

0 0 D5 D4 D3 D2 D1 D0

(MSB) (LSB)

There are four 6-bit Data Registers associated with the
potentiometer.

– {D5~D0}: These bits are for general purpose Non-

volatile data storage or for storage of up to four dif­ferent wiper values.

Table 2. Wiper Counter Register, (6-bit), Volatile

0 0 WP5 WP4 WP3 WP2 WP1 WP0

(MSB) (LSB)

– {WP5~WP0}: These bits specify the wiper position

of the potentiometer.

FN8195.1

April 26, 2006

Figure 1. Detailed Potentiometer Block Diagram

X9420

Serial Data Path

From Interface
Circuitry

Register 0 Register 1

8 6

REGISTER 2 REGISTER 3

IF WCR = 00[H] THEN VW = V
IF WCR = 3F[H] THEN VW = V

L
H

Write in Process

The contents of the Data Registers are saved to
nonvolatile memory when the CS

pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a Write In Process bit (WIP). The
WIP bit is read with a Read Status command.

INSTRUCTIONS

UP/DN

Modified SCK

Figure 2. Address/Identification Byte Format

Serial
Bus
Input

Parallel
Bus
Input

Wiper
Counter
Register

(WCR)

INC/DEC

Logic

UP/DN

CLK

Device Type

Identifier

100

C
O
U
N
T
E
R

D
E
C
O
D
E

1

11 0A0

V

H

V

L

V

W

Device Address

Address/Identification (ID) Byte

The first byte sent to the X9420 from the host,
following a CS

going HIGH to LOW, is called the
Address or Identification byte. The most significant
four bits of the slave address are a device type
identifier, for the X9420 this is fixed as 0101[B] (refer
to Figure 2).

The least significant bit in the ID byte selects one of
two devices on the bus. The physical device address
is defined by the state of the A

input pin. The X9420

0

compares the serial data stream with the address
input state; a successful compare of the address bit is
required for the X9420 to successfully continue the
command sequence. The A
driven by a CMOS input signal or tied to V

input can be actively

0

or VSS.

CC

The remaining three bits in the ID byte must be set to 110.

5

Instruction Byte

The next byte sent to the X9420 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next two
bits point to one of four data registers. The format is
shown below in Figure 3.

Figure 3. Instruction Byte Format

Register

Select

I1I2I3 I0 R1 R0 0 0

Instructions

FN8195.1

April 26, 2006

X9420

The four high order bits of the instruction byte specify
the operation. The next two bits (R

and R0) select

1

one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits are defined as 0.

Two of the eight instructions are two bytes in length
and end with the transmission of the instruction byte.
These instructions are:

– XFR Data Register to Wiper Counter Register

—
This instruction transfers the contents of one speci­fied Data Register to the Wiper Counter Register.

– XFR Wiper Counter Register to Data Register

—This
instruction transfers the contents of the Wiper
Counter Register to the specified associated Data
Register.

The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by t

. A transfer from

WRL

the WCR (current wiper position), to a Data Register is
a write to nonvolatile memory and takes a minimum of
t

to complete. The transfer can occur between the

WR

potentiometer and one of its associated registers.

Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9420; either between the host and
one of the Data Registers or directly between the host
and the WCR. These instructions are:

– Read Wiper Counter Register

—read the current

wiper position of the pot,

– Write Wiper Counter Register

—change current

wiper position of the pot,

– Read Data Register

—read the contents of the

selected data register;

– Write Data Register

—write a new value to the

selected data register.

– Read Status

—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.

The sequence of these operations is shown in Figure
5 and Figure 6.

The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the wiper up and/or down in one
resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
(t

) while SI is HIGH, the selected wiper will move

HIGH

one resistor segment towards the V

H/RH

terminal.
Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the V

terminal. A detailed illustration of

L/RL

the sequence and timing for this operation are shown
in Figure 7 and Figure 8.

Figure 4. Two-Byte Instruction Sequence

CS

SCK

SI

0101110A0I3 I2 I1 I0 R1 R0 0 0

6

FN8195.1

April 26, 2006

Figure 5. Three-Byte Instruction Sequence (Write)

CS

SCL

SI

X9420

0 101 0A0 I3 I2 I1 I0 R1 R0 0 0

11

Figure 6. Three-Byte Instruction Sequence (Read)

CS

SCL

SI

0 101 0A0 I3 I2 I1 I0 R1 R0 0 0

S0

11

Figure 7. Increment/Decrement Instruction Sequence

CS

SCK

0 0 D5 D4 D3 D2 D1 D0

Don’t Care

0 0 D5 D4 D3 D2 D1 D0

SI

0101110A0 I3 I2 I1 I0 0 0 0

Figure 8. Increment/Decrement Timing Limits

SCK

SI

V

W

INC/DEC CMD Issued

7

Voltage Out

I

0

t

WRID

I

N

N

C

C

1

2

D

I

E

N

C

C

1

n

D
E

C

n

FN8195.1

April 26, 2006

X9420

Table 3. Instruction Set

Instruction Set

Instruction

Read Wiper Counter

3I2I1I0R1R0

1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register

Register
Write Wiper Counter

1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register

Register
Read Data Register 1 0 1 1 R

1R0

Write Data Register 1 1 0 0 R1R

XFR Data Register to

1101R1R

Wiper Counter

0 0 Read the contents of the Data Register pointed to by

- R

R

1

0

0 0 Write new value to the Data Register pointed to by

0

0 0 Transfer the contents of the Data Register pointed to

0

- R

R

1

0

- R0 to the Wiper Counter Register

by R

1

Register
XFR Wiper Counter

Register to Data

1110R

1R0

0 0 Transfer the contents of the Wiper Counter

Register to the Data Register pointed to by R

Register
Increment/Decrement

Wiper Counter

0 0 1 0 0 0 0 0 Enable Increment/decrement of the Wiper Counter

Register

Register
Read Status (WIP bit) 0 1 0 1 0 0 0 1 Read the status of the internal write cycle, by check-

ing the WIP bit.

OperationI

- R

1

0

8

FN8195.1

April 26, 2006

X9420

Instruction Format

Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.

(2) WPx refers to wiper position data in the Wiper Counter Register

“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).

(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).

Read Wiper Counter Register (WCR)

CS

device type

identifier

device

addresses

instruction

opcode

Falling

Edge

0101110

A

1001000000WP

0

Write Wiper Counter Register (WCR)

CS

device type

identifier

device

addresses

instruction

opcode

Falling

Edge

0101110

A

1010000000WP

0

Read Data Register (DR)

Read the contents of the Register pointed to by R1 - R0.

CS

device type

identifier

device

addresses

instruction

opcode

register

addresses

Falling

Edge

0101110

A

1011

0

R1R

0

Write Data Register (DR)

Write a new value to the Register pointed to by R1 - R0.

wiper position

(sent by X9420 on SO)

(sent by Host on SI)

(sent by X9420 on SO)

0000WP

W

W

P

P

5

4

3

Data Byte

W

W

P

P

5

4

3

Data Byte

W

W

P

P

5

4

3

W

W

W

CS

Rising

W

W

P

P

2

1

Edge

P
0

CS

Rising

W

W

P

P

2

1

Edge

P
0

CS

Rising

W

W

P

P

2

1

Edge

P
0

CS

device type

identifier

device

addresses

instruction

opcode

register

addresses

Data Byte

(sent by host on SI)

Falling

Edge

0101110

A

1100

0

R1R

0

0000WP

5

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Transfer the contents of the Register pointed to by R1 - R0 to the WCR.

CS

Falling

Edge

device type

identifier

0101110

device

addresses

9

instruction

opcode

A

1101

0

register

addresses

R1R

00

0

CS

Rising

Edge

W
P

CS

W

P
1

W
P

0

Rising

Edge

W

W

P

P

4

3

2

HIGH-VOLTAGE

WRITE CYCLE

FN8195.1

April 26, 2006

X9420

Transfer Wiper Counter Register (WCR) to Data Register (DR)

CS

Falling

Edge

device type

identifier

0101110

device

addresses

instruction

opcode

A

1110

0

register

addresses

R1R

00

0

Increment/Decrement Wiper Counter Register (WCR)

CS

Falling

Edge

device type

identifier

0101110

device

addresses

instruction

opcode

A

00100000I/DI/D. . . . I/DI/D

0

Read Status

CS

device type

identifier

device

addresses

instruction

opcode

Falling

Edge

0101110

A

010100010000000WI

0

CS

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

increment/decrement

(sent by master on SDA)

Data Byte

(sent by X9420 on SO)

P

CS

Rising

Edge

CS

Rising

Edge

10

FN8195.1

April 26, 2006

X9420

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .....................-65C to +135C

Storage temperature ..........................-65C to +150C

Voltage on SCK, SCL or any

address input with respect to V
Voltage on V+ (referenced to V
Voltage on V- (referenced to V

........... -1V to +7V

SS

)........................ 10V

SS

)........................-10V

SS

(V+) - (V-) .............................................................. 12V

Any V

, VL/RL, VW/RW ........................... V- to V+

H/RH

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device

reliability.

Lead temperature (soldering, 10s) .....................300C

I

(10s) .............................................................. ±6mA

W

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C+70°C

Industrial -40°C+85°C

Device Supply Voltage (VCC) Limits

X9420 5V ± 10%

X9420-2.7 2.7V to 5.5V

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Limits

Symbol Parameter

R

TOTAL

End to End Resistance ±20 %

Test ConditionsMin. Typ. Max. Units

Power Rating 50 mW 25C, each pot

I

W

R

W

Wiper Current ±3 mA
Wiper Resistance 150 250 Ω Wiper Current = ± 1mA,

V+/V- = ±3V

40 100 Ω Wiper Current = ± 1mA,

V+/V- = ±5V

Vv+ Voltage on V+ Pin X9420 +4.5 +5.5 V

X9420-2.7 +2.7 +5.5

Vv- Voltage on V- Pin X9420 -5.5 -4.5 V

X9420-2.7 -5.5 -2.7

V

TERM

Voltage on any VH/RH, VL/RL, VW/R

V- V+ V

W

Noise -140 dBV Ref: 1kHz
Resolution
Absolute Linearity
Relative Linearity
Temperature Coefficient of R

(4)

(2)

(1)

TOTAL

1.6 % See Note 5
±1 MI

±0.2 MI

(3)

(3)

V

w(n)(actual)

V

w(n + 1)

- [V

±300 ppm/C See Note 5

Ratiometric Temperature Coefficient ±20 ppm/C See Note 5

C

H/CL/CW

I

AL

Potentiometer Capacitances 10/10/25 pF See Circuit #3
Rh, RI, Rw leakage current 0.1 10 µA Vin = V- to V+. Device is in

stand-by mode.

- V

w(n)(expected)

w(n) + MI

]

Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as

a potentiometer.

(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-

ometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (V
(4) Typical = Individual array resolution.

- VL)/63, single pot.

H

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X9420

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter

I

CC1

I

CC2

VCC Supply Current (Active) 400 µA f

VCC Supply Current
(Non-volatile Write)

I

SB

I

LI

I

LO

V

IH

V

IL

V

OL

VCC Current (Standby) 1 μA SCK = SI = VSS, Addr. = V

Input Leakage Current 10 μAVIN = VSS to V

Output Leakage Current 10 μAV

Input HIGH Voltage VCC x 0.7 VCC + 0.5 V

Input LOW Voltage -0.5 VCC x 0.1 V

Output LOW Voltage 0.4 V IOL = 3mA

ENDURANCE AND DATA RETENTION

Parameter Min. Units

Minimum Endurance 100,000 Data Changes per Bit per Register

Data Retention 100 Years

1mAf

Test ConditionsMin. Typ. Max. Units

= 2MHz, SO = Open,

SCK

Other Inputs = V

= 2MHz, SO = Open,

SCK

Other Inputs = V

CC

= VSS to V

OUT

SS

SS

SS

CC

CAPACITANCE

Symbol Test Max. Units Test Conditions

(5)

C

OUT

C

IN

(5)

Output Capacitance (SO) 8 pF V

OUT

Input Capacitance (A0, SI, and SCK) 6 pF VIN = 0V

POWER-UP TIMING

Symbol Parameter Max. Max. Units

(6)

t

PUR

t

PUW

t

RVCC

(6)

Power-up to Initiation of Read Operation 1 1 ms

Power-up to Initiation of Write Operation 5 5 ms

VCC Power-up Ramp 0.2 50 V/msec

POWER-UP REQUIREMENTS (Power-up sequencing can affect correct recall of the wiper registers)

The preferred power-on sequence is as follows: First V
and R

. Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The VCC ramp rate

W

specification should be met, and any glitches or slope changes in the V
If V

powers down, it should be held below 0.1V for more than 1 second before powering up again in order for

CC

proper wiper register recall. Also, V
be complete until V

Notes: (5) This parameter is periodically sampled and not 100% tested.

(6) t

and t

PUR

can be issued. These parameters are periodically sampled and not 100% tested.

, V+ and V- reach their final value.

CC

are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction

PUW

should not reverse polarity by more than 0.5V. Recall of wiper position will not

CC

, then V+ and V-, and then the potentiometer pins, RH, RL,

CC

line should be held to <100mV if possible.

CC

= 0V

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X9420

A.C. TEST CONDITIONS EQUIVALENT A.C. LOAD CIRCUIT

I

nput pulse levels VCC x 0.1 to VCC x 0.9

Input rise and fall times 10ns

Input and output timing level V

CC

x 0.5

SDA Output

AC TIMING

Symbol Parameter Min. Max. Units

f

SCK

t

CYC

t

WH

t

WL

t

LEAD

t

LAG

t

SU

t

H

t

RI

t

FI

t

DIS

t

V

t

HO

t

RO

t

FO

t

HOLD

t

HSU

t

HH

t

HZ

t

LZ

T

I

t

CS

t

WPASU

t

WPAH

SSI/SPI Clock Frequency 2.0 MHz

SSI/SPI Clock Cycle Time 500 ns

SSI/SPI Clock High Time 200 ns

SSI/SPI Clock Low Time 200 ns

Lead Time 250 ns

Lag Time 250 ns

SI, SCK, HOLD and CS Input Setup Time 50 ns

SI, SCK, HOLD and CS Input Hold Time 50 ns

SI, SCK, HOLD and CS Input Rise Time 2 µs

SI, SCK, HOLD and CS Input Fall Time 2 µs

SO Output Disable Time 0 500 ns

SO Output Valid Time 100 ns

SO Output Hold Time 0 ns

SO Output Rise Time 50 ns

SO Output Fall Time 50 ns

HOLD Time 400 ns

HOLD Setup Time 100 ns

HOLD Hold Time 100 ns

HOLD Low to Output in High Z 100 ns

HOLD High to Output in Low Z 100 ns

Noise Suppression Time Constant at SI, SCK, HOLD and CS inputs 20 ns

CS Deselect Time 2 µs

WP, A0 and A1 Setup Time 0 ns

WP, A0 and A1 Hold Time 0 ns

5V

1533Ω

100pF

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April 26, 2006

X9420

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Typ. Max. Units

t

WR

XDCP TIMING

Symbol Parameter Min. Max. Units

t

WRPO

t

WRL

t

WRID

Wiper Response Time After The Third (Last) Power Supply Is Stable 10 µs

Wiper Response Time After Instruction Issued (All Load Instructions) 10 µs

Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement
Instruction)

SYMBOL TABLE

WAVEFORM INPUTS OUTPUTS

High-voltage Write Cycle Time (Store Instructions) 5 10 ms

450 ns

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

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TIMING DIAGRAMS

Input Timing

CS

t

LEAD

X9420

t

CYC

t

CS

t

LAG

SCK

SI

SO

Output Timing

CS

SCK

SO

SI

Hold Timing

t

SU

MSB LSB

High Impedance

ADDR

t

H

t

WL

t

WH

...

t

FI

t

RI

...

...

t

V

MSB LSB

t

HO

...

t

DIS

CS

SCK

SO

HOLD

t

HSU

t

HH

...

t

RO

SI

15

t

FO

t

t

HOLD

HZ

t

LZ

FN8195.1

April 26, 2006

XDCP Timing (for All Load Instructions)

CS

X9420

SCK

MSB LSB

V

SO

SI

W

High Impedance

XDCP Timing (for Increment/Decrement Instruction)

CS

SCK

V

W

ADDR

SI

Inc/Dec

Inc/Dec

...

t

WRID

...

...

...

...

t

WRL

High Impedance

SO

Write Protect and Device Address Pins Timing

CS

t

WP

A0

A1

WPASU

(Any Instruction)

t

WPAH

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X9420

APPLICATIONS INFORMATION

Electronic potentiometers provide three powerful application advantages: (1) the variability and reliability of a solid­state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory
used for the storage of multiple potentiometer settings or data.

Basic Configurations of Electronic Potentiometers

V

V

R

V

H

V

W

V

L

R

I

Basic Circuits

R

+V

1

V

W

Voltage Regulator

Three terminal Potentiometer;

Variable voltage divider

+5V

V

W

OP-07

+

–

V

OUT

-5V

Two terminal Variable Resistor;

Variable current

= V

Cascading TechniquesBuffered Reference Voltage

+V +V

W

X

V

W

Noninverting Amplifier

+5V

V

S

+

–

-5V

+V

R

1

V

W

(a) (b)

VO = (1+R2/R1)V

Offset Voltage Adjustment Comparator with Hysterisis

LM308A

R

2

S

V

O

IN

317

I

adj

R

2

VO (REG) = 1.25V (1+R2/R1)+I

17

R

1

adj R2

R

VO (REG)V

V

S

1

100kΩ

R

2

V

S

–

V

+

O

–

V

+

TL072

10kΩ

10kΩ10kΩ

O

}

}

R

R

2

1

VUL = {R1/CR1+R2} VO(max)
V

= {R1/CR1+R2} VO(min)

LL

-12V+12V

FN8195.1

April 26, 2006

X9420

Thin Shrink Small Outline Plastic Packages (TSSOP)

N

INDEX
AREA

123

-A-

0.05(0.002)

D

SEATING PLANE

e

b

0.10(0.004) C AM BS

M

E1

-B-

A

-C-

0.25(0.010) BM M

E

α

A1

0.10(0.004)

GAUGE
PLANE

0.25

0.010

A2

L

c

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen­sion at maximum material condition. Minimum space between protru­sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)

M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.041 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.195 0.199 4.95 5.05 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N14 147

o

α

0

o

8

o

0

o

8

NOTESMIN MAX MIN MAX

-

Rev. 2 4/06

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Small Outline Plastic Packages (SOIC)

X9420

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.

A1

C

0.10(0.004)

M16.3 (JEDEC MS-013-AA ISSUE C)

16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.3977 0.4133 10.10 10.50 3

E 0.2914 0.2992 7.40 7.60 4

e 0.050 BSC 1.27 BSC ­H 0.394 0.419 10.00 10.65 -

h 0.010 0.029 0.25 0.75 5

L 0.016 0.050 0.40 1.27 6
N16 167

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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