intersil X9410 DATA SHEET

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X9410

Low Noise/Low Power/SPI Bus

Data Sheet October 12, 2006

Dual Digitally Controlled Potentiometer (XDCP™)

FEATURES

• Two potentiometers per package

• SPI serial interface

• Register oriented format

- Direct read/write/transfer wiper positions

- Store as many as four positions per potentiometer

• Power supplies = 2.7V to 5.5V

-V

- V+ = 2.7V to 5.5V

- V- = -2.7V to -5.5V

• Low power CMOS

- Standby current < 1µA

- High reliability

- Endurance - 100,000 data changes per bit per register

- Register data retention - 100 years

• 8-bytes of nonvolatile EEPROM memory

•10kΩ resistor arrays

• Resolution: 64 taps each pot

• 24 Ld SOIC, 24 Ld TSSOP, and 24 Ld plastic DIP packages

• Pb-free plus anneal available (RoHS compliant)

FN8193.2

DESCRIPTION

The X9410 integrates two digitally controlled potentiometers (XDCPs) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI serial bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power-up recalls the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

BLOCK DIAGRAM

HOLD

SCK

A0 A1

V+

V-

Interface

and

Control

Circuitry

R0 R1

R2 R3

Data

R0 R1

R2 R3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Pot 0

Wiper Counter Register

(WCR)

Pot 1

Wiper

Counter Register

(WCR)

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Resistor

Array

Pot1

VH0/R

VL0/R

VW0/R

VW1/R

H1/RH1

VL1/R

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Ordering Information

POTENTIOMETER

LIMITS

PART NUMBER PART MARKING

X9410YS24I X9410YS I 5 ±10% 2.5 -40 to 85 24 Ld SOIC (300 mil) M24.3 X9410YS24IZ (Note) X9410YS ZI -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027 X9410WP24I X9410WP I 10 -40 to 85 24 Ld PDIP E24.6 X9410WS24I* X9410WS I -40 to 85 24 Ld SOIC (300 mil) M24.3 X9410WS24IZ* (Note) X9410WS ZI -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027 X9410WV24I* X9410WV I -40 to 85 24 Ld TSSOP (4.4mm) MDP0044 X9410WV24IZ* (Note) X9410WV ZI -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9410YS24I-2.7 X9410YS G 2.7 to 5.5 2.5 -40 to 85 24 Ld SOIC (300 mil) M24.3 X9410YS24IZ-2.7 (Note) X9410YS ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027 X9410WP24I-2.7 X9410WP G 10 -40 to 85 24 Ld PDIP E24.6 X9410WS24I-2.7* X9410WS G -40 to 85 24 Ld SOIC (300 mil) M24.3 X9410WS24IZ-2.7* (Note) X9410WS ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027 X9410WV24-2.7* X9410WV F 0 to 70 24 Ld TSSOP (4.4mm) MDP0044 X9410WV24Z-2.7* (Note) X9410WV ZF 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9410WV24I-2.7* X9410WV G -40 to 85 24 Ld TSSOP (4.4mm) MDP0044 X9410WV24IZ-2.7* (Note) X9410WV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

(V)

ORGANIZATION

(kΩ)

TEMP RANGE

(°C) PACKAGE PKG. DWG. #

PIN DESCRIPTIONS

Host Interface Pins

Serial Output (SO)

SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.

Serial Input

SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock.

Serial Clock (SCK)

The SCK input is used to clock data into and out of the X9410.

Chip Select (CS

When CS

is HIGH, the X9410 is deselected and the

)

SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS

LOW enables the X9410, placing it

in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS

required prior to the start of any operation.

Hold (HOLD

HOLD

)

is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD

may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD

must be brought LOW while SCK is LOW. To resume communication, HOLD

is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times.

Device Address (A

- A1)

The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9410. A maximum of 4 devices may occupy the SPI serial bus.

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Potentiometer Pins

H/RH

The V

(VH0/R

H/RH

- VH1/RH1), VL/RL (VL0/R

- VL1/RL1)

and VL/RL inputs are equivalent to the terminal

connections on either end of a mechanical potentiometer.

W/RW

(VW0/R

- VW1/RW1)

The wiper outputs are equivalent to the wiper output of a mechanical potentiometer.

Hardware Write Protect Input (WP

The WP

pin when LOW prevents nonvolatile writes to

)

the Data Registers.

Analog Supplies (V+, V-)

The analog supplies V+, V- are the supply voltages for the XDCP analog section.

PIN CONFIGURATION

DIP/SOIC

VL0/R

VH0/R

VW0/R

VL1/R

VH1/R

VW1/R

X9410

V+

HOLD

SCK

V-

PIN NAMES

Symbol Description

SCK Serial Clock

, S

- A

H0/RH0

L0/RL0

W0/RW0

- VH1/RH1,

- VL1/R

- VW1/R

Serial Data

Device Address

Potentiometer Pins (terminal equivalent)

Potentiometer Pin (wiper equivalent)

Hardware Write Protection

V+,V- Analog Supplies

System Supply Voltage

System Ground

NC No Connection

DEVICE DESCRIPTION

The X9410 is a highly integrated microcircuit incorporating two resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers.

Serial Interface

The X9410 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS LOW and the HOLD

and WP pins must be HIGH

must be

during the entire operation.

The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count.

Array Description

TSSOP

The X9410 is comprised of two resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (V

At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (V

) output. Within each individual array only one

W/RW

switch may be turned on at a time.

These switches are controlled by a Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches.

VL1/R

VH1/R

W1/RW1

HOLD

SCK

X9410

V-

VW0/R

VH0/R

VL0/R

V+

and VL/RL inputs).

H/RH

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Wiper Counter Register (WCR)

The X9410 contains two Wiper Counter Registers, one for each XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register or Global XFR Data Register instructions (parallel load); it can be modified one step at a time by the Increment/ Decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9410 is powereddown. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down.

Figure 1. Detailed Potentiometer Block Diagram

(One of Two Arrays)

Data Registers

Each potentiometer has four 6-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms.

If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data.

Data Register Detail

(MSB) (LSB)

D5 D4 D3 D2 D1 D0

NV NV NV NV NV NV

Serial Data Path

From Interface

Circuitry

If WCR = 00[H] then VW/RW = VL/R

If WCR = 3F[H] then VW/RW = VH/R

Serial Bus

Input

8 6

UP/DN

Modified SCL

Parallel Bus

Input

Wiper

Counter

(WCR)

INC/DEC

Logic

UP/DN

CLK

C o

u n

e c

o d e

VH/R

VL/R

VW/R

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Write in Process

The contents of the Data Registers are saved to nonvolatile memory when the CS

pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a Write In Process bit (WIP). The WIP bit is read with a Read Status command.

INSTRUCTIONS

Identification (ID) Byte

The first byte sent to the X9410 from the host, following a CS

going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier, for the X9410 this is fixed as 0101[B] (refer to Figure 2).

The two least significant bits in the ID byte select one of four devices on the bus. The physical device address is defined by the state of the A

- A1 input

pins. The X9410 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9410 to successfully continue the command sequence. The A

- A1 inputs

can be actively driven by CMOS input signals or tied to

or VSS.

The remaining two bits in the ID byte must be set to 0.

Figure 2. Identification Byte Format

Device Type

Identifier

100

0 0 A1 A0

Device Address

Instruction Byte

The next byte sent to the X9410 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of the two pots and when applicable they point to one of four associated registers. The format is shown below in Figure 3.

Figure 3. Instruction Byte Format

Select

I1I2I3 I0 R1 R0 0 P0

Instructions

Pot Select

The four high order bits of the instruction byte specify the operation. The next two bits (R

and R0) select one

of the four registers that is to be acted upon when a register oriented instruction is issued. The last bit (P selects which one of the two potentiometers is to be affected by the instruction.

Four of the ten instructions are two bytes in length and end with the transmission of the instruction byte. These instructions are:

– XFR Data Register to Wiper Counter Register

—This transfers the contents of one specified Data Register to the associated Wiper Counter Register.

– XFR Wiper Counter Register to Data Register

—This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register.

– Global XFR Data Register to Counter Register

—This transfers the contents of both specified Data Registers to the associated Wiper Counter Registers.

– Global XFR Wiper Counter Register to Data

The basic sequence of the two byte instructions is illustrated in Figure 4. These two-byte instructions exchange data between the WCR and one of the data registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by t

. A transfer

WRL

from the WCR (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t

to complete. The transfer can occur

between one of the two potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between both potentiometers and one associated register.

)

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Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9410; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are:

– Read Wiper Counter Register

—read the current

wiper position of the selected pot,

– Write Wiper Counter Register

—change current

wiper position of the selected pot,

– Read Data Register

—read the contents of the

selected data register;

– Write Data Register

—write a new value to the

selected data register.

– Read Status

—This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress.

Figure 4. Two-Byte Instruction Sequence

SCK

The sequence of these operations is shown in Figure 5 and Figure 6.

The final command is Increment/Decrement. It is different from the other commands because it’s length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps, thereby providing a fine tuning capability to the host. For each SCK clock pulse

) while SI is HIGH, the selected wiper will move

HIGH

one resistor segment towards the V

H/RH

terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the V

terminal. A detailed illustration of the

L/RL

sequence and timing for this operation are shown in Figure 7 and Figure 8.

010100A1A0I3 I2 I1 I0 R1 R0 0 P0

Figure 5. Three-Byte Instruction Sequence (Write)

SCL

0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 0 P0

Figure 6. Three-Byte Instruction Sequence (Read)

SCL

0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 0 P0

0 0 D5 D4 D3 D2 D1 D0

Don’t Care

0 0 D5 D4 D3 D2 D1 D0

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Figure 7. Increment/Decrement Instruction Sequence

SCK

010100A1A0 I3 I2 I1 I0 0 0 P0

D E C

Figure 8. Increment/Decrement Timing Limits

WRID

SCK

VW/R

INC/DEC CMD Issued

Voltage Out

Table 1. Instruction Set

Instruction Set

Instruction

3I2I1I0

R1R0P1P

OperationI

Read Wiper Counter Register 1 0 01000P0Read the contents of the Wiper Counter

Write Wiper Counter Register1010000P0Write new value to the Wiper Counter Register

pointed to by P

Read Data Register 1 0 1 1 R1R00P0Read the contents of the Data Register pointed

to by P

and R1 - R

Write Data Register 1 1 0 0 R1R00P0Write new value to the Data Register pointed to

and R1 - R

by P

XFR Data Register to Wiper Counter Register

XFR Wiper Counter Register to Data Register

Global XFR Data Register to Wiper Counter Register

1101R1R00P0Transfer the contents of the Data Register

pointed to by R Register pointed to by P

1110R1R00P0Transfer the contents of the Wiper Counter

0001R1R00 0 Transfer the contents of the Data Registers

pointed to by R

- R0 to the Wiper Counter

to the Register

- R

- R0 of both pots to their

respective Wiper Counter Register

Global XFR Wiper Counter Register to Data Register

Increment/Decrement Wiper Counter Register

1000R

1R0

0010000P

0 0 Transfer the contents of all Wiper Counter

Registers to their respective data Registers pointed to by R

Enable Increment/decrement of the Wiper

Counter Register pointed to by P

- R0 of both pots

Read Status (WIP bit) 0 1 010001Read the status of the internal write cycle, by

checking the WIP bit.

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