intersil X9410 DATA SHEET

®

www.BDTIC.com/Intersil

X9410

Low Noise/Low Power/SPI Bus

Data Sheet October 12, 2006

Dual Digitally Controlled Potentiometer
(XDCP™)

FEATURES

• Two potentiometers per package

• SPI serial interface

• Register oriented format

- Direct read/write/transfer wiper positions

- Store as many as four positions per
potentiometer

• Power supplies
= 2.7V to 5.5V

-V

CC

- V+ = 2.7V to 5.5V

- V- = -2.7V to -5.5V

• Low power CMOS

- Standby current < 1µA

- High reliability

- Endurance - 100,000 data changes per bit per
register

- Register data retention - 100 years

• 8-bytes of nonvolatile EEPROM memory

•10kΩ resistor arrays

• Resolution: 64 taps each pot

• 24 Ld SOIC, 24 Ld TSSOP, and 24 Ld plastic DIP
packages

• Pb-free plus anneal available (RoHS compliant)

FN8193.2

DESCRIPTION

The X9410 integrates two digitally controlled
potentiometers (XDCPs) on a monolithic CMOS
integrated circuit.

The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI
serial bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and four nonvolatile Data Registers (DR0:DR3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array through the switches.
Power-up recalls the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

BLOCK DIAGRAM

V

V

HOLD

CS

SCK

SO

A0
A1

WP

1

CC

SS

V+

V-

SI

Interface

and

Control

Circuitry

R0 R1

R2 R3

8

Data

R0 R1

R2 R3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved

Pot 0

Wiper
Counter
Register

(WCR)

Pot 1

Wiper

Counter
Register

(WCR)

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Resistor

Array

Pot1

VH0/R

VL0/R

VW0/R

VW1/R

V

H1/RH1

VL1/R

H0

L0

W0

W1

L1

X9410

www.BDTIC.com/Intersil

Ordering Information

POTENTIOMETER

V

LIMITS

PART NUMBER PART MARKING

X9410YS24I X9410YS I 5 ±10% 2.5 -40 to 85 24 Ld SOIC (300 mil) M24.3
X9410YS24IZ (Note) X9410YS ZI -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027
X9410WP24I X9410WP I 10 -40 to 85 24 Ld PDIP E24.6
X9410WS24I* X9410WS I -40 to 85 24 Ld SOIC (300 mil) M24.3
X9410WS24IZ* (Note) X9410WS ZI -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027
X9410WV24I* X9410WV I -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9410WV24IZ* (Note) X9410WV ZI -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9410YS24I-2.7 X9410YS G 2.7 to 5.5 2.5 -40 to 85 24 Ld SOIC (300 mil) M24.3
X9410YS24IZ-2.7 (Note) X9410YS ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027
X9410WP24I-2.7 X9410WP G 10 -40 to 85 24 Ld PDIP E24.6
X9410WS24I-2.7* X9410WS G -40 to 85 24 Ld SOIC (300 mil) M24.3
X9410WS24IZ-2.7* (Note) X9410WS ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027
X9410WV24-2.7* X9410WV F 0 to 70 24 Ld TSSOP (4.4mm) MDP0044
X9410WV24Z-2.7* (Note) X9410WV ZF 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9410WV24I-2.7* X9410WV G -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9410WV24IZ-2.7* (Note) X9410WV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

CC

(V)

ORGANIZATION

(kΩ)

TEMP RANGE

(°C) PACKAGE PKG. DWG. #

PIN DESCRIPTIONS

Host Interface Pins

Serial Output (SO)

SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.

Serial Input

SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.

Serial Clock (SCK)

The SCK input is used to clock data into and out of the
X9410.

Chip Select (CS

When CS

is HIGH, the X9410 is deselected and the

)

SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS

LOW enables the X9410, placing it

in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS

is

required prior to the start of any operation.

Hold (HOLD

HOLD

)

is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD

may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD

must
be brought LOW while SCK is LOW. To resume
communication, HOLD

is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.

Device Address (A

0

- A1)

The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9410. A maximum of 4 devices may occupy the
SPI serial bus.

2

FN8193.2

October 12, 2006

X9410

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Potentiometer Pins

V

H/RH

The V

(VH0/R

H/RH

- VH1/RH1), VL/RL (VL0/R

H0

- VL1/RL1)

L0

and VL/RL inputs are equivalent to the terminal

connections on either end of a mechanical potentiometer.

V

W/RW

(VW0/R

- VW1/RW1)

W0

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

Hardware Write Protect Input (WP

The WP

pin when LOW prevents nonvolatile writes to

)

the Data Registers.

Analog Supplies (V+, V-)

The analog supplies V+, V- are the supply voltages for
the XDCP analog section.

PIN CONFIGURATION

DIP/SOIC

VL0/R

VH0/R

VW0/R

VL1/R

VH1/R

VW1/R

V

WP

V

CC

L0

H0

W0

CS

SI

A

L1

H1

W1

SS

1

2

3

4

5

6

X9410

7

8

1

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

V+

NC

NC

NC

A

0

SO

HOLD

SCK

NC

NC

NC

V-

PIN NAMES

Symbol Description

SCK Serial Clock

S

, S

I

- A

A

0

V

H0/RH0

V

L0/RL0

V

W0/RW0

O

1

- VH1/RH1,

- VL1/R

- VW1/R

L1

W1

Serial Data

Device Address

Potentiometer Pins
(terminal equivalent)

Potentiometer Pin
(wiper equivalent)

WP

Hardware Write Protection

V+,V- Analog Supplies

V

CC

V

SS

System Supply Voltage

System Ground

NC No Connection

DEVICE DESCRIPTION

The X9410 is a highly integrated microcircuit
incorporating two resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.

Serial Interface

The X9410 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS
LOW and the HOLD

and WP pins must be HIGH

must be

during the entire operation.

The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.

Array Description

TSSOP

The X9410 is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V

) output. Within each individual array only one

W/RW

switch may be turned on at a time.

These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.

VL1/R

VH1/R

V

W1/RW1

HOLD

A

H1

V

SS

NC

NC

NC

SCK

SI

L1

1

2

1

3

4

5

6

X9410

7

8

9

10

V-

11

12

15

24

23

22

21

20

19

18

17

16

14

13

WP

CS

VW0/R

VH0/R

VL0/R

V

CC

NC

NC

NC

V+

A

0

SO

W0

H0

L0

3

and VL/RL inputs).

H/RH

FN8193.2

October 12, 2006

X9410

www.BDTIC.com/Intersil

Wiper Counter Register (WCR)

The X9410 contains two Wiper Counter Registers, one
for each XDCP potentiometer. The WCR is equivalent
to a serial-in, parallel-out register/counter with its
outputs decoded to select one of sixty-four switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by the
host via the Write Wiper Counter Register instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated Data Registers
via the XFR Data Register or Global XFR Data Register
instructions (parallel load); it can be modified one step
at a time by the Increment/ Decrement instruction.
Finally, it is loaded with the contents of its Data Register
zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9410 is powered­down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.

Figure 1. Detailed Potentiometer Block Diagram

(One of Two Arrays)

Data Registers

Each potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.

Data Register Detail

(MSB) (LSB)

D5 D4 D3 D2 D1 D0

NV NV NV NV NV NV

Serial Data Path

From Interface

Circuitry

Register 0 Register 1

Register 2 Register 3

If WCR = 00[H] then VW/RW = VL/R

If WCR = 3F[H] then VW/RW = VH/R

Serial
Bus

Input

8 6

L

H

UP/DN

Modified SCL

Parallel
Bus

Input

Wiper

Counter

Register

(WCR)

INC/DEC

Logic

UP/DN

CLK

C
o

u
n

t

e

r

D

e
c

o
d
e

VH/R

VL/R

VW/R

H

L

W

4

FN8193.2

October 12, 2006

X9410

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Write in Process

The contents of the Data Registers are saved to
nonvolatile memory when the CS

pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a Write In Process bit
(WIP). The WIP bit is read with a Read Status
command.

INSTRUCTIONS

Identification (ID) Byte

The first byte sent to the X9410 from the host,
following a CS

going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9410 this is fixed as 0101[B] (refer to Figure 2).

The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A

- A1 input

0

pins. The X9410 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9410 to successfully
continue the command sequence. The A

- A1 inputs

0

can be actively driven by CMOS input signals or tied to

or VSS.

V

CC

The remaining two bits in the ID byte must be set to 0.

Figure 2. Identification Byte Format

Device Type

Identifier

100

1

0 0 A1 A0

Device Address

Instruction Byte

The next byte sent to the X9410 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the two pots and when applicable
they point to one of four associated registers. The
format is shown below in Figure 3.

Figure 3. Instruction Byte Format

Register

Select

I1I2I3 I0 R1 R0 0 P0

Instructions

Pot Select

The four high order bits of the instruction byte specify
the operation. The next two bits (R

and R0) select one

1

of the four registers that is to be acted upon when a
register oriented instruction is issued. The last bit (P
selects which one of the two potentiometers is to be
affected by the instruction.

Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:

– XFR Data Register to Wiper Counter Register

—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.

– XFR Wiper Counter Register to Data Register

—This
transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.

– Global XFR Data Register to Counter Register

—This
transfers the contents of both specified Data Registers
to the associated Wiper Counter Registers.

– Global XFR Wiper Counter Register to Data

Register—This transfers the contents of both Wiper
Counter Registers to the specified associated Data
Registers.

The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t

. A transfer

WRL

from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

WR

between one of the two potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between both potentiometers and
one associated register.

)

0

5

FN8193.2

October 12, 2006

X9410

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Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9410; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:

– Read Wiper Counter Register

—read the current

wiper position of the selected pot,

– Write Wiper Counter Register

—change current

wiper position of the selected pot,

– Read Data Register

—read the contents of the

selected data register;

– Write Data Register

—write a new value to the

selected data register.

– Read Status

—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.

Figure 4. Two-Byte Instruction Sequence

CS

SCK

SI

The sequence of these operations is shown in Figure 5
and Figure 6.

The final command is Increment/Decrement. It is
different from the other commands because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps, thereby providing a fine
tuning capability to the host. For each SCK clock pulse

) while SI is HIGH, the selected wiper will move

(t

HIGH

one resistor segment towards the V

H/RH

terminal.
Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the V

terminal. A detailed illustration of the

L/RL

sequence and timing for this operation are shown in
Figure 7 and Figure 8.

010100A1A0I3 I2 I1 I0 R1 R0 0 P0

Figure 5. Three-Byte Instruction Sequence (Write)

CS

SCL

SI

0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 0 P0

00

Figure 6. Three-Byte Instruction Sequence (Read)

CS

SCL

SI

0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 0 P0

S0

00

0 0 D5 D4 D3 D2 D1 D0

Don’t Care

6

0 0 D5 D4 D3 D2 D1 D0

FN8193.2

October 12, 2006

X9410

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Figure 7. Increment/Decrement Instruction Sequence

CS

SCK

SI

010100A1A0 I3 I2 I1 I0 0 0 P0

0

I

I

N

N

C

C

1

2

D

I

E

N

C

C

1

n

D
E
C

n

Figure 8. Increment/Decrement Timing Limits

t

WRID

SCK

SI

VW/R

W

INC/DEC CMD Issued

Voltage Out

Table 1. Instruction Set

Instruction Set

Instruction

3I2I1I0

R1R0P1P

0

OperationI

Read Wiper Counter Register 1 0 01000P0Read the contents of the Wiper Counter

Register pointed to by P

0

Write Wiper Counter Register1010000P0Write new value to the Wiper Counter Register

pointed to by P

0

Read Data Register 1 0 1 1 R1R00P0Read the contents of the Data Register pointed

to by P

and R1 - R

0

0

Write Data Register 1 1 0 0 R1R00P0Write new value to the Data Register pointed to

and R1 - R

by P

XFR Data Register to Wiper
Counter Register

XFR Wiper Counter Register
to Data Register

Global XFR Data Register to
Wiper Counter Register

0

1101R1R00P0Transfer the contents of the Data Register

pointed to by R
Register pointed to by P

1110R1R00P0Transfer the contents of the Wiper Counter

Register pointed to by P
pointed to by R

0001R1R00 0 Transfer the contents of the Data Registers

pointed to by R

0

- R0 to the Wiper Counter

1

0

to the Register

- R

1

- R0 of both pots to their

1

0

0

respective Wiper Counter Register

Global XFR Wiper Counter
Register to Data Register

Increment/Decrement Wiper
Counter Register

1000R

1R0

0010000P

0 0 Transfer the contents of all Wiper Counter

Registers to their respective data Registers
pointed to by R

Enable Increment/decrement of the Wiper

0

Counter Register pointed to by P

- R0 of both pots

1

0

Read Status (WIP bit) 0 1 010001Read the status of the internal write cycle, by

checking the WIP bit.

7

FN8193.2

October 12, 2006

X9410

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Instruction Format

Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.

(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).

Read Wiper Counter Register (WCR)

CS

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

1001000

0

Write Wiper Counter Register (WCR)

CS

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

1010000

0

Read Data Register (DR)

CS

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

1011

0

Write Data Register(DR)

WCR

addresses

P
0

WCR

addresses

P
0

DR and WCR

addresses

R1R

0

P

0

0

wiper position

(sent by X9410 on SO)

W

W

W

W

00WP

(sent by Host on SI)

00WP

(sent by X9410 on SO)

00WP

P

P

5

4

3

Data Byte

W

W

P

P

5

4

3

Data Byte

W

P

5

4

W

P
3

P
2

W

P
2

W

W

P
2

CS

Rising

W

W

P
1

P
0

W

P
0

Rising

W

P
0

Edge

CS

Edge

CS

Rising

Edge

P
1

P
1

CS

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

1100

0

DR and WCR

addresses

R1R

0

0

P
0

00WP

Transfer Data Register (DR) to Wiper Counter Register (WCR)

CS

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

1101

0

DR and WCR

addresses

R1R

0

0

P
0

CS

Rising

Edge

Transfer Wiper Counter Register (WCR) to Data Register (DR)

CS

Falling

Edge

device type

identifier

010100DA

device

addresses

1

instruction

opcode

D
A01110

DR and WCR

addresses

R1R

0

0

P
0

CS

Rising

Edge

Data Byte

(sent by host on SI)

W

W

W

W

P

P

P

P

5

4

3

2

1

HIGH-VOLTAGE

WRITE CYCLE

W
P

0

CS

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

8

FN8193.2

October 12, 2006

X9410

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Increment/Decrement Wiper Counter Register (WCR)

CS

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

0010XX0

0

addresses

WCR

increment/decrement

(sent by master on SDA)

P0I/DI/

....

D

Global Transfer Data Register (DR) to Wiper Counter Register (WCR)

CS

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

0001

0

DR

addresses

R1R

0

00

CS

Rising

Edge

Global Transfer Wiper Counter Register (WCR) to Data Register (DR)

CS

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcodeDRaddresses

1000

0

R1R

0

00

CS

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

Read Status

CS

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

010100010000000WI

0

wiper

addresses

Data Byte

(sent by X9410 on SO)

I/DI/

P

Rising

Edge

D

CS

Rising

Edge

CS

9

FN8193.2

October 12, 2006

X9410

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ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C

Storage temperature ......................... -65°C to +150°C

Voltage on SCK, SCL or any address

input with respect to V
Voltage on V+ (referenced to V
Voltage on V- (referenced to V

......................... -1V to +7V

SS

) ........................ 10V

SS

) ........................-10V

SS

(V+) - (V-) .............................................................. 12V

Any V
Any V

..................................................................... V+

H

...................................................................... V-

L

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Lead temperature (soldering, 10s) .................. +300°C

(10s) ............................................................ ±12mA

I

W

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C+70°C

Industrial -40

°C+85°C

Device Supply Voltage (VCC) Limits

X9410 5V ± 10%

X9410-2.7 2.7V to 5.5V

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Limits

Symbol Parameter

R

TOTAL

End to end resistance ±20 %

Power rating 50 mW +25

I

W

R

W

Wiper current ±6 mA

Wiper resistance 150 250 Ω Wiper Current = ± 1mA,

Test ConditionsMin. Typ. Max. Unit

°C, each pot

=3V

V

CC

40 100 Ω Wiper Current = ± 1mA,

=5V

V

CC

Vv+ Voltage on V+ Pin X9410 +4.5 +5.5 V

X9410-2.7 +2.7 +5.5

Vv- Voltage on V- Pin X9410 -5.5 -4.5 V

X9410-2.7 -5.5 -2.7

V

TERM

Voltage on any VH/RH or VL/RL Pin V- V+ V

Noise -120 dBV Ref: 1kHz

Resolution

Absolute linearity

Relative linearity

Temperature coefficient of R

(4)

(1)

(2)

TOTAL

1.6 %

±1 MI

±0.2 MI

(3)

(3)

±300 ppm/°C

R

w(n)(actual)

R

w(n + 1)

- [R

- R

w(n) + MI

w(n)(expected)

]

Ratiometric temp. coefficient ±20 ppm/°C

C

H/CL/CW

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

(3) MI = RTOT/63 or (R
(4) Individual array resolution

Potentiometer capacitances 10/10/25 pF See Circuit #3

used as a potentiometer.

potentiometer. It is a measure of the error in step size.

- RL)/63, single pot

H

10

FN8193.2

October 12, 2006

X9410

www.BDTIC.com/Intersil

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter

I

CC1

I

CC2

VCC supply current (Active) 400 µA f

VCC supply current (Nonvolatile
Write)

I

SB

I

LI

I

LO

V

IH

V

IL

V

OL

VCC current (standby) 1 µA SCK = SI = VSS, Addr. = V

Input leakage current 10 µA VIN = VSS to V

Output leakage current 10 µA V

Input HIGH voltage VCC x 0.7 VCC + 0.5 V

Input LOW voltage -0.5 VCC x 0.1 V

Output LOW voltage 0.4 V IOL = 3mA

ENDURANCE AND DATA RETENTION

Parameter Min. Unit

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 years

1mAf

Test ConditionsMin. Typ. Max. Units

= 2MHz, SO = Open,

SCK

Other Inputs = V

= 2MHz, SO = Open,

SCK

Other Inputs = V

CC

= VSS to V

OUT

SS

SS

SS

CC

CAPACITANCE

Symbol Test Max. Unit Test Conditions

(5)

C

OUT

C

(5)

IN

Output capacitance (SO) 8 pF V

OUT

= 0V

Input capacitance (A0, A1, SI, and SCK) 6 pF VIN = 0V

POWER-UP TIMING

Symbol Parameter Min. Max. Unit

(6)

t

PUR

(6)

t

PUW

t

R VCC

POWER-UP AND POWER-DOWN

Power-up to initiation of read operation 1 1 ms

Power-up to initiation of write operation 5 5 ms

VCC Power-up ramp 0.2 50 V/msec

EQUIVALENT A.C. LOAD CIRCUIT

There are no restrictions on the power-up or power­down sequencing of the bias supplies V

, V+, and V-

CC

5V

2.7V

provided that all three supplies reach their final values
within 1msec of each other. However, at all times, the

1533Ω

voltages on the potentiometer pins must be less than
V+ and more than V-. The recall of the wiper position

SDA Output

from nonvolatile memory is not in effect until all
supplies reach their final value.

100pF

100pF

11

FN8193.2

October 12, 2006

X9410

www.BDTIC.com/Intersil

A.C. TEST CONDITIONS

nput pulse levels VCC x 0.1 to VCC x 0.9

I

Input rise and fall times 10ns

Input and output timing level V

Notes: (5) This parameter is periodically sampled and not 100% tested

(6) t

and t

PUR

third (last) power supply (V
the specific instruction can be issued. These parameters
are periodically sampled and not 100% tested.

are the delays required from the time the

PUW

x 0.5

CC

, V+ or V-) is stable until

CC

Test Circuit #3 SPICE Macro Model

R

R

H

10pF

TOTAL

C

H

C

W

25pF

R

W

C

L

10pF

R

AC TIMING

Symbol Parameter Min. Max. Unit

f

SCK

t

CYC

t

WH

t

WL

t

LEAD

t

LAG

t

SU

t

H

t

RI

t

FI

t

DIS

t

V

t

HO

t

RO

t

FO

t

HOLD

t

HSU

t

HH

t

HZ

t

LZ

T

I

t

CS

t

WPASU

t

WPAH

SSI/SPI clock frequency 2.0 MHz

SSI/SPI clock cycle time 500 ns

SSI/SPI clock high time 200 ns

SSI/SPI clock low time 200 ns

Lead time 250 ns

Lag time 250 ns

SI, SCK, HOLD and CS input setup time 50 ns

SI, SCK, HOLD and CS input hold time 50 ns

SI, SCK, HOLD and CS input rise time 2 µs

SI, SCK, HOLD and CS input fall time 2 µs

SO output disable time 0 500 ns

SO output valid time 100 ns

SO output hold time 0 ns

SO output rise time 50 ns

SO output fall time 50 ns

HOLD time 400 ns

HOLD setup time 100 ns

HOLD hold time 100 ns

HOLD low to output in High Z 100 ns

HOLD high to output in Low Z 100 ns

Noise suppression time constant at SI, SCK, HOLD and CS inputs 20 ns

CS deselect time 2 µs

WP, A0 and A1 setup time 0 ns

WP, A0 and A1 hold time 0 ns

L

12

FN8193.2

October 12, 2006

X9410

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HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Typ. Max. Unit

t

WR

XDCP TIMING

Symbol Parameter Min. Max. Unit

t

WRPO

t

WRL

t

WRID

SYMBOL TABLE

WAVEFORM INPUTS OUTPUTS

High-voltage write cycle time (store instructions) 5 10 ms

Wiper response time after the third (last) power supply is stable 10 µs

Wiper response time after instruction issued (all load instructions) 10 µs

Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 450 ns

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

TIMING DIAGRAMS

Input Timing

CS

SCK

t

SU

SI

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

t

LEAD

t

H

MSB LSB

t

WL

t

CYC

t

WH

...

...

t

FI

t

CS

t

LAG

t

RI

SO

High Impedance

13

FN8193.2

October 12, 2006

Output Timing

www.BDTIC.com/Intersil

CS

X9410

SCK

SO

Hold Timing

CS

SCK

SO

t

V

MSB LSB

ADDR

SI

t

HSU

t

HO

t

DIS

...

t

HH

...

...

t

RO

SI

t

t

HOLD

FO

t

HZ

t

LZ

HOLD

XDCP Timing (for All Load Instructions)

CS

SCK

MSB LSB

VW/R

SI

W

SO

High Impedance

...

...

t

WRL

14

FN8193.2

October 12, 2006

XDCP Timing (for Increment/Decrement Instruction)

www.BDTIC.com/Intersil

CS

X9410

SCK

V

W/RW

ADDR

SI

SO

High Impedance

Inc/Dec

Write Protect and Device Address Pins Timing

CS

t

WP

A0

A1

WPASU

...

t

WRID

Inc/Dec

(Any Instruction)

...

...

t

WPAH

15

FN8193.2

October 12, 2006

APPLICATIONS INFORMATION

www.BDTIC.com/Intersil

Basic Configurations of Electronic Potentiometers

V

R

VW/R

W

Three terminal Potentiometer;
Variable voltage divider

Application Circuits

NONINVERTING AMPLIFIER VOLTAGE REGULATOR

X9410

V

R

I

Two terminal Variable Resistor;
Variable current

V

S

VO = (1+R2/R1)V

OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERESIS

V

S

10kΩ

R

R

1

100kΩ

-12V+12V

+

–

R

1

S

–

+

TL072

10kΩ10kΩ

V

O

2

R

2

V

O

IN

VO (REG) = 1.25V (1+R2/R1)+I

V

S

VUL = {R1/(R1+R2)} VO(max)
V

= {R1/(R1+R2)} VO(min)

LL

317

I

adj

R

2

–

+

}

}

R

R

2

1

R

1

adj R2

VO (REG)V

V

O

16

FN8193.2

October 12, 2006

Application Circuits (continued)

www.BDTIC.com/Intersil

ATTENUATOR FILTER

R

1

V

S

V

S

R

3

R

4

All RS = 10kΩ

VO = G V

S

-1/2 ≤ G ≤ +1/2

INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT

R

R

1

}

VO = G V
G = -R2/R

2

}

S

1

X9410

C

V

R

2

–

V

+

O

S

R

G

= 1 + R2/R

O

fc = 1/(2πRC)

C

–

V

+

O

V

Z

IN

1

S

+

–

R

2

R

1

1

R

2

+

–

R

1

R

3

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R

FUNCTION GENERATOR

+ R3) >> R

1

2

C

R

–

2

+

R

}

A

R

}

B

R

1

–

+

frequency ∝ R1, R2, C
amplitude ∝ R

, R

A

B

17

FN8193.2

October 12, 2006

Dual-In-Line Plastic Packages (PDIP)

www.BDTIC.com/Intersil

X9410

N

D1

-C-

E1

-B-

A1

A2

E

A

L

e

C

C

L

e

A

C

e

B

INDEX

AREA

BASE

PLANE

SEATING

PLANE

D1

B1

12 3 N/2

-A­D

e

B

0.010 (0.25) C AM BS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpendic-

7. e

e

A

ular to datum .

and eC are measured at the lead tips with the leads unconstrained.

B

must be zero or greater.

e

C

-C-

8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

E24.6 (JEDEC MS-011-AA ISSUE B)

24 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.250 - 6.35 4

A1 0.015 - 0.39 - 4

A2 0.125 0.195 3.18 4.95 -

B 0.014 0.022 0.356 0.558 -

B1 0.030 0.070 0.77 1.77 8

C 0.008 0.015 0.204 0.381 -

D 1.150 1.290 29.3 32.7 5

D1 0.005 - 0.13 - 5

E 0.600 0.625 15.24 15.87 6

E1 0.485 0.580 12.32 14.73 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

0.600 BSC 15.24 BSC 6

- 0.700 - 17.78 7

L 0.115 0.200 2.93 5.08 4

N24 249

NOTESMIN MAX MIN MAX

Rev. 0 12/93

18

FN8193.2

October 12, 2006

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

X9410

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.5985 0.6141 15.20 15.60 3
E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6

N24 247

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 4/06

19

FN8193.2

October 12, 2006

Small Outline Package Family (SO)

www.BDTIC.com/Intersil

A

D

NN

(N/2)+1

X9410

h X 45°

PIN #1

E

C

SEATING
PLANE

0.004 C

E1

B

0.010 BM CA

I.D. MARK

1

e

0.010 BM CA

(N/2)

c

SEE DETAIL “X”

L1

H

A2

GAUGE
PLANE

A1

b

DETAIL X

L

4° ±4°

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL SO-8 SO-14

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28) TOLERANCE NOTES

A

0.010

Rev. L 2/01

20

FN8193.2

October 12, 2006

X9410

www.BDTIC.com/Intersil

Thin Shrink Small Outline Package Family (TSSOP)

E

C

SEATING
PLANE

N LEADS

0.25 CAB

M

N

E1

1

B

e

0.10 C

TOP VIEW

b

SIDE VIEW

SEE DETAIL “X”

(N/2)+1

(N/2)

0.10 CABM

AD

PIN #1 I.D.

0.20 C2XB A

N/2 LEAD TIPS

0.05

MDP0044

THIN SHRINK SMALL OUTLINE PACKAGE FAMILY

SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE

A 1.20 1.20 1.20 1.20 1.20 Max

A1 0.10 0.10 0.10 0.10 0.10 ±0.05

A2 0.90 0.90 0.90 0.90 0.90 ±0.05

b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06

c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06

D 5.00 5.00 6.50 7.80 9.70 ±0.10

E 6.40 6.40 6.40 6.40 6.40 Basic

E1 4.40 4.40 4.40 4.40 4.40 ±0.10

e 0.65 0.65 0.65 0.65 0.65 Basic

H

L 0.60 0.60 0.60 0.60 0.60 ±0.15

L1 1.00 1.00 1.00 1.00 1.00 Reference

Rev. E 12/02

NOTES:

1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.

3. Dimensions “D” and “E1” are measured at dAtum Plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

c

A2

A

A1

END VIEW

DETAIL X

L1

GAUGE
PLANE

0.25

L

0° - 8°

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

21

FN8193.2

October 12, 2006