intersil X9409 DATA SHEET

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X9409

Low Noise/Low Power/2-Wire Bus

Data Sheet FN8192.4October 12, 2006

Quad Digitally Controlled Potentiometers (XDCP™)

FEATURES

• Four potentiometers per package

• 64 resistor taps

• 2-wire serial interface for write, read, and transfer operations of the potentiometer

•50Ω Wiper resistance, typical at 5V.

• Four non-volatile data registers for each potentiometer

• Non-volatile storage of multiple wiper position

• Power-on recall. Loads saved wiper position on power-up.

• Standby current < 1µA typical

•System V

•10kΩ, 2.5kΩ End to end resistance

• 100 yr. data retention

• Endurance: 100,000 data changes per bit per register

• Low power CMOS

• 24 Ld SOIC, 24 Ld TSSOP

• Pb-free plus anneal available (RoHS compliant)

: 2.7V to 5.5V operation

DESCRIPTION

The X9409 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit.

The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power-up recalls the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

BLOCK DIAGRAM

SCL

SDA

A0 A1

A2 A3

Interface

and

Control

Circuitry

Data

Pot 0

R0R

Wiper Counter Register

(WCR)

Wiper

Counter Register

(WCR)

Resistor

Array Pot 1

R2R

R0R

R2R

VH0/R

VL0/ R

VW0/ R

L1/RL1

R0R

R2R

R0R

R2R

Wiper Counter Register

(WCR)

Wiper

Counter

(WCR)

Resistor

Array Pot 2

Resistor

Array

Pot 3

H2/RH2

VL2/R

VW2/R

VW3/R

H3/RH3

VL3/R

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Ordering Information

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X9409

POTENTIOMETER

LIMITS

PART NUMBER PART MARKING

X9409WS24I-2.7* X9409WS G 2.7 to 5.5 10 -40 to 85 24 Ld SOIC (300 mil) M24.3 X9409WS24IZ-2.7* (Note) X9409WS ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027 X9409WV24-2.7 X9409WV F 0 to 70 24 Ld TSSOP (4.4mm) MDP0044 X9409WV24Z-2.7 (Note) X9409WV ZF 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9409WV24I-2.7* X9409WV G -40 to 85 24 Ld TSSOP (4.4mm) MDP0044 X9409WV24IZ-2.7* (Note) X9409WV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

(V)

PIN DESCRIPTIONS

ORGANIZATION

(kΩ)

TEMP

RANGE

(°C) PACKAGE

W0/RW0 - VW3/RW3

PKG.

DWG. #

The wiper outputs are equivalent to the wiper output of

Host Interface Pins

Serial Clock (SCL)

The SCL input is used to clock data into and out of the X9409.

a mechanical potentiometer.

Hardware Write Protect Input (WP)

The WP pin when low prevents nonvolatile writes to the Data Registers.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph.

Device Address (A

- A3)

The address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9409. A maximum of 16 devices may occupy the 2-wire serial bus.

Potentiometer Pins

H0/RH0

- VH3/RH3, VL0/R

- VL3/R

The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer.

PIN NAMES

Symbol Description

SCL Serial Clock

SDA Serial Data

A0-A3 Device Address

H0/RH0

L0/RL0

W0/RW0

- VH3/RH3,

- VL3/R

- VW3/R

Potentiometer Pin (terminal equivalent)

Potentiometer Pin

(wiper equivalent)

Hardware Write Protection

System Supply Voltage

System Ground (Digital)

NC No Connection

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PIN CONFIGURATION

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X9409

SOIC

L3/RL3

VH3/R

VW3/R

SCL

L2/RL2

VH2/R

VW2/R

VL0/R

VH0/R

VW0/R

VL1/R

VH1/R

VW1/R

SDA

X9409

PRINCIPLES OF OPERATION

The X9409 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers.

Serial Interface

The X9409 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9409 will be considered a slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW periods (t

). SDA state changes during

LOW

SCL HIGH are reserved for indicating start and stop conditions.

Start Condition

All commands to the X9409 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (t

). The X9409 continuously

HIGH

monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met.

TSSOP

VW0/R

H0/RH0

VL0/R

L3/RL3

VH3/R

VW3/R

VL1/R

VH1/R

VW1/R

VW2/R

VH2/R

VL2/R

SDA

SCL

X9409

Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data.

The X9409 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9409 will respond with a final acknowledge.

Array Description

The X9409 is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (V

and VL/RL inputs).

H/RH

At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (V

) output. Within each individual array only one

W/RW

switch may be turned on at a time. These switches are

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X9409

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controlled by the Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches.

The WCR may be written directly, or it can be changed by transferring the contents of one of four associated Data Registers into the WCR. These Data Registers and the WCR can be read and written by the host system.

Device Addressing

Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9409 this is fixed as 0101[B].

Figure 1. Slave Address

Device Type

Identifier

100

A3 A2 A1 A0

Device Address

Flow 1. ACK Polling Sequence

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

YES

Further

Operation?

YES

Issue

Instruction

Issue STOP

The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0 - A3 inputs. The X9409 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9409 to respond with an acknowledge. The

- A3 inputs can be actively driven by CMOS input

signals or tied to V

or VSS.

Acknowledge Polling

The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical nonvolatile write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9409 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9409 is still busy with the write operation no ACK will be returned. If the X9409 has completed the write operation an ACK will be returned and the master can then proceed with the next operation.

Proceed

Instruction Structure

The next byte sent to the X9409 contains the instruction and register pointer information. The format is shown in Figure 2.

Figure 2. Instruction Byte Format

Select

I1I2I3 I0 R1 R0 P1 P0

Instructions

Pot Select

The four high order bits define the instruction. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last bits (P1, P0) select which one of the four potentiometers is to be affected by the instruction.

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X9409

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Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the Wiper Counter Register and one of the data registers. A transfer from a Data Register to a Wiper Counter Register is essentially a write to a static RAM. The response of the wiper to this action will be delayed t

. A transfer from the Wiper

WRL

Counter Register (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of t

to complete. The transfer can occur

between one of the four potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between all of the potentiometers and one of their associated registers.

Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9409; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: Read Wiper Counter Register (read the current

Table 1. Instruction Set

Instruction Set

Instruction

Read Wiper Counter Register

Write Wiper Counter Register

Read Data Register 1 0 1 1 R1R

Write Data Register 1 1 0 0 R1R

XFR Data Register to Wiper Counter Register

XFR Wiper Counter Register to Data Register

Global XFR Data Registers to Wiper Counter Registers

Global XFR Wiper Counter Registers to Data Register

Increment/Decrement Wiper Counter Register

Note: (7) 1/0 = data is one or zero

3I2I1I0

10010 0P1P0Read the contents of the Wiper Counter Register

10100 0P1P0Write new value to the Wiper Counter Register

1101R1R

1110R

0001R

1000R

00100 0P

R1R0P1P

1R0

wiper position of the selected pot), Write Wiper Counter Register (change current wiper position of the selected pot), Read Data Register (read the contents of the selected nonvolatile register) and Write Data Register (write a new value to the selected Data Register). The sequence of operations is shown in Figure 4.

The Increment/Decrement command is different from the other commands. Once the command is issued and the X9409 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse

) while SDA is HIGH, the selected wiper will

HIGH

move one resistor segment towards the V terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the V

terminal. A detailed

L/RL

illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively.

pointed to by P

P0Read the contents of the Data Register pointed to

P0Write new value to the Data Register pointed to

P0Transfer the contents of the Data Register

P0Transfer the contents of the Wiper Counter

0 0 Transfer the contents of the Data Registers

0 0 Transfer the contents of both Wiper Counter

P0Enable Increment/decrement of the WCR Latch

- P0 and R1 - R

by P

- P0 and R1 - R

by P

pointed to by P Wiper Counter Register

pointed to by R respective Wiper Counter Registers

Registers to their respective Data Registers pointed to by R

pointed to by P

OperationI

- P

- P0 and R1 - R0 to its associated

- P0 to the Data

- R

- R0 of all four pots to their

- R0 of all four pots

1 - P0

H/RH

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Figure 3. Two-Byte Instruction Sequence

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SCL

SDA

0101A3A2A1A0A T A R T

Figure 4. Three-Byte Instruction Sequence

SCL

SDA

X9409

I3 I2 I1 I0 R1 R0 P1 P0 A C K

O P

0 1 0 1 A3 A2 A1 A0 T A R

I3 I2 I1 I0 R1 R0 P1 P0 C K

Figure 5. Increment/Decrement Instruction Sequence

SCL

SDA

0 1 0 1 A3 A2 A1 A0 A T A R T

I3 I2 I1 I0 R0 P1 P0 A C K

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

Issued

SCL

0 0 D5 D4 D3 D2 D1 D0 C K

I N C 1

WRID

I N C

C K

N C

O P

D E C

SDA

VW/R

Voltage Out

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