intersil X9409 DATA SHEET

®

www.BDTIC.com/Intersil

X9409

Low Noise/Low Power/2-Wire Bus

Data Sheet FN8192.4October 12, 2006

Quad Digitally Controlled Potentiometers
(XDCP™)

FEATURES

• Four potentiometers per package

• 64 resistor taps

• 2-wire serial interface for write, read, and trans­fer operations of the potentiometer

•50Ω Wiper resistance, typical at 5V.

• Four non-volatile data registers for each
potentiometer

• Non-volatile storage of multiple wiper position

• Power-on recall. Loads saved wiper position on
power-up.

• Standby current < 1µA typical

•System V

•10kΩ, 2.5kΩ End to end resistance

• 100 yr. data retention

• Endurance: 100,000 data changes per bit per
register

• Low power CMOS

• 24 Ld SOIC, 24 Ld TSSOP

• Pb-free plus anneal available (RoHS compliant)

: 2.7V to 5.5V operation

CC

DESCRIPTION

The X9409 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.

The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

BLOCK DIAGRAM

V

CC

V

SS

WP

SCL

SDA

A0
A1

A2
A3

Interface

and

Control

Circuitry

Data

Pot 0

R0R

1

Wiper
Counter
Register

3

1

3

(WCR)

Wiper

Counter
Register

(WCR)

Resistor

Array
Pot 1

R2R

8

R0R

R2R

VH0/R

VL0/
R

LO

VW0/
R

WO

V

W1

R

W1

V

H1

R

H1

V

L1/RL1

HO

/

/

R0R

R2R

R0R

R2R

1

3

1

3

Wiper
Counter
Register

(WCR)

Wiper

Counter

Register

(WCR)

Resistor

Array
Pot 2

Resistor

Array

Pot 3

V

H2/RH2

VL2/R

VW2/R

VW3/R

V

H3/RH3

VL3/R

L2

W2

W3

L3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Ordering Information

www.BDTIC.com/Intersil

X9409

POTENTIOMETER

V

LIMITS

PART NUMBER PART MARKING

X9409WS24I-2.7* X9409WS G 2.7 to 5.5 10 -40 to 85 24 Ld SOIC (300 mil) M24.3
X9409WS24IZ-2.7* (Note) X9409WS ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027
X9409WV24-2.7 X9409WV F 0 to 70 24 Ld TSSOP (4.4mm) MDP0044
X9409WV24Z-2.7 (Note) X9409WV ZF 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9409WV24I-2.7* X9409WV G -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9409WV24IZ-2.7* (Note) X9409WV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

CC

(V)

PIN DESCRIPTIONS

ORGANIZATION

(kΩ)

V

TEMP

RANGE

(°C) PACKAGE

W0/RW0 - VW3/RW3

PKG.

DWG. #

The wiper outputs are equivalent to the wiper output of

Host Interface Pins

Serial Clock (SCL)

The SCL input is used to clock data into and out of the
X9409.

a mechanical potentiometer.

Hardware Write Protect Input (WP)

The WP pin when low prevents nonvolatile writes to
the Data Registers.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.

Device Address (A

0

- A3)

The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9409. A maximum of 16 devices may occupy the
2-wire serial bus.

Potentiometer Pins

V

H0/RH0

- VH3/RH3, VL0/R

L0

- VL3/R

L3

The VH/RH and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.

PIN NAMES

Symbol Description

SCL Serial Clock

SDA Serial Data

A0-A3 Device Address

V

H0/RH0

V

L0/RL0

V

W0/RW0

- VH3/RH3,

- VL3/R

L3

- VW3/R

Potentiometer Pin
(terminal equivalent)

Potentiometer Pin

W3

(wiper equivalent)

WP

V

CC

V

SS

Hardware Write Protection

System Supply Voltage

System Ground (Digital)

NC No Connection

2

FN8192.4

October 12, 2006

PIN CONFIGURATION

www.BDTIC.com/Intersil

X9409

SOIC

24

23

22

21

20

19

18

17

16

15

14

13

NC

V

L3/RL3

VH3/R

VW3/R

A

0

NC

A

3

SCL

V

L2/RL2

VH2/R

VW2/R

NC

H3

W3

H2

W2

VL0/R

VH0/R

VW0/R

VL1/R

VH1/R

VW1/R

V

CC

L0

H0

W0

A

WP

SDA

A

L1

H1

W1

V

SS

1

2

3

4

5

2

6

X9409

7

8

1

9

10

11

12

PRINCIPLES OF OPERATION

The X9409 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.

Serial Interface

The X9409 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9409 will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods (t

). SDA state changes during

LOW

SCL HIGH are reserved for indicating start and stop
conditions.

Start Condition

All commands to the X9409 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t

). The X9409 continuously

HIGH

monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.

TSSOP

24

23

22

21

20

19

18

17

16

15

14

13

WP

A

2

VW0/R

V

H0/RH0

VL0/R

V

CC

NC

V

L3/RL3

VH3/R

VW3/R

A

0

NC

W0

L0

H3

W3

VL1/R

VH1/R

VW1/R

VW2/R

VH2/R

VL2/R

SDA

A

L1

H1

W1

V

SS

NC

W2

H2

L2

SCL

A

1

2

1

3

4

5

6

X9409

7

8

9

10

11

12

3

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

The X9409 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9409 will respond with a final acknowledge.

Array Description

The X9409 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

and VL/RL inputs).

H/RH

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V

) output. Within each individual array only one

W/RW

switch may be turned on at a time. These switches are

3

FN8192.4

October 12, 2006

X9409

www.BDTIC.com/Intersil

controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9409
this is fixed as 0101[B].

Figure 1. Slave Address

Device Type

Identifier

100

1

A3 A2 A1 A0

Device Address

Flow 1. ACK Polling Sequence

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

YES

Further

Operation?

YES

Issue

Instruction

NO

NO

Issue STOP

Issue STOP

The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0 - A3 inputs. The X9409 compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9409 to respond with an acknowledge. The

- A3 inputs can be actively driven by CMOS input

A

0

signals or tied to V

or VSS.

CC

Acknowledge Polling

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical nonvolatile write cycle time.
Once the stop condition is issued to indicate the end of
the nonvolatile write command the X9409 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9409 is
still busy with the write operation no ACK will be
returned. If the X9409 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.

Proceed

Proceed

Instruction Structure

The next byte sent to the X9409 contains the
instruction and register pointer information. The format
is shown in Figure 2.

Figure 2. Instruction Byte Format

Register

Select

I1I2I3 I0 R1 R0 P1 P0

Instructions

Pot Select

The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the four
registers that is to be acted upon when a register
oriented instruction is issued. The last bits (P1, P0)
select which one of the four potentiometers is to be
affected by the instruction.

4

FN8192.4

October 12, 2006

X9409

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Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the Wiper Counter Register
and one of the data registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
action will be delayed t

. A transfer from the Wiper

WRL

Counter Register (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

WR

between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all of the potentiometers
and one of their associated registers.

Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9409; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are: Read Wiper Counter Register (read the current

Table 1. Instruction Set

Instruction Set

Instruction

Read Wiper Counter
Register

Write Wiper Counter
Register

Read Data Register 1 0 1 1 R1R

Write Data Register 1 1 0 0 R1R

XFR Data Register to
Wiper Counter Register

XFR Wiper Counter
Register to Data
Register

Global XFR Data
Registers to Wiper
Counter Registers

Global XFR Wiper
Counter Registers to
Data Register

Increment/Decrement
Wiper Counter Register

Note: (7) 1/0 = data is one or zero

3I2I1I0

10010 0P1P0Read the contents of the Wiper Counter Register

10100 0P1P0Write new value to the Wiper Counter Register

1101R1R

1110R

0001R

1000R

00100 0P

R1R0P1P

1R0

1R0

1R0

wiper position of the selected pot), Write Wiper
Counter Register (change current wiper position of the
selected pot), Read Data Register (read the contents
of the selected nonvolatile register) and Write Data
Register (write a new value to the selected Data
Register). The sequence of operations is shown in
Figure 4.

The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9409 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse

) while SDA is HIGH, the selected wiper will

(t

HIGH

move one resistor segment towards the V
terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the V

terminal. A detailed

L/RL

illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.

0

pointed to by P

pointed to by P

P

0

0

0

P0Read the contents of the Data Register pointed to

1

P

P0Write new value to the Data Register pointed to

1

P

P0Transfer the contents of the Data Register

1

P

P0Transfer the contents of the Wiper Counter

1

0 0 Transfer the contents of the Data Registers

0 0 Transfer the contents of both Wiper Counter

P0Enable Increment/decrement of the WCR Latch

1

- P0 and R1 - R

by P

1

- P0 and R1 - R

by P

1

pointed to by P
Wiper Counter Register

Register pointed to by P
Register pointed to by R

pointed to by R
respective Wiper Counter Registers

Registers to their respective Data Registers
pointed to by R

pointed to by P

OperationI

- P

1

0

- P

1

0

0

0

- P0 and R1 - R0 to its associated

1

- P0 to the Data

1

- R

1

0

- R0 of all four pots to their

1

- R0 of all four pots

1

1 - P0

H/RH

5

FN8192.4

October 12, 2006

Figure 3. Two-Byte Instruction Sequence

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SCL

SDA

S

0101A3A2A1A0A
T
A
R
T

Figure 4. Three-Byte Instruction Sequence

SCL

SDA

X9409

I3 I2 I1 I0 R1 R0 P1 P0 A
C
K

S

C

T

K

O
P

S

0 1 0 1 A3 A2 A1 A0
T
A
R

T

A

I3 I2 I1 I0 R1 R0 P1 P0
C
K

Figure 5. Increment/Decrement Instruction Sequence

SCL

SDA

S

0 1 0 1 A3 A2 A1 A0 A
T
A
R
T

I3 I2 I1 I0 R0 P1 P0 A
C
K

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

Issued

SCL

R1

A

0 0 D5 D4 D3 D2 D1 D0
C
K

I
N
C
1

t

WRID

I
N
C

2

C
K

I

N
C

n

A

S

C

T

K

O
P

D
E
C

1

S

D

T

E

O

C

P

n

SDA

VW/R

W

Voltage Out

6

FN8192.4

October 12, 2006

Figure 7. Acknowledge Response from Receiver

www.BDTIC.com/Intersil

X9409

SCL from

Master

Data Output

from Transmitter

Data Output

from Receiver

START

1

Figure 8. Detailed Potentiometer Block Diagram

Serial Data Path

From Interface

Circuitry

Register 0 Register 1

8 6

Register 2 Register 3

If WCR = 00[H] then VW/RW = VL/R

If WCR = 3F[H] then VW/RW = VH/R

L

H

UP/DN

Modified SCL

Serial
Bus
Input

Parallel
Bus
Input

Register

UP/DN

CLK

89

Acknowledge

C
o

u
n

t

e

r

Wiper

Counter

(WCR)

INC/DEC

Logic

D

e
c

o
d

e

VH/R

VL/R

H

L

7

VW/R

W

FN8192.4

October 12, 2006

X9409

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DETAILED OPERATION

All XDCP potentiometers share the serial interface
and share a common architecture. Each potentiometer
has a Wiper Counter Register and 4 Data Registers. A
detailed discussion of the register organization and
array operation follows.

Wiper Counter Register

The X9409 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The Wiper Counter
Register can be envisioned as a 6-bit parallel and
serial load counter with its outputs decoded to select
one of sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
the four associated Data Registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
Data Register zero (DR0) upon power-up.

The WCR is a volatile register; that is, its contents are
lost when the X9409 is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be
different from the value present at power-down.

Data Registers

Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the Wiper Counter Register. It
should be noted all operations changing data in one of
these registers is a nonvolatile operation and will take
a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.

Register Descriptions

Data Registers, (6-Bit), Nonvolatile:

D5 D4 D3 D2 D1 D0

NV NV NV NV NV NV

(MSB) (LSB)

Four 6-bit Data Registers for each XDCP. (sixteen 6­bit registers in total).

– {D5~D0}: These bits are for general purpose not vol-

atile data storage or for storage of up to four differ­ent wiper values. The contents of Data Register 0
are automatically moved to the wiper counter regis­ter on power-up.

Wiper Counter Register, (6-Bit), Volatile:

WP5 WP4 WP3 WP2 WP1 WP0

VVVVVV

(MSB) (LSB)

One 6-bit Wiper Counter Register for each XDCP.
(Four 6-bit registers in total.)

– {D5~D0}: These bits specify the wiper position of the

respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register

. The contents of the WCR can be loaded from

R

0

any of the other Data Register or directly by com­mand. The contents of the WCR can be saved in a
DR.

8

FN8192.4

October 12, 2006

X9409

www.BDTIC.com/Intersil

Instruction Format

Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.

(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

Read Wiper Counter Register (WCR)

S

device type

T

identifier
A
R

0101

T

Write Wiper Counter Register (WCR)

device type

S

identifier

T
A
R

0101

T

Read Data Register (DR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

device

addresses

A3A2A

1A0

device

addresses

A3A2A1A

instruction

S

opcode

A

C

100100

K

0

instruction

S

opcode

A
C

101

K

instruction

S

opcode

A

C

1011

K

0

WCR

addresses

WCR

addresses

000

DR and WCR

addresses

R1R0P1P

P1P

P1P

S

(sent by slave on SDA)

A
C

00WP

K

0

S

(sent by master on SDA)

A

C

00WP

K

0

S

(sent by slave on SDA)

A
C

00WP

K

0

wiper position

W

W

W

P

P

P

5

4

3

2

wiper position

W

W

W

P

P

P

5

4

3

2

wiper position

W

W

P

P

5

4

3

W

P

S

M

T

A

W

W

O

C

P

P

P

K

1

0

S

S

T

A

W

W

O

C

P

P

P

K

1

0

S

M

T

A

W

W

O

C

P

P

P

2

K

1

0

Write Data Register (DR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

S
A
C
K

0

instruction

opcode

1100

DR and WCR

addresses

R1R0P1P

S

(sent

A
C

00WP

K

0

Transfer Data Register (DR) to Wiper Counter Register (WCR)

S

device type

T

identifier
A
R

0101

T

device

addresses

A3A2A1A

S
A
C
K

0

instruction

opcode

1101

DR and WCR

addresses

R1R0P1P

S

S

T

A

O

C

P

K

0

Write Wiper Counter Register (WCR) to Data Register (DR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

S

A
C
K

0

instruction

opcode

1110

DR and WCR

addresses

R1R0P1P

S

S

T

A

O

C

P

K

0

wiper position

by master on SDA)

W

W

W

W

P

P

P

P

5

4

3

2

1

HIGH-VOLTAGE

WRITE CYCLE

W
P

0

S

S

T

A

HIGH-VOLTAGE

O

C

K

WRITE CYCLE

P

9

FN8192.4

October 12, 2006

X9409

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Increment/Decrement Wiper Counter Register (WCR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

instruction

S

opcode

A
C

001000

K

0

WCR

addresses

P1P

0

Global Transfer Data Register (DR) to Wiper Counter Register (WCR)

device type

S

identifier

T

A
R

0101

T

device

addresses

A3A2A1A

S
A

C

K

0

instruction

opcode

0001

DR

addresses

R1R

00

0

Global Transfer Wiper Counter Register (WCR) to Data Register (DR)

S

device type

T

identifier
A
R

0101

T

device

addresses

A3A2A1A

0

i

nstruction

S

opcodeDRaddresses

A
C

1000

K

R1R

0

00

S
A

C

K

increment/decrement

S

(sent by master on SDA)

A
C

I/DI/

K

S

S

T

A

O

C

P

K

....

D

S
T

HIGH-VOLTAGE

O

WRITE CYCLE

P

I/DI/

S

T
O
P

D

SYMBOL TABLE Guidelines for Calculating Typical Values of Bus

Pull-Up Resistors

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

Resistance (K)

120

100

80

60

40

20

0

V

R

R

Min.
Resistance

20 40 60 80 100 120

0

BUS CAPACITANCE (pF)

CC MAX

=

MIN

I

OL MIN

t

=

MAX

C

BUS

Max.
Resistance

R

=1.8kΩ

10

FN8192.4

October 12, 2006

X9409

www.BDTIC.com/Intersil

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C

Storage temperature ......................... -65°C to +150°C

Voltage on SDA, SCL or any address

input with respect to V

Δ V = |V

- VL | ........................................................ 5V

H

......................... -1V to +7V

SS

Lead temperature (soldering, 10s) .................. +300°C

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C+70°C

Industrial -40°C+85

°C

Device Supply Voltage (VCC) Limits

X9409-2.7 2.7V to 5.5V

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Limits

Symbol Parameter

End to end resistance tolerance ±20 %

Power rating 15 mW 25°C, each pot @5V, 2.5K

I

W

R

W

V

TERM

C

H/CL/CW

I

AL

Wiper current -3 +3 mA

Wiper resistance 50 150 Ω IW = ± 3mA, VCC = 3V to 5V

Voltage on any VH/RH or VL/RL pin V

Noise -120 dBV Ref: 1kHz

Resolution

Absolute linearity

Relative linearity

Temperature coefficient of R

Ratiometric temp. coefficient 20 ppm/

Potentiometer capacitances 10/10/25 pF See Macro Model

RH, RL, RW leakage current 0.1 10 µA VIN = VSS to VCC. Device is

(4)

(1)

(2)

TOTAL

SS

1.6 %

-1 +1 MI

-0.2 +0.2 MI

±300 ppm/°C

V

CC

VVSS = 0V

(3)

(3)

°C

Test ConditionsMin. Typ. Max. Unit

V

w(n)(actual)

V

w(n + 1)

in stand-by mode.

- [V

- V

w(n)(expected)

w(n) + MI

]

Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as

a potentiometer.

(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-

ometer. It is a measure of the error in step size.

(3) MI = RTOT/63 or (V

- VL)/63, single pot

H

11

FN8192.4

October 12, 2006

X9409

www.BDTIC.com/Intersil

D.C. OPERATING CHARACTERISTICS

(Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter

I

CC1

I

CC2

I

SB

I

LI

I

LO

V

IH

V

IL

V

OL

ENDURANCE AND DATA RETENTION

VCC supply current (Active) 100 µA f

VCC supply current

1mAf

(Nonvolatile Write)

VCC current (standby) 1 µA SCL = SDA = VCC, Addr. = V

Input leakage current 10 µA VIN = VSS to V

Output leakage current 10 µA V

Input HIGH voltage VCC x 0.7 VCC + 0.5 V

Input LOW voltage -0.5 VCC x 0.1 V

Output LOW voltage 0.4 V IOL = 3mA

Parameter Min. Unit

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 Years

Test ConditionsMin. Typ. Max. Unit

= 400kHz, SDA = Open,

SCL

Other Inputs = V

= 400kHz, SDA = Open,

SCL

Other Inputs = V

= VSS to V

OUT

SS

SS

CC

CC

SS

CAPACITANCE

Symbol Test Max. Unit Test Conditions

(4)

C

I/O

(4)

C

IN

Input/output capacitance (SDA) 8 pF V

I/O

= 0V

Input capacitance (A0, A1, A2, A3, and SCL) 6 pF VIN = 0V

POWER-UP TIMING

Symbol Parameter Min. Max. Unit

(6)

tr V

CC

VCC power-up rate 0.2 50 V/ms

POWER-UP REQUIREMENTS (Power-up sequencing can affect correct recall of the wiper registers)

The preferred power-on sequence is as follows: First V

, then the potentiometer pins, RH, RL, and RW. The V

CC

CC

ramp rate specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if
possible. If V
for proper wiper register recall. Also, V
not be complete until V

Notes: (4) This parameter is periodically sampled and not 100% tested

(5) t

(6) Sample tested only.

powers down, it should be held below 0.1V for more than 1 second before powering up again in order

CC

reaches its final value.

CC

and t

PUR

These parameters are periodically sampled and not 100% tested.

are the delays required from the time the (last) power supply (VCC) is stable until the specific instruction can be issued.

PUW

should not reverse polarity by more than 0.5V. Recall of wiper position will

CC

12

FN8192.4

October 12, 2006

X9409

www.BDTIC.com/Intersil

A.C. TEST CONDITIONS

nput pulse levels VCC x 0.1 to VCC x 0.9

I

Input rise and fall times 10ns

Input and output timing level V

CC

x 0.5

Circuit #3 SPICE Macro Model

R

R

H

TOTAL

C

H

C

C

L

W

10pF

EQUIVALENT A.C. LOAD CIRCUIT

10pF

5V

1533Ω

SDA Output

100pF

25pF

R

W

AC TIMING (over recommended operating condition)

Symbol Parameter Min. Max. Unit

f

SCL

t

CYC

t

HIGH

t

LOW

t

SU:STA

t

HD:STA

t

SU:STO

t

SU:DAT

t

HD:DAT

t

R

t

F

t

AA

t

DH

T

I

t

BUF

t

SU:WPA

t

HD:WPA

Clock frequency 400 kHz

Clock cycle time 2500 ns

Clock high time 600 ns

Clock low time 1300 ns

Start setup time 600 ns

Start hold time 600 ns

Stop setup time 600 ns

SDA data input setup time 100 ns

SDA data input hold time 30 ns

SCL and SDA rise time 300 ns

SCL and SDA fall time 300 ns

SCL low to SDA data output valid time 900 ns

SDA data output hold time 50 ns

Noise suppression time constant at SCL and SDA inputs 50 ns

Bus free time (prior to any transmission) 1300 ns

WP, A0, A1, A2 and A3 setup time 0 ns

WP, A0, A1, A2 and A3 hold time 0 ns

R

L

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Typ. Max. Unit

t

WR

High-voltage write cycle time (store instructions) 5 10 ms

13

FN8192.4

October 12, 2006

X9409

www.BDTIC.com/Intersil

XDCP TIMING

Symbol Parameter Min. Typ. Max. Unit

t

WRPO

t

WRL

t

WRID

Note: (9) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling

TIMING DIAGRAMS

START and STOP Timing

g

Wiper response time after the third (last) power supply is stable 2 10 µs

Wiper response time after instruction issued (all load instructions) 2 10 µs

Wiper response time from an active SCL/SCK edge (increment/decrement

210µs

instruction)

edge of SCL.

(START) (STOP)

t

F

t

SU:STO

t

F

SCL

SDA

t

SU:STA

t

HD:STA

t

R

t

R

Input Timing

SCL

SDA

Output Timing

SCL

SDA

t

CYC

t

SU:DAT

t

HIGH

t

LOW

t

HD:DAT

t

AA

t

DH

t

BUF

14

FN8192.4

October 12, 2006

APPLICATIONS INFORMATION

www.BDTIC.com/Intersil

Basic Configurations of Electronic Potentiometers

V

R

VW/R

W

Three terminal Potentiometer;
Variable voltage divider

Application Circuits

NONINVERTING AMPLIFIER VOLTAGE REGULATOR

X9409

+V

R

I

Two terminal Variable Resistor;
Variable current

V

S

VO = (1+R2/R1)V

OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERESIS

V

S

10kΩ

V

S

R

R

1

100kΩ

+

–

R

1

S

–

+

TL072

10kΩ10kΩ

V

O

2

R

2

V

O

IN

VO (REG) = 1.25V (1+R2/R1)+I

V

S

VUL = {R1/(R1+R2)} VO(max)

= {R1/(R1+R2)} VO(min)

V

LL

317

R

1

I

adj

R

2

–

+

}

}

R

R

2

1

adj R2

VO (REG)V

V

O

15

FN8192.4

October 12, 2006

Application Circuits (continued)

www.BDTIC.com/Intersil

ATTENUATOR FILTER

R

1

V

S

V

R

3

R

VO = G V

-1/2 ≤ G ≤ +1/2

INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT

R

R

1

S

}

4

All RS = 10kΩ

S

2

}

–

+

–

+

X9409

C

V

R

2

V

O

V

O

S

R

G

O

fc = 1/(2πRC)

C

1

V

S

R

1

= 1 + R2/R

+

–

R

1

R

2

+

–

V

O

2

VO = G V
G = - R2/R

R

Z

S

1

FUNCTION GENERATOR

R

–

+

R

}

A

R

}

B

frequency ∝ R1, R2, C
amplitude ∝ R

2

, R

A

IN

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R

R

1

B

1

–

+

1

R

3

+ R3) >> R

C

2

16

FN8192.4

October 12, 2006

XDCP Timing (for All Load Instructions)

www.BDTIC.com/Intersil

SCL

X9409

(STOP)

SDA

VWx

XDCP Timing (for Increment/Decrement Instruction)

SCL

Wiper Register Address Inc/Dec Inc/Dec

V

W/RW

SDA

Write Protect and Device Address Pins Timing

LSB

t

WRL

t

WRID

SCL

SDA

WP

A0, A1

A2, A3

(START) (STOP)

...

(Any Instruction)

...

...

t

SU:WPA

t

HD:WPA

17

FN8192.4

October 12, 2006

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

X9409

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.5985 0.6141 15.20 15.60 3
E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6

N24 247

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 4/06

18

FN8192.4

October 12, 2006

Small Outline Package Family (SO)

www.BDTIC.com/Intersil

A

D

NN

(N/2)+1

X9409

h X 45°

PIN #1

E

C

SEATING
PLANE

0.004 C

E1

B

0.010 BM CA

I.D. MARK

1

e

0.010 BM CA

(N/2)

c

SEE DETAIL “X”

L1

H

A2

GAUGE
PLANE

A1

b

DETAIL X

L

4° ±4°

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL SO-8 SO-14

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28) TOLERANCE NOTES

A

0.010

Rev. L 2/01

19

FN8192.4

October 12, 2006

X9409

www.BDTIC.com/Intersil

Thin Shrink Small Outline Package Family (TSSOP)

C

SEATING
PLANE

N LEADS

0.25 CAB

M

E

E1

B

0.10 C

N

1

TOP VIEW

e

b

SEE DETAIL “X”

(N/2)+1

SIDE VIEW

(N/2)

0.10 CABM

AD

PIN #1 I.D.

0.20 C2XB A

N/2 LEAD TIPS

0.05

MDP0044

THIN SHRINK SMALL OUTLINE PACKAGE FAMILY

SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE

A 1.20 1.20 1.20 1.20 1.20 Max

A1 0.10 0.10 0.10 0.10 0.10 ±0.05

A2 0.90 0.90 0.90 0.90 0.90 ±0.05

b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06

c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06

D 5.00 5.00 6.50 7.80 9.70 ±0.10

E 6.40 6.40 6.40 6.40 6.40 Basic

E1 4.40 4.40 4.40 4.40 4.40 ±0.10

e 0.65 0.65 0.65 0.65 0.65 Basic

H

L 0.60 0.60 0.60 0.60 0.60 ±0.15

L1 1.00 1.00 1.00 1.00 1.00 Reference

Rev. E 12/02

NOTES:

1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.

3. Dimensions “D” and “E1” are measured at dAtum Plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

c

A2

A

A1

END VIEW

DETAIL X

L1

GAUGE
PLANE

0.25

L

0° - 8°

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or i t s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

20

FN8192.4

October 12, 2006