intersil X9408 DATA SHEET

®

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X9408

Low Noise/Low Power/2-Wire Bus

Data Sheet FN8191.3December 9, 2005

Quad Digitally Controlled (XDCP™)
Potentiometers

FEATURES

• Four potentiometers in one package

• 64 resistor taps per potentiometer

• 2-wire serial interface

• Wiper resistance, 40Ω typical at 5V

• Four nonvolatile data registers for each pot

• Nonvolatile storage of wiper position

• Standby current < 1µA max (total package)
= 2.7V to 5.5V operation

•V

CC

V+ = 2.7V to 5.5V
V- = –2.7V to -5.5V

•10kΩ, 2.5kΩ end to end resistances

• High reliability

—Endurance–100,000 data changes per bit per

register

—Register data retention–100 years

• 24 Ld SOIC, 24 Ld TSSOP, 24 Ld PDIP packages

• Pb-free plus anneal available (RoHS compliant)

BLOCK DIAGRAM

V

CC

V

SS

WP

SCL

SDA

A0
A1
A2
A3

V+
V-

Interface

and

Control

Circuitry

Data

Pot 0

R0 R1

R2 R3

8

R0 R1

R2 R3

Wiper
Counter
Register

(WCR)

Wiper
Counter

Register

(WCR)

Resistor

Array
Pot 1

DESCRIPTION

The X9408 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user th rough the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and four
non-volatile Data Registers that can be directly written
to and read by the user. The contents of the WCR
controls the position of the wiper on the re sistor array
though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

VH0/

VL0/

VW0/

VW1/

V

H1

VL1/

R

H0

R

L0

R

W0

R

W1

/

R

H1

R

L1

R0 R1

R2 R3

R0 R1

R2 R3

Wiper
Counter
Register

(WCR)

Wiper
Counter
Register

(WCR)

Resistor

Array
Pot 2

Resistor

Array
Pot 3

V

H2

VL2/

VW2/

VW3/

V

H3

VL3/

/

R

H2

R

L2

R

W2

R

W3

/

R

H3

R

L3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9408

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Ordering Information

POTENTIOMETER

ORGANIZATION

PART NUMBER PART MARKING VCC LIMITS (V)

X9408YP24 X9408YP 5 ±10% 2.5 0 to 70 24 Ld PDIP

X9408YS24* X9408YS 0 to 70 24 Ld SOIC (300 mil)

X9408YS24Z* (Note) X9408YS Z 0 to 70 24 Ld SOIC (300 mil) (Pb-free)

X9408YS24I* X9408YS I -40 to 85 24 Ld SOIC (300 mil)

X9408YS24IZ* (Note) X9408YS Z I -40 to 85 24 Ld SOIC (300 mil) (Pb-free)

X9408YV24* X9408YV 0 to 70 24 Ld TSSOP (4.4mm)

X9408YV24Z* (Note) X9408YV Z 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free)

X9408YV24I* X9408YV I -40 to 85 24 Ld TSSOP (4.4mm)

X9408YV24IZ* (Note) X9408YV Z I -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free)

X9408WP24 X9408WP 10 0 to 70 24 Ld PDIP

X9408WP24I X9408WP I -40 to 85 24 Ld PDIP

X9408WS24* X9408WS 0 to 70 24 Ld SOIC (300 mil)

X9408WS24Z* (Note) X9408WS Z 0 to 70 24 Ld SOIC (300 mil) (Pb-free)

X9408WS24I* X9408WS I -40 to 85 24 Ld SOIC (300 mil)

X9408WS24IZ* (Note) X9408WS Z I -40 to 85 24 Ld SOIC (300 mil) (Pb-free)

X9408WV24* X9408WV 0 to 70 24 Ld TSSOP (4.4mm)

X9408WV24Z* (Note) X9408WV Z 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free)

X9408WV24I* X9408WV I -40 to 85 24 Ld TSSOP (4.4mm)

X9408WV24IZ* (Note) X9408WV Z I -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free)

X9408YP24I-2.7 X9408YP G 2.7 to 5.5 2.5 -40 to 85 24 Ld PDIP

X9408YS24-2.7* X9408YS F 0 to 70 24 Ld SOIC (300 mil)

X9408YS24Z-2.7* (Note) X9408YS Z F 0 to 70 24 Ld SOIC (300 mil) (Pb-free)

X9408YS24I-2.7* X9408YS G -40 to 85 24 Ld SOIC (300 mil)

X9408YS24IZ-2.7* (Note) X9408YS Z G -40 to 85 24 Ld SOIC (300 mil) (Pb-free)

X9408YV24-2.7* X9408YV F 0 to 70 24 Ld TSSOP (4.4mm)

X9408YV24Z-2.7* (Note) X9408YV Z F 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free)

X9408YV24I-2.7* X9408YV G -40 to 85 24 Ld TSSOP (4.4mm)

X9408YV24IZ-2.7T1 (Note) X9408YV Z G -40 to 85 24 Ld TSSOP (4.4mm) Tape and Reel

X9408WP24-2.7 X9408WP F 10 0 to 70 24 Ld PDIP

X9408WP24I-2.7 X9408WP G -40 to 85 24 Ld PDIP

X9408WS24-2.7* X9408WS F 0 to 70 24 Ld SOIC (300 mil)

X9408WS24Z-2.7* (Note) X9408WS Z F 0 to 70 24 Ld SOIC (300 mil) (Pb-free)

X9408WS24I-2.7* X9408WS G -40 to 85 24 Ld SOIC (300 mil)

X9408WS24IZ-2.7* (Note) X9408WS Z G -40 to 85 24 Ld SOIC (300 mil) (Pb-free)

X9408WV24-2.7* X9408WV F 0 to 70 24 Ld TSSOP (4.4mm)

X9408WV24Z-2.7* (Note) X9408WV Z F 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free)

X9408WV24I-2.7* X9408WV G -40 to 85 24 Ld TSSOP (4.4mm)

X9408WV24IZ-2.7* (Note) X9408WV Z G -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free)

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

(kΩ)

TEMP RANGE

(°C) PACKAGE

(Pb-free)

2

FN8191.3

December 9, 2005

X9408

www.BDTIC.com/Intersil

PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)

The SCL input is used to clock data into and out of the
X9408.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open col lector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.

Device Address (A

0

- A3)

The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9408. A maximum of 16 devices may occupy the
2-wire serial bus.

Potentiometer Pins

V

H/RH

The V

(VH0/R

H/RH

- VH3/RH3), VL/RL (VL0/R

H0

- VL3/RL3)

L0

and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.

V

W/RW (VW0/RW0

– VW3/RW3)

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

Hardware Write Protect Input (WP)

The WP pin when low prevents nonvolatile writes to
the Data Registers.

Analog Supplies V+, V-

The Analog Supplies V+, V- are the supply voltages
for the XDCP analog section.

PIN NAMES

Symbol Description

SCL Serial Clock
SDA Serial Data
A0-A3 Device Address
V

H0/RH0

V

L0/RL0

V

W0/RW0

- VH3/RH3,

- VL3/R

L3

- VW3/R

Potentiometer Pins
(terminal equivalent)

Potentiometer Pins

W3

(wiper equivalent)

WP

Hardware Write Protection
V+,V- Analog Supplies
V

CC

V

SS

System Supply Voltage

System Ground
NC No Connection

PIN CONFIGURATION

V

CC

VL0/R

L0

VH0/R

H0

VW0/R

W0

A

2

WP

SDA

A

1

VL1/R

L1

VH1/R

H1

VW1/R

W1

V

SS

DIP/SOIC

1
2
3
4
5
6
7
8
9

10

11
12

X9408

TSSOP

V+

24

V

23

L3/RL3

VH3/R

22
21
20
19
18
17
16

15
14
13

VW3/R
A

0

NC
A

3

SCL
V

L2/RL2

VH2/R
VW2/R

V-

H3

W3

H2

W2

VL1/R

VH1/R

VW1/R

VW2/R

VH2/R

V

L2/RL2

SDA

W1

V

W2

SCL

A

H1

SS

V-

H2

A

1
2

1

3

L1

4
5
6

X9408

7
8
9

10

11
12

3

WP

24

A

23
22
21
20
19
18
17
16
15

14

13

2

VW0/R
V

H0/RH0

VL0/R
V

CC

V+
V

L3/RL3

VH3/R
VW3/R

A

0

NC

W0

L0

H3

W3

3

FN8191.3

December 9, 2005

X9408

www.BDTIC.com/Intersil

PRINCIPLES OF OPERATION

The X9408 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.

Serial Interface

The X9408 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9408 will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods (t
SCL HIGH are reserved for indicating start and stop
conditions.

Start Condition

All commands to the X9408 are preceded by the start
condition, which is a HIGH to LOW transit ion of SDA
while SCL is HIGH (t
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.

). SDA state changes during

LOW

). The X9408 continuously

HIGH

The X9408 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9408 will respond with a final acknowledge.

Array Description

The X9408 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (R

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper

) output. Within each individual array only one

(R

W

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9408
this is fixed as 0101[B].

and RLinputs).

H

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transit ion of SDA
while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

4

Figure 1. Slave Address

Device Type

Identifier

100

The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9408 to respond with an acknowledge. The

- A3 inputs can be actively driven by CMOS input

A

0

signals or tied to V

1

A3 A2 A1 A0

Device Address

- A3 inputs. The X9408 compares

0

or VSS.

CC

FN8191.3

December 9, 2005

X9408

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Acknowledge Polling

The disabling of the inputs, during the internal
Nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9408
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9408 is still busy with the write operation no ACK will
be returned. If the X9408 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.

Flow 1. ACK Polling Sequence

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

YES

NO

Issue STOP

Figure 2. Instruction Byte Format

Register

Select

I1I2I3 I0 R1 R0 P1 P0

Instructions

Wiper Counter

Register Select

The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the four
registers that is to be acted upon when a register
oriented instruction is issued. The last bits (P1, P0)
select which one of the four potentiometers is to be
affected by the instruction.

Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the Wiper Counter Register
and one of the Data Registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
action will be delayed t

. A transfer from the Wiper

WRL

Counter Register (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

WR

between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all of the potentiometers
and one of their associated registers.

Further

Operation?

YES

Issue

Instruction

Proceed

NO

Issue STOP

Proceed

Instruction Structure

The next byte sent to the X9408 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the two pots and when applicable they
point to one of four associated registers. The format is
shown below in Figure 2.

Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9408; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are: Read Wiper Counter Register (read the current
wiper position of the selected pot), Write Wiper
Counter Register (change current wiper position of the
selected pot), Read Data Register (read the contents
of the selected nonvolatile register) and Write Data
Register (write a new value to the selected Data
Register). The sequence of operations is shown in
Figure 4.

5

FN8191.3

December 9, 2005

Figure 3. Two-Byte Instruction Sequence

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SCL

SDA

S

0101A3A2A1A0A
T
A
R
T

X9408

I3 I2 I1 I0 R1 R0 P1 P0 A
C
K

S

C

T

K

O
P

The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9408 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; ther eby, providing a fine
tuning capability to the host. For each SCL clock pulse

) while SDA is HIGH, the selected wiper will

(t

HIGH

move one resistor segment towards the R

terminal.

H

Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the R

terminal. A detailed illustration of the

L

sequence and timing for this operation are shown in
Figures 5 and 6 respectively.

Table 1. Instruction Set

Instruction Set

Instruction

Read Wiper Counter
Register

Write Wiper Counter
Register

0

100100P1P0Read the contents of the Wiper Counter Register

pointed to by P

101000P1P0Write new value to the Wiper Counter Register pointed

to by P

- P

1

0

OperationI3I2I1I0R1R0P1P

- P

1

0

Read Data Register 1 0 1 1 R1R0P1P0Read the contents of the Data Register pointed to by

- P0 and R1 - R

P

1

0

Write Data Register 1 1 0 0 R1R0P1P0Write new value to the Data Register pointed to by

- P0 and R1 - R

P

XFR Data Register to
Wiper Counter Register

1

1101R1R0P1P0Transfer the contents of the Data Register pointed to

- P0 and R1 - R0 to its associated Wipe r C ou nt er

by P

1

0

Register

XFR Wiper Counter

1110R
Register to Data
Register

Global XFR Data Regis-

0001R
ters to Wiper Counter
Registers

Global XFR Wiper

1000R
Counter Registers to
Data Register

Increment/Decrement

001000P
Wiper Counter Register

Note: (7) 1/0 = data is one or zero

1R0P1P0

1R0

1R0

0 0 Transfer the contents of the Data Registers pointed to by

0 0 Transfer the contents of both Wiper Counter Registers

1P0

Transfer the contents of the Wiper Counter Register
pointed to by P

- R

by R

1

0

- R0 of all four pots to their respective Wiper Counter

R

1

- P0 to the Data Register pointed to

1

Registers

to their respective Data Registers pointed to by

- R0 of all four pots

R

1

Enable Increment/decrement of the Wiper Counter
Register pointed to by P

- P

1

0

6

FN8191.3

December 9, 2005

Figure 4. Three-Byte Instruction Sequence

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SCL

SDA

X9408

S

0 1 0 1 A3 A2 A1 A0
T
A
R

T

Figure 5. Increment/Decrement Instruction Sequence

SCL

SDA

S

0 1 0 1 A3 A2 A1 A0
T
A
R
T

A

I3 I2 I1 I0 R1 R0 P1 P0
C
K

A

I3 I2 I1 I0 R0 P1 P0 A
C
K

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

Issued

SCL

R1

A

0 0 D5 D4 D3 D2 D1 D0
C
K

I
N
C
1

t

WRID

I
N
C

2

C
K

I
N
C
n

A

S

C

T

K

O
P

D
E
C
1

S

D

T

E

O

C

P

n

SDA

VW/R

W

7

Voltage Out

FN8191.3

December 9, 2005