intersil X9408 DATA SHEET

®

www.BDTIC.com/Intersil

X9408

Low Noise/Low Power/2-Wire Bus

Data Sheet FN8191.3December 9, 2005

Quad Digitally Controlled (XDCP™)
Potentiometers

FEATURES

• Four potentiometers in one package

• 64 resistor taps per potentiometer

• 2-wire serial interface

• Wiper resistance, 40Ω typical at 5V

• Four nonvolatile data registers for each pot

• Nonvolatile storage of wiper position

• Standby current < 1µA max (total package)
= 2.7V to 5.5V operation

•V

CC

V+ = 2.7V to 5.5V
V- = –2.7V to -5.5V

•10kΩ, 2.5kΩ end to end resistances

• High reliability

—Endurance–100,000 data changes per bit per

register

—Register data retention–100 years

• 24 Ld SOIC, 24 Ld TSSOP, 24 Ld PDIP packages

• Pb-free plus anneal available (RoHS compliant)

BLOCK DIAGRAM

V

CC

V

SS

WP

SCL

SDA

A0
A1
A2
A3

V+
V-

Interface

and

Control

Circuitry

Data

Pot 0

R0 R1

R2 R3

8

R0 R1

R2 R3

Wiper
Counter
Register

(WCR)

Wiper
Counter

Register

(WCR)

Resistor

Array
Pot 1

DESCRIPTION

The X9408 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user th rough the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and four
non-volatile Data Registers that can be directly written
to and read by the user. The contents of the WCR
controls the position of the wiper on the re sistor array
though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

VH0/

VL0/

VW0/

VW1/

V

H1

VL1/

R

H0

R

L0

R

W0

R

W1

/

R

H1

R

L1

R0 R1

R2 R3

R0 R1

R2 R3

Wiper
Counter
Register

(WCR)

Wiper
Counter
Register

(WCR)

Resistor

Array
Pot 2

Resistor

Array
Pot 3

V

H2

VL2/

VW2/

VW3/

V

H3

VL3/

/

R

H2

R

L2

R

W2

R

W3

/

R

H3

R

L3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9408

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Ordering Information

POTENTIOMETER

ORGANIZATION

PART NUMBER PART MARKING VCC LIMITS (V)

X9408YP24 X9408YP 5 ±10% 2.5 0 to 70 24 Ld PDIP

X9408YS24* X9408YS 0 to 70 24 Ld SOIC (300 mil)

X9408YS24Z* (Note) X9408YS Z 0 to 70 24 Ld SOIC (300 mil) (Pb-free)

X9408YS24I* X9408YS I -40 to 85 24 Ld SOIC (300 mil)

X9408YS24IZ* (Note) X9408YS Z I -40 to 85 24 Ld SOIC (300 mil) (Pb-free)

X9408YV24* X9408YV 0 to 70 24 Ld TSSOP (4.4mm)

X9408YV24Z* (Note) X9408YV Z 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free)

X9408YV24I* X9408YV I -40 to 85 24 Ld TSSOP (4.4mm)

X9408YV24IZ* (Note) X9408YV Z I -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free)

X9408WP24 X9408WP 10 0 to 70 24 Ld PDIP

X9408WP24I X9408WP I -40 to 85 24 Ld PDIP

X9408WS24* X9408WS 0 to 70 24 Ld SOIC (300 mil)

X9408WS24Z* (Note) X9408WS Z 0 to 70 24 Ld SOIC (300 mil) (Pb-free)

X9408WS24I* X9408WS I -40 to 85 24 Ld SOIC (300 mil)

X9408WS24IZ* (Note) X9408WS Z I -40 to 85 24 Ld SOIC (300 mil) (Pb-free)

X9408WV24* X9408WV 0 to 70 24 Ld TSSOP (4.4mm)

X9408WV24Z* (Note) X9408WV Z 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free)

X9408WV24I* X9408WV I -40 to 85 24 Ld TSSOP (4.4mm)

X9408WV24IZ* (Note) X9408WV Z I -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free)

X9408YP24I-2.7 X9408YP G 2.7 to 5.5 2.5 -40 to 85 24 Ld PDIP

X9408YS24-2.7* X9408YS F 0 to 70 24 Ld SOIC (300 mil)

X9408YS24Z-2.7* (Note) X9408YS Z F 0 to 70 24 Ld SOIC (300 mil) (Pb-free)

X9408YS24I-2.7* X9408YS G -40 to 85 24 Ld SOIC (300 mil)

X9408YS24IZ-2.7* (Note) X9408YS Z G -40 to 85 24 Ld SOIC (300 mil) (Pb-free)

X9408YV24-2.7* X9408YV F 0 to 70 24 Ld TSSOP (4.4mm)

X9408YV24Z-2.7* (Note) X9408YV Z F 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free)

X9408YV24I-2.7* X9408YV G -40 to 85 24 Ld TSSOP (4.4mm)

X9408YV24IZ-2.7T1 (Note) X9408YV Z G -40 to 85 24 Ld TSSOP (4.4mm) Tape and Reel

X9408WP24-2.7 X9408WP F 10 0 to 70 24 Ld PDIP

X9408WP24I-2.7 X9408WP G -40 to 85 24 Ld PDIP

X9408WS24-2.7* X9408WS F 0 to 70 24 Ld SOIC (300 mil)

X9408WS24Z-2.7* (Note) X9408WS Z F 0 to 70 24 Ld SOIC (300 mil) (Pb-free)

X9408WS24I-2.7* X9408WS G -40 to 85 24 Ld SOIC (300 mil)

X9408WS24IZ-2.7* (Note) X9408WS Z G -40 to 85 24 Ld SOIC (300 mil) (Pb-free)

X9408WV24-2.7* X9408WV F 0 to 70 24 Ld TSSOP (4.4mm)

X9408WV24Z-2.7* (Note) X9408WV Z F 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free)

X9408WV24I-2.7* X9408WV G -40 to 85 24 Ld TSSOP (4.4mm)

X9408WV24IZ-2.7* (Note) X9408WV Z G -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free)

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

(kΩ)

TEMP RANGE

(°C) PACKAGE

(Pb-free)

2

FN8191.3

December 9, 2005

X9408

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PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)

The SCL input is used to clock data into and out of the
X9408.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open col lector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.

Device Address (A

0

- A3)

The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9408. A maximum of 16 devices may occupy the
2-wire serial bus.

Potentiometer Pins

V

H/RH

The V

(VH0/R

H/RH

- VH3/RH3), VL/RL (VL0/R

H0

- VL3/RL3)

L0

and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.

V

W/RW (VW0/RW0

– VW3/RW3)

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

Hardware Write Protect Input (WP)

The WP pin when low prevents nonvolatile writes to
the Data Registers.

Analog Supplies V+, V-

The Analog Supplies V+, V- are the supply voltages
for the XDCP analog section.

PIN NAMES

Symbol Description

SCL Serial Clock
SDA Serial Data
A0-A3 Device Address
V

H0/RH0

V

L0/RL0

V

W0/RW0

- VH3/RH3,

- VL3/R

L3

- VW3/R

Potentiometer Pins
(terminal equivalent)

Potentiometer Pins

W3

(wiper equivalent)

WP

Hardware Write Protection
V+,V- Analog Supplies
V

CC

V

SS

System Supply Voltage

System Ground
NC No Connection

PIN CONFIGURATION

V

CC

VL0/R

L0

VH0/R

H0

VW0/R

W0

A

2

WP

SDA

A

1

VL1/R

L1

VH1/R

H1

VW1/R

W1

V

SS

DIP/SOIC

1
2
3
4
5
6
7
8
9

10

11
12

X9408

TSSOP

V+

24

V

23

L3/RL3

VH3/R

22
21
20
19
18
17
16

15
14
13

VW3/R
A

0

NC
A

3

SCL
V

L2/RL2

VH2/R
VW2/R

V-

H3

W3

H2

W2

VL1/R

VH1/R

VW1/R

VW2/R

VH2/R

V

L2/RL2

SDA

W1

V

W2

SCL

A

H1

SS

V-

H2

A

1
2

1

3

L1

4
5
6

X9408

7
8
9

10

11
12

3

WP

24

A

23
22
21
20
19
18
17
16
15

14

13

2

VW0/R
V

H0/RH0

VL0/R
V

CC

V+
V

L3/RL3

VH3/R
VW3/R

A

0

NC

W0

L0

H3

W3

3

FN8191.3

December 9, 2005

X9408

www.BDTIC.com/Intersil

PRINCIPLES OF OPERATION

The X9408 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.

Serial Interface

The X9408 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9408 will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods (t
SCL HIGH are reserved for indicating start and stop
conditions.

Start Condition

All commands to the X9408 are preceded by the start
condition, which is a HIGH to LOW transit ion of SDA
while SCL is HIGH (t
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.

). SDA state changes during

LOW

). The X9408 continuously

HIGH

The X9408 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9408 will respond with a final acknowledge.

Array Description

The X9408 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (R

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper

) output. Within each individual array only one

(R

W

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9408
this is fixed as 0101[B].

and RLinputs).

H

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transit ion of SDA
while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

4

Figure 1. Slave Address

Device Type

Identifier

100

The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9408 to respond with an acknowledge. The

- A3 inputs can be actively driven by CMOS input

A

0

signals or tied to V

1

A3 A2 A1 A0

Device Address

- A3 inputs. The X9408 compares

0

or VSS.

CC

FN8191.3

December 9, 2005

X9408

www.BDTIC.com/Intersil

Acknowledge Polling

The disabling of the inputs, during the internal
Nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9408
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9408 is still busy with the write operation no ACK will
be returned. If the X9408 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.

Flow 1. ACK Polling Sequence

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

YES

NO

Issue STOP

Figure 2. Instruction Byte Format

Register

Select

I1I2I3 I0 R1 R0 P1 P0

Instructions

Wiper Counter

Register Select

The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the four
registers that is to be acted upon when a register
oriented instruction is issued. The last bits (P1, P0)
select which one of the four potentiometers is to be
affected by the instruction.

Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the Wiper Counter Register
and one of the Data Registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
action will be delayed t

. A transfer from the Wiper

WRL

Counter Register (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

WR

between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all of the potentiometers
and one of their associated registers.

Further

Operation?

YES

Issue

Instruction

Proceed

NO

Issue STOP

Proceed

Instruction Structure

The next byte sent to the X9408 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the two pots and when applicable they
point to one of four associated registers. The format is
shown below in Figure 2.

Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9408; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are: Read Wiper Counter Register (read the current
wiper position of the selected pot), Write Wiper
Counter Register (change current wiper position of the
selected pot), Read Data Register (read the contents
of the selected nonvolatile register) and Write Data
Register (write a new value to the selected Data
Register). The sequence of operations is shown in
Figure 4.

5

FN8191.3

December 9, 2005

Figure 3. Two-Byte Instruction Sequence

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SCL

SDA

S

0101A3A2A1A0A
T
A
R
T

X9408

I3 I2 I1 I0 R1 R0 P1 P0 A
C
K

S

C

T

K

O
P

The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9408 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; ther eby, providing a fine
tuning capability to the host. For each SCL clock pulse

) while SDA is HIGH, the selected wiper will

(t

HIGH

move one resistor segment towards the R

terminal.

H

Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the R

terminal. A detailed illustration of the

L

sequence and timing for this operation are shown in
Figures 5 and 6 respectively.

Table 1. Instruction Set

Instruction Set

Instruction

Read Wiper Counter
Register

Write Wiper Counter
Register

0

100100P1P0Read the contents of the Wiper Counter Register

pointed to by P

101000P1P0Write new value to the Wiper Counter Register pointed

to by P

- P

1

0

OperationI3I2I1I0R1R0P1P

- P

1

0

Read Data Register 1 0 1 1 R1R0P1P0Read the contents of the Data Register pointed to by

- P0 and R1 - R

P

1

0

Write Data Register 1 1 0 0 R1R0P1P0Write new value to the Data Register pointed to by

- P0 and R1 - R

P

XFR Data Register to
Wiper Counter Register

1

1101R1R0P1P0Transfer the contents of the Data Register pointed to

- P0 and R1 - R0 to its associated Wipe r C ou nt er

by P

1

0

Register

XFR Wiper Counter

1110R
Register to Data
Register

Global XFR Data Regis-

0001R
ters to Wiper Counter
Registers

Global XFR Wiper

1000R
Counter Registers to
Data Register

Increment/Decrement

001000P
Wiper Counter Register

Note: (7) 1/0 = data is one or zero

1R0P1P0

1R0

1R0

0 0 Transfer the contents of the Data Registers pointed to by

0 0 Transfer the contents of both Wiper Counter Registers

1P0

Transfer the contents of the Wiper Counter Register
pointed to by P

- R

by R

1

0

- R0 of all four pots to their respective Wiper Counter

R

1

- P0 to the Data Register pointed to

1

Registers

to their respective Data Registers pointed to by

- R0 of all four pots

R

1

Enable Increment/decrement of the Wiper Counter
Register pointed to by P

- P

1

0

6

FN8191.3

December 9, 2005

Figure 4. Three-Byte Instruction Sequence

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SCL

SDA

X9408

S

0 1 0 1 A3 A2 A1 A0
T
A
R

T

Figure 5. Increment/Decrement Instruction Sequence

SCL

SDA

S

0 1 0 1 A3 A2 A1 A0
T
A
R
T

A

I3 I2 I1 I0 R1 R0 P1 P0
C
K

A

I3 I2 I1 I0 R0 P1 P0 A
C
K

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

Issued

SCL

R1

A

0 0 D5 D4 D3 D2 D1 D0
C
K

I
N
C
1

t

WRID

I
N
C

2

C
K

I
N
C
n

A

S

C

T

K

O
P

D
E
C
1

S

D

T

E

O

C

P

n

SDA

VW/R

W

7

Voltage Out

FN8191.3

December 9, 2005

Figure 7. Acknowledge Response from Receiver

www.BDTIC.com/Intersil

SCL from

Master

Data Output

from Transmitter

Data Output

from Receiver

1

X9408

89

START

Figure 8. Detailed Potentiometer Block Diagram

Serial Data Path
From Interface

Circuitry

Register 0 Register 1

8 6

Register 2 Register 3

If WCR = 00[H] then VW/RW = VL/R
If WCR = 3F[H] then VW/RW = VH/R

L

H

UP/DN

Modified SCL

Serial
Bus

Input

Parallel
Bus

Input

Counter
Register

INC/DEC

UP/DN
CLK

Wiper

(WCR)

Logic

Acknowledge

C
o

u
n

t

e

r

D

e
c
o
d

e

VH/R

VL/R

H

L

8

VW/R

W

FN8191.3

December 9, 2005

X9408

www.BDTIC.com/Intersil

DETAILED OPERATION

All XDCP potentiometers share the serial interface
and share a common architecture. Each potentiomete r
has a Wiper Counter Register and four Data
Registers. A detailed discussion of the register
organization and array operation follows.

Wiper Counter Register

The X9408 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The Wiper Counter
Register can be envisioned as a 6-bit parallel and
serial load counter with its outputs decoded to select
one of sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transfer ring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (DR0) upon power-up.

The WCR is a volatile register; that is, its contents are
lost when the X9408 is powered-down. Although the
register is automatically loaded with the value in R0
upon power-up, it should be noted this may be
different from the value present at power-do wn.

Data Registers

Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred bet ween any of the
four Data Registers and the WCR. It should be noted
all operations changing data in one of these registers
is a nonvolatile operation and will take a maximum of
10ms.

If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.

Register Descriptions

Data Registers, (6-Bit), Nonvolatile

D5 D4 D3 D2 D1 D0
NV NV NV NV NV NV

(MSB) (LSB)

Four 6-bit Data Registers for each XDCP. (sixteen 6­bit registers in total).

– {D5~D0}: These bits are for genera l pur pose n ot vol-

atile data storage or for storage of up to four differ­ent wiper values. The contents of Data Register 0
are automatically moved to the wiper counter regis­ter on power-up.

Wiper Counter Register, (6-Bit), Volatile

WP5 WP4 WP3 WP2 WP1 WP0

VVVVVV

(MSB) (LSB)

One 6-bit Wiper Counter Register for each XDCP.
(Four 6-bit registers in total.)

– {D5~D0}: These bits specify the wiper position of the

respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register 0.
The contents of the WCR can be loaded from any of
the other Data Register or directly. The contents of
the WCR can be saved in a DR.

9

FN8191.3

December 9, 2005

X9408

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Instruction Format

Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.

(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

Read Wiper Counter Register (WCR)

S

device type

T

identifier
A
R

0101

T

Write Wiper Counter Register (WCR)

device type

S

identifier

T
A
R

0101

T

Read Data Register (DR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

device

addresses

A3A2A1A

device

addresses

A3A2A1A

instruction

S

opcode

A
C

100100

K

0

instruction

S

opcode

A
C

101000

K

0

instruction

S

opcode

A
C

1011

K

0

WCR

addresses

P1P

0

WCR

addresses

P1P

0

DR and WCR

addresses

R1R0P1P

S

(sent by slave on SDA)

A
C

00WP

K

S

(sent by master on SDA)

A
C

00WP

K

S

(sent by slave on SDA)

A
C

00WP

K

0

wiper position

W

W

W

W

P

P

P

P

5

4

3

2

1

wiper position

W

W

W

W

P

P

P

P

5

4

3

2

1

wiper position/data

W

W

W

P

P

P

5

4

3

2

W

S

M

T

A

W

O

C

P

P

K

0

S

S

T

A

W

O

C

P

P

K

0

S

M

T

A

W

O

C

P

P

P

K

1

0

Write Data Register (DR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

S
A
C
K

0

instruction

opcode

1100

DR and WCR

addresses

R1R0P1P

0

S
A
C
K

XFR Data Register (DR) to Wiper Counter Register (WCR)

S

device type

T

identifier
A
R

0101

T

device

addresses

A3A2A1A

S
A
C
K

0

instruction

opcode

1101

DR and WCR

addresses

R1R0P1P

S
A
C
K

0

Write Wiper Counter Register (WCR) to Data Register (DR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

S
A
C
K

0

instruction

opcode

1110

DR and WCR

addresses

R1R0P1P

S
A
C
K

0

wiper position/data

(sent by master on SDA)

W

W

W

W

00WP

S
T
O
P

S

T
O
P

P

P

P

P

5

4

3

2

1

HIGH-VOLTAGE

WRITE CYCLE

W

P
0

S

S

HIGH-VOLTAGE

T

A

WRITE CYCLE

O

C

P

K

10

FN8191.3

December 9, 2005

X9408

www.BDTIC.com/Intersil

Increment/Decrement Wiper Counter Register (WCR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

instruction

S

opcode

A
C

001000

K

0

WCR

addresses

P1P

0

Global XFR Data Register (DR) to Wiper Counter Register (WCR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

S
A
C
K

0

instruction

opcode

0001

DR

addresses

R1R

00

0

Global XFR Wiper Counter Register (WCR) to Data Register (DR)

S

device type

T

identifier
A
R

0101

T

device

addresses

A3A2A1A

S
A
C
K

0

instruction

opcodeDRaddresses

1000

R1R

0

00

S
A
C
K

increment/decrement

S

(sent by master on SDA)

A
C

I/DI/

K

D

S

S

T

A

O

C

P

K

S

T

HIGH-VOLTAGE

O

WRITE CYCLE

P

....

I/DI/

S
T
O
P

D

SYMBOL TABLE Guidelines for Calculating Typical Values of Bus

Pull-Up Resistors

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

Resistance (Κ)

120
100

80
60

40
20

Min.
Resistance

0

20 40 60 80 100 120

0

Bus Capacitance (pF)

V

R

=

MIN

I

R

=

MAX

Max.
Resistance

CC MAX

OL MIN

t

R

C

BUS

=1.8kΩ

11

FN8191.3

December 9, 2005

X9408

www.BDTIC.com/Intersil

ABSOLUTE MAXIMUM RATINGS

Temperature under bias....................-65°C to +135°C

Storage temperature .........................-65°C to +150°C

Voltage on SDA, SCL or any address

input with respect to V
Voltage on V+ (referenced to V
Voltage on V- (referenced to V

......................... -1V to +7V

SS

)........................10V

SS

)........................-10V

SS

(V+) - (V-) ..............................................................12V

Any V

, VL/RL, VW/RW............................ V- to V+

H/RH

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.

Lead temperature (soldering, 10s) .................... 300°C

(10s)..............................................................±6mA

I

W

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C+70°C

Industrial -40°C+85°C

Device Supply Voltage (VCC) Limits

X9408 5V ± 10%

X9408-2.7 2.7V to 5.5V

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Limits

Symbol Parameter

R

TOTAL

I

W

R

W

V

V

V

V

V

TERM

C

H/CL/CW

I

AL

End to end resistance tolerance -20 +20 %
Power rating 50 mW 25°C, each pot
Wiper current -3 +3 mA
Wiper resistance 150 250 Ω IW = ± 1mA @ V+, V- = ±3V

40 100 Ω I

+ Voltage on V+ pin X9408 +4.5 +5.5 V

X9408-2.7 +2.7 +5.5

- Voltage on V- pin X9408 -5.5 -4.5 V
X9408-2.7 -5.5 -2.7

Voltage on any VH/RH, VL/RL or

W/RW

pin

(1)

(2)

TOTAL

V
Noise -120 dBV Ref: 1kHz
Resolution 1.6 % See Note 4
Absolute linearity

Relative linearity

Temperature coefficient of R
Ratiometric Temperature Coefficient 20 ppm/°C See Note 4
Potentiometer Capacitances 10/10/25 pF See Macro model
VH/RH, VL/RL, VW/RW Leakage

Current

V- V+ V

-1 +1 MI

-0.2 +0.2 MI

±300 ppm/°C See Note 4

0.1 10 µA VIN = V- to V+. Device is in

W

(3)

V(Vwn/Rwn)
V(V

(3)

V(V
[V(V

Stand-by mode.

Test ConditionMin. Typ. Max. Unit

= ± 1mA @ V+, V- = ±5V

(actual)

wn/Rwn)(expected)
w(n+1)/Rw(n+1)

w(n)/Rw(n)

) + MI]

-

) -

(4)

(4)

12

FN8191.3

December 9, 2005

X9408

www.BDTIC.com/Intersil

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter

I

CC1

VCC supply current (nonvolatile

1mAf

write)

I

CC2

VCC supply current (move wiper,

100 µA f

write, read)

I

SB

I

LI

I

LO

V

IH

V

IL

V

OL

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

VCC current (standby) 1 µA SCL = SDA = VCC, Addr. = V
Input leakage current 10 µA VIN = VSS to V
Output leakage current 10 µA V
Input HIGH voltage VCC x 0.7 VCC +0.5 V
Input LOW voltage –0.5 VCC x 0.1 V
Output LOW voltage 0.4 V IOL = 3mA

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-

eter. It is a measure of the error in step size.

(3) MI = RTOT

/ 63 or [V(V

) – V(VL/RL)] / 63, single pot

H/RH

Test ConditionsMin. Typ. Max. Unit

= 400kHz, SDA = Open,

SCL

Other Inputs = V

= 400kHz, SDA = Open,

SCL

Other Inputs = V

= VSS to V

OUT

SS

SS

CC

CC

SS

ENDURANCE AND DATA RETENTION

Parameter Min. Unit

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 years

CAPACITANCE

Symbol Test Max. Unit Test Condition

(4)

C

I/O

(4)

C

IN

Input/output capacitance (SDA) 8 pF V

I/O

= 0V

Input capacitance (A0, A1, A2, A3, and SCL) 6 pF VIN = 0V

POWER-UP TIMING

Symbol Parameter Min. Max. Unit

(5)

t

PUR

t

PUW

t

RVCC

(5)

(6)

Power-up to initiation of read operation 1 ms
Power-up to initiation of write operation 5 ms
VCC Power-up Ramp 0.2 50 V/msec

Power-up Requirements (Power-up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V-, then V

, and VW/RW. Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The V

V

L/RL

and V+, and then the potentiometer pins, VH/RH,

CC

CC

ramp rate specification should be met, and any glitches or slop e change s i n the VCC line should be held to <100mV if
possible. If V
for proper wiper register recall. Also, V
not be complete until V

Notes: (4) This parameter is periodically sampled and not 100% tested

(5) t

(6) This is not a tested or guaranteed parameter and should only be used as a guidance.

powers down, it should be held below 0.1V fo r more than 1 second befo re powe ring up aga in in order

CC

, V+ and V- reach their final value.

CC

and t

PUR

instruction can be issued. These parameters are periodically sampled and not 100% tested.

are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific

PUW

should not reverse polarity by more than 0.5V. Recall of wiper position will

CC

13

FN8191.3

December 9, 2005

X9408

www.BDTIC.com/Intersil

A.C. TEST CONDITIONS

nput pulse levels VCC x 0.1 to VCC x 0.9

I

Input rise and fall times 10ns
Input and output timing level V

CC

x 0.5

Circuit #3 SPICE Macro Model

R

VH/R

H

TOTAL

C

H

C

C

L

W

10pF

EQUIVALENT A.C. LOAD CIRCUIT

10pF

5V

1533Ω

SDA Output

100pF

V

W/RW

25pF

AC TIMING (over recommended operating condition)

Symbol Parameter Min. Max. Unit

f

SCL

t

CYC

t

HIGH

t

LOW

t

SU:STA

t

HD:STA

t

SU:STO

t

SU:DAT

t

HD:DAT

t

R

t

F

t

AA

t

DH

T

I

t

BUF

t

SU:WPA

t

HD:WPA

Clock frequency 400 kHz
Clock cycle time 2500 ns
Clock high time 600 ns
Clock low time 1300 ns
Start setup time 600 ns
Start hold time 600 ns
Stop setup time 600 ns
SDA data input setup time 100 ns
SDA data input hold time 30 ns
SCL and SDA rise time 300 ns
SCL and SDA fall time 300 ns
SCL low to SDA data output valid time 900 ns
SDA Data output hold time 50 ns
Noise suppression time constant at SCL and SDA inputs 50 ns
Bus free time (prior to any transmission) 1300 ns
WP, A0, A1, A2 and A3 setup time 0 ns
WP, A0, A1, A2 and A3 hold time 0 ns

VL/R

L

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Typ. M ax. Unit

t

WR

High-voltage write cycle time (store instructions) 5 10 ms

14

FN8191.3

December 9, 2005

X9408

www.BDTIC.com/Intersil

XDCP TIMING

Symbol Parameter Min. Max. Unit

t

WRPO

t

WRL

t

WRID

Notes: (9) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling

TIMING DIAGRAMS

START and STOP Timing

g

Wiper response time after the third (last) power supply is stable 10 µs
Wiper response time after instruction issued (all load instructions) 10 µs
Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 10 µs

edge of SCL.

(START) (STOP)

t

F

t

SU:STO

t

F

SCL

SDA

t

SU:STA

t

HD:STA

t

R

t

R

Input Timing

SCL

SDA

Output Timing

SCL

SDA

t

CYC

t

SU:DAT

t

AA

t

HIGH

t

HD:DAT

t

DH

t

LOW

t

BUF

15

FN8191.3

December 9, 2005

APPLICATIONS INFORMATION

www.BDTIC.com/Intersil

Basic Configurations of Electronic Potentiometers

V

R

Three terminal Potentiometer;
Variable voltage divider

Application Circuits

Noninverting Amplifier Voltage Regulator

X9408

+V

R

I

Two terminal Variable Resistor;
Variable current

V

S

VO = (1+R2/R1)V

Offset Voltage Adjustment Comparator with Hysteresis

V

S

10kΩ

R

100kΩ

-12V+12V

+
–

R

R

1

S

1

–
+

TL072

10kΩ10kΩ

V

O

2

R

2

V

O

IN

VO (REG) = 1.25V (1+R2/R1)+I

V

S

VUL = {R1/(R1+R2)} VO(max)
V

= {R1/(R1+R2)} VO(min)

LL

317

I

adj

R

2

–
+

}

}

R

R

2

1

R

1

adj R2

VO (REG)V

V

O

16

FN8191.3

December 9, 2005

Application Circuits (continued)

www.BDTIC.com/Intersil

Attenuator Filter

R

1

V

S

V

R

3

R

VO = G V

-1/2 ≤ G ≤ +1/2

Inverting Amplifier Equivalent L-R Circuit

R

R

1

S

}

4

All RS = 10kΩ

S

2

}

–
+

–
+

X9408

C

V

R

2

V

O

V

O

S

R

G

O

fc = 1/(2πRC)

C

1

V

S

R

1

= 1 + R2/R

+
–

R

1

R

2

+
–

V

O

2

VO = G V
G = - R2/R

R

Z

S

1

Function Generator

R

–
+

R

}

A

R

}

B

frequency ∝ R1, R2, C
amplitude ∝ R

2

, R

A

IN

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R

R

1

B

1

–
+

1

R

3

+ R3) >> R

C

2

17

FN8191.3

December 9, 2005

XDCP Timing (for All Load Instructions)

www.BDTIC.com/Intersil

SCL

X9408

(STOP)

SDA

VWx

XDCP Timing (for Increment/Decrement Instruction)

SCL

SDA

VWx

Wiper Register Address Inc/Dec Inc/Dec

Write Protect and Device Address Pins Timing

LSB

t

WRL

t

WRID

SCL

SDA

WP
A0, A1
A2, A3

(START) (STOP)

...

(Any Instruction)

...

...

t

SU:WPA

t

HD:WPA

18

FN8191.3

December 9, 2005

PACKAGING INFORMATION

www.BDTIC.com/Intersil

Pin 1 Index

Pin 1

X9408

24-Lead Plastic Dual In-Line Package Type P

1.265 (32.13)

1.230 (31.24)

1.100 (27.94)
Ref.

0.557 (14.15)

0.530 (13.46)

0.080 (2.03)

0.065 (1.65)

Seating

Plane

0.150 (3.81)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

Typ. 0.010 (0.25)

0.065 (1.65)

0.040 (1.02)

0.625 (15.87)

0.600 (15.24)

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.022 (0.56)

0.014 (0.36)

0°

15°

0.162 (4.11)

0.140 (3.56)

0.030 (0.76)

0.015 (0.38)

19

FN8191.3

December 9, 2005

PACKAGING INFORMATION

www.BDTIC.com/Intersil

24-Lead Plastic Small Outline Gull Wing Package Type S

X9408

0° - 8°

Pin 1 Index

(4X) 7°

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

0.015 (0.40)

0.050 (1.27)

Pin 1

X 45°

0.014 (0.35)

0.020 (0.50)

0.598 (15.20)

0.610 (15.49)

0.009 (0.22)

0.013 (0.33)

0.420"

0.290 (7.37)

0.299 (7.60)

0.003 (0.10)

0.012 (0.30)

0.050" Typical

0.393 (10.00)

0.420 (10.65)

0.092 (2.35)

0.105 (2.65)

0.050"

Typical

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

20

0.030" Typical
24 Places

FN8191.3

December 9, 2005

PACKAGING INFORMATION

www.BDTIC.com/Intersil

.026 (.65) BSC

X9408

24-Lead Plastic, TSSOP Package Type V

0° - 8°

.0075 (.19)
.0118 (.30)

.303 (7.70)
.311 (7.90)

.020 (.50)
.030 (.75)

Detail A (20X)

.169 (4.3)
.177 (4.5)

.047 (1.20)

.002 (.06)
.005 (.15)

.010 (.25)

Gage Plane

Seating Plane

.252 (6.4) BSC

(1.78)

(0.42)

(0.65)

(4.16)

(7.72)

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

ALL MEASUREMENTS ARE TYPICAL

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

21

FN8191.3

December 9, 2005