intersil X9400 DATA SHEET

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X9400

Low Noise/Low Power/SPI Bus

Data Sheet FN8189.3July 28, 2006

Quad Digitally Controlled Potentiometers (XDCP™)

FEATURES

• Four potentiometers per package

• 64 resistor taps

• SPI serial interface for write, read, and transfer operations of the potentiometer

• Wiper resistance, 40Ω typical at 5V.

• Four non-volatile data registers for each potentiometer

• Non-volatile storage of multiple wiper position

• Power-on recall. Loads saved wiper position on power-up.

• Standby current < 1µA max

•System V

•Analog V

•10kΩ, 2.5kΩ end to end resistance

• 100 yr. data retention

• Endurance: 100,000 data changes per bit per register

• Low power CMOS

• 24 Ld SOIC and 24 Ld TSSOP

• Pb-free plus anneal available (RoHS compliant)

: 2.7V to 5.5V operation

+/V–

: -5V to +5V

DESCRIPTION

The X9400 integrates four digitally controlled potentiometers (XDCPs) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI serial bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four nonvolatile Data Registers (DR0-3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power-up recalls the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

BLOCK DIAGRAM

V+

V-

HOLD

SCK

SI A0 A1

Interface

and

Control

Circuitry

Data

Pot 0

R0 R1

R2 R3

R0 R1

R2 R3

Wiper Counter Register

(WCR)

Wiper Counter

(WCR)

Resistor

Array Pot 1

VH0/R

VL0/R

VW0/R

VW1/R

H1/RH1

VL1/R

R0 R1

R2 R3

R0 R1

R2 R3

Wiper Counter Register

(WCR)

Wiper Counter Register

(WCR)

Resistor

Array Pot 2

Resistor

Array Pot 3

H2/RH2

VL2/R

VW2/R

VW3/R

H3/RH3

VL3/R

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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Ordering Information

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X9400

POTENTIOMETER

PART

PART NUMBER

X9400WS24* X9400WS 5 ±10% 10 0 to +70 24 Ld SOIC (300 mil) M24.3 X9400WS24ZT1

(Note) X9400WS24I* X9400WS I -40 to +85 24 Ld SOIC (300 mil) M24.3 X9400WS24IZ*

(Note) X9400WV24* X9400WV 0 to +70 24 Ld TSSOP (4.4mm) MDP0044 X9400WV24I* X9400WV I -40 to +85 24 Ld TSSOP (4.4mm) MDP0044 X9400WV24IZ*

(Note) X9400WV24Z*

(Note) X9400YS24* X9400YS 2.5 0 to +70 24 Ld SOIC (300 mil) M24.3 X9400YS24I* X9400YS I -40 to +85 24 Ld SOIC (300 mil) M24.3 X9400YV24* X9400YV 0 to +70 24 Ld TSSOP (4.4mm) MDP0044 X9400YV24I* X9400YV I -40 to +85 24 Ld TSSOP (4.4mm) MDP0044 X9400YV24IZ*

(Note) X9400YV24Z*

(Note) X9400WS24-2.7* X9400WS F 2.7 to 5.5 10 0 to +70 24 Ld SOIC (300 mil) M24.3 X9400WS24I-2.7* X9400WS G -40 to +85 24 Ld SOIC (300 mil) M24.3 X9400WS24IZ-2.7*

(Note) X9400WV24-2.7* X9400WV F 0 to +70 24 Ld TSSOP (4.4mm) MDP0044 X9400WV24I-2.7* X9400WV G -40 to +85 24 Ld TSSOP (4.4mm) MDP0044 X9400WV24IZ-2.7*

(Note) X9400WV24Z-2.7*

(Note) X9400YS24-2.7* X9400YS F 2.5 0 to +70 24 Ld SOIC (300 mil) M24.3 X9400YS24I-2.7* X9400YS G -40 to +85 24 Ld SOIC (300 mil) M24.3 X9400YV24-2.7* X9400YV F 0 to +70 24 Ld TSSOP (4.4mm) MDP0044 X9400YV24I-2.7* X9400YV G -40 to +85 24 Ld TSSOP (4.4mm) MDP0044 X9400YV24IZ-2.7*

(Note) X9400YV24Z-2.7*

(Note)

*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING

X9400WS Z 0 to +70 24 Ld SOIC (300 mil) (Pb-free)

X9400WS ZI -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3

X9400WV ZI -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9400WV Z 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9400YV ZI -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9400YV Z 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9400WS ZG -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3

X9400WV ZG -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9400WV ZF 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9400YV ZG -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9400YV ZF 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

LIMITS

(V)

ORGANIZATION

(kΩ)

TEMPERATURE

RANGE

(°C) PACKAGE PKG. DWG. #

M24.3

Tape and Reel

FN8189.3

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X9400

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PIN DESCRIPTIONS

Host Interface Pins

Serial Output (SO)

SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.

Serial Input

SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock.

Serial Clock (SCK)

The SCK input is used to clock data into and out of the X9400.

Chip Select (CS

When CS

is HIGH, the X9400 is deselected and the

)

SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS

LOW enables the X9400, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS

required prior to the start of any operation.

Hold (HOLD

HOLD

)

is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD

may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD

must

be brought LOW while SCK is LOW. To resume communication, HOLD

is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times.

Device Address (A

- A1)

The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9400. A maximum of 4 devices may occupy the SPI serial bus.

Potentiometer Pins

H/RH

L3/RL3

The V

(VH0/R

)

H/RH

- VH3/RH3), VL/RL (VL0/R

and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer.

W/RW

(VW0/R

- VW3/RW3)

The wiper outputs are equivalent to the wiper output of a mechanical potentiometer.

Hardware Write Protect Input (WP

The WP

pin when LOW prevents nonvolatile writes to

)

the Data Registers.

Analog Supplies (V+, V-)

The analog Supplies V+, V- are the supply voltages for the XDCP analog section.

PIN CONFIGURATION

VL0/R

VH0/R

VW0/R

VL1/R

VH1/R

VW1/R

SOIC

X9400

V+

L3/RL3

VH3/R

VW3/R

HOLD

SCK

L2/RL2

VH2/R

VW2/R

V-

VL1/R

VH1/R

VW1/R

VW2/R

VH2/R

L2/RL2

HOLD

SCK

V-

TSSOP

VW0/R

H0/RH0

VL0/R

V+

L3/RL3

VH3/R

VW3/R

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X9400

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PIN NAMES

Symbol Description

SCK Serial Clock

SI, SO Serial Data

- A

H0/RH0

L0/RL0

W0/RW0

NC No Connection

- VH3/RH3,

- VL3/R

- VW1/R

Device Address

Potentiometer Pins (terminal equivalent)

Potentiometer Pins (wiper

equivalent)

Hardware Write Protection

System Supply Voltage

System Ground

DEVICE DESCRIPTION

The X9400 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers.

Serial Interface

The X9400 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS LOW and the HOLD

and WP pins must be HIGH

must be

during the entire operation.

Wiper Counter Register (WCR)

The X9400 contains four Wiper Counter Registers, one for each XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register or global XFR data register instructions (parallel load); it can be modified one step at a time by the increment/decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9400 is powereddown. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down.

Data Registers

Each potentiometer has four 6-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms.

The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count.

Array Description

The X9400 is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (V

and VL/RL inputs).

H/RH

At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (V

) output. Within each individual array only one

W/RW

switch may be turned on at a time.

These switches are controlled by a wiper counter register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches.

If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data.

Data Register Detail

(MSB) (LSB)

D5 D4 D3 D2 D1 D0

NV NV NV NV NV NV

FN8189.3

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Figure 1. Detailed Potentiometer Block Diagram

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(One of Four Arrays)

X9400

Serial Data Path

From Interface

Circuitry

If WCR = 00[H] then VW/RW = VL/R

If WCR = 3F[H] then VW/RW = VH/R

Serial Bus

Input

8 6

UP/DN

Modified SCL

Parallel Bus

Input

Wiper Counter Register

(WCR)

INC/DEC

Logic

UP/DN

CLK

C o

u n

e c

o d e

VH/R

VL/R

VW/R

Write in Process

The contents of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a write in process bit (WIP). The WIP bit is read with a read status command.

INSTRUCTIONS

Identification (ID) Byte

The first byte sent to the X9400 from the host, following a CS

going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier, for the X9400 this is fixed as 0101[B] (refer to Figure 2).

The two least significant bits in the ID byte select one of four devices on the bus. The physical device address is defined by the state of the A

- A1 input

pins. The X9400 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9400 to successfully

continue the command sequence. The A

- A1 inputs

can be actively driven by CMOS input signals or tied to

or VSS.

The remaining two bits in the slave byte must be set to 0.

Figure 2. Identification Byte Format

Device Type

Identifier

100

0 0 A1 A0

Device Address

Instruction Byte

The next byte sent to the X9400 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of the four pots and, when applicable, they point to one of four associated registers. The format is shown below in Figure 3.

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Figure 3. Instruction Byte Format

Select

I1I2I3 I0 R1 R0 P1 P0

Instructions

The four high order bits of the instruction byte specify the operation. The next two bits (R one of the four registers that is to be acted upon when a register oriented instruction is issued. The last two bits (P potentiometers is to be affected by the instruction.

Four of the ten instructions are two bytes in length and end with the transmission of the instruction byte. These instructions are:

– XFR Data Register to Wiper Counter Register

– XFR Wiper Counter Register to Data Register

– Global XFR Data Register to Wiper Counter Register

– Global XFR Wiper Counter Register to Data Register

The basic sequence of the two byte instructions is illustrated in Figure 4. These two-byte instructions exchange data between the WCR and one of the data registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by t from the WCR (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register.

and P0) selects which one of the four

transfers the contents of one specified Data Register to the associated Wiper Counter Register.

This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register.

—This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers.

—This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers.

to complete. The transfer can occur

Pot Select

and R0) select

—This

—

. A transfer

WRL

Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9400; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are:

– Read Wiper Counter Register

wiper position of the selected pot,

– Write Wiper Counter Register

wiper position of the selected pot,

– Read Data Register

selected data register;

– Write Data Register

selected data register.

– Read Status

of the WIP bit which indicates if the internal write cycle is in progress.

The sequence of these operations is shown in Figure 5 and Figure 6.

The final command is Increment/Decrement. It is different from the other commands, because it’s length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse

) while SI is HIGH, the selected wiper will move

HIGH

one resistor segment towards the V Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the V

L/RL

sequence and timing for this operation are shown in Figure 7 and Figure 8.

—This command returns the contents

terminal. A detailed illustration of the

—read the contents of the

—write a new value to the

—read the current

—change current

terminal.

H/RH

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