intersil X93256 DATA SHEET

®

www.BDTIC.com/Intersil

X93256

Data Sheet February 1, 2008

Dual Digitally Controlled Potentiometers
(XDCPs™)

The Intersil X93256 is a dual digitally controlled
potentiometer (XDCP). The device consists of two resistor
arrays, wiper switches, a control section, and nonvolatile
memory. The wiper positions are controlled by individual
Up/Down interfaces.

A potentiometer is implemented by a resistor array
composed of 31 resistive elements and a wiper switching
network. The position of each wiper element is controlled by
a set of independent CS

, U/D, and INC inputs. The position
of the wiper can be stored in nonvolatile memory and then
be recalled upon a subsequent power-up operation.

Each potentiometer is connected as a three-terminal
variable resistor and can be used in a wide variety of
applications including:

• Bias and Gain Control

• LCD Contrast Adjustment

Pinout

X93256

(14 LD TSSOP)

TOP VIEW

Rw1

R

CS
INC
U/D

R

V

*NC can be left unconnected, or connected to
any voltage between V

L1

H2

SS

1

2

2

1

2

3

4
5

6
7

and VCC.

SS

14

13

12

11
10

R

H1

U/D

1

INC

1

V

CC

CS

2

R

9
8

L2

Rw2

Features

• Dual solid-state potentiometers

• Individual Up/Down interfaces

• 32 wiper tap points per potentiometer

- Wiper position stored in nonvolatile memory and
recalled on power-up

• 31 resistive elements per potentiometer

- Temperature compensated

- Maximum resistance tolerance of ±25%

- Terminal voltage, 0 to V

• Low power CMOS

-V

= 2.7V to 5.5V.

CC

- Active current, 200µA typical per potentiometer

- Standby current, 4µA max per potentiometer

• High reliability

- Endurance 200,000 data changes per bit

- Register data retention, 100 years

•R

value = 12.5kΩ, 50kΩ

TOTAL

• Package

- 14 Ld TSSOP

• Pb-free available (RoHS compliant)

CC

FN8188.2

Ordering Information

TEMPERATURE

PART NUMBER PART MARKING VCC LIMITS (V) R

X93256UV14I-2.7* X9325 6UVG 2.7 to 5.5 50 -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X93256UV14IZ-2.7*

(Note)
X93256WV14I-2.7* X9325 6WVG 12.5 -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X93256WV14IZ-2.7*

(Note)
*Add "T1" suffix for tape and reel.Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.

X9325 6UZG 50 -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173

X9325 6WZG 12.5 -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173

1

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2008. All Rights Reserved

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

TOTAL

(kΩ)

RANGE (°C) PACKAGE

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

PKG.

DWG. #

X93256

www.BDTIC.com/Intersil

Block Diagram

DETAILED SINGLE POTENTIOMETER DESCRIPTION

5-BIT
UP/DOWN
COUNTER

5-BIT

NONVOLATILE

MEMORY

STORE AND

CONTROL

RECALL

CIRCUITRY

UP/DOWN

(U/D

AND U/D2)

1

INCREMENT

(INC

AND INC2)

1

DEVICE SELECT

AND CS2)

(CS

1

GENERAL DESCRIPTION

(SUPPLY VOLTAGE)

V

CC

30k

CONTROL

AND

MEMORY

(GROUND)

V

SS

U/D1

INC

R

H1

R

W1

R

L1

R

H2

R

W2

R

L2

1

CS

1

V

CC

V

SS

Pin Descriptions

TSSOP SYMBOL BRIEF DESCRIPTION

1R

2R

3CS

4INC

5U/D

6R

7V
8R

9R

10 CS

11 V
12 INC

13 U/D

14 R

RW1. The RW1 pin of the X93256 is the wiper terminal of the first potentiometer, which is equivalent to the movable

W1

terminal of a mechanical potentiometer.

RL1. The R

L1

minimum voltage is V
the terminal in relation to wiper movement direction selected by the U/D

Chip Select 1 (CS1). The first potentiometer is selected when the CS1 input is LOW. The current counter value is stored

1

in nonvolatile memory when CS
complete, the first potentiometer of the X93256 will be placed in the low power standby mode until the first potentiometer

H1

and R

pins of the X93256 are equivalent to the fixed terminals of a mechanical potentiometer. The

L1

and the maximum is VCC. The terminology of RH1 and RL1 references the relative position of

SS

is returned HIGH while the INC1 input is also HIGH. After the store operation is

1

is selected once again.
Increment 2 (INC2). The INC2 input is negative-edge triggered. Toggling INC2 will move the wiper of the second

2

potentiometer and either increment or decrement the counter in the direction indicated by the logic level on the U/D
input.

Up/Down 2 (U/D2). The U/D2 input controls the direction of the second potentiometer wiper movement and whether the

2

counter for the second potentiometer is incremented or decremented.

RH2. The R

H2

minimum voltage is VSS and the maximum is VCC. The terminology of RH2 and RL2 references the relative position of

H2

and R

pins of the X93256 are equivalent to the fixed terminals of a mechanical potentiometer. The

L2

the wiper terminal for the second potentiometer in relation to the wiper movement direction selected by the U/D
Ground.

SS

RW2. The RW2 pin of the X93256 is the wiper terminal of the second potentiometer, which is equivalent to the movable

W2

terminal of a mechanical potentiometer.

RL2. The R

L2

minimum voltage is VSS and the maximum is VCC. The terminology of RH2 and RL2 references the relative position of

H2

and R

pins of the X93256 are equivalent to the fixed terminals of a mechanical potentiometer. The

L2

the wiper terminal for the second potentiometer in relation to the wiper movement direction selected by the U/D
Chip Select 2 (CS2). The second potentiometer is selected when the CS2 input is LOW. The current counter value is

2

stored in nonvolatile memory when CS

is returned HIGH while the INC2 input is also HIGH. After the store operation is

2

complete, the second potentiometer of the X93256 will be placed in the low power standby mode until the second
potentiometer is selected once again.

Supply Voltage.

CC

Increment 1(INC1). The INC1 input is negative-edge triggered. Toggling INC1 will move the wiper of the first

1

potentiometer and either increment or decrement the counter in the direction indicated by the logic level on the U/D
input.

Up/Down 1 (U/D1). The U/D1 input controls the direction of the first potentiometer wiper movement and whether the

1

counter for the first potentiometer is incremented or decremented.

RH1. The R

H1

minimum voltage is V
the wiper terminal for the first potentiometer in relation to the wiper movement direction selected by the U/D

H1

and R

pins of the X93256 are equivalent to the fixed terminals of a mechanical potentiometer. The

L1

and the maximum is VCC. The terminology of RH1 and RL1 references the relative position of

SS

ONE

OF

THIRTY

TWO

DECODER

input.

input.

1

R

H1

R

R

L1

input.

2

input.

2

W

2

1

31

30

29
28

TRANSFER

GATES

2

1
0

RESISTOR

ARRAY

2

FN8188.2

February 1, 2008

X93256

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Voltage on CS, INC, U/D, RH, RL and V

with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . .-1V to +6.5V

Maximum resistor current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA

CC

Recommended Operating Conditions

Temperature Range

Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V (Note 6)

V

CC

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:

1. Absolute linearity is utilized to determine actual wiper resistance vs expected resistance = (V
n = 1 .. 29 only.

2. Relative linearity is a measure of the error in step size between taps = V

3. 1 Ml = Minimum Increment = R

4. Typical values are for T

5. Limits established by characterization and are not production tested.

6. When performing multiple write operations, V

7. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.

= +25°C and nominal supply voltage.

A

TOT

/31.

must not decrease by more than 150mV from its initial value.

CC

Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Maximum reflow temperature (40s). . . . . . . . . . . . . . . . . . . . +240°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

H(n+1)

(actual) - V

H(n)

- [V

+ Ml] = ±0.5 Ml, n = 1 .. 29 only.

H(n)

(expected)) = ±1 Ml Maximum.

H(n)

Potentiometer Characteristics Over recommended operating conditions, unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS/NOTES

R

TOT

V

R

I

W

C

H/CL/CW

R

W

End-to-End Resistance W option 9.375 12.5 15.625 kΩ

U option 37.5 50 62.5 kΩ
RH, RL Terminal Voltages 0 V
Power Rating R

Noise Ref: 1kHz (Note 5) -120 dBV

Wiper Resistance ((Note 5) 1100 Ω
Wiper Current (Notes 5) 0.6 mA
Resolution 3%
Absolute Linearity (Note 1) V

Relative Linearity (Note 2) V

Temperature Coefficient (Note 5) ±35 ppm/°C

R

TOTAL

Potentiometer Capacitances See “Circuit #2 SPICE Macro Model” on

= 50kΩ (Note 5) 1 mW

TOTAL

H(n)(actual)

H(n+1)

page 4

- [V

H(n) + MI

- V

H(n)(expected)

] ±0.5 MI

MIN

(Note 7)

TYP

(Note 4)

10/10/25 pF

MAX

(Note 7) UNIT

CC

(Note 6)

(Note 6)

±1 MI

(Note 3)

(Note 3)

(Note 5)

V

3

FN8188.2

February 1, 2008

X93256

www.BDTIC.com/Intersil

DC Operating Characteristics

Over recommended operating conditions, unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

CC2

VCC Active Current (Increment) CS = VIL, U/D = VIL or VIH and

=0.4V @ max. t

VCC Active Current (Store)
(EEPROM Store)

INC
CS

= VIL, U/D = VIL or VIH and

INC

=0.4V @ max. t

CS = VIH, U/D = VIL or VIH and

=V

INC

@ max. t

IH

CYC VCC

CYC VCC

WR VCC

CS = VIH, U/D = VIL or VIH and

=V

@ max. t

IH

- 0.3V , U/D and INC = VSS or

CC

- 0.3V V

CC

WR VCC

= 3V

= VCC - 0.3V , U/D and INC = VSS or

- 0.3V V

CC

SS

to V

CC

= 5V

CC

I

SB

I

LI

I

LI

I

LI

I

LI

V

IH

V

IL

C

IN

(Note 6)

INC

Standby Supply Current CS = V

V

CC

CS
V

CC

CS input Leakage Current VIN = V
CS input Leakage Current VCC = 3V, CS = 0 60 100 150 µA
CS input Leakage Current VCC = 5V, CS = 0 120 200 250 µA
INC, U/D Input Leakage Current VIN = V
CS, INC, U/D input HIGH Voltage V
CS, INC, U/D input LOW Voltage -0.5 V

, INC, U/D Input Capacitance VCC = 3V, VIN = VSS, TA= +25°C,

CS

f = 1MHz (Note 5)

= 3V

= 5V

= 3V

= 5V

MIN

(Note 7)

TYP

(Note 4)

MAX

(Note 7) UNIT

50 250 µA

200 300

600 µA

1400 µA

1µA

4µA

±1 µA

±1 µA

x 0.7 VCC + 0.5 V

CC

x 0.1 V

CC

10 pF

Endurance and Data Retention

PARAMETER MIN UNIT

Minimum endurance 200,000 Data changes per bit

Data retention 100 Years

AC Conditions of Test

Input pulse levels 0V to 3V
Input rise and fall times 10ns
Input reference levels 1.5V

Test Circuit #1 Circuit #2 SPICE Macro Model

TEST POINT

VH/R

H

R

H

10pF

R

TOTAL

C

C

H

W

25pF

C

10pF

R

L

L

AC Operating Characteristics Over recommended operating conditions, unless otherwise specified. In the table, CS, INC, U/D, R

are used to refer to either CS1 or CS2, etc.

R

L

SYMBOL PARAMETER

t

Cl

t

lD

t

DI

t

t

lH

CS to INC Setup 100 ns
INC HIGH to U/D Change 100 ns
U/D to INC Setup 100 ns
INC LOW Period 1 µs

lL

INC HIGH Period 1 µs

MIN

(Note 7)

TYP

(Note 4)

MAX

(Note 7) UNIT

H

and

4

FN8188.2

February 1, 2008

X93256

www.BDTIC.com/Intersil

AC Operating Characteristics Over recommended operating conditions, unless otherwise specified. In the table, CS, INC, U/D, R

are used to refer to either CS1 or CS2, etc. (Continued)

R

L

SYMBOL PARAMETER

t

lC

t

CPH

t

CPH

t

CYC

t

R, tF

(Note 5)

t

R VCC

(Note 5)

t

WR

INC Inactive to CS Inactive 1 µs
CS Deselect Time (No store) 250 ns
CS Deselect Time (Store) 10 ms
INC Cycle Time 2 µs
INC

Input Rise and Fall time 500 µs

VCC Power-up Rate 0.2 50 V/ms

Store Cycle 510ms

MIN

(Note 7)

TYP

(Note 4)

MAX

(Note 7) UNIT

AC Timing

CS

t

INC

CYC

t

CI

t

IL

t

IH

t

IC

(STORE)

t

CPH

90% 90%

10%

H

and

t

ID

U/D

Note: CS, INC, U/D, RH and RL are used to refer
to either CS

or CS2, etc.

1

t

DI

Power-up and Power-down Requirements

There are no restrictions on the power-up or power-down
conditions of V
potentiometer pins provided that V
positive than or equal to V
V

ramp rate specification is always in effect.

CC

and the voltages applied to the

CC

and VL, i.e., VCC ≥ VH,VL. The

H

is always more

CC

Pin Descriptions

In the text, CS, INC, U/D, RH, RW, and RL are used to refer
to either CS
applied independently or at the same time.

RH and R

The R
fixed terminals of a mechanical potentiometer. The minimum
voltage is V
R

and R

H

relation to wiper movement direction selected by the U/D
input per potentiometer.

or CS2, etc. Note: These signals can be

1

L

and RL pins of the X93256 are equivalent to the

H

and the maximum is VCC. The terminology of

SS

references the relative position of the terminal in

L

t

F

t

R

Up/Down (U/D)

The U/D input controls the direction of a single
potentiometer’s wiper movement and whether the counter is
incremented or decremented.

Increment (INC)

The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
pertaining potentiometer’s counter in the direction indicated
by the logic level on the pertaining potentiometer’s U/D
input.

Chip Select (CS)

A potentiometer is selected when the pertaining CS input is
LOW. Its current counter value is stored in nonvolatile memory
when the pertaining CS
INC

input is also HIGH. After the store operation is complete
the affected potentiometer will be placed in the low power
standby mode until the potentiometer is selected once again.

is returned HIGH while the pertaining

R

W

The R

pin of the X93256 is the wiper terminal of the

W

potentiometer, which is equivalent to the movable terminal of
a mechanical potentiometer.

Principles of Operation

There are multiple sections for each potentiometer in the
X93256: an input control, a counter and decode section; the
nonvolatile memory; and a resistor array. Each input control

5

FN8188.2

February 1, 2008

X93256

www.BDTIC.com/Intersil

section operates just like an up/down counter. The output of
this counter is decoded to turn on a single electronic switch
connecting a point on the resistor array to the wiper outpu t.
Under the proper conditions, the contents of the counter can
be stored in nonvolatile memory and retained for future use.
Each resistor array is comprised of 31 individual resistors
connected in series. At either end of the array and between
each resistor is an electronic switch that transfers the
connection at that point to the wiper.

Each wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.

If the wiper is moved several positions, multiple taps are
connected to the wiper for t

(INC to VW change). The

IW

2-terminal resistance value for the device can temporarily
change by a significant amount if the wiper is moved several
positions.

When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory for each
potentiometer. When power is restored, the contents of the
memory are recalled and each wiper is set to the value last
stored.

Instructions and Programming

The INC, U/D and CS inputs control the movement of the
pertaining wiper along the resistor array. With CS
the pertaining potentiometer is selected and enabled to
respond to the U/D
on INC

will increment or decrement (depending on the state

of the U/D

input) a 5-bit counter. The output of this counter is

and INC inputs. HIGH to LOW transitions

decoded to select one of thirty two wiper positions along the
resistive array.

The value of the counter is stored in nonvolatile memory
whenever each CS
INC

input is also HIGH. In order to avoid an accidental store
during power-up, each CS
initial power-up. When left open, each CS
pulled up to V

transitions HIGH while the pertaining

must go HIGH with VCC during

pin is internally

by an internal 30k resistor.

CC

The system may select the X93256, move any wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as previously described and once the new
position is reached, the system must keep INC
taking CS

HIGH. The new wiper position will be maintained
until changed by the system or until a power-up/down cycle
recalled the previously stored data. In order to recall the
stored position of the wiper on po wer-up, the CS
held HIGH.

set LOW

LOW while

pin must be

parameter changes due to temperature drift, or other system
trim requirements.

The state of U/D

may be changed while CS remains LOW.
This allows the host system to enable the device and then
move each wiper up and down until the proper trim is
attained.

Mode Selection

CS INC U/D MODE

L H Wiper Up
L L Wiper Down

H X Store Wiper Position

H X X Standby Current

L X No Store, Return to Standby
L H Wiper Up (not recommended)
L L Wiper Down (not recommended)

Symbol Table

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments could be made. The
adjustments might be based on user preference, system

6

FN8188.2

February 1, 2008

X93256

www.BDTIC.com/Intersil

Thin Shrink Small Outline Plastic Packages (TSSOP)

N

INDEX
AREA

123

0.05(0.002)

-A­D

e

b

0.10(0.004) C AM BS

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen­sion at maximum material condition. Minimum space between protru­sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)

E1

-B-

SEATING PLANE

A

-C-

M

0.25(0.010) BM M

E

α

A1

0.10(0.004)

GAUGE

PLANE

0.25

0.010

A2

L

c

M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.041 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.195 0.199 4.95 5.05 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N14 147

o

α

0

o

8

o

0

o

8

NOTESMIN MAX MIN MAX

-

Rev. 2 4/06

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

7

FN8188.2

February 1, 2008