intersil X9318 DATA SHEET

®

www.BDTIC.com/Intersil

X9318

Data Sheet September 14, 2005

Digitally Controlled Potentiometer
(XDCP™)

FEATURES

• Solid-state potentiometer

• 3-wire serial interface

• Terminal voltage, 0 to +8V

• 100 wiper tap points
—Wiper position stored in nonvolatile memory

and recalled on power-up

• 99 resistive elements
—Temperature compensated
—End to end resistance range ± 20%

• Low power CMOS

CC

TOTAL

= 5V

value = 10kΩ

—V
—Active current, 3mA max.
—Standby current, 1mA max.

• High reliability
—Endurance, 100,000 data changes per bit
—Register data retention, 100 years

•R

• Packages
—8 Ld SOIC and DIP

• Pb-free plus anneal available (RoHS compliant)

APPLICATIONS

FN8184.1

DESCRIPTION

The Intersil X9318 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory.
The wiper position is controlled by a 3-wire interface.

The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switch­ing network. Between each element and at either end
are tap points accessible to the wiper terminal. The
position of the wiper element is controlled by the CS

, and INC inputs. The position of the wiper can be

U/D
stored in nonvolatile memory and then be recalled
upon a subsequent power-up operation.

The device can be used as a three-terminal potentiome­ter for voltage control or as a two-terminal variable resis­tor for current control in a wide variety of applications.

PIN CONFIGURATION

DIP/SOIC

INC
U/D

R

V

SS

1
2

X9318

3

H

4

V

8

CC

CS

7

R

6
5

L

R

W

,

• LCD bias control

• DC bias adjustment

• Gain and offset trim

• Laser diode bias control

• Voltage regulator output control

BLOCK DIAGRAM

V

(Supply Voltage)

CC

Up/Down

(U/D

)

Increment

(INC

Device Select

(CS

Control

Memory

V

SS

General

and

(Ground)

)

)

U/D
INC

CS

R

H

R

W

R

L

V

CC

V

SS

Up/Down

Counter

7-Bit

Nonvolatile

Memory

Store and

Recall

Control

Circuitry

One

of

One
Hundred
Decoder

99

98
97
96

2

1
0

Detailed

Wiper

Switches

Resistor

Array

R

H

R

L

R

W

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Ordering Information

www.BDTIC.com/Intersil

X9318

PART NUMBER PART MARKING R

X9318WP8 X9318WP 10 0 to 70 8 Ld PDIP

X9318WP8I X9318WP I -40 to 85 8 Ld PDIP

X9318WS8* X9318W 0 to 70 8 Ld SOIC (150 mil)

X9318WS8Z* (Note) X9318W Z 0 to 70 8 Ld SOIC (150 mil) (Pb-free)

X9318WS8I* X9318W I -40 to 85 8 Ld SOIC (150 mil)

X9318WS8IZ* (Note) X9318W Z I -40 to 85 8 Ld SOIC (150 mil) (Pb-free)

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

(kΩ) TEMP RANGE (°C) PACKAGE

TOTAL

PIN DESCRIPTIONS

DIP/SOIC Symbol Brief Description

1INCIncrement. Toggling INC while CS is low moves the wiper either up or down.
2U/D
3R
4V

SS

5R
6

R

7CS
8V

CC

Up/Down. The U/D input controls the direction of the wiper movement.
The high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.

H

Ground.

The wiper terminal is equivalent to the movable terminal of a mechanical potentiometer.

W

The low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.

L

Chip Select. The device is selected when the CS input is LOW, and de-selected when CS is high.
Supply Voltage.

2

FN8184.1

September 14, 2005

X9318

www.BDTIC.com/Intersil

ABSOLUTE MAXIMUM RATINGS

Junction Temperature under bias...... -65°C to +135°C

Storage temperature ......................... -65°C to +150°C

Voltage on CS

, INC, U/D and V

CC

with respect to VSS................................. -1V to +7V

, RW, RL to ground..........................................+10V

R

H

Lead temperature (soldering 10s) ..................... 300°C

(10s)..............................................................±6mA

I

W

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con­ditions for extended periods may affect device reliability.

POTENTIOMETER CHARACTERISTICS

= 5V ± 10%, TA = Full Operating Temperature Range unless otherwise stated)

(V

CC

Limits

Symbol Parameter

End to end resistance tolerance -20 +20 % See ordering information

V

RH/RL

R

I

W

C

H/CL/CW

W

)

RH/RL terminal voltage V
Power rating 25 mW
Wiper resistance 40 200 Ω IW = 1mA
Wiper current

(7)

Noise
Resolution 1 %
Absolute linearity
Relative linearity
R

TOTAL

Ratiometric temperature coeffi-

(5),(6)

cient

(5

Potentiometer capacitances 10/10/25 pF See equivalent circuit

(5)

(1)

(2)

temperature coefficient

SS

-3.0 +3.0 mA See test circuit

-1 +1 MI

-0.2 +0.2 MI

(5)

-20 +20 ppm/°C

(4)

-120 dBV Ref: 1kHz

±300 ppm/°C

Max. Unit

8VV

(3)
(3)

Test Conditions/NotesMin. Typ.

for values

SS

V(RH) = 8V,
V(RL) = 0V

= 0V

V

CC

Supply Voltage 4.5 5.5 V

3

FN8184.1

September 14, 2005

X9318

www.BDTIC.com/Intersil

D.C. OPERATING CHARACTERISTICS

= 5V ± 10%, TA = Full Operating Temperature Range unless otherwise stated)

(V

CC

Limits

Symbol Parameter

I

CC

I

SB

I

LI

V

IH

V

IL

C

IN

VCC active current (Increment) 1 3 mA CS = VIL, U/D = VIL or VIH and

Standby supply current 300 1000 µA CS ≥ 2.4V, U/D and INC =0.4V

CS, INC, U/D input leakage current -10 +10 µA VIN = V
CS, INC, U/D input HIGH voltage 2 VCC + 1 V
CS, INC, U/D input LOW voltage -1 0.8 V

(5)

CS, INC, U/D input capacitance 10 pF V

ENDURANCE AND DATA RETENTION

(V

= 5V ± 10%, TA = Full Operating Temperature Range)

CC

Parameter Min. Unit

Minimum endurance 100,000 Data changes per bit

Data retention 100 Years

(4)

Max.

Unit Test ConditionsMin. Typ.

= 0.4V/2.4V @ min. t

INC

CYC

RL, RH, RW not connected

, RH, RW not connected

R

L

to V

SS

= 5V, VIN = VSS, TA = 25°C,

CC

CC

f = 1MHz

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(R

V(R

W(n)(expected)

(2) Relative linearity is a measure of the error in step size between taps = [V(R
(3) 1 Ml = Minimum Increment = [V(R
(4) Typical values are for T
(5) This parameter is not 100% tested.
(6) Ratiometric temperature coefficient = (V(R

from 0 to 99.

(7) Measured with wiper at tap position 31, R

) = n(V(RH) - V(RL))/99 + V(RL), with n from 0 to 99.

) - V(RL)]/99.

= 25°C and nominal supply voltage.

A

H

- V(RW)

W)T1(n)

grounded, using test circuit.

L

T2(n)

)/[V(RW)

) - (V(R

W(n+1)

(T1 - T2) x 106], with T1 & T2 being 2 temperatures, and n

T1(n)

W(n)

Test Circuit Equivalent Circuit

R

Test Point

R

W

Force
Current

R

H

10pF

TOTAL

C

C

H

W

25pF

R

W

C

10pF

R

L

L

A.C. CONDITIONS OF TEST

Input pulse levels 0.8V to 2.0V
Input rise and fall times 10ns
Input reference levels 1.4V

W(n)(actual)

) - MI)]/MI

) - V(R

W(n)(expected)

)]/MI

4

FN8184.1

September 14, 2005

X9318

www.BDTIC.com/Intersil

A.C. OPERATING CHARACTERISTICS

= 5V ± 10%, TA = Full Operating Temperature Range unless otherwise stated)

(V

CC

Symbol Parameter

t

Cl

t

lD

t

DI

t

lL

t

lH

t

lC

t

CPHS

t

CPHNS

)

(5)
(5)

CS to INC setup 100 ns
INC HIGH to U/D change 100 ns
U/D to INC setup 1 µs
INC LOW period 1 µs
INC HIGH period 1 µs
INC inactive to CS inactive 1 µs
CS deselect time (STORE) 20 ms

(5

CS deselect time (NO STORE) 1 µs

Limits

(4)

Max.

UnitMin. Typ.

t

IW

t

CYC

t

t

,

R

t

PU

t

R VCC

F

INC to RW change 100 500 µs
INC cycle time 4 µs

(5)

INC input rise and fall time 500 µs

(5)

Power-up to wiper stable 500 µs

(5)

VCC power-up rate 0.2 50 V/ms

POWER-UP AND DOWN REQUIREMENTS

The recommended power-up sequence is to apply V

CC/VSS

the data sheet parameters for the DCP do not fully apply until 1 millisecond after V

first, then the potentiometer voltages. During power-up,

reaches its final value. The V

CC

CC

ramp spec is always in effect. In order to prevent unwanted tap position changes, or an inadvertant store, bring the

and INC high before or concurrently with the VCC pin on powerup.

CS

A.C. TIMING

CS

t

INC

CYC

t

CI

t

IL

t

ID

t

IH

t

IC

t

DI

t

CPHS

t

F

90% 90%

10%

t

CPHNS

t

R

U/D

t

IW

(3)

R

W

MI

5

FN8184.1

September 14, 2005

X9318

www.BDTIC.com/Intersil

PIN DESCRIPTIONS
R

and R

H

L

The high (RH) and low (RL) terminals of the X9318 are
equivalent to the fixed terminals of a mechanical
potentiometer. The terminology of R

and RH refer-

L

ences the relative position of the terminal in relatio n to
wiper movement direction selected by the U/D

input

and not the voltage potential on the terminal.

R

W

Rw is the wiper terminal and is equivalent to the mov­able terminal of a mechanical potentiometer. The posi­tion of the wiper within the array is determined by the
control inputs. The wiper terminal series resistance is
typically 40Ω.

Up/Down (U/D

The U/D

)

input controls the direction of the wiper move­ment and whether the counter is incremented or dec­remented.

Increment (INC

The INC
INC

input is negative-edge triggered. Toggling

will move the wiper and either increment or decre-

)

ment the counter in the direction indicated by the logic
level on the U/D

Chip Select (CS

The device is selected when the CS

input.

)

input is LOW. The
current counter value is stored in nonvola tile memory
when CS

is returned HIGH while the INC input is also
HIGH. After the store operation is complete the X9318
will be placed in the low power standby mode until the
device is selected once again.

PIN CONFIGURATION

DIP/SOIC

INC
U/D

R

V

SS

1
2

X9318

3

H

4

V

8

CC

CS

7

R

6

L

R

5

W

PIN NAMES

Symbol Description

R

R

W

R

V

SS

V

CC

U/D
INC

CS

H

L

High terminal
Wiper terminal
Low terminal
Ground
Supply voltage
Up/Down control input
Increment control input
Chip select control input

PRINCIPLES OF OPERATION

There are three sections of the X9318: the control
section, the nonvolatile memory, and the resistor
array. The control section operates just like an
up/down counter. The output of this counter is
decoded to turn on a single electronic switch
connecting a point on the resistor array to the wiper
output. The contents of the counter can be stored in
nonvolatile memory and retained for future use. The
resistor array is comprised of 99 individual resistors
connected in series. Electronic switches at either end
of the array and between each resistor provide an
electrical connection to the wiper pin, R

W

.

The wiper acts like its mechanical equivalent and does
not move beyond the first or last position. That is, the
counter does not wrap around when clocked to either
extreme.

The electronic switches on the device operate in a
“make before break” mode when the wiper changes
tap positions. If the wiper is moved several positions,
multiple taps are connected to the wiper for t

change). The R

V

W

value for the device can

TOTAL

(INC to

IW

temporarily be reduced by a significant amount if the
wiper is moved several positions.

When the device is powered-down, the last wiper posi­tion stored will be maintained in the nonvolatile mem­ory. When power is restored, the contents of the
memory are recalled and the wiper is set to the value
last stored.

6

FN8184.1

September 14, 2005

X9318

www.BDTIC.com/Intersil

INSTRUCTIONS AND PROGRAMMING

The INC
the wiper along the resistor array. With CS
the device is selected and enabled to respond to the
U/D
will increment or decrement (depending on the state of
the U/D
counter is decoded to select one of one hundred wiper
positions along the resistive array.

The value of the counter is stored in nonvola tile mem­ory whenever CS
is also HIGH.

The system may select the X9318, move the wiper
and deselect the device without having to store the lat­est wiper position in nonvolatile memory. After the
wiper movement is performed as described above and
once the new position is reached, the system must
keep INC
position will be maintained until changed by the sys­tem or until a powerup/down cycle recalled the previ­ously stored data.

This procedure allows the system to always power-up
to a preset value stored in nonvolatile memory; then
during system operation minor adjustments could be
made. The adjustments might be based on user pref­erence, system parameter changes due to tempera­ture drift, etc.

, U/D and CS inputs control the movement of

set LOW

and INC inputs. HIGH to LOW transitions on INC

input) a seven bit counter. The output of this

transitions HIGH while the INC input

LOW while taking CS HIGH. The new wiper

MODE SELECTION

INC U/D Mode

CS

L H Wiper up
L L Wiper down

HX

H X X Standby

L X No store, return to standby
L H Wiper Up (not recommended)

LL

Store wiper position to
nonvolatile memory

Wiper Down
(not recommended)

The state of U/D
LOW. This allows the host system to enable the
device and then move the wiper up and down until the
proper trim is attained.

may be changed while CS remains

7

FN8184.1

September 14, 2005

X9318

www.BDTIC.com/Intersil

APPLICATIONS INFORMATION

Electronic digitally controlled (XDCP) potentiometers provide three powerful application advantages; (1) the variability
and reliability of a solid-state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity
of nonvolatile memory used for the storage of multiple potentiometer settings or data.

Basic Configurations of Electronic Potentiometers

V

REF

R

H

R

W

R

L

V

REF

I

Basic Circuits

R

+V

IN

1

V

REF

Voltage Regulator

I

adj

Three terminal potentiometer;
variable voltage divider

+5V

317

R

W

V

R

2

OUT

R

+
–

= VW/R

1

LMC7101

V

W

VO (REG)V

OUT

Cascading TechniquesBuffered Reference Voltage

+V +V

R

W

+V

(a) (b)

Offset Voltage Adjustment

R

+12V

–
+

LMC7101

V

S

10kΩ

R

1

100kΩ

Two terminal variable resistor;
variable current

Single Supply Inverting Amplifier

R

R

1

V

S

X

100K

+8V

R

W

Comparator with Hysteresis

2

V

O

LT311A

V

S

}

R

1

2

–
+

100K

VO = (R2/R1)V

–
+

}

R

2

+8V

LMC7101

V

O

S

V

O

10kΩ10kΩ

VO (REG) = 1.25V (1+R2/R1)+I

adj R2

+12V

8

= {R1/(R1+R2)} VO(max)

V

UL

= {R1/(R1+R2)} VO(min)

V

LL

(for additional circuits see AN115)

FN8184.1

September 14, 2005

PACKAGING INFORMATION

www.BDTIC.com/Intersil

8-Lead Plastic Small Outline Package, Type S (8-lead SOIC)

X9318

Pin 1 Index

(4X) 7°

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

Pin 1

X 45°

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

0.150 (3.80)

0.158 (4.00)

0.004 (0.19)

0.010 (0.25)

0.228 (5.80)

0.244 (6.20)

0.053 (1.35)

0.069 (1.75)

0.050"Typical

0° - 8°

0.0075 (0.19)

0.010 (0.25)

0.016 (0.410)

0.037 (0.937)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.250"

9

0.050"
Typical

0.030"

Typical

8 PlacesFOOTPRINT

FN8184.1

September 14, 2005

PACKAGING INFORMATION

www.BDTIC.com/Intersil

Half Shoulder Width On

All End Pins Optional

X9318

8-Lead Plastic, DIP, Package Code P8

0.430 (10.92)

0.360 (9.14)

0.260 (6.60)

0.240 (6.10)

Pin 1 Index

Pin 1

0.300

(7.62) Ref.

Seating
Plane

0.150 (3.81)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

0.065 (1.65)

0.045 (1.14)

0.020 (0.51)

0.016 (0.41)

0.060 (1.52)

0.020 (0.51)

0.145 (3.68)

0.128 (3.25)

0.025 (0.64)

0.015 (0.38)

.073 (1.84)

Max.

Typ. 0.010 (0.25)

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.325 (8.25)

0.300 (7.62)

0°

15°

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

10

FN8184.1

September 14, 2005