intersil X93155 DATA SHEET

®

www.BDTIC.com/Intersil

X93155

Data Sheet February 19, 2008

Digitally Controlled Potentiometer
(XDCP™)

The Intersil X93155 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a 3-wire interface.

The potentiometer is implemented by a resistor array
composed of 31 resistive elements and a wiper switching
network. The position of the wiper element is controlled by
the CS

, U/D, and INC inputs. The position of the wiper can
be stored in nonvolatile memory and then be recalled upon
during a subsequent power-up operation.

The device is connected as a two-terminal variable resistor
and can be used in a wide variety of applications including:

- Bias and Gain Control

- LCD Contrast Adjustment

Pinout

X93155

(8 LD MSOP)

TOP VIEW

8

INC

U/D

V

1

2

R

H

3

SS

4

V

CC

7

CS
R

6

5

NC

L

*

Features

• Solid-state potentiometer

• Up/Down interface

• 32 wiper tap points per potentiometer

- Wiper position stored in nonvolatile memory and
recalled on power-up

• 31 resistive elements per potentiometer

- Temperature compensated

- Maximum resistance tolerance ±25%

- Terminal voltage, 0 to V

• Low power CMOS

-V

= 5V ±10%

CC

- Active current, 200µA typ.

- Standby current, 2.0µA max

• High reliability

- Endurance 200,000 data changes per bit

- Register data retention, 100 years

TOTAL

value = 50kΩ

•R

• Packages

- 8 Ld MSOP

• Pb-free available (RoHS compliant)

CC

FN8181.2

*NC can be left unconnected, or connected to any voltage between VSS

and V

CC.

Ordering Information

TEMP

PART NUMBER PART MARKING VCC LIMITS (V) R

X93155UM8I* AGM 5 ±10% 50 -40 to +85 8 Ld MSOP M8.118
X93155UM8IZ* (Note) DCH -40 to +85 8 Ld MSOP

*Add "T1" suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%

matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved

TOTAL

(kΩ)

RANGE (°C) PACKAGE PKG DWG. #

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

M8.118

(Pb-free)

Block Diagram

www.BDTIC.com/Intersil

(SUPPLY VOLTAGE)

V

CC

30kΩ

U/D
INC

CS

X93155

5-BIT
UP/DOWN
COUNTER

31

30

R

H

ONE

OF

THIRTY

TWO

29

28

TRANSFER

GATES

2

1

0

RESISTOR

ARRAY

UP/DOWN

)

(U/D

INCREMENT

)

(INC

DEVICE SELECT

(CS

)

CONTROL

AND

MEMORY

(Ground)

V

SS

R

H

5-BIT

NONVOLATILE

MEMORY

STORE AND

CONTROL

RECALL

R

L

V

CC

V

SS

CIRCUITRY

DECODER

GENERAL

DETAILED

Pin Descriptions

MSOP SYMBOL BRIEF DESCRIPTION

1INC

2U/DUp/Down (U/D). The U/D input controls the direction of the wiper movement and whether the counter is incremented or

3R
4V
5NCNo Connection (or can be connected to any voltage between V
6R
7CS

8V

Increment (INC). The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or
decrement the counter in the direction indicated by the logic level on the U/D

input.

decremented.

SS

H

L

RH. The R
Ground.

RL. The R

and RL pins of the X93155 are equivalent to the end terminals of a variable resistor.

H

and VCC.)

SS

and RL pins of the X93155 are equivalent to the end terminals of a variable resistor.

H

Chip Select (CS). The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile
memory when CS

is returned HIGH while the INC input is also HIGH. After the store operation is complete, the X93155

will be placed in the low power standby mode until the device is selected once again.

Supply Voltage.

CC

R

L

2

FN8181.2

February 19, 2008

X93155

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Voltage on CS, INC, U/D, RH, RL and V

with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . .-1V to +6.5V

Maximum resistor current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA

CC

Recommended Operating Conditions

Temperature Range

Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10% (Note 6)

V

CC

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:

1. Absolute linearity is utilized to determine actual wiper resistance versus expected resistance = (R
n = 1 .. 29 only

2. Relative linearity is a measure of the error in step size between taps = R

3. 1 Ml = Minimum Increment = R

4. Typical values are for T

5. Limits established by characterization and are not production tested.

6. When performing multiple write operations, V

7. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.

= +25°C and nominal supply voltage.

A

TOT

/31.

must not decrease by more than 150mV from its initial value.

CC

Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Maximum reflow temperature (40s). . . . . . . . . . . . . . . . . . . . +240°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

H(n+1)

(actual)-R

H(n)

—[R

+ Ml] = ±0.5 Ml, n = 1 .. 29 only.

H(n)

(expected)) = ±1 Ml Maximum.

H(n)

Potentiometer Specifications Over recommended operating conditions, unless otherwise stated.

MIN

SYMBOL PARAMETER TEST CONDITIONS/NOTES

R

TOT

V

I

R

C

H/CL/CW

R

End-to-end Resistance 37.5 50 62.5 kΩ
RH, RL Terminal Voltages 0 V
Power Rating R

Noise Ref: 1kHz -120 dBV

Potentiometer Current (Note 5) 0.6 mA
Resolution 3%
Absolute linearity

Relative linearity

Temperature Coefficient (Note 5) ±35 ppm/°C

R

TOTAL

Potentiometer Capacitances See “Circuit #2 SPICE Macro

(Note 1) R

(Note 2) R

=50kΩ 1mW

TOTAL

H(n)(actual)-RH(n)(expected)

-[R

H(n+1)

Model” on page 4

]±0.5MI

H(n)+MI

(Note 7)

DC Electrical Specifications Over recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

CC2

I

I

SB

VCC Active Current (Increment) CS = VIL, U/D = VIL or VIH and

= 0.4V @ max. t

INC

VCC Active Current (Store)
(EEPROM Store)

Standby Supply Current CS = VCC - 0.3V , U/D and INC= VSS

CS VCS = V

LI

CS = VIH, U/D = VIL or VIH and

=V

CC

@ max. t

IH

- 0.3V

CC

INC

or V

CYC

WR

MIN

(Note 7)

TYP

(Note 4)

10/10/25 pF

TYP

(Note 4)

200 300 µA

MAX

(Note 7) UNIT

CC

(Note 5)

(Note 5)

±1 MI

(Note 3)

(Note 3)

(Note 5)

MAX

(Note 7) UNIT

1400 µA

2.0 µA

±1 µA

V

3

FN8181.2

February 19, 2008

X93155

www.BDTIC.com/Intersil

DC Electrical Specifications Over recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

I
I

V

V

C

(Note 5)

CS VCC = 5V, CS = 0 120 200 250 µA

LI

INC, U/D Input Leakage Current VIN = V

LI

CS, INC, U/D Input HIGH Voltage V

IH

CS, INC, U/D Input LOW Voltage -0.5 V

IL

CS

IN

, INC, U/D Input Capacitance VCC = 5V, VIN = VSS, TA= +25°C,

f=1MHz

SS

to V

CC

MIN

(Note 7)

x 0.7 VCC + 0.5 V

CC

TYP

(Note 4)

MAX

(Note 7) UNIT

±1 µA

x 0.1 V

CC

10 pF

Endurance and Data Retention

Circuit #2 SPICE Macro Model

PARAMETER MIN UNIT

Minimum endurance 200,000 Data changes per bit

Data retention 100 Years

R

H

R

TOTAL

C

H

Test Circuit #1

TEST POINT

VH/R

H

10pF

AC Conditions of Test

V

L

Input pulse levels 0V to 5V
Input rise and fall times 10ns
Input reference levels 1.5V

AC Electrical Specifications Over recommended operating conditions, unless otherwise specified.

SYMBOL PARAMETER

t

Cl

t

lD

t

DI

t

t

lH

t

lC

t

CPH

t

CPH

t

CYC

t

R, tF

lL

CS to INC Setup 100 ns
INC HIGH to U/D Change 100 ns
U/D to INC Setup 100 ns
INC LOW Period 1 µs
INC HIGH Period 1 µs
INC Inactive to CS Inactive 1 µs
CS Deselect Time (No Store) 250 ns
CS Deselect Time (Store) 10 ms
INC Cycle Time 2 µs
INC

Input Rise and Fall time 500 µs

(Note 5)

t

R VCC

(Note 5)

t

WR

VCC Power-up Rate 1 50 V/ms

Store Cycle 510ms

MIN

(Note 7)

TYP

(Note 4)

C

C

W

25pF

L

10pF

MAX

(Note 7) UNIT

R

L

4

FN8181.2

February 19, 2008

AC Timing

www.BDTIC.com/Intersil

CS

INC

X93155

t

CYC

t

CI

t

IL

t

IH

t

IC

(STORE)

t

CPH

90% 90%

10%

U/D

t

ID

t

DI

Power-up and Power-down Requirements

There are no restrictions on the power-up or power-down
conditions of V
potentiometer pins provided that V
positive than or equal to V
V

ramp rate specification is always in effect.

CC

and the voltages applied to the

CC

and VL, i.e., VCC ≥ VH,VL. The

H

is always more

CC

Pin Descriptions

RH and R

The R
terminals of a variable resistor. The minimum voltage is V
and the maximum is V
references the relative position of the terminal in relation to
wiper movement direction selected by the U/D input.

Up/Down (U/D)

The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.

Increment (INC)

The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the
U/D

Chip Select (CS)

The device is selected when the CS input is LOW. The
current counter value is stored in nonvolatile memory when
CS

is returned HIGH while the INC input is also HIGH. After
the store operation is complete, the X93155 will be placed in
the low power standby mode until the device is selected
once again.

L

and RL pins of the X93155 are equivalent to the end

H

. The terminology of RH and R

CC

input.

SS

L

Principles of Operation

There are three sections of the X93155: the input control,
counter and decode section; the nonvolatile memory; and
the resistor array. The input control section operates just like
an up/down counter. The output of this counter is decoded to
turn on a single electronic switch connecting a point on the

t

F

t

R

resistor array to the wiper output. Under the proper
conditions the contents of the counter can be stored in
nonvolatile memory and retained for future use. The resistor
array is comprised of 31 individual resistors connected in
series. At either end of the array and between each resistor
is an electronic switch that transfers the connection at that
point to the wiper. The wiper is connected to the R
forming a variable resistor from R

to RL.

H

terminal,

L

The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.

If the wiper is moved several positions, multiple taps are
connected to the wiper for up to 10µs. The 2-terminal
resistance value for the device can temporarily change by a
significant amount if the wiper is moved several positions.

When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is set to the value last stored.

Instructions and Programming

The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS
is selected and enabled to respond to the U/D
inputs. HIGH to LOW transitions on INC
decrement (depending on the state of the U/D
bit counter. The output of this counter is decoded to select
one of thirty two wiper positions along the resistive array.

The value of the counter is stored in nonvolatile memory
whenever CS

transitions HIGH while the INC input is also
HIGH. In order to avoid an accidental store during power-up,
CS

must go HIGH with VCC during initial power-up. When

left open, the CS

pin is internally pulled up to VCC by an

internal 30kΩ resistor.
The system may select the X93155, move the wiper and

deselect the device without having to store the latest wiper

set LOW, the device

and INC

will increment or

input) a five

5

FN8181.2

February 19, 2008

X93155

www.BDTIC.com/Intersil

position in nonvolatile memory. After the wiper movement is
performed as previously described and once the new
position is reached, the system must keep INC
taking CS

HIGH. The new wiper position will be maintained

LOW while

until changed by the system or until a power-up/down cycle
recalled the previously stored data. In order to recall the
stored position of the wiper on po wer-up, the CS

pin must be

held HIGH.
This procedure allows the system to always power-up to a

preset value stored in nonvolatile memory; then during
system operation, minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, or other system
trim requirements.

The state of U/D

may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.

Mode Selection

CS INC U/D MODE

L H Wiper Up
L L Wiper Down

H X Store Wiper Position

H X X Standby Current

L X No Store, Return to Standby
L H Wiper Up (not recommended)
L L Wiper Down (not recommended)

Symbol Table

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

Applications Information

Electronic digitally controlled (XDCP) potentiometers provide
three powerful application advantages:

1. The variability and reliability of a solid-state potentiometer

2. The flexibility of computer-based digital controls

3. The retentivity of nonvolatile memory used for the storage
of multiple potentiometer settings or data

V

R

I

Two terminal variable resistor.

6

FN8181.2

February 19, 2008

X93155

www.BDTIC.com/Intersil

Low Voltage High Impedance Instrumentation Amplifier

5V

50k

10k

10k

-

+

U1A

­50k

X93155 (R

­U1B

+

5V

+

U1A

100k

TOTAL

50k

100k

)

300k

­U1B

+

-15V

+

V

IN

-

Micro-Power LCD Contrast Control

5V

240k

100k

10k 50k

­U1C

+

10k

50k

= -4.41

V

OUT

V

= -8.82V TO -13.23V

OUT

U1 = LMC6042

50k

GAIN =

10k

U1 = LT1467

(

1 +

V

OUT

(

1 +

100k

50k + R

50k

R

TOTAL

TOTAL

)

)

X93155 (R

TOTAL

Single Supply Variable Gain Amplifier

V

IN

)

20k

20k

10k

5V

5V

+

U1

-

X93155
(R

TOTAL

V

OUT

GAIN =

U1 = LMC6042

)

R

TOTAL

10k

7

FN8181.2

February 19, 2008

X93155

www.BDTIC.com/Intersil

Mini Small Outline Plastic Packages (MSOP)

N

EE1

INDEX

AREA

AA1A2

-H-

SIDE VIEW

12

TOP VIEW

b

e

D

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

.

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only.

-B-

0.20 (0.008) A

GAUGE

PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING
PLANE

a

0.20 (0.008) C

- H -

B

4X θ

C

D

4X θ

L1

C

C

L

E

1

END VIEW

R1

R

L

-B-

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.010 0.014 0.25 0.36 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.026 BSC 0.65 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N8 87

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

05

α

o

o

0

15

o

o

6

o

5

o

0

15

o

o

6

Rev. 2 01/03

NOTESMIN MAX MIN MAX

-

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

8

FN8181.2

February 19, 2008