intersil X9313 DATA SHEET

®

www.BDTIC.com/Intersil

X9313

Digitally Controlled Potentiometer (XDCP™)

Data Sheet January 15, 2008

Linear, 32 Taps, 3 Wire Interface, Terminal
Voltages ± V

The Intersil X9313 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a 3-wire interface.

The potentiometer is implemented by a resistor array
composed of 31 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS
The position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent power-up
operation.

The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including:

• Control

• Parameter adjustments

• Signal processing

CC

, U/D, and INC inputs.

Features

• Solid-state potentiometer

• 3-wire serial interface

• 32 wiper tap points

- Wiper position stored in nonvolatile memory and
recalled on power-up

• 31 resistive elements

- Temperature compensated

- End-to-end resistance range ±20%

- Terminal voltages, -V

• Low power CMOS
= 3V or 5V

-V

CC

- Active current, 3mA max.

- Standby current, 500µA max.

• High reliability

- Endurance, 100,000 data changes per bit

- Register data retention, 100 years

•R

values = 1kΩ, 10kΩ, 50kΩ

TOTAL

• Packages

- 8 Ld SOIC, 8 Ld MSOP and 8 Ld PDIP

• Pb-free available (RoHS compliant)

CC

to +V

CC

FN8177.6

Block Diagram

(SUPPLY VOLTAGE)

V

CC

UP/DOWN

(U/D)

INCREMENT

(INC

)

DEVICE SELECT

(CS

)

V

SS

CONTROL

AND

MEMORY

(GROUND)

GENERAL

R

H/VH

RW/V

RL/V

DECODER

U/D
INC

CS

W

L

V

CC

V

SS

5-BIT
UP/DOWN
COUNTER

5-BIT

NONVOLATILE

MEMORY

STORE AND

RECALL

CONTROL

CIRCUITRY

31

30

29

28

ONE OF

THIRTY-TWO

OUTPUTS

ACTIVE

AT A
TIME

DETAILED

RH/V

H

TRANSFER

GATES

2

1

0

RESISTOR

ARRAY

RL/V
RW/V

L

W

1

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2008. All Rights Reserved

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9313

www.BDTIC.com/Intersil

Ordering Information

TEMPERATURE

PART

PART NUMBER

X9313UMI 13UI 4.5 to 5.5 50 -40 to +85 8 Ld MSOP M8.118
X9313UMIZ (Note) DDB -40 to +85 8 Ld MSOP (Pb-free) M8.118
X9313UP X9313UP 0 to +70 8 Ld PDIP MDP0031

,

X9313US*
X9313USZ* (Note) X9313U Z 0 to +70 8 Ld SOIC (Pb-free) M8.15
X9313USI X9313U I -40 to +85 8 Ld SOIC MDP0027
X9313USIZ (Note) X9313U ZI -40 to +85 8 Ld SOIC (Pb-free) M8.15
X9313WMZ (Note) DDF 10 0 to +70 8 Ld MSOP (Pb-free) M8.118
X9313WMI* 13WI -40 to +85 8 Ld MSOP M8.118
X9313WMIZ* (Note) DDE -40 to +85 8 Ld MSOP (Pb-free) M8.118
X9313WP X9313WP 0 to +70 8 Ld PDIP MDP0031
X9313WPZ-3 X9313WP ZD -40 to +85 8 Ld PDIP*** (Pb-free) MDP0031
X9313WPI X9313WP I -40 to +85 8 Ld PDIP MDP0031
X9313WPIZ X9313WP ZI -40 to +85 8 Ld PDIP*** (Pb-free) MDP0031
X9313WS*
X9313WSZ*
X9313WSI*
X9313WSIZ* (Note) X9313WS ZI -40 to +85 8 Ld SOIC (Pb-free) M8.15
X9313ZM 313Z 1 0 to +70 8 Ld MSOP M8.118
X9313ZMZ (Note) DDJ 0 to +70 8 Ld MSOP (Pb-free) M8.118
X9313ZMI*
X9313ZMIZ*
X9313ZP X9313ZP 0 to +70 8 Ld PDIP MDP0031
X9313ZPI X9313ZP I -40 to +85 8 Ld PDIP MDP0031
X9313ZPIZ (Note) X9313ZP ZI -40 to +85 8 Ld PDIP*** (Pb-free) MDP0031
X9313ZS*
X9313ZSZ*
X9313ZSI* X9313ZS I -40 to +85 8 Ld SOIC MDP0027
X9313ZSIZ* (Note) X9313ZS ZI -40 to +85 8 Ld SOIC (Pb-free) M8.15
X9313UM-3T1 13UD 3 to 5.5 50 0 to +70 8 Ld MSOP Tape and Reel M8.118
X9313UMZ-3T1 (Note) DDD 0 to +70 8 Ld MSOP Tape and Reel

X9313UMI-3* 13UE -40 to +85 8 Ld MSOP M8.118
X9313UMIZ-3* (Note) 13UEZ -40 to +85 8 Ld MSOP (Pb-free) M8.118
X9313US-3*
X9313USZ-3*
X9313WM-3* 13WD 10 0 to +70 8 Ld MSOP M8.118
X9313WMZ-3* (Note) DDG 0 to +70 8 Ld MSOP (Pb-free) M8.118
X9313WMI-3* 13WE -40 to +85 8 Ld MSOP M8.118
X9313WMIZ-3* (Note) 13WEZ -40 to +85 8 Ld MSOP (Pb-free) M8.118

** X9313U 0 to +70 8 Ld SOIC MDP0027

,

** X9313WS 0 to +70 8 Ld SOIC MDP0027

, **

(Note) X9313W Z 0 to +70 8 Ld SOIC (Pb-free) M8.15

,

** X9313WS I -40 to +85 8 Ld SOIC MDP0027

,

** 13ZI -40 to +85 8 Ld MSOP M8.118

,

** (Note) DDH -40 to +85 8 Ld MSOP (Pb-free) M8.118

,

** X9313ZS 0 to +70 8 Ld SOIC MDP0027

,

** (Note) X9313 Z 0 to +70 8 Ld SOIC (Pb-free) M8.15

,

** X9313U D 0 to +70 8 Ld SOIC MDP0027

, **

(Note) X9313U ZD 0 to +70 8 Ld SOIC (Pb-free) M8.15

MARKING

V

CC

RANGE

(V)

R

TOTAL

(kΩ)

RANGE

(°C) PACKAGE

(Pb-free)

PKG.

DWG. #

M8.118

2

FN8177.6

January 15, 2008

X9313

www.BDTIC.com/Intersil

Ordering Information (Continued)

TEMPERATURE

PART NUMBER

X9313WS-3*, ** X9313W D 3 to 5.5 10 0 to +70 8 Ld SOIC MDP0027
X9313WSZ-3* (Note) X9313W ZD 0 to +70 8 Ld SOIC (Pb-free) M8.15
X9313ZM-3* 13ZD 1 0 to +70 8 Ld MSOP M8.118
X9313ZMZ-3* (Note) DDK 0 to +70 8 Ld MSOP (Pb-free) M8.118
X9313ZMI-3* 13ZE -40 to +85 8 Ld MSOP M8.118
X9313ZMIZ-3* (Note) 13ZEZ -40 to +85 8 Ld MSOP (Pb-free) M8.118
X9313ZP-3 X9313ZP D 0 to +70 8 Ld PDIP MDP0031
X9313ZPZ-3 (Note) X9313ZP ZD 0 to +70 8 Ld PDIP (Pb-free)*** MDP0031

,

X9313ZS-3*
X9313ZSZ-3* (Note) X9313Z ZD 0 to +70 8 Ld SOIC (Pb-free) M8.15
X9313ZSI-3* X9313Z E -40 to +85 8 Ld SOIC MDP0027
X9313ZSIZ-3* (Note) X9313Z ZE -40 to +85 8 Ld SOIC (Pb-free) M8.15

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets ; m olding compoun ds/die a ttach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free sold ering operations. Intersil
Pb-free products are MSL classified at Pb-free peak re flow t empe ratures t hat mee t or excee d t he P b-free requ ire ments of IPC/JEDEC J STD-020.

*Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
**Add "T2" suffix for tape and reel. Please refer to TB347 for details on reel specifications.
***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

** X9313Z D 0 to +70 8 Ld SOIC MDP0027

PART

MARKING

V

CC

RANGE

(V)

R

TOTAL

(kΩ)

RANGE

(°C) PACKAGE

PKG.

DWG. #

Pin Descriptions

RH/VH and RL/VL

The high (RH/VH) and low (RL/VL) terminals of the X9313
are equivalent to the fixed terminals of a mechanical
potentiometer. The terminology of RL/VL and RH/VH
references the relative position of the terminal in relation to
wiper movement direction selected by the U/D
the voltage potential on the terminal.

RW/VW

RW/VW is the wiper terminal and is equivalent to the
movable terminal of a mechanical potentiometer. The
position of the wiper within the array is determined by the
control inputs. The wiper terminal series resistance is
typically 40Ω at V

CC

= 5V.

Up/Down (U/D)

The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.

Increment (INC)

The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the
U/D

input.

input and not

Chip Select (CS)

The device is selected when the CS input is LOW . The current
counter value is stored in nonvolatile memory when CS
returned HIGH while the INC

input is also HIGH. After the

is

store operation is complete, the X9313 will be placed in the
low power standby mode until the device is selected once
again.

Pinouts

X9313

(8 LD PDIP, 8 LD SOIC)

TOP VIEW

INC
U/D

RH/VH

VSS

RH/VH

VSS

RW/VW

RL/VL

1
2

X9313

3
4

X9313

(8 LD MSOP)

TOP VIEW

1
2

X9313

3
4

VCC

8

CS

7

RL/VL

6

RW/VW

5

U/D

8

INC

7

VCC

6

CS

5

3

FN8177.6

January 15, 2008

X9313

www.BDTIC.com/Intersil

TABLE 1. PIN NAMES

SYMBOL DESCRIPTION

RH/VH High terminal

RW/VW Wiper terminal

RL/VL Low terminal

VSS Ground

VCC Supply voltage

U/D
INC Increment control input

CS Chip Select control input

Up/Down control input

Principles of Operation

There are three sections of the X9313: the input control,
counter and decode section; the nonvolatile memory; and
the resistor array. The input control section operates just like
an up/down counter. The output of this counter is decoded to
turn on a single electronic switch connecting a point on the
resistor array to the wiper output. Under the proper
conditions, the contents of the counter can be stored in
nonvolatile memory and retained for future use. The resistor
array is comprised of 31 individual resistors connected in
series. At either end of the array and between each resistor
is an electronic switch that transfers the potential at that
point to the wiper.

The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.

The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
connected to the wiper for t
R

value for the device can temporarily be reduced by

TOTAL

a significant amount if the wiper is moved several positions.
When the device is powered-down, the last wiper position

stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is set to the value last stored.

Instructions and Programming

The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS
is selected and enabled to respond to the U/D
inputs. HIGH to LOW transitions on INC
decrement (depending on the state of the U/D
bit counter. The output of this counter is decoded to select
one of thirty-two wiper positions along the resistive array.

(INC to VW change). The

IW

set LOW the device

and INC

will increment or

input) a seven

The system may select the X9313, move the wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as previously described and once the new
position is reached, the system must keep INC
taking CS

HIGH. The new wiper position will be maintained

LOW while

until changed by the system or until a power-up/down cycle
recalled the previously stored data.

This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation, minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, etc.

The state of U/D

may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.

TABLE 2. MODE SELECTION

CS INC U/D MODE

L H Wiper up
L L Wiper down

H X Store wiper position

H X X Standby current

L X No store, return to standby
L H Wiper up (not recommended)
L L Wiper down (not recommended)

Symbol Table

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

The value of the counter is stored in nonvolatile memory
whenever CS

transitions HIGH while the INC input is also

HIGH.

4

FN8177.6

January 15, 2008

X9313

www.BDTIC.com/Intersil

Absolute Maximum Ratings Recommended Operating Conditions

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on CS
V

CC

Voltage on V

with respect to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +7V

ΔV = |V

X9313Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V

X9313W, X9313U. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±8.8mA

I

W

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

, INC, U/D, and

with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

, VL, V

H

W

- VL|:

H

Potentiometer Characteristics Over recommended operating conditions, unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS

End-to-End Resistance Tolerance ±20 %
V
V

R

I

C

H/CL/CW

(Note 5)

NOTES:

1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (V

2. Relative linearity is a measure of the error in step size between taps = R

3. 1 MI = minimum increment = R

VH Terminal Voltage -V

VH

VL Terminal Voltage -V

VL

Wiper Resistance IW = (VH - VL)/R

W

Wiper Current ±4.4 mA

W

Noise (Note 5) Ref: 1kHz -120 dBV

Resolution 3%

Absolute Linearity (Note 1) R

Relative Linearity (Note 2) R

Temperature Coefficient (Note 5) ±300 ppm/°C

R

TOTAL

Ratiometric Temperature Coefficient

(Note 5)

Potentiometer Capacitances See Circuit #3 10/10/25 pF

/31.

TOT

W(n)(actual)

- (R

W(n+1)

Temperature:

Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage (VCC):

X9313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%

X9313-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V

Max Wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±4.4mA

Power rating:

≥ 10kΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10mW

R

TOTAL

1kΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16mW

R

TOTAL

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications

LIMITS

CC
CC

, VCC = 5V 40 100 Ω

TOTAL

- R

W(n)(expected)

+MI) ±0.2 MI

W(n)

±20 ppm/°C

- V

W(n)(expected)

W(n+1)

- (R

W(n)(actual)

+ MI) = ±0.2 MI.

W(n)

+V

CC

+V

CC

±1 MI

) = ±1 MI maximum.

UNITMIN TYP MAX

V
V

(Note 3)

(Note 3)

5

FN8177.6

January 15, 2008

X9313

www.BDTIC.com/Intersil

DC Electrical Specifications Over recommended operating conditions, unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS/NOTES

I

CC

I

SB

I
V
V
C

(Note 5)

Endurance and Data Retention

PARAMETER MIN UNIT

Minimum endurance 100,000 Data changes per bit

Data retention 100 Years

VCC Active Current CS = VIL, U/D = VIL or VIH and

= 0.42/2.4V @ max t

INC

CYC

Standby Supply Current CS = VCC - 0.3V , U/D and INC = VSS or

- 0.3V

V

CC

CS, INC, U/D Input Leakage Current VIN = VSS to V

LI

CS, INC, U/D Input HIGH Current 2 V

IH

CS, INC, U/D Input LOW Current +0.8 V

IL

, INC, U/D Input Capacitance VCC = 5V, VIN = VSS, TA = +25°C,

CS

IN

f = 1MHz

CC

per register

LIMITS

TYP

(Note 4) MAX

UNITMIN

13mA

200 500 µA

±10 µA

10 pF

VH/R

VL/R

H

TEST POINT

VW/R

VW

L

W

FORCE
CURRENT

R

H

10pF

VH/R

H

V

S

VL/R

VW/R

L

TEST POINT

W

R

TOTAL

C

C

H

W

25pF

R

W

FIGURE 1. TEST CIRCUIT #1 FIGURE 2. TEST CIRCUIT #2 FIGURE 3. CIRCUIT #3 SPICE MACRO

MODEL

C

10pF

R

L

L

6

FN8177.6

January 15, 2008

X9313

www.BDTIC.com/Intersil

AC Electrical Specifications Over recommended operating conditions, unless otherwise stated.

LIMITS

SYMBOL PARAMETER

t

CI

t

ID

t

DI

t

IL

t

IH

t

IC

t

CPH

t

CPH

t

IW

t

CYC

, tF (Note 5) INC Input Rise and Fall Time 500 µs

t

R

CS to INC Setup 100 ns
INC HIGH to U/D Change 100 ns
U/D to INC Setup 2.9 µs
INC LOW Period 1 µs
INC HIGH Period 1 µs
INC Inactive to CS Inactive 1 µs
CS Deselect Time (STORE) 20 ms
CS Deselect Time (NO STORE) 100 ns
INC to VW Change 5 µ s
INC Cycle Time 2 µs

tPU (Note 5) Power-up to Wiper Stable 10 µs

(Note 5) VCC Power-up Rate 0.2 50 V/ms

t

R VCC

(Note 5) Store Cycle 10 ms

t

WR

NOTES:

4. Typical values are for T

= +25°C and nominal supply voltage.

A

5. This parameter is not 100% tested.

TYP

(Note 4) MAX

UNITMIN

Power-Up and Power-Down Requirements

The recommended power-up sequence is to apply VCC/VSS
first, then the potentiometer voltages. During power-up, the
data sheet parameters for the DCP do not fully apply until
1ms after V

reaches its final value. The VCC ramp

CC

CS

t

CYC

INC

U/D

V

t

CI

t

IW

W

t

IL

t

ID

t

IH

t

DI

t

IC

MI

specification is always in effect. In order to prevent unwanted
tap position changes, or an inadvertent store, bring the CS
and INC

high before or concurrently with the VCC pin on

power-up.

t

CPH

90% 90%

10%

(SEE NOTE)

t

F

t

R

NOTE: MI IN THE AC TIMING DIAGRAM REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE VW OUTPUT DUE TO A CHANGE IN
THE WIPER POSITION.

FIGURE 4. AC TIMING DIAGRAM

7

FN8177.6

January 15, 2008

X9313

www.BDTIC.com/Intersil

Applications Information

Electronic digitally controlled potentiometers (XDCP) provide
three powerful application advantages:

1. The variability and reliability of a solid-state potentiometer.

2. The flexibility of computer-based digital controls.

3. The retentivity of nonvolatile memory used for the storage
of multiple potentiometer settings or data.

Basic Configurations of Electronic Potentiometers

V

R

V

H

V

L

VW/R

W

V

R

I

THREE-TERMINAL POTENTIOMETER;

Basic Circuits

R

+V

IN

1

V

REF

VOLTAGE REGULATOR

317

I

adj

VO (REG) = 1.25V (1 + R2/R1) + I

VARIABLE VOLTAGE DIVIDER

+5V

R

VW

V

2

OUT

+
–

= VW/R

R

1

ADJ R2

-5V

OP-07

W

V

OUT

VO (REG)V

CASCADING TECHNIQUESBUFFERED REFERENCE VOLTAGE

+V +V

VW/RW

+V

(a) (b)

OFFSET VOLTAGE ADJUSTMENT

–
+

R

2

TL072

R

V

S

10kΩ

1

100kΩ

10kΩ10kΩ

-12V+12V

TWO-TERMINAL VARIABLE RESIST OR;

VARIABLE CURRENT

NONINVERTING AMPLIFIER

V

S

X

R

V

W

COMPARATOR WITH HYSTERESIS

LT311A

V

S

V

O

V

= [R1/(R1 + R2)] VO(max)

UL

= [R1/(R1 + R2)] VO(min)

V

LL

(FOR ADDITIONAL CIRCUITS SEE AN115)

1

VO = (1 + R2/R1)V

}

}

R

R

1

+5V

LM308A

+
–

-5V

R

–
+

2

V

O

2

S

V

O

8

FN8177.6

January 15, 2008

X9313

www.BDTIC.com/Intersil

Mini Small Outline Plastic Packages (MSOP)

N

EE1

INDEX

AREA

AA1A2

-H-

SIDE VIEW

12

TOP VIEW

b

e

D

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

.

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only.

-B-

0.20 (0.008) A

GAUGE

PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING
PLANE

a

0.20 (0.008) C

- H -

B

4X θ

C

D

4X θ

L1

C

L

E

1

END VIEW

R1

R

L

C

-B-

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.010 0.014 0.25 0.36 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.026 BSC 0.65 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N8 87

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

05

α

o

o

0

15

o

o

6

o

5

o

0

15

o

o

6

Rev. 2 01/03

NOTESMIN MAX MIN MAX

-

-

9

FN8177.6

January 15, 2008

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

X9313

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

10

FN8177.6

January 15, 2008

Small Outline Package Family (SO)

www.BDTIC.com/Intersil

A

D

NN

(N/2)+1

X9313

h X 45°

PIN #1

E

C

SEATING
PLANE

0.004 C

E1

B

0.010 BM CA

I.D. MARK

1

e

0.010 BM CA

(N/2)

c

SEE DETAIL “X”

L1

H

A2

GAUGE
PLANE

A1

b

DETAIL X

L

4° ±4°

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

INCHES

SO16

SYMBOL

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28)

TOLERANCE NOTESSO-8 SO-14

A

0.010

Rev. M 2/07

11

FN8177.6

January 15, 2008

Plastic Dual-In-Line Packages (PDIP)

www.BDTIC.com/Intersil

X9313

E

eA

eB

SEATING
PLANE

D

A2

A

L

L

e

b

A1

NOTE 5

c

MDP0031

PLASTIC DUAL-IN-LINE PACKAGE

INCHES

SYMBOL

A 0.210 0.210 0.210 0.210 0.210 MAX

A1 0.015 0.015 0.015 0.015 0.015 MIN

A2 0.130 0.130 0.130 0.130 0.130 ±0.005

b 0.018 0.018 0.018 0.018 0.018 ±0.002

b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015

c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002

D 0.375 0.750 0.750 0.890 1.020 ±0.010 1

E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010

E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2

e 0.100 0.100 0.100 0.100 0.100 Basic

eA 0.300 0.300 0.300 0.300 0.300 Basic

eB 0.345 0.345 0.345 0.345 0.345 ±0.025

L 0.125 0.125 0.125 0.125 0.125 ±0.010

N 8 14 16 18 20 Reference

NOTES:

1. Plastic or metal protrusions of 0.010” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.

4. Dimension eB is measured with the lead tips unconstrained.

5. 8 and 16 lead packages have half end-leads as shown.

N

PIN #1

E1

TOLERANCE NOTESPDIP8 PDIP14 PDIP16 PDIP18 PDIP20

INDEX

12 N/2

b2

Rev. C 2/07

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

12

FN8177.6

January 15, 2008