®
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X9279
Single Supply/Low Power/256-Tap/2-Wire Bus
Data Sheet November 22, 2005
Single Digitally-Controlled (XDCP™)
Potentiometer
FEATURES
• 256 Resistor Taps
• 2-Wire Serial Interface for Write, Read, and
Transfer Operations of the Potentiometer
• Wiper Resistance, 100Ω Typical @ 5V
• 16 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power -on Recall. Loads Sa ved Wiper P osition o n
Power-up.
• Standby Current < 5µA Max
: 2.7V to 5.5V Operation
•V
CC
•50kΩ, 100kΩ Versions of End to End Resistance
• Endurance: 100,000 Data Changes per Bit per
Register
• 100 yr. Data Retention
• 14 Ld TSSOP
• Low Power CMOS
• Pb-Free Plus Anneal Available (RoHS Compliant)
FN8175.3
DESCRIPTION
The X9279 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected t o the
wiper terminal through switches. The position of the
wiper on the array is controlled b y th e user throug h the
2-Wire bus interface. The potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and a four nonvolatile Data Registers that can
be directly written to and read by the user. The
contents of the WCR controls the position of the wiper
on the resistor array though the switches. Powerup
recalls the contents of the default data register (DR0)
to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two ter minal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
Address
Data
2-Wire
Bus
Interface
Status
V
CC
Bus
Interface
and Control
V
SS
Write
Read
Transfer
Inc/Dec
Control
Power-on Recall
Wiper Counter
Register (WCR)
Data Registers
16 Bytes
R
H
50kΩ and 100kΩ
R
256-taps
POT
L
wiper
R
W
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
X9279
www.BDTIC.com/Intersil
Ordering Information
POTENTIOMETER
PART NUMBER PART MARKING VCC LIMITS (V)
X9279TV14* X9279TV 5 ±10% 100 0 to 70 14 Ld TSSOP (4.4mm)
X9279TV14Z* X9279TVZ 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)
X9279TV14I* X9279TV I -40 to 85 14 Ld TSSOP (4.4mm)
X9279TV14IZ* X9279TV ZI -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)
X9279UV14* X9279UV 50 0 to 70 14 Ld TSSOP (4.4mm)
X9279UV14Z* (Note) X9279UV Z 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)
X9279UV14I* X9279UV I -40 to 85 14 Ld TSSOP (4.4mm)
X9279UV14IZ* (Note) X9279UV ZI -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)
X9279TV14-2.7* X9279TV F 2.7 to 5.5 100 0 to 70 14 Ld TSSOP (4.4mm)
X9279TV14Z-2.7* X9279TV ZF 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)
X9279TV14I-2.7* X9279TV G -40 to 85 14 Ld TSSOP (4.4mm)
X9279TV14IZ-2.7* X9279TV ZG -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)
X9279UV14-2.7* X9279UV F 50 0 to 70 14 Ld TSSOP (4.4mm)
X9279UV14Z-2.7* (Note) X9279UV ZF 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)
X9279UV14I-2.7* X9279UV G -40 to 85 14 Ld TSSOP (4.4mm)
X9279UV14IZ-2.7* (Note) X9279UV ZG -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE
DETAILED FUNCTIONAL DIAGRAM
V
CC
SCL
SDA
A2
A1
A0
WP
INTERFACE
AND
CONTROL
CIRCUITRY
V
SS
DATA
Control
Bank 0
DR0 DR1
DR2 DR3
Power-on Recall
WIPER
COUNTER
REGISTER
(WCR)
Bank 1
DR0
DR2 DR3
12 additional nonvolatile registers
3 Banks of 4 registers x 8-bits
DR1
Bank 2
DR0 DR1
DR2 DR3
50kΩ and 100kΩ
Bank 3
DR0 DR1
DR2 DR3
256-taps
R
H
R
L
R
W
2
FN8175.3
November 22, 2005
X9279
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CIRCUIT LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage
amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the freque n cy an d du ty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
PIN CONFIGURATION
NC
A0
NC
A2
SCL
SDA
V
SS
TSSOP
1
X9279
2
3
4
5
6
7
SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF
wireless systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
14
V
CC
R
13
12
11
10
9
8
R
R
A3
A1
WP
L
H
W
PIN ASSIGNMENTS
Pin
TSSOP Symbol Function
1 NC No Connect
2 A0 Device Address for 2-Wire bus.
3 NC No Connect
4 A2 Device Address for 2-Wire bus.
5 SCL Serial Clock for 2-Wire bus.
6 SDA Serial Data Input/Output for 2-Wire bus.
7V
SS
8WP
System Ground.
Hardware Write Protect
9 A1 Device Address for 2-Wire bus.
10 A3 Device Address for 2 wire-bus.
11 R
12 R
13 R
14 V
W
H
L
CC
3
Wiper Terminal of the Potentiometer.
High Terminal of the Potentiometer.
Low Terminal of the Potentiometer.
System Supply Voltage.
FN8175.3
November 22, 2005
X9279
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PIN DESCRIPTIONS
Bus Interface Pins
ERIAL DATA INPUT/OUTPUT (SDA)
S
The SDA is a bidirectional serial data input/output pin
for a 2-Wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-Wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of the
serial clock SCL.
It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the
guidelines for calculating typical values on the bus
pull-up resistors graph.
ERIAL CLOCK (SCL)
S
This input is used by 2-Wire master to supply 2-Wire
serial clock to the X9279.
Potentiometer Pins
, RL
R
H
The R
connections on a mechanical potentiometer.
R
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
S
G
The V
pin is the system ground.
Other Pins
N
No connect pins should be left open. This pins are used
for Intersil manufacturing and testing purposes.
and RL pins are equivalent to the terminal
H
W
YSTEM SUPPLY VOLTAGE (V
ROUND (V
CC
O CONNECT
)
SS
pin is the system supply voltage. The V
) AND SUPPLY
CC
SS
EVICE ADDRESS (A2 - A0)
D
The Address inputs are used to set the least
significant 3 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9279. A maximum of 8
devices may occup y the 2-Wire serial bus .
ARDWARE WRITE PROTECT INPUT (WP)
H
The WP
the Data Registers.
pin when LOW prevents nonvolatile writes to
4
FN8175.3
November 22, 2005
X9279
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PRINCIPLES OF OPERATION
The X9279 is a integrated microcircuit incorporating a
resistor array and associated registers and counter
and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the followi ng:
– Resistor Array Description.
– Serial Interface Description.
– Instruction and Register Description.
Array Description
The X9279 is comprised of a resistor array (See Figure
1). The array contains, in effect, 255 discrete resistive
segments that are connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (R
and RL inputs).
H
Figure 1. Detailed Potentiometer Block Diagram
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
) output. Within each individual array only one
(R
W
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).
The WCR may be written directly. These Data
Registers can the WCR can be read and written b y the
host system.
Power-up and Down Recommendations.
There are no restrictions on the power-up or powerdown conditions of V
the potentiometer pins provided that V
more positive than or equal to V
≥ VH, VL, VW. The VCC ramp rate specification is
V
CC
and the voltages applied to
CC
, VL, and VW, i.e.,
H
is always
CC
always in effect.
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
IF WCR = 00[H] THEN RW = R
IF WCR = FF[H] THEN RW = R
REGISTER 0 REGISTER 1
(DR0) (DR1)
8 8
BANK_0 Only
REGISTER 2 REGISTER 3
(DR2)
L
H
(DR3)
MODIFIED SCK
UP/DN
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
UP/DN
CLK
R
H
C
O
U
N
T
E
R
D
E
C
O
D
E
R
L
R
W
5
FN8175.3
November 22, 2005
X9279
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SERIAL INTERFACE DESCRIPTION
Serial Interface
The X9279 supports a bidirectional bus oriented
protocol. The protocol de fines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9279 will be considered a
slave de vice in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 2.
Start Condition
All commands to the X9279 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9279 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 2.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 2.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on th e bus to indicate the success ful re cei pt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9279 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9279 will respond with a final acknowledge.
See Figure 2.
Figure 2. Acknowledge Response from Receiver
SCL FROM
MASTER
DATA
OUTPUT
TRANSMITTER
FROM
DATA
OUTPUT
FROM
RECEIVER
START
1
89
ACKNOWLEDGE
6
FN8175.3
November 22, 2005
X9279
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Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9279
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9279 is still busy with the write operation no ACK
will be returned. If the X9279 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
FLOW 1: ACK Polling Sequence
Nonvolatile Write
Command Completed
EnterACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Yes
Further
Operation?
Yes
No
No
Issue STOP
INSTRUCTION AND REGISTER DESCRIPTION
Device Addressing: Identification Byte ( ID and A)
The first byte sent to the X9279 from the host,
following a CS
going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bits is the device ID for the X9279; this is fixed as
0101[B] (refer to Table 1).
The A[2:0] bits in the ID byte is the internal slave
address. The physica l de vice a ddress is defined by the
state of the A2 - A0 input pins. The slave address is
externally specified by the user. The X9279 compares
the serial data stream with the address input state; a
successful compare of both address bits is required f or
the X9279 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A2 - A0 inputs
can be actively driven by CM OS input signals or tied to
or VSS.
V
CC
Instruction Byte (I)
The next byte sent to the X9279 contains the
instruction and register po inter information. The three
most significant bits are used provide the instruction
opcode I [2:0]. The RB and RA bits point to one of the
four Data Registers . P0 is the POT selection; since the
X9279 is single POT, the P0 = 0. The format is shown
in Table 2.
Register Bank Selection (RB, RA, P1, P0)
There are 16 registers organized into four banks. Bank
0 is the default bank of registers. Only Bank 0 registers
can be used for Data Register to Wiper Counter
Register operations .
Issue
Instruction
Issue STOP
Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for 2-Wire write and read
operations. The Data Registers in Banks 1, 2, and 3
cannot be used for direct read/write operations
Proceed
Proceed
7
between the Wiper Counter Reg ister.
FN8175.3
November 22, 2005
X9279
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Register Selection (R0 to R3) Table Register Bank Selection (Bank 0 to Bank 3) Table
Register
RB RA
Selection Operations
0 0 0 Data Register Read and Write;
Wiper Counter Register
Operations
0 1 1 Data Register Read and Write;
Wiper Counter Register
Operations
1 0 2 Data Register Read and Write;
Wiper Counter Register
Operations
1 1 3 Data Register Read and Write;
Wiper Counter Register
Operations
Table 1. Identification Byte Fo rmat
P1 P0
0 0 0 Data Register Read and Write;
0 1 1 Data Register Read and
1 0 2 Data Register Read and
1 1 3 Data Register Read and
Bank
Selection Operations
Wiper Counter Register
Operations
Write Only
Write Only
Write Only
Device Type
Identifier
Set to 0
for proper operation
Internal Slave
Address
ID3 ID2 ID1 ID0 0 A2 A1 A0
0101
(MSB) (LSB)
Table 2. Instruction Byte Format
P1 and P0 are used also for register Bank Selection
Instruction Opcode
I3 I2 I1 I0 RB RA P1 P0
(MSB) (LSB)
Register
Selection
for 2-Wire Register Write and Read operations
Pot Selection (Bank Selection)
Set to P0 = 0 for potentiometer operations
Register Selection
Register Selected RB RA
DR0 0 0
DR1 0 1
DR2 1 0
DR3 1 1
8
FN8175.3
November 22, 2005
X9279
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Table 3. Instruction Set
Instruction Set
Instruction
Read Wiper Counter
Register
Write Wiper Coun ter
Register
Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed to
Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register
XFR Data Register to
Wipe r Counter Register
XFR Wiper Counter
Register to Data Register
Increment/Decrement
Wiper Counter Register
Note: 1/0 = data is one or zero
1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter
1 0 1 0 0 0 0 0 Write new value to the Wiper Counter
1 1 0 1 1/0 1/0 0 0 Transfer the contents of the Data Register
1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter Register
0 0 1 0 0 0 0 0 Enable Increment/decrement of the Wiper Counter
1P0
Register
Register
by P1 - P0 and RB - RA
pointed to by P1 - P0 and RB - RA
pointed to by RB - RA (Bank 0 only) to the Wiper
Counter Register
to the Register pointed to by RB-RA (Bank 0 only)
Register
OperationI3 I2 I1 I0 RB RA P
DEVICE DESCRIPTION
Wiper Counter Register (WCR)
The X9279 contains contains a Wiper Counter
Register, for the DCP potentiometer. The Wiper
Counter Register can be envisioned as a 8-bit parallel
and serial load counter with its outputs decoded to
select one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (See Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9279 is powereddown. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR. The
DR0 value of Bank 0 is the def ault va lue.
Data Registers (DR)
The potentiometer has four 8-bit nonvolatile Data
Registers (DR3-DR0). These can be read or written
directly by the host. Data can also be transferred
between any of the four Data Registers and the
associated Wiper Counter Register. All operations
changing data in one of the Data Registers is a
nonvolatile operatio n and will tak e a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user pref erence d ata.
Bit [7:0] are used to store one of the 256 wiper
positions (0~255).
9
FN8175.3
November 22, 2005
X9279
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Table 4. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
VVVVVVVV
(MSB) (LSB)
Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
NV NV NV NV NV NV NV NV
MSB LSB
Instructions
Four of the seven instructions are three bytes in
length. These instructions are:
– Read Wiper Counter Register – read the current
wiper position of the potentiometer,
– Write Wiper Counter Register – change current
wiper position of the potentiometer,
– Read Data Register – read the contents of the
selected Data Register;
– Write Data Register – write a new value to the
selected Data Register.
The basic sequence of the three byte instructions is
illustrated in Figure 4. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t
. A transfer
WRL
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and t akes a
minimum of t
to complete. The transfer can occur
WR
between the potentiometer and one of its four
associated registers (Bank 0).
Two instructions require a two-byte sequence to
complete. These instructions transfer data between the
host and the X9279; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
– XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the Wiper Counter Register.
– XFR Wiper Counter Register to Data Register –
This transfers the contents of the Wiper Counter
Register to the specified Data Register.
The final command is Increment/Decrement (Figure 5
and 6). The Increment/Decrement command is
different from the other commands. Once the
command is issued and the X9279 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (t
) while SDA is HIGH,
HIGH
the selected wiper will move one resistor segment
towards the R
terminal. Similarly, for each SCL clock
H
pulse while SDA is LOW, the selected wiper will move
one resistor segment tow ards the R
terminal.
L
See Instruction format for more details.
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
0101
ID3 ID2 ID1 ID0
S
T
A
R
Device ID
T
10
A1
A2 A0
0
Internal
Address
A
C
K
I3 I2
Instruction
Opcode
RB RA P1 A
I0
I1
Register
Address
00
These commands only valid when P1 = P0 = 0
P0
C
K
Pot/Bank
Address
S
T
O
P
FN8175.3
November 22, 2005
Figure 4. Three-Byte Instruction Sequence
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SCL
X9279
SDA
0101
S
ID3 ID2
T
A
R
Device ID
T
ID1
ID0
0
0
A2 A1 A0
External
Address
A
C
K
I3
I2
Instruction
Opcode
I1
Figure 5. Increment/Decrement Instruction Squence
SCL
SDA
0101
ID3 ID2 ID1 ID0
S
T
A
Device ID
R
T
0
0
A2 A1 A0
External
Address
A
C
K
I3
Instruction
I2
Opcode
Figure 6. Increment/Decrement Timing Limits
I0
I1
RB RA
Register
Address
I0
RB
Register
Address
A
P1 P0
Pot/Bank
Address
RA P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
C
K
WCR[7:0] valid only when P1=P0=0;
Data Register D[7:0] for all values of P1 and P0
A
C
N
K
Pot/Bank
Address
C
1
or
I
I
N
C
2
I
N
C
n
S
A
T
C
O
K
P
D
E
C
1
S
D
T
E
O
C
P
n
INC/DEC
CMD
Issued
SCL
SDA
VW/R
t
WRID
W
Voltage Out
11
FN8175.3
November 22, 2005
INSTRUCTION FORMAT
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Read Wiper Counter Register (WCR)
X9279
Device Type
S
Identifier
T
A
R
0 1 0 10A 2A 1A 0 10010000
T
Device
Addresses
Instruction
S
A
C
K
Opcode
DR/Bank
Addresses
Write Wiper Counter Register (WCR)
Device Type
S
Identifier
T
A
R
01010A 2A 1A 0 10100000
T
Device
Addresses
Instruction
S
A
C
K
Opcode
DR/Bank
Addresses
Read Data Register (DR)
Device Type
S
Identifier
T
A
R
01010A 2A 1A 0 1011RBRAP1 P0
T
Device
Addresses
Instruction
S
A
C
K
Opcode
DR/Bank
Addresses
Wiper Position
S
(Sent by X9279 on SDA)
A
W
W
W
W
C
C
C
R
R
K
7
6
Wiper Position
S
(Sent by Master on SDA)
A
W
W
C
C
C
R
R
K
7
6
S
(Sent by X9279 on SDA)
A
W
C
C
R
K
7
W
C
C
C
R
R
R
5
4
3
W
W
W
C
C
C
R
R
R
5
4
3
Wiper Position
W
W
C
C
R
R
5
6
W
C
R
4
W
C
R
W
C
R
2
S
M
T
W
2
W
C
R
1
W
C
R
3
A
W
O
C
C
C
P
K
R
R
1
0
S
S
T
A
W
O
C
C
P
K
R
0
S
M
T
W
C
R
A
W
O
C
C
P
K
R
1
0
W
C
R
2
Write Data Register (DR)
Device Type
S
Identifier
T
A
R
0 1 0 1 0A 2A 1A 0 1 1 0 0RBRAP1 P0
T
Device
Addresses S
Instruction
Opcode
A
C
K
DR/Bank
Addresses S
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type
S
Identifier
T
A
R
0 1 0 1 0A 2A 1A 0 1 1 1 0 RBRA 0 0
T
Device
Addresses
Instruction
S
A
C
K
Opcode
DR/Bank
Addresses
Wiper Position
(Sent by Master on SDA) S
A
W
W
W
W
C
C
C
R
R
K
7
6
S
S
HIGH-VOLTAGE
T
A
WRITE CYCLE
O
C
P
K
W
C
C
C
R
R
R
5
4
3
W
C
R
S
T
A
W
W
O
C
C
C
P
K
R
R
2
1
0
WRITE CYCLE
HIGH-VOLTAGE
12
FN8175.3
November 22, 2005
X9279
www.BDTIC.com/Intersil
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
S
Identifier
T
A
R
0 1 010A 2A 1A 0 1101RBRA00
T
Device
Addresses
Instruction
S
A
C
K
Opcode
DR/Bank
Addresses
S
S
T
A
O
C
P
K
Increment/Decrement Wiper Counter Register (WCR)
Device Type
S
Identifier
T
A
R
0 1 0 1 0 A 2 A 1 A 0 0 0 1 0 0 0 0 0 I/D I/D . . . . I/D I/D
T
Notes: (1) “MACK”/”SACK”: stands for the ac knowledge sent b y the master/slav e.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during activ e SCL phase (high).
Device
Addresses
S
A
C
K
Instruction
Opcode
DR/Bank
Addresses
S
A
C
K
Increment/Decrement
(Sent by Master on SDA)
S
T
O
P
13
FN8175.3
November 22, 2005
X9279
www.BDTIC.com/Intersil
ABSOLUTE MAXIMUM RATINGS
Temperature under bias..................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
V oltage on SCL, SD A any ad dress input
with respect to V
∆V = | (V
- VL) |...................................................5.5V
H
................................. -1V to +7V
SS
Lead temperature (soldering, 10s) .................... 300°C
(10s)..............................................................±6mA
I
W
RECOMMENDED OPERATING CONDITIONS
Temp Min. Max.
Commercial 0°C+70°C
Industrial -40°C+85°C
ANALOG CHARACTERISTICS
(Over recommended industrial (2.7V) operating conditions unless otherwise stated.)
Symbol Parameter
R
TOTAL
R
TOTAL
End to End Resistance 100 kΩ T version
End to End Resistance 50 kΩ U version
End to End Resistance Tolerance ±20 %
Power Rating 50 mW 25°C, each pot
I
W
R
W
R
W
V
TERM
Wiper Current ±3 mA
Wiper Resistance 300 Ω IW = ± 3mA @ VCC = 3V
Wiper Resistance 150 Ω IW = ± 3mA @ VCC = 5V
Voltage on any RH or RL Pin V
SS
Noise -120 dBV/√
Resolution
Absolute Linearity
(1)
COMMENT
Stresses above those liste d under “Abso lute Maxim um
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect de vice reliabi lity.
Device Supply Voltage (VCC)
(4)
X9279 5V ± 10%
X9279-2.7 2.7V to 5.5V
Limits
Test ConditionsMin. Typ. Max. Units
V
CC
VV
SS
= 0V
Hz Ref: 1V
0.4 %
±1 MI
(3)
R
w(n)(actual)
- R
w(n)(expected)
Limits
(5)
Relative Linearity
(2)
Temperature Coefficient of
R
TOTAL
±0.2 MI
±300 ppm/°C
(3)
R
w(n + 1)
- [R
w(n) + MI
]
(5)
Ratiometric Temp. Coefficient 20 ppm/°C
C
H/CL/CW
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
(3) MI = RTO T / 255 or (R
(4) During power-up V
(5) n = 0, 1, 2, ....,255; m =0, 1, 2, ...., 254.
Potentiometer Capacitances 10/10/25 pF See Macro model
potentiometer.
potentiometer. It is a measure of the error in step size.
- RL) / 255, single pot
H
> VH, VL, and VW.
CC
14
FN8175.3
November 22, 2005
X9279
www.BDTIC.com/Intersil
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol Parameter
I
CC1
VCC supply current
(active)
I
CC2
VCC supply current
(nonvolatile write)
I
SB
I
LI
I
LO
V
IH
V
IL
V
OL
V
OH
VCC current (standby) 5 µAVCC = +6V; VIN = VSS or VCC;
Input leakage current 10 µAVIN = VSS to V
Output leakage current 10 µAV
Input HIGH voltage VCC x 0.7 VCC + 1 V
Input LOW voltage -1 VCC x 0.3 V
Output LOW voltage 0.4 V IOL = 3mA
Output HIGH voltage
ENDURANCE AND DATA RETENTION
3mAf
SCL
SDA = Open; (for 2-Wire, Active, Read
and Volatile Write States only)
5mAf
SCL
SDA = Open; (for 2-Wire, Active,
Nonvolatile Write State only)
SDA = V
State only)
OUT
Test ConditionsMin. Typ. Max. Units
= 400kHz; VCC = +6V;
= 400kHz; VCC = +6V;
; (for 2-Wire, Standby
CC
CC
= VSS to V
CC
Parameter Min. Units
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 years
CAPACITANCE
Symbol Test Max. Units Test Conditions
IN/OUT
(6)
IN
(6)
Input / Output capacitance (SDA) 8 pF V
Input capacitance (SCL, WP, A2, A1 and A0)6 pFV
OUT
IN
= 0V
C
C
POWER-UP TIMING
Symbol Parameter Min. Max. Units
(6)
tr V
t
PUR
t
PUW
CC
(7)
(7)
VCC Power-up rate 0.2 50 V/ms
Power-up to initiation of read operation 1 ms
Power-up to initiation of write operation 50 ms
A.C. TEST CONDITIONS
Input Pulse Levels V
x 0.1 to VCC x 0.9
CC
Input rise and fall times 10ns
Input and output timing level V
Notes: (6) This parameter is not 100% tested
(7) t
and t
PUR
These parameters are periodically sampled and not 100% tested.
are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued.
PUW
CC
x 0.5
= 0V
15
FN8175.3
November 22, 2005
EQUIVALENT A.C. LOAD CIRCUIT
www.BDTIC.com/Intersil
X9279
SPICE Macromodel
R
TOTAL
C
L
10pF
R
W
C
W
25pF
C
10pF
R
L
L
SDA pin
5V
1533
100pF
3V
Ω
SDA pin
867
Ω
100pF
R
H
AC TIMING
Symbol Parameter Min. Max. Units
f
SCL
t
CYC
t
HIGH
t
LOW
t
SU:STA
t
HD:STA
t
SU:STO
t
SU:DAT
t
HD:DAT
t
R
t
F
t
AA
t
DH
T
I
t
BUF
t
SU:WPA
t
HD:WPA
Clock Frequency 400 kHz
Clock Cycle Time 2500 ns
Clock High Time 600 ns
Clock Low Time 1300 ns
Start Setup Time 600 ns
Start Hold Time 600 ns
Stop Setup Time 600 ns
SDA Data Input Setup Time 100 ns
SDA Data Input Hold Time 30 ns
SCL and SDA Rise Time 300 ns
SCL and SDA Fall Time 300 ns
SCL Low to SDA Data Output Valid Time 0.9 µs
SDA Data Output Hold Time 0 ns
Noise Suppression Time Constant at SCL and SDA inputs 50 ns
Bus Free Time (Prior to Any Transmission) 1200 ns
A0, A1 Setup Time 0 ns
A0, A1 Hold Time 0 ns
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol Parameter Typ. Max. Units
t
WR
High-voltage write cycle time (store instructions) 5 10 ms
16
FN8175.3
November 22, 2005
X9279
www.BDTIC.com/Intersil
XDCP TIMING
Symbol Parameter Min. Max. Units
t
WRPO
t
WRL
SYMBOL TABLE
WAVEFORM INPUTS OUTPUTS
Wiper response time after the third (last) power supply is stable 5 10 µs
Wiper response time after instruction issued (all load instructions) 5 10 µs
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/A Center Line
.
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
is High
Impedance
17
FN8175.3
November 22, 2005
TIMING DIAGRAMS
www.BDTIC.com/Intersil
Start and Stop Timing
SCL
t
SU:STA
SDA
Input Timing
X9279
(START) (STOP)
t
F
t
SU:STO
t
F
t
HD:STA
t
R
t
R
SCL
SDA
Output Timing
SCL
SDA
t
CYC
t
SU:DAT
t
HIGH
t
LOW
t
HD:DAT
t
AA
t
DH
t
BUF
18
FN8175.3
November 22, 2005
XDCP Timing (for All Load Instructions)
www.BDTIC.com/Intersil
SCL
X9279
(STOP)
SDA
VWx
Write Protect and Device Address Pins Timing
(START) (STOP)
SCL
SDA
WP
A0, A1
t
SU:WPA
LSB
t
WRL
...
(Any Instruction)
...
...
t
HD:WPA
19
FN8175.3
November 22, 2005
APPLICATIONS INFORMATION
www.BDTIC.com/Intersil
Basic Configurations of Electronic Potentiometers
V
R
RW
X9279
+V
R
I
Three terminal Potentiometer;
Application Circuits
Noninverting Amplifier Voltage Regulator
V
S
VO = (1+R2/R1)V
Offset Voltage Adjustment Comparator with Hysterisis
Variable v oltage divider
+
–
R
2
R
1
S
Two terminal Variable Resistor;
Variable current
V
O
IN
VO (REG) = 1.25V (1+R2/R1)+I
I
adj
317
R
1
R
2
VO (REG)V
adj R2
–
+
R
2
TL072
V
S
V
O
}
R
VUL = {R1/(R1+R2)} VO(max)
RL
= {R1/(R1+R2)} VO(min)
L
V
S
10kΩ
R
1
100kΩ
-12V+12V
10kΩ10kΩ
20
–
+
}
R
2
1
V
O
FN8175.3
November 22, 2005
Application Circuits (continued)
www.BDTIC.com/Intersil
Attenuator Filter
R
1
V
S
R
3
R
4
VO = G V
-1/2 ≤ G ≤ +1/2
R
–
+
R1 = R2 = R3 = R4 = 10kΩ
S
Inverting Amplifier Equivalent L-R Circuit
R
R
V
S
2
1
}
}
–
+
X9279
C
V
S
2
V
O
V
V
O
S
R
C
1
G
= 1 + R2/R
O
fc = 1/(2πRC)
+
–
R
R
1
1
R
2
+
–
V
O
2
VO = G V
G = - R2/R
S
1
Function Generator
–
+
frequency ∝ R1, R2, C
amplitude ∝ R
, R
A
B
R
Z
IN
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R
R
2
R
}
A
R
}
B
R
1
1
–
+
1
R
3
+ R3) >> R
C
2
21
FN8175.3
November 22, 2005
PACKAGING INFORMATION
www.BDTIC.com/Intersil
X9279
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
0° - 8°
.0075 (.19)
.0118 (.30)
.193 (4.9)
.200 (5.1)
.019 (.50)
.029 (.75)
DetailA (20X)
.169 (4.3)
.177 (4.5)
.047 (1.20)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
Seating Plane
.252 (6.4) BSC
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
22
FN8175.3
November 22, 2005
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