intersil X9279 DATA SHEET

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X9279

Single Supply/Low Power/256-Tap/2-Wire Bus

Data Sheet November 22, 2005

Single Digitally-Controlled (XDCP™) Potentiometer

FEATURES

• 256 Resistor Taps

• 2-Wire Serial Interface for Write, Read, and Transfer Operations of the Potentiometer

• Wiper Resistance, 100Ω Typical @ 5V

• 16 Nonvolatile Data Registers for Each Potentiometer

• Nonvolatile Storage of Multiple Wiper Positions

• Power -on Recall. Loads Sa ved Wiper P osition o n Power-up.

• Standby Current < 5µA Max

: 2.7V to 5.5V Operation

•V

•50kΩ, 100kΩ Versions of End to End Resistance

• Endurance: 100,000 Data Changes per Bit per Register

• 100 yr. Data Retention

• 14 Ld TSSOP

• Low Power CMOS

• Pb-Free Plus Anneal Available (RoHS Compliant)

FN8175.3

DESCRIPTION

The X9279 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit.

The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected t o the wiper terminal through switches. The position of the wiper on the array is controlled b y th e user throug h the 2-Wire bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four nonvolatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR.

The XDCP can be used as a three-terminal potentiometer or as a two ter minal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

Address

Data

2-Wire

Bus

Interface

Status

Bus

Interface

and Control

Write Read

Transfer

Inc/Dec

Control

Power-on Recall

Wiper Counter Register (WCR)

Data Registers

16 Bytes

50kΩ and 100kΩ

256-taps

POT

wiper

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

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Ordering Information

POTENTIOMETER

PART NUMBER PART MARKING VCC LIMITS (V)

X9279TV14* X9279TV 5 ±10% 100 0 to 70 14 Ld TSSOP (4.4mm)

X9279TV14Z* X9279TVZ 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)

X9279TV14I* X9279TV I -40 to 85 14 Ld TSSOP (4.4mm)

X9279TV14IZ* X9279TV ZI -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9279UV14* X9279UV 50 0 to 70 14 Ld TSSOP (4.4mm)

X9279UV14Z* (Note) X9279UV Z 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)

X9279UV14I* X9279UV I -40 to 85 14 Ld TSSOP (4.4mm)

X9279UV14IZ* (Note) X9279UV ZI -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9279TV14-2.7* X9279TV F 2.7 to 5.5 100 0 to 70 14 Ld TSSOP (4.4mm)

X9279TV14Z-2.7* X9279TV ZF 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)

X9279TV14I-2.7* X9279TV G -40 to 85 14 Ld TSSOP (4.4mm)

X9279TV14IZ-2.7* X9279TV ZG -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9279UV14-2.7* X9279UV F 50 0 to 70 14 Ld TSSOP (4.4mm)

X9279UV14Z-2.7* (Note) X9279UV ZF 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free)

X9279UV14I-2.7* X9279UV G -40 to 85 14 Ld TSSOP (4.4mm)

X9279UV14IZ-2.7* (Note) X9279UV ZG -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE

DETAILED FUNCTIONAL DIAGRAM

SCL

SDA

A2 A1

INTERFACE

AND

CONTROL

CIRCUITRY

DATA

Control

Bank 0

DR0 DR1

DR2 DR3

Power-on Recall

WIPER

COUNTER REGISTER

(WCR)

Bank 1

DR0

DR2 DR3 12 additional nonvolatile registers

3 Banks of 4 registers x 8-bits

DR1

Bank 2

DR0 DR1

DR2 DR3

50kΩ and 100kΩ

Bank 3

DR0 DR1

DR2 DR3

256-taps

FN8175.3

November 22, 2005

X9279

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CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal conditioning circuits

• Vary the freque n cy an d du ty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF circuits

• Provide a control variable (I, V, or R) in feedback circuits

PIN CONFIGURATION

SCL

SDA

TSSOP

X9279

2 3 4 5 6 7

SYSTEM LEVEL APPLICATIONS

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in communication systems

• Set and regulate the DC biasing point in an RF power amplifier in wireless systems

• Control the gain in audio and home entertainment systems

• Provide the variable DC bias for tuners in RF wireless systems

• Set the operating points in temperature control systems

• Control the operating point for sensors in industrial systems

• Trim offset and gain errors in artificial intelligent systems

13 12 11 10

9 8

R R

A3 A1 WP

L H

PIN ASSIGNMENTS

TSSOP Symbol Function

1 NC No Connect 2 A0 Device Address for 2-Wire bus. 3 NC No Connect 4 A2 Device Address for 2-Wire bus. 5 SCL Serial Clock for 2-Wire bus. 6 SDA Serial Data Input/Output for 2-Wire bus. 7V

8WP

System Ground. Hardware Write Protect

9 A1 Device Address for 2-Wire bus. 10 A3 Device Address for 2 wire-bus. 11 R 12 R 13 R 14 V

H L

Wiper Terminal of the Potentiometer. High Terminal of the Potentiometer. Low Terminal of the Potentiometer. System Supply Voltage.

FN8175.3

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X9279

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PIN DESCRIPTIONS

Bus Interface Pins

ERIAL DATA INPUT/OUTPUT (SDA)

The SDA is a bidirectional serial data input/output pin for a 2-Wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from an 2-Wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL.

It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph.

ERIAL CLOCK (SCL)

This input is used by 2-Wire master to supply 2-Wire serial clock to the X9279.

Potentiometer Pins

, RL

The R connections on a mechanical potentiometer.

The wiper pin is equivalent to the wiper terminal of a mechanical potentiometer.

Bias Supply Pins

S G

The V pin is the system ground.

Other Pins

No connect pins should be left open. This pins are used for Intersil manufacturing and testing purposes.

and RL pins are equivalent to the terminal

YSTEM SUPPLY VOLTAGE (V

ROUND (V

O CONNECT

)

pin is the system supply voltage. The V

) AND SUPPLY

EVICE ADDRESS (A2 - A0)

The Address inputs are used to set the least significant 3 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9279. A maximum of 8 devices may occup y the 2-Wire serial bus .

ARDWARE WRITE PROTECT INPUT (WP)

The WP the Data Registers.

pin when LOW prevents nonvolatile writes to

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X9279

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PRINCIPLES OF OPERATION

The X9279 is a integrated microcircuit incorporating a resistor array and associated registers and counter and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. This section provides detail description of the followi ng:

– Resistor Array Description. – Serial Interface Description. – Instruction and Register Description.

Array Description

The X9279 is comprised of a resistor array (See Figure

1). The array contains, in effect, 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R

and RL inputs).

Figure 1. Detailed Potentiometer Block Diagram

At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper

) output. Within each individual array only one

switch may be turned on at a time. These switches are controlled by a Wiper Counter

The WCR may be written directly. These Data Registers can the WCR can be read and written b y the host system.

Power-up and Down Recommendations.

There are no restrictions on the power-up or powerdown conditions of V the potentiometer pins provided that V more positive than or equal to V

≥ VH, VL, VW. The VCC ramp rate specification is

and the voltages applied to

, VL, and VW, i.e.,

is always

always in effect.

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

IF WCR = 00[H] THEN RW = R

IF WCR = FF[H] THEN RW = R

(DR0) (DR1)

8 8

BANK_0 Only

(DR2)

(DR3)

MODIFIED SCK

UP/DN

SERIAL BUS INPUT

PARALLEL BUS INPUT

WIPER COUNTER REGISTER

(WCR)

INC/DEC

LOGIC

UP/DN CLK

C O

U N

T E R

D E C O D E

FN8175.3

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X9279

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SERIAL INTERFACE DESCRIPTION

Serial Interface

The X9279 supports a bidirectional bus oriented protocol. The protocol de fines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9279 will be considered a slave de vice in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 2.

Start Condition

All commands to the X9279 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9279 continuously monitors

the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. See Figure 2.

Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. See Figure 2.

Acknowledge

Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on th e bus to indicate the success ful re cei pt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data.

The X9279 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9279 will respond with a final acknowledge. See Figure 2.

Figure 2. Acknowledge Response from Receiver

SCL FROM

MASTER

DATA

OUTPUT

TRANSMITTER

FROM

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

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Acknowledge Polling

The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9279 initiates the internal write cycle. ACK polling, Flow 1, can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9279 is still busy with the write operation no ACK will be returned. If the X9279 has completed the write operation an ACK will be returned and the master can then proceed with the next operation.

FLOW 1: ACK Polling Sequence

Nonvolatile Write

Command Completed

EnterACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Yes

Further

Operation?

Yes

Issue STOP

INSTRUCTION AND REGISTER DESCRIPTION

Device Addressing: Identification Byte ( ID and A)

The first byte sent to the X9279 from the host, following a CS

going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device ID for the X9279; this is fixed as 0101[B] (refer to Table 1).

The A[2:0] bits in the ID byte is the internal slave address. The physica l de vice a ddress is defined by the state of the A2 - A0 input pins. The slave address is externally specified by the user. The X9279 compares the serial data stream with the address input state; a successful compare of both address bits is required f or the X9279 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A2 - A0 inputs can be actively driven by CM OS input signals or tied to

or VSS.

Instruction Byte (I)

The next byte sent to the X9279 contains the instruction and register po inter information. The three most significant bits are used provide the instruction opcode I [2:0]. The RB and RA bits point to one of the four Data Registers . P0 is the POT selection; since the X9279 is single POT, the P0 = 0. The format is shown in Table 2.

There are 16 registers organized into four banks. Bank 0 is the default bank of registers. Only Bank 0 registers can be used for Data Register to Wiper Counter Register operations .

Issue

Instruction

Issue STOP

Banks 1, 2, and 3 are additional banks of registers (12 total) that can be used for 2-Wire write and read operations. The Data Registers in Banks 1, 2, and 3 cannot be used for direct read/write operations

Proceed

between the Wiper Counter Reg ister.

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