intersil X9271 DATA SHEET

®

www.BDTIC.com/Intersil

X9271

Single Supply/Low Power/256-Tap/SPI Bus

Data Sheet November 22, 2005

Single Digitally-Controlled (XDCP™)
Potentiometer

FEATURES

• 256 Resistor Taps

• SPI Serial Interface for write, read, and transfer
operations of the potentiometer

• Wiper Resistance, 100Ω typical @ V

• 16 Nonvolatile Data Registers

• Nonvolatile Storage of Multiple Wiper Positions

• Power -on Recall. Loads Sa ved Wiper P osition o n
Power-up.

• Standby Current < 3µA Max

: 2.7V to 5.5V Operation

•V

CC

•50kΩ, 100kΩ versions of End to End Resistance

• 100 yr. Data Retention

• Endurance: 100,000 Data Changes per Bit per
Register

• 14-Lead TSSOP

• Low Power CMOS

• Pb-Free Plus Anneal Available (RoHS Compliant)

CC

= 5V

FN8174.2

DESCRIPTION

The X9271 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and a four
nonvolatile Data Registers that can be directly written to
and read by the user. The contents of the WCR controls
the position of the wiper on the resistor array though the
switches. Powerup recalls the contents of the default
data register (DR0) to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two ter minal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

Address

Data

SPI
Bus

Interface

Status

V

CC

Bus

Interface

and Control

V

SS

Write
Read

Transfer

Inc/Dec

Control

Power-on Recall

Wiper Counter
Register (WCR)

Data Registers

16 Bytes

R

H

50kΩ and 100kΩ

256-taps

POT

R

R

W

L

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9271

www.BDTIC.com/Intersil

Ordering Information

POTENTIOMETER

V

LIMITS

PART NUMBER PART MARKING

X9271UV14* X9271UV 5 ±10% 50 0 to +70 14 Ld TSSOP (4.4mm)

X9271UV14I* X9271UV I -40 to 85 14 Ld TSSOP (4.4mm)

X9271UV14IZ* (Note) X9271UV ZI -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9271UV14Z* (Note) X9271UV Z 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free)

X9271TV14* X9271TV 100 0 to +70 14 Ld TSSOP (4.4mm)

X9271TV14I* X9271TV I -40 to 85 14 Ld TSSOP (4.4mm)

X9271TV14IZ* (Note) X9271TV ZI -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9271TV14Z* (Note) X9271TV Z 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free)

X9271UV14-2.7* X9271UV F 2.7 to 5.5 50 0 to +70 14 Ld TSSOP (4.4mm)

X9271UV14I-2.7* X9271UV G -40 to 85 14 Ld TSSOP (4.4mm)

X9271UV14IZ-2.7* (Note) X9271UV ZF -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9271UV14Z-2.7* (Note) X9271UV ZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free)

X9271TV14-2.7* X9271TV F 100 0 to +70 14 Ld TSSOP (4.4mm)

X9271TV14I-2.7* X9271TV G -40 to 85 14 Ld TSSOP (4.4mm)

X9271TV14IZ-2.7* (Note) X9271TV ZG -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9271TV14Z-2.7* (Note) X9271TV ZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free)

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

CC

(V)

ORGANIZATION

(kΩ)

TEMPERATURE

RANGE (°C) PACKAGE

2

FN8174.2

November 22, 2005

DETAILED FUNCTIONAL DIAGRAM

www.BDTIC.com/Intersil

V

CC

X9271

HOLD

CS

SCK

SO

SI

A0
A1

WP

INTERFACE

AND

CONTROL

CIRCUITRY

V

SS

DATA

Control

CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a v oltage am plifier
circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and
Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

• Vary the freque n cy an d du ty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF
circuits

• Provide a control variable (I, V, or R) in feedback
circuits

Bank 0
R0R

R2R

Power-on Recall

1

WIPER

COUNTER
REGISTER

(WCR)

3

Bank 1

R0R

R2R

12 additional nonvolatile registers
3 Banks of 4 registers x 8-bits

1

3

Bank 2
R0R

R2R

50kΩ and 100kΩ

Bank 3
R0R

1

R2R

3

256-taps

1

3

R

R

R

SYSTEM LEVEL APPLICATIONS

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems

• Control the gain in audio and home entertainment
systems

• Provide the variable DC bias for tuners in RF
wireless systems

• Set the operating points in temperature control
systems

• Control the operating point for sensors in industrial
systems

• Trim offset and gain errors in artificial intelligent
systems

H

L

W

3

FN8174.2

November 22, 2005

X9271

www.BDTIC.com/Intersil

PIN CONFIGURATION

TSSOP

S0

1

A0

2

NC

3

CS

SCK

V

4
5

SI

6
7

SS

PIN ASSIGNMENTS

TSSOP Symbol Function

1 SO Serial Data Output.
2 A0 Device Address.
3 NC No Connect.
4CS
5 SCK Serial Clock.
6 SI Serial Data Input.
7V
8WP

9 A1 Device Address.
10 HOLD
11 R
12 R
13 R
14 V

X9271

SS

W

H

L

CC

14

V

CC

R

13
12
11
10

L

R

H

R

W

HOLD

A1

9

8

WP

Chip Select.

System Ground.
Hardware Write Protect.

Device select. Pause the serial bus.
Wiper Terminal of the Potentiometer.
High Terminal of the Potentiometer.
Low Terminal of the Potentiometer.
System Supply Voltage.

4

FN8174.2

November 22, 2005

X9271

www.BDTIC.com/Intersil

PIN DESCRIPTIONS

Bus Interface Pins

ERIAL OUTPUT (SO)

S

SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.

ERIAL INPUT

S

SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.

ERIAL CLOCK (SCK)

S

The SCK input is used to clock data into and out of the
X9271.

OLD (HOLD)

H

HOLD

is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD
serial communication with the controller without resetting
the serial sequence. To pause, HOLD
LOW while SCK is LOW. To resume communication,

is brought HIGH, again while SCK is LOW. If the

HOLD
pause feature is not u se d, HO L D
all times. CMOS level input.

may be used to pause the

must be brought

should be held HIGH at

Potentiometer Pins

, RL

R

H

The R
connections on a mechanical potentiometer.

R

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.

Supply Pins

S
G

The V
pin is the system ground.

Other Pins

H

The WP
the Data Registers.

N

No connect pins should be left floating . This pins are
used for Intersil man uf acturing and test ing purposes.

and RL pins are equivalent to the terminal

H

W

YSTEM SUPPLY VOLTAGE (V
ROUND (V

CC

ARDWARE WRITE PROTECT INPUT (WP)

O CONNECT.

)

SS

pin is the system supply voltage. The V

pin when LOW prevents nonvolatile writes to

) AND SUPPLY

CC

SS

EVICE ADDRESS (A1 - A0)

D

The address inputs are used to set the the 8-bit slave
address. A match in the slave address serial data
stream must be made with the address input in order
to initiate communication with the X9271.

HIP SELECT (CS)

C

When CS
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS
required prior to the start of any operati on.

is HIGH, the X9271 is deselected and the

LOW enables the X9271, placing it

is

5

FN8174.2

November 22, 2005

X9271

www.BDTIC.com/Intersil

PRINCIPLES OF OPERATION

Device Description

ERIAL INTERFACE

S

The X9271 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS
LOW and the HOLD

and WP pins must be HIGH

must be

during the entire operation.
The SO and SI pins can be connected together, since

they have three state outputs. This can help to reduce
system pin count.

RRAY DESCRIPTION

A

The X9271 is comprised of a resistor array (See
Figure 1). The array contains the equivalent of 255
discrete resistive segments that are connected in

Figure 1. Detailed Potentiometer Block Diagram

series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer

and RL inputs).

(R

H

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper

) output. Within each individual array only one

(R

W

switch may be turned on at a time.
These switches are controlled by a Wiper Counter

Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).

OWER-UP AND DOWN RECOMMENDATIONS.

P

There are no restrictions on the power-up or power­down conditions of V
the potentiometer pins provided that V
more positive than or equal to V

≥ VH, VL, VW. The VCC ramp rate specification is

V

CC

and the voltages applied to

CC

, VL, and VW, i.e.,

H

is always

CC

always in effect.

SERIAL DATA PATH
FROM INTERFACE

CIRCUITRY

IF WCR = 00[H] THEN RW = R
IF WCR = FF[H] THEN RW = R

REGISTER 0 REGISTER 1

(DR0) (DR1)

8 8

BANK_0 Only

REGISTER 2

(DR2) (DR3)

L

H

REGISTER 3

MODIFIED SCK

UP/DN

SERIAL
BUS
INPUT

PARALLEL
BUS
INPUT

WIPER

COUNTER

REGISTER

(WCR)

INC/DEC

LOGIC

UP/DN
CLK

R

H

C
O

U
N

T
E
R

D
E
C
O
D
E

R

L

R

W

6

FN8174.2

November 22, 2005

X9271

www.BDTIC.com/Intersil

DEVICE DESCRIPTION

Wiper Counter Register (WCR)

The X9271 contains a Wiper Counter Register for the
DCP potentiometer. The Wiper Counter Register can
be envisioned as a 8-bit parallel and serial load
counter with its outputs decoded to select one of 256
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written
directly by the host via the Write Wiper Counter
Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step
at a time by the Increment/ Decrement instruction.
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9271 is powered­down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the R0 value into the WCR. The
DR0 value of Bank 0 is the def ault va lue.

Data Registers (DR3–DR0)

The potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user pref erence d ata.

Bits [7:0] are used to store one of the 256 wiper
positions or data (0 ~255).

Status Register (SR)

This 1-bit Status Register is used to store the system
status.

WIP: Write In Progress status bit, read only.
– When WIP=1, indicates that high-v oltage write cycle

is in progress.

– When WIP=0, indicates that no high-voltage write

cycle is in progress

Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).

WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0

VVVVVVVV

(MSB) (LSB)

Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Nonvolatile, NV).

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

NV NV NV NV NV NV NV NV

MSB LSB

Table 3. Status Register, SR (WIP is 1-bit)

WIP

(LSB)

7

FN8174.2

November 22, 2005