intersil X9268 DATA SHEET

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X9268

Dual Supply/Low Power/256-Tap/2-Wire Bus

Data Sheet August 29, 2006

Dual Digitally-Controlled (XDCP™) Potentiometers

FEATURES

• Dual–Two Separate Potentiometers

• 256 Resistor Taps/Pot–0.4% Resolution

• 2-Wire Serial Interface for Write, Read, and Transfer Operations of the Potentiometer

• Wiper Resistance, 100Ω typical @ V+ = 5V, V- = -5V

• 16 Nonvolatile Data Registers for Each Potentiometer

• Nonvolatile Storage of Multiple Wiper Positions

• Power-on Recall. Loads Saved Wiper Position on Power-up.

• Standby Current <5µA Max

: ±2.7V to ±5.5V Operation

•V

•50kΩ, 100kΩ Versions of End to End Pot Resistance

• Endurance: 100,000 Data Changes per Bit per Register

• 100 yr. Data Retention

• 24 Ld SOIC

• Low Power CMOS

• Power Supply V

• Pb-Free Plus Anneal Available (RoHS Compliant)

= ±2.7V to ±5.5V

V+ = 2.7V to 5.5V V- = -2.7V to -5.5V

FN8172.4

DESCRIPTION

The X9268 integrates 2 digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit.

The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-Wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four nonvolatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default Data Register (DR0) to the WCR.

The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

2-Wire

Bus

Interface

Address

Data

Status

Bus

Interface

and Control

Write Read

Transfer

Inc/Dec

Control

Power-on Recall

Wiper Counter

Registers (WCR)

Data Registers

(DR0–DR3)

V-

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

50kΩ or 100kΩ versions

Ordering Information

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X9268

PART

PART NUMBER

X9268TS24 X9268TS 5 ±10% 100 0 to +70 24 Ld SOIC (300mil) M24.3 X9268TS24Z (Note) X9268TS Z 0 to +70 24 Ld SOIC (300mil) (Pb-free) M24.3 X9268TS24I X9268TS I -40 to +85 24 Ld SOIC (300mil) M24.3 X9268TS24IZ (Note) X9268TS ZI -40 to +85 24 Ld SOIC (300mil) (Pb-free) M24.3 X9268US24 X9268US 50 0 to +70 24 Ld SOIC (300mil) M24.3 X9268US24Z (Note) X9268US Z 0 to +70 24 Ld SOIC (300mil) (Pb-free) M24.3 X9268US24I X9268US I -40 to +85 24 Ld SOIC (300mil) M24.3 X9268US24IZ (Note) X9268US ZI -40 to +85 24 Ld SOIC (300mil) (Pb-free) M24.3 X9268TS24I-2.7 X9268TS G 2.7 to 5.5 100 -40 to +85 24 Ld SOIC (300mil) M24.3 X9268TS24IZ-2.7 (Note) X9268TS ZG -40 to +85 24 Ld SOIC (300mil) (Pb-Free) M24.3

*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING

LIMITS

(V)

POTENTIOMETER

ORGANIZATION (kΩ)

TEMP. RANGE

(°C) PACKAGE

PKG.

DWG. #

FN8172.4

August 29, 2006

DETAILED FUNCTIONAL DIAGRAM

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X9268

SCL

SDA

A3 A2

INTERFACE

AND

CONTROL

CIRCUITRY

Data

V-

CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF circuits

• Provide a control variable (I, V, or R) in feedback circuits

Power-on Recall

R0R

R2R

Power-on Recall

R0R

R2R

Wiper Counter Register

(WCR)

Wiper Counter Register

(WCR)

Pot 0

50k

Resistor

Array Pot 1

Ω

and 100k

256-taps

Ω

SYSTEM LEVEL APPLICATIONS

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in communication systems

• Set and regulate the DC biasing point in an RF power amplifier in wireless systems

• Control the gain in audio and home entertainment systems

• Provide the variable DC bias for tuners in RF wireless systems

• Set the operating points in temperature control systems

• Control the operating point for sensors in industrial systems

• Trim offset and gain errors in artificial intelligent systems

FN8172.4

August 29, 2006

PIN CONFIGURATION

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X9268

24 LD SOIC

SCL

V-

SDA

V+

X9268

PIN ASSIGNMENTS

(SOIC) Symbol Function

1 NC No Connect

2 A0 Device Address for 2-Wire bus.

3 NC No Connect

4 NC No Connect

5 NC No Connect

6 V+ Analog Suppy Pin (Positive)

10 R

System Supply Voltage

Low Terminal for Potentiometer 0.

High Terminal for Potentiometer 0.

Wiper Terminal for Potentiometer 0.

11 A2 Device Address for 2-Wire bus.

12 WP

Hardware Write Protect

13 SDA Serial Data Input/Output for 2-Wire bus.

14 A1 Device Address for 2-Wire bus.

15 R

16 R

17 R

18 V

Low Terminal for Potentiometer 1.

High Terminal for Potentiometer 1.

Wiper Terminal for Potentiometer 1.

System Ground

19 V- Analog Supply Pin (Negative)

20 NC No Connect

21 NC No Connect

22 NC No Connect

23 SCL Serial Clock for 2-Wire bus.

24 A3 Device Address for 2-Wire bus.

FN8172.4

August 29, 2006

X9268

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PIN DESCRIPTIONS

Bus Interface Pins

ERIAL DATA INPUT/OUTPUT (SDA)

The SDA is a bidirectional serial data input/output pin for a 2-Wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from an 2-Wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL.

It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph.

ERIAL CLOCK (SCL)

This input is used by 2-Wire master to supply 2-Wire serial clock to the X9268.

EVICE ADDRESS (A3 - A0)

The address inputs are used to set the least significant 3 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9268. A maximum of 8 devices may occupy the 2-Wire serial bus.

The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 4 potentiometers, there are 2 sets of R is the terminal of POT 0 and so on.

Bias Supply Pins

YSTEM SUPPLY VOLTAGE (V

ROUND (V

The V

pin is the system ground.

Analog Supply Voltages (V+ and V

These supplies are the analog voltage supplies for the potentiometer. The V+ supply is tied to the wiper switches while the V- supply is used to bias the switches and the internal P+ substrate of the integrated circuit. Both of these supplies set the voltage limits of the potentiometer.

Other Pins

O CONNECT

No connect pins should be left open. This pins are used for Intersil manufacturing and testing purposes.

ARDWARE WRITE PROTECT INPUT (WP)

The WP the Data Registers.

)

pin is the system supply voltage. The V

pin when LOW prevents nonvolatile writes to

such that R

) AND SUPPLY

Potentiometer Pins

, RL

The R connections on a mechanical potentiometer. Since there are 2 potentiometers, there are 2 sets of R R and so on.

and RL pins are equivalent to the terminal

and

such that RH0 and RL0 are the terminals of POT 0

FN8172.4

August 29, 2006

X9268

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PRINCIPLES OF OPERATION

The X9268 is a integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. This section provides detail description of the following:

– Resistor Array Description

– Serial Interface Description

– Instruction and Register Description.

Array Description

The X9268 is comprised of a resistor array (See Figure 1). Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R

and R

inputs).

Figure 1. Detailed Potentiometer Block Diagram

One of Two Potentiometers

At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper

) output. Within each individual array only one

switch may be turned on at a time.

These switches are controlled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (See Table 1).

The WCR may be written directly. These Data Registers can the WCR can be read and written by the host system.

Power-up and Down Requirements.

At all times, the voltages on the potentiometer pins must be less than V+ and more than V-. During powerup and power-down, V final values within 1msecs of each other. The V

ramp rate spec is always in effect.

, V+, and V- must reach their

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

IF WCR = 00[H] THEN RW = R IF WCR = FF[H] THEN RW = R

(DR0) (DR1)

8 8

(DR2) (DR3)

MODIFIED SCL

UP/DN

SERIAL BUS INPUT

PARALLEL BUS INPUT

WIPER

COUNTER

(WCR)

INC/DEC

LOGIC

UP/DN

CLK

C O U N T E R

D E C O D E

FN8172.4

August 29, 2006

X9268

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SERIAL INTERFACE DESCRIPTION

Serial Interface

The X9268 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9268 will be considered a slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 2.

Start Condition

All commands to the X9268 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9268 continuously monitors

the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. See Figure 2.

Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. See Figure 2.

Acknowledge

Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data.

The X9268 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9268 will respond with a final acknowledge. See Figure 2.

Figure 2. Acknowledge Response from Receiver

SCL FROM

MASTER

DATA

OUTPUT

TRANSMITTER

FROM

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOW LEDGE

FN8172.4

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