intersil X9268 DATA SHEET

®

www.BDTIC.com/Intersil

X9268

Dual Supply/Low Power/256-Tap/2-Wire Bus

Data Sheet August 29, 2006

Dual Digitally-Controlled (XDCP™)
Potentiometers

FEATURES

• Dual–Two Separate Potentiometers

• 256 Resistor Taps/Pot–0.4% Resolution

• 2-Wire Serial Interface for Write, Read, and
Transfer Operations of the Potentiometer

• Wiper Resistance, 100Ω typical @ V+ = 5V,
V- = -5V

• 16 Nonvolatile Data Registers for Each
Potentiometer

• Nonvolatile Storage of Multiple Wiper Positions

• Power-on Recall. Loads Saved Wiper Position
on Power-up.

• Standby Current <5µA Max

: ±2.7V to ±5.5V Operation

•V

CC

•50kΩ, 100kΩ Versions of End to End Pot
Resistance

• Endurance: 100,000 Data Changes per Bit per
Register

• 100 yr. Data Retention

• 24 Ld SOIC

• Low Power CMOS

• Power Supply V

• Pb-Free Plus Anneal Available (RoHS Compliant)

= ±2.7V to ±5.5V

CC

V+ = 2.7V to 5.5V
V- = -2.7V to -5.5V

FN8172.4

DESCRIPTION

The X9268 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-Wire bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and a four nonvolatile Data Registers that can
be directly written to and read by the user. The
contents of the WCR controls the position of the wiper
on the resistor array though the switches. Powerup
recalls the contents of the default Data Register (DR0)
to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

2-Wire

Bus

Interface

Address

Data

Status

V

CC

Bus

Interface

and Control

V

SS

1

Write
Read

Transfer

Inc/Dec

Control

V

+

Power-on Recall

Wiper Counter

Registers (WCR)

Data Registers

(DR0–DR3)

V-

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

R

R

W0

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

H0

R

R

L0

R

H1

R

W1

L1

50kΩ or 100kΩ versions

Ordering Information

www.BDTIC.com/Intersil

X9268

PART

PART NUMBER

X9268TS24 X9268TS 5 ±10% 100 0 to +70 24 Ld SOIC (300mil) M24.3
X9268TS24Z (Note) X9268TS Z 0 to +70 24 Ld SOIC (300mil) (Pb-free) M24.3
X9268TS24I X9268TS I -40 to +85 24 Ld SOIC (300mil) M24.3
X9268TS24IZ (Note) X9268TS ZI -40 to +85 24 Ld SOIC (300mil) (Pb-free) M24.3
X9268US24 X9268US 50 0 to +70 24 Ld SOIC (300mil) M24.3
X9268US24Z (Note) X9268US Z 0 to +70 24 Ld SOIC (300mil) (Pb-free) M24.3
X9268US24I X9268US I -40 to +85 24 Ld SOIC (300mil) M24.3
X9268US24IZ (Note) X9268US ZI -40 to +85 24 Ld SOIC (300mil) (Pb-free) M24.3
X9268TS24I-2.7 X9268TS G 2.7 to 5.5 100 -40 to +85 24 Ld SOIC (300mil) M24.3
X9268TS24IZ-2.7 (Note) X9268TS ZG -40 to +85 24 Ld SOIC (300mil) (Pb-Free) M24.3

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING

V

CC

LIMITS

(V)

POTENTIOMETER

ORGANIZATION (kΩ)

TEMP. RANGE

(°C) PACKAGE

PKG.

DWG. #

2

FN8172.4

August 29, 2006

DETAILED FUNCTIONAL DIAGRAM

www.BDTIC.com/Intersil

X9268

R

R

R

H0

L0

W0

SCL

SDA

A3
A2

A1

A0

WP

V

CC

INTERFACE

AND

CONTROL

CIRCUITRY

V

SS

Data

V-

V

+

8

CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage ampli­fier circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and
Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF
circuits

• Provide a control variable (I, V, or R) in feedback
circuits

Power-on
Recall

R0R

1

R2R

3

Power-on
Recall

R0R

1

R2R

3

Wiper
Counter
Register

(WCR)

Wiper
Counter
Register

(WCR)

Pot 0

50k

Resistor

Array
Pot 1

Ω

and 100k

256-taps

R

R

L1

H1

Ω

R

W1

SYSTEM LEVEL APPLICATIONS

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems

• Control the gain in audio and home entertainment
systems

• Provide the variable DC bias for tuners in RF wire­less systems

• Set the operating points in temperature control
systems

• Control the operating point for sensors in industrial
systems

• Trim offset and gain errors in artificial intelligent
systems

3

FN8172.4

August 29, 2006

PIN CONFIGURATION

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X9268

24 LD SOIC

A3

SCL

NC

NC

NC

V-

V

SS

R

W1

R

H1

R

L1

A1

SDA

V

R

R

NC

A0

NC

NC

NC

V+

CC

R

H0

W0

A2

WP

L0

10

11

12

1

2

3

4

5

6

X9268

7

8

9

24

23

22

21

20

19

18

17

16

15

14

13

PIN ASSIGNMENTS

Pin

(SOIC) Symbol Function

1 NC No Connect

2 A0 Device Address for 2-Wire bus.

3 NC No Connect

4 NC No Connect

5 NC No Connect

6 V+ Analog Suppy Pin (Positive)

7V

8R

9R

10 R

CC

L0

H0

W0

System Supply Voltage

Low Terminal for Potentiometer 0.

High Terminal for Potentiometer 0.

Wiper Terminal for Potentiometer 0.

11 A2 Device Address for 2-Wire bus.

12 WP

Hardware Write Protect

13 SDA Serial Data Input/Output for 2-Wire bus.

14 A1 Device Address for 2-Wire bus.

15 R

16 R

17 R

18 V

L1

H1

W1

SS

Low Terminal for Potentiometer 1.

High Terminal for Potentiometer 1.

Wiper Terminal for Potentiometer 1.

System Ground

19 V- Analog Supply Pin (Negative)

20 NC No Connect

21 NC No Connect

22 NC No Connect

23 SCL Serial Clock for 2-Wire bus.

24 A3 Device Address for 2-Wire bus.

4

FN8172.4

August 29, 2006

X9268

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PIN DESCRIPTIONS

Bus Interface Pins

ERIAL DATA INPUT/OUTPUT (SDA)

S

The SDA is a bidirectional serial data input/output pin
for a 2-Wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-Wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of
the serial clock SCL.

It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the
guidelines for calculating typical values on the bus
pull-up resistors graph.

ERIAL CLOCK (SCL)

S

This input is used by 2-Wire master to supply 2-Wire
serial clock to the X9268.

EVICE ADDRESS (A3 - A0)

D

The address inputs are used to set the least significant
3 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9268. A maximum of 8 devices may occupy the
2-Wire serial bus.

R

W

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4
potentiometers, there are 2 sets of R
is the terminal of POT 0 and so on.

Bias Supply Pins

YSTEM SUPPLY VOLTAGE (V

S

ROUND (V

G

The V

CC

pin is the system ground.

Analog Supply Voltages (V+ and V

These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper
switches while the V- supply is used to bias the
switches and the internal P+ substrate of the
integrated circuit. Both of these supplies set the
voltage limits of the potentiometer.

Other Pins

O CONNECT

N

No connect pins should be left open. This pins are
used for Intersil manufacturing and testing purposes.

ARDWARE WRITE PROTECT INPUT (WP)

H

The WP
the Data Registers.

)

SS

pin is the system supply voltage. The V

pin when LOW prevents nonvolatile writes to

CC

such that R

W

) AND SUPPLY

-)

W0

SS

Potentiometer Pins

, RL

R

H

The R
connections on a mechanical potentiometer. Since
there are 2 potentiometers, there are 2 sets of R
R
and so on.

and RL pins are equivalent to the terminal

H

and

such that RH0 and RL0 are the terminals of POT 0

L

H

5

FN8172.4

August 29, 2006

X9268

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PRINCIPLES OF OPERATION

The X9268 is a integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:

– Resistor Array Description

– Serial Interface Description

– Instruction and Register Description.

Array Description

The X9268 is comprised of a resistor array (See
Figure 1). Each array contains 255 discrete resistive
segments that are connected in series. The physical
ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R

and R

H

inputs).

Figure 1. Detailed Potentiometer Block Diagram

One of Two Potentiometers

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper

) output. Within each individual array only one

(R

W

switch may be turned on at a time.

These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).

The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.

Power-up and Down Requirements.

At all times, the voltages on the potentiometer pins
must be less than V+ and more than V-. During power­up and power-down, V
final values within 1msecs of each other. The V

L

ramp rate spec is always in effect.

, V+, and V- must reach their

CC

CC

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

IF WCR = 00[H] THEN RW = R
IF WCR = FF[H] THEN RW = R

REGISTER 0 REGISTER 1

(DR0) (DR1)

8 8

REGISTER 2 REGISTER 3

(DR2) (DR3)

L

H

MODIFIED SCL

UP/DN

SERIAL
BUS
INPUT

PARALLEL
BUS
INPUT

WIPER

COUNTER

REGISTER

(WCR)

INC/DEC

LOGIC

UP/DN

CLK

R

H

C
O
U
N
T
E
R

D
E
C
O
D
E

R

L

R

W

6

FN8172.4

August 29, 2006

X9268

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SERIAL INTERFACE DESCRIPTION

Serial Interface

The X9268 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9268 will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 2.

Start Condition

All commands to the X9268 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9268 continuously monitors

the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 2.

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 2.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

The X9268 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9268 will respond with a final acknowledge.
See Figure 2.

Figure 2. Acknowledge Response from Receiver

SCL FROM

MASTER

DATA

OUTPUT

TRANSMITTER

FROM

DATA

OUTPUT

FROM

RECEIVER

START

1

89

ACKNOW LEDGE

7

FN8172.4

August 29, 2006

X9268

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Acknowledge Polling

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms nonvolatile write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9268
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9268 is still busy with the write operation no ACK
will be returned. If the X9268 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.

FLOW 1: ACK Polling Sequence

Nonvolatile Write

Command Completed

EnterACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Yes

No

Issue STOP

INSTRUCTION AND REGISTER DESCRIPTION

Instructions

EVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A)

D

The first byte sent to the X9268 from the host is called
the Identification Byte. The most significant four bits of
the slave address are a device type identifier. The
ID[3:0] bits is the device id for the X9268; this is fixed
as 0101[B] (refer to Table 1).

The A[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A3 - A0 input pins. The slave address
is externally specified by the user. The X9268
compares the serial data stream with the address
input state; a successful compare of both address
bits is required for the X9268 to successfully continue
the command sequence. Only the device which slave
address matches the incoming device address sent
by the master executes the instruction. The A3 - A0
inputs can be actively driven by CMOS input signals
or tied to V

NSTRUCTION BYTE (I)

I

or VSS.

CC

The next byte sent to the X9268 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode I [3:0]. The RB and RA bits point to one of the
four Data Registers of each associated XDCP. The
least significant bit points to one of two Wiper Counter
Registers or Pots. The format is shown in Table 2.

Further

Operation?

Yes

Issue

Instruction

Proceed

No

Issue STOP

Proceed

Register Selection

Register Selected RB RA

DR0 0 0

DR1 0 1

DR2 1 0

DR3 1 1

8

FN8172.4

August 29, 2006

X9268

www.BDTIC.com/Intersil

Table 1. Identification Byte Format

Device Type

Identifier

ID3 ID2 ID1 ID0 A3 A2 A1 A0

0101

(MSB) (LSB)

Table 2. Instruction Byte Format

Instruction

Opcode

I3 I2 I1 I0 RB RA 0 P0

(MSB) (LSB)

Data

Register

Selection

Table 3. Instruction Set

Instruction Set

Instruction

Read Wiper Counter
Register

Write Wiper Counter Register 101000 01/0Write new value to the Wiper Counter

Read Data Register 10111/01/001/0Read the contents of the Data Register

Write Data Register 11001/01/001/0Write new value to the Data Register

XFR Data Register to Wiper
Counter Register

XFR Wiper Counter Register
to Data Register

Global XFR Data Registers to
Wiper Counter Registers

Global XFR Wiper Counter
Registers to Data Register

Increment/Decrement Wiper
Counter Register

100100 01/0Read the contents of the Wiper Counter

11011/01/001/0Transfer the contents of the Data Register

11101/01/001/0Transfer the contents of the Wiper Counter

00011/01/00 0Transfer the contents of the Data Registers

10001/01/00 0Transfer the contents of both Wiper Counter

001000 01/0Enable Increment/decrement of the Control

Note: 1/0 = data is one or zero

Slave Address

Pot Selection

(WCR Selection)

OperationI3 I2 I1 I0 RB RA 0 P0

Register pointed to by P0

Register pointed to by P0

pointed to by P0 and RB - RA

pointed to by P0 and RB - RA

pointed to by P0 and RB - RA to its
associated Wiper Counter Register

Register pointed to by P0 to the Data
Register pointed to by RB - RA

pointed to by RB - RA of all four pots to their
respective Wiper Counter Registers

Registers to their respective data Registers
pointed to by RB - RA of all four pots

Latch pointed to by P0

9

FN8172.4

August 29, 2006

X9268

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DEVICE DESCRIPTION

Wiper Counter Register (WCR)

The X9268 contains two Wiper Counter Registers, one
for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (See Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9268 is powered­down. Although the register is automatically loaded

Table 4. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).

with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR (See
Design Considerations Section).

Data Registers (DR)

Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.

Bit [7:0] are used to store one of the 256 wiper
positions (0~255).

WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0

VVVVVVVV

(MSB) (LSB)

Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

NV NV NV NV NV NV NV NV

MSB LSB

10

FN8172.4

August 29, 2006

X9268

www.BDTIC.com/Intersil

DEVICE DESCRIPTION

Instructions

Four of the nine instructions are three bytes in length.
These instructions are:

– Read Wiper Counter Register – read the current

wiper position of the selected potentiometer,

– Write Wiper Counter Register – change current

wiper position of the selected potentiometer,

– Read Data Register – read the contents of the

selected Data Register;

– Write Data Register – write a new value to the

selected Data Register.

The basic sequence of the three byte instructions is
illustrated in Figure 4. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t
between one of the four potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and
one associated register

Four instructions require a two-byte sequence to
complete. These instructions transfer data between the
host and the X9268; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:

to complete. The transfer can occur

WR

. A transfer

WRL

– XFR Data Register to Wiper Counter Register –

This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.

– XFR Wiper Counter Register to Data Register –

This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.

– Global XFR Data Register to Wiper Counter

Register – This transfers the contents of all speci­fied Data Registers to the associated Wiper Counter
Registers.

– Global XFR Wiper Counter Register to Data

Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.

INCREMENT/DECREMENT COMMAND

The final command is Increment/Decrement (Figure 5
and 6). The Increment/Decrement command is
different from the other commands. Once the
command is issued and the X9268 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (t
the selected wiper will move one resistor segment
towards the R
pulse while SDA is LOW, the selected wiper will move
one resistor segment towards the R

See Instruction format for more details.

terminal. Similarly, for each SCL clock

H

) while SDA is HIGH,

HIGH

terminal.

L

11

FN8172.4

August 29, 2006

Figure 3. Two-Byte Instruction Sequence

www.BDTIC.com/Intersil

SCL

X9268

SDA

0101

ID3 ID2 ID1 ID0

S
T
A
R
T

Device ID

A3

A1

A2 A0

Internal
Address

A

I3
C
K

Figure 4. Three-Byte Instruction Sequence

SCL

SDA

0101

S

ID3 ID2

T
A

Device ID

R
T

ID1

ID0

A3

A2 A1 A0

Internal
Address

A
C
K

I3

I1

I2

Instruction
Opcode

I0

Figure 5. Increment/Decrement Instruction Sequence

SCL

I2 I1

Instruction
Opcode

RB RA

Register
Address

I0

RB RA 0

Register
Address

0

0P0

Pot/WCR

Address

P0

Pot/WCR

Address

A

D7 D6 D5 D4 D3 D2 D1 D0
C
K

Data Register D[7:0]

S

A

T

C

O

K

P

WCR[7:0]

or

A

S

C

T

K

O
P

SDA

0101

ID3 ID2 ID1 ID0

S
T
A

Device ID
R
T

A3

A2 A1 A0

Internal
Address

A
C
K

I3 I2

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

Issued

SCL

SDA

R

W

Voltage Out

I1

Instruction
Opcode

I0

RB

RA 0 P0

Register
Address

0

Pot/WCR

Address

A

I
N
C
1

t

WRID

I
N
C
2

C
K

D

I

E

N

C

C

1

n

S

D

T

E

O

C

P

n

12

FN8172.4

August 29, 2006

INSTRUCTION FORMAT

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Read Wiper Counter Register (WCR)

X9268

Device Type

S

Identifier

T
A
R

0101A3A2A1A0 100100 0 P0

T

Device

Addresses

Instruction
S
A
C
K

Opcode

DR/WCR

Addresses

Write Wiper Counter Register (WCR)

Device Type

S

Identifier

T
A
R

0101A3A2A1A0 101000 0 P0

T

Device

Addresses

Instruction
S
A
C
K

Opcode

DR/WCR

Addresses

Read Data Register (DR)

e Type

Devic

S

Identifier

T
A
R

01 01A3A2A1A0 1011RBRA0 P0

T

Device

Addresses

Instruction
S
A
C
K

Opcode

DR/WCR

Addresses

Wiper Position

S

(Sent by X9268 on SDA)

A

W

W

W

W

C

C

C

R

K

R
7

6

Wiper Position

S

(Sent by Master on SDA)

A

W

W

C

C

C

R

K

R
7

6

S

(Sent by X9268 on SDA)

A

W

W

C

C

C

R

K

R

7

W

C

C

C

R

R

R

5

4

3

W

W

W

C

C

C

R

R

R

5

3

4

Wiper Position

W

W

W

C

C

C

R

R

R

5

4

6

S

M

T

W

W

2

A

W

O

C

C

C

P

K

R

R

1

0

S

S

T

A

W

O

C

C

C

P

K

R

R

1

0

S

M

T

A

W

W

O

C

C

C

P

K

R

R

1

0

W
C
R

2

W
C
R

2

W

C
R

3

Write Data Register (DR)

Device Type

S

Identifier

T
A
R

0101A3A2A1A0 1100RBRA0 P0

T

Device

Addresses

Instruction
S
A
C
K

Opcode

DR/WCR

Addresses

S
A
C
K

Global XFR Data Register (DR) to Wiper Counter Register (WCR)

Device Type

S

Identifier

T
A
R

0 1 0 1 A3 A2 A1 A0 0 0 0 1 RB RA 0 0

T

Device

Addresses

S

A
C
K

Instruction

Opcode

DR/WCR

Addresses

Wiper Position

(Sent by Master on SDA)

W

W

W

W

W

W

W

C

C

C

C

R

R

7

6

S
A
C
K

C

R

R

R

5

4

3

S

T
O
P

W

C

C

C

R

R

R

2

1

S

S

T

A

O

C

P

K

0

WRITE CYCLE

HIGH-VOLTAGE

13

FN8172.4

August 29, 2006

X9268

www.BDTIC.com/Intersil

Global XFR Wiper Counter Register (WCR) to Data Register (DR)

Device Type

S

Identifier

T
A
R

0 1 0 1A3A2A1A0 1000RBRA00

T

Device

Addresses

Instruction

S
A
C
K

Opcode

DR/WCR

Addresses

S

S

T

A
C
K

HIGH-VOLTAGE

O

WRITE CYCLE

P

Transfer Wiper Counter Register (WCR) to Data Register (DR)

S

Device Type

T

Identifier
A
R

0 1 0 1A3A2A1A0 1110RBRA 0 P0

T

Device

Addresses

Instruction

S
A
C
K

Opcode

DR/WCR

Addresses

S

S

A

T

HIGH-VOLTAGE

C

O

WRITE CYCLE

K

P

Transfer Data Register (DR) to Wiper Counter Register (WCR)

S

Device Type

T

Identifier
A
R

0 1 0 1 A3 A2 A1 A0 1 1 0 1 RB RA 0 P0

T

Device

Addresses

Instruction

S
A
C
K

Opcode

DR/WCR

Addresses

S

S

T

A

O

C

P

K

Increment/Decrement Wiper Counter Register (WCR)

Device Type

S

Identifier

T
A
R

0101A3A2A1A0 001000 0 P0 I/DI/D. . . .I/DI/D

T

Device

Addresses

S
A
C
K

Instruction

Opcode

DR/WCR

Addresses

S
A
C
K

Increment/Decrement

(Sent by Master on SDA)

S
T

O

P

Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.

(2) “A3 ~ A0”: stands for the device addresses sent by the master.

(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.

(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).

(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

14

FN8172.4

August 29, 2006

X9268

www.BDTIC.com/Intersil

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C

Storage temperature ......................... -65°C to +150°C

Voltage on SDA, SCL or any address input

with respect to V
Voltage on V+ (referenced to V
Voltage on V- (referenced to V

................................. -1V to +7V

SS

)........................ 10V

SS

)........................-10V

SS

(V+) - (V-) .............................................................. 12V

Any V
Any V

.............................................................. V+

H/RH

.................................................................V-

L/RL

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.

Lead temperature (soldering, 10s) .................. +300°C

(10s) .............................................................. ±6mA

I

W

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C+70°C

Industrial -40°C+85°C

Device Supply Voltage (VCC)

X9268 5V ±10%

X9268-2.7 2.7V to 5.5V

V+ 2.7V to 5.5V

V- -2.7V to -5.5V

(4)

Limits

POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

R

TOTAL

R

TOTAL

I

W

R

W

R

W

V+ Voltage on V+ Pin X9268 +4.5 +5.5 V

V- Voltage on V- Pin X9268 -5.5 -4.5 V

V

TERM

C

H/CL/CW

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

End to End Resistance T version 100 kΩ

End to EndResistance U version 50 kΩ

End to end resistance tolerance ±20 %

Power rating +25°C, each pot 50 mW

Wiper current ±3 mA

Wiper resistance IW = ± 1mA, V+ = 3V; V- = -3V 250 Ω

Wiper resistance IW = ± 1mA, V+ = 5V; V- = -5V 150 Ω

X9268-2.7 +2.7 +5.5

X9268 -2.7 -5.5 -2.7

Voltage on any VH/RH or VL/RL pin V- V+ V

Noise Ref: 1kHz -120 dBV

Resolution

Absolute linearity

Relative linearity

Temperature coefficient of resistance ±300 ppm/°C

Ratiometric Temperature Coefficient ±20 ppm/°C

Potentiometer Capacitance See Circuit #3 10/10/25 pF

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (R
(4) During power-up V
(5) n = 0, 1, 2, …,255; m =0, 1, 2, …, 254.

(4)

(1)

(2)

- RL) / 255, single pot

H

> VH, VL, and VW.

CC

V

w(n)(actual)

V

w(n + 1)

- [V

- V

w(n) + MI

0.4 %

w(n)(expected)

]±0.6MI

±1 MI

(3)

(3)

15

FN8172.4

August 29, 2006

X9268

www.BDTIC.com/Intersil

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Symbol Parameter Test Conditions Min. Typ. Max. Units

I

CC1

I

CC2

I

SB

I

LI

I

LO

V

IH

V

IL

V

OL

V

OH

ENDURANCE AND DATA RETENTION

VCC supply current
(active)

f

= 400kHz; VCC = +6V;

SCL

SDA = Open; (for 2-Wire, Active, Read and

3mA

Volatile Write States only)

VCC supply current
(nonvolatile write)

f

= 400kHz; VCC = +6V;

SCL

SDA = Open; (for 2-Wire, Active,

5mA

Nonvolatile Write State only)

VCC current (standby) VCC = +6V; VIN = VSS or VCC;

5 µA

SDA = VCC; (for 2-Wire, Standby State only)

Input leakage current VIN = VSS to V

Output leakage current V

= VSS to V

OUT

CC

CC

10 µA

10 µA

Input HIGH voltage VCC x 0.7 VCC + 1 V

Input LOW voltage -1 VCC x 0.3 V

Output LOW voltage IOL = 3mA 0.4 V

Output HIGH voltage

Parameter Min. Units

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 years

CAPACITANCE

Symbol Test Max. Units Test Conditions

IN/OUT

(6)

IN

(6)

Input / Output capacitance (SDA) 8 pF V

Input capacitance (SCL, WP, A3, A2, A1 and A0)6 pF V

OUT

IN

= 0V

= 0V

C

C

POWER-UP TIMING

Symbol Parameter Min. Max. Units

tr V

t

PUR

CC

(6)

(7)

VCC Power-up rate

0.2 50 V/ms

Power-up to initiation of read operation 1 ms

POWER-UP AND DOWN REQUIREMENTS

The are no restrictions on the sequencing of the bias supplies V

, V+, and V- provided that all three supplies reach

CC

their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+
and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their
final value. The V

ramp rate spec is always in effect.

CC

A.C. TEST CONDITIONS

V

Input Pulse Levels

x 0.1 to VCC x 0.9

CC

Input rise and fall times 10ns

V

Input and output timing level

Notes: (6) This parameter is not 100% tested

(7) t

and t

PUR

These parameters are periodically sampled and not 100% tested.

are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued.

PUW

CC

x 0.5

16

FN8172.4

August 29, 2006

EQUIVALENT A.C. LOAD CIRCUIT

www.BDTIC.com/Intersil

X9268

SDA pin

5V

1533

100pF

Ω

SDA pin

3V

867

100pF

SPICE Macromodel

Ω

R

H

10pF

R

TOTAL

C

L

C

W

25pF

R

W

C

L

10pF

R

L

AC TIMING

Symbol Parameter Min. Max. Units

f

SCL

t

CYC

t

HIGH

t

LOW

t

SU:STA

t

HD:STA

t

SU:STO

t

SU:DAT

t

HD:DAT

t

R

t

F

t

AA

t

DH

T

I

t

BUF

t

SU:WPA

t

HD:WPA

Clock Frequency 400 kHz

Clock Cycle Time 2500 ns

Clock High Time 600 ns

Clock Low Time 1300 ns

Start Setup Time 600 ns

Start Hold Time 600 ns

Stop Setup Time 600 ns

SDA Data Input Setup Time 100 ns

SDA Data Input Hold Time 30 ns

SCL and SDA Rise Time 300 ns

SCL and SDA Fall Time 300 ns

SCL Low to SDA Data Output Valid Time 0.9 µs

SDA Data Output Hold Time 0 ns

Noise Suppression Time Constant at SCL and SDA inputs 50 ns

Bus Free Time (Prior to Any Transmission) 1200 ns

A0, A1 Setup Time 0 ns

A0, A1 Hold Time 0 ns

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Typ. Max. Units

t

WR

High-voltage write cycle time (store instructions) 5 10 ms

XDCP TIMING

Symbol Parameter Min. Max. Units

t

WRPO

t

WRL

Wiper response time after the third (last) power supply is stable 5 10 µs

Wiper response time after instruction issued (all load instructions) 5 10 µs

17

FN8172.4

August 29, 2006

TIMING DIAGRAMS

www.BDTIC.com/Intersil

Start and Stop Timing

SCL

t

SU:STA

SDA

Input Timing

X9268

(START) (STOP)

t

F

t

SU:STO

t

F

t

HD:STA

t

R

t

R

SCL

SDA

Output Timing

SCL

SDA

t

CYC

t

SU:DAT

t

HIGH

t

LOW

t

HD:DAT

t

AA

t

DH

t

BUF

18

FN8172.4

August 29, 2006

XDCP Timing (for All Load Instructions)

www.BDTIC.com/Intersil

SCL

X9268

(STOP)

SDA

VWx

Write Protect and Device Address Pins Timing

(START) (STOP)

SCL

SDA

t

SU:WPA

WP

A0, A1

LSB

t

WRL

...

(Any Instruction)

...

...

t

HD:WPA

19

FN8172.4

August 29, 2006

APPLICATIONS INFORMATION

www.BDTIC.com/Intersil

Basic Configurations of Electronic Potentiometers

V

R

RW

X9268

+V

R

I

Three terminal Potentiometer;

Application Circuits

Noninverting Amplifier Voltage Regulator

V

S

VO = (1+R2/R1)V

Offset Voltage Adjustment Comparator with Hysterisis

Variable voltage divider

+

–

R

2

R

1

S

Two terminal Variable Resistor;

Variable current

V

O

IN

VO (REG) = 1.25V (1+R2/R1)+I

317

R

1

I

adj

R

2

VO (REG)V

adj R2

–

+

R

2

TL072

V

S

V

O

}

R

VUL = {R1/(R1+R2)} VO(max)
V

= {R1/(R1+R2)} VO(min)

LL

V

S

10kΩ

R

1

100kΩ

-12V+12V

10kΩ10kΩ

20

–

+

}
R

2

1

V

O

FN8172.4

August 29, 2006

Application Circuits (continued)

www.BDTIC.com/Intersil

Attenuator Filter

R

1

V

S

R

3

R

4

VO = G V

-1/2 ≤ G ≤ +1/2

R

–

+

R1 = R2 = R3 = R4 = 10kΩ

S

Inverting Amplifier Equivalent L-R Circuit

R

R

V

S

2

1

}

}

–

+

X9268

C

V

S

2

V

O

V

V

O

S

R

C

1

G

O

fc = 1/(2πRC)

R

1

= 1 + R2/R

R

+

–

R

1

2

+

–

V

O

2

VO = G V
G = - R2/R

S

1

Function Generator

–

+

frequency ∝ R1, R2, C
amplitude ∝ R

, R

A

B

R

Z

IN

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R

R

2

R

}

A

R

}

B

R

1

1

–

+

1

R

3

+ R3) >> R

C

2

21

FN8172.4

August 29, 2006

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

X9268

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.5985 0.6141 15.20 15.60 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC ­H 0.394 0.419 10.00 10.65 ­h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N24 247

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 4/06

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

22

FN8172.4

August 29, 2006