intersil X9261 DATA SHEET

®

www.BDTIC.com/Intersil

X9261

Single Supply/Low Power/256-Tap/SPI Bus

Data Sheet October 12, 2006

Dual Digitally-Controlled (XDCP™)
Potentiometers

FEATURES

• Dual–Two Separate Potentiometers

• 256 Resistor Taps/pot–0.4% Resolution

• SPI Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer Single Supply
Device

• Wiper Resistance, 100Ω typical @ V

• 4 Nonvolatile Data Registers for Each
Potentiometer

• Nonvolatile Storage of Multiple Wiper Positions

• Power-on Recall Loads Saved Wiper Position on
Power-up.

• Standby Current < 5µA Max

•50kΩ, 100kΩ Versions of End to End Resistance

• 100 yr. Data Retention

• Endurance: 100,000 Data Changes per Bit per
Register

• 24 Ld SOIC, 24 Ld TSSOP

• Low Power CMOS

• Power Supply V

= 5V ±10%

CC

• Pb-Free Plus Anneal Available (RoHS Compliant)

CC

= 5V

FN8171.4

DESCRIPTION

The X9261 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and
four non-volatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the
contents of the default Data Register (DR0) to the
WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

Address

Data

SPI
Bus

Interface

Status

V

CC

Bus

Interface

and Control

V

SS

Write
Read

Transfer

Inc/Dec

Control

Power-on Recall

Wiper Counter

Register (WCR)

Data Registers

(DR0-DR3)

R

H0

W0

R

L0

R

R

H1

R

R

W1

50kΩ or 100kΩ versions

L1

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Ordering Information

www.BDTIC.com/Intersil

X9261

PART

PART NUMBER

X9261US24 X9261US 5 ±10% 50 0 to 70 24 Ld SOIC (300 mil) M24.3
X9261US24Z (Note) X9261US Z 0 to 70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9261UV24 X9261UV 0 to 70 24 Ld TSSOP (4.4mm) MDP0044
X9261UV24Z (Note) X9261UV Z 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING

V

CC

LIMITS

(V) R

(kΩ) TEMP RANGE (°C) PACKAGE

TOTAL

PKG.

DWG. #

DETAILED FUNCTIONAL DIAGRAM

R

R

R

H0

L0

W0

V

CC

Power-on

HOLD

CS

SCK

SO

A0
A1

WP

Recall

R0R

1

Wiper

Counter

INTERFACE

AND

SI

CONTROL

CIRCUITRY

8

Data

R2R

Power-on
Recall

R0R

R2R

3

1

3

Register

(WCR)

Wiper
Counter
Register

(WCR)

Pot 0

Ω

50k

256-taps

Resistor

Array
Pot 1

and 100k

Ω

V

SS

CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF
circuits

• Provide a control variable (I, V, or R) in feedback
circuits

• Trim out the offset voltage error in a voltage ampli­fier circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and
Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

2

R

R

R

H1

L1

W1

FN8171.4

October 12, 2006

X9261

www.BDTIC.com/Intersil

SYSTEM LEVEL APPLICATIONS

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems

• Control the gain in audio and home entertainment
systems

• Provide the variable DC bias for tuners in RF wire­less systems

• Set the operating points in temperature control
systems

• Control the operating point for sensors in industrial
systems

• Trim offset and gain errors in artificial intelligent
systems

PIN CONFIGURATION

SOIC/TSSOP

HOLD

SCK

NC

NC

NC

NC

V

SS

R

W1

R

H1

R

L1

A1

SI

V

R

R

SO

A0

NC

NC

NC

NC

CC

R

H0

W0

CS

WP

1

2

3

4

5

6

X9261

7

L0

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

PIN ASSIGNMENTS

Pin

(SOIC/

TSSOP) Symbol Function

1 SO Serial Data Output for SPI bus
2 A0 Device Address for SPI bus.
3 NC No Connect.
4 NC No Connect.
5 NC No Connect.
6 NC No Connect.
7V
8R

9R
10 R
11 CS
12 WP
13 SI Serial Data Input for SPI bus
14 A1 Device Address for SPI bus.
15 R
16 R
17 R
18 V
19 NC No Connect
20 NC No Connect
21 NC No Connect
22 NC No Connect
23 SCK Serial Clock for SPI bus
24 HOLD

System Supply Voltage

CC

Low Terminal for Potentiometer 0.

L0

High Terminal for Potentiometer 0.

H0

Wiper Terminal for Potentiometer 0.

W0

Device Address for SPI bus.
Hardware Write Protect

Low Terminal for Potentiometer 1.

L1

High Terminal for Potentiometer 1.

H1

Wiper Terminal for Potentiometer 1.

W1

System Ground

SS

Device select. Pause the SPI serial bus.

PIN DESCRIPTIONS

Bus Interface Pins

S

ERIAL OUTPUT (SO)

SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.

ERIAL INPUT

S

SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.

ERIAL CLOCK (SCK)

S

The SCK input is used to clock data into and out of the
X9261.

3

FN8171.4

October 12, 2006

X9261

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HOLD (HOLD)

HOLD

is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD

may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD

must
be brought LOW while SCK is LOW. To resume
communication, HOLD

is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.

EVICE ADDRESS (A1 - A0)

D

The address inputs are used to set the 4-bit slave
address. A match in the slave address serial data
stream must be made with the address input in order
to initiate communication with the X9261.

HIP SELECT (CS)

C

When CS

is HIGH, the X9261 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS

LOW enables the X9261, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS

is

required prior to the start of any operation.

Potentiometer Pins

, RL

R

H

The R

and RL pins are equivalent to the terminal

H

connections on a mechanical potentiometer. Since
there are 2 potentiometers, there are 2 sets of R

such that RH0 and RL0 are the terminals of POT 0

R

L

H

and

and so on.

R

W

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 2
potentiometers, there are 2 sets of R

such that R

W

W0

is the terminals of POT 0 and so on.

Supply Pins

YSTEM SUPPLY VOLTAGE (V

S

ROUND (V

G

The V

CC

)

SS

pin is the system supply voltage. The V

) AND SUPPLY

CC

SS

pin is the system ground.

Other Pins

O CONNECT

N

No connect pins should be left floating. This pins are
used for Intersil manufacturing and testing purposes.

ARDWARE WRITE PROTECT INPUT (WP)

H

The WP

pin when LOW prevents nonvolatile writes to

the Data Registers.

PRINCIPLES OF OPERATION

Serial Interface

The X9261 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS
LOW and the HOLD

and WP pins must be HIGH

must be

during the entire operation.

The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.

Array Description

The X9261 is comprised of a resistor array (See
Figure 1). The array contains the equivalent of 255
discrete resistive segments that are connected in
series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer

and RL inputs).

(R

H

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper

) output. Within each individual array only one

(R

W

switch may be turned on at a time.

These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).

Power-up and Down Requirements.

There are no restrictions on the power-up or power­down conditions of V
the potentiometer pins provided that V
more positive than or equal to V

, VH, VL, VW. The VCC ramp rate specification is

V

CC

and the voltages applied to

CC

, VL, and VW, i.e.,

H

is always

CC

always in effect.

4

FN8171.4

October 12, 2006

Figure 1. Detailed Potentiometer Block Diagram

www.BDTIC.com/Intersil

One of Two Potentiometers

X9261

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

IF WCR = 00[H] THEN RW = R
IF WCR = FF[H] THEN RW = R

REGISTER 0

(DR0)

REGISTER 2 REGISTER 3

(DR2)

L

H

REGISTER 1

(DR1)

8 8

(DR3)

MODIFIED SCK

DEVICE DESCRIPTION

Wiper Counter Register (WCR)

The X9261 contains two Wiper Counter Registers, one
for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (See Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9261 is powered­down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR.

UP/DN

SERIAL
BUS
INPUT

PARALLEL
BUS
INPUT

WIPER
COUNTER
REGISTER

(WCR)

INC/DEC

LOGIC

UP/DN

CLK

C
O
U
N
T
E
R

D
E
C
O
D
E

R

H

R

L

R

W

Data Registers (DR)

Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.

Bits [7:0] are used to store one of the 256 wiper
positions or data (0~255).

Status Register (SR)

This 1-bit Status Register is used to store the system
status.

WIP: Write In Progress status bit, read only.

– When WIP=1, indicates that high-voltage write cycle

is in progress.

– When WIP=0, indicates that no high-voltage write

cycle is in progress.

5

FN8171.4

October 12, 2006

X9261

www.BDTIC.com/Intersil

Table 1. Wiper Counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).

WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0

VVVVVVVV

(MSB) (LSB)

Table 2. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

NV NV NV NV NV NV NV NV

MSB LSB

DEVICE DESCRIPTION

input state; a successful compare of both address bits
is required for the X9261 to successfully continue the

Instructions

command sequence. Only the device which slave
address matches the incoming device address sent

DENTIFICATION BYTE ( ID AND A )

I

The first byte sent to the X9261 from the host,
following a CS

going HIGH to LOW, is called the
Identification Byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bits is the device id for the X9261; this is fixed as
0101[B] (refer to Table 3).

The AD[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A3 - A0 input pins. The slave address
is externally specified by the user. The X9261
compares the serial data stream with the address

by the master executes the instruction. The A3-A0
inputs can be actively driven by CMOS input signals
or tied to V

NSTRUCTION BYTE ( I[3:0] )

I

or VSS.

CC

The next byte sent to the X9261 contains the instruction
and register pointer information. The three most
significant bits are used provide the instruction opcode
(I[3:0]). The RB and RA bits point to one of the four
Data Registers of each associated XDCP. The least
significant bit points to one of two Wiper Counter
Registers or Pots.The format is shown below in Table 4.

Table 3. Identification Byte Format

Device Type

Identifier Slave Address

ID3 ID2 ID1 ID0 A3 A2 A1 A0

0101

(MSB) (LSB)

Table 4. Instruction Byte Format

Data

Instruction

Opcode

I3 I2 I1 I0 RB RA 0 P0

(MSB) (LSB)

6

Register

Selection

Pot Selection

(WCR Selection)

FN8171.4

October 12, 2006