intersil X9259 DATA SHEET

www.BDTIC.com/Intersil

X9259

Single Supply/Low Power/256-Tap/2-Wire bus

Data Sheet April 13, 2007

Quad Digitally-Controlled (XDCP™) Potentiometers

The X9259 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The content of the WCR controls the position of the wiper. At power-up, the device recalls the content of the default Data Registers of each DCP (DR00, DR10, DR20, and DR30) to the corresponding WCR.

The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

FN8169.5

Features

• Four Separate Potentiometers in One Package

• 256 Resistor Taps–0.4% Resolution

• 2-Wire Serial Interface for Write, Read, and Transfer Operations of the Potentiometer

• Wiper Resistance: 100Ω typical @ V

• 4 Non-volatile Data Registers for Each Potentiometer

• Non-volatile Storage of Multiple Wiper Positions

• Standby Current <5µA Max

: 2.7V to 5.5V Operation

•V

•50kΩ, 100kΩ versions of Total Resistance

• Endurance: 100,000 Data Changes per Bit per Register

• 100 year Data Retention

• Single Supply Version of X9258

• 24 Ld SOIC, 24 Ld TSSOP

• Low Power CMOS

• Pb-Free Plus Anneal Available (RoHS Compliant)

= 5V

Functional Diagram

SDA

SCL

2-Wire

Interface

POWER UP,

INTERFACE

CONTROL

STATUS

AND

WCR0 DR00

DR01 DR02 DR03

DCP0

DCP1

WCR2 DR20

DR21 DR22 DR23

WCR1 DR10

DR11 DR12 DR13

DCP2

WCR3 DR30

DR31 DR32 DR33

DCP3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9259

www.BDTIC.com/Intersil

Ordering Information

TEMPERATURE

PART

NUMBER PART MARKING

X9259TS24 X9259TS 5 ±10% 100 0 to +70 24 Ld SOIC M24.3 X9259TS24Z (Note) X9259TS Z 0 to +70 24 Ld SOIC (Pb-free) M24.3 X9259TS24I X9259TS I -40 to +85 24 Ld SOIC M24.3 X9259TS24IZ (Note) X9259TS ZI -40 to +85 24 Ld SOIC (Pb-free) M24.3 X9259TV24I X9259TV I -40 to +85 24 Ld TSSOP MDP0044 X9259TV24IZ (Note) X9259TV ZI -40 to +85 24 Ld TSSOP (Pb-free) MDP0044 X9259US24* X9259US 50 0 to +70 24 Ld SOIC M24.3 X9259US24Z* (Note) X9259US Z 0 to +70 24 Ld SOIC (Pb-free) M24.3 X9259US24I X9259US I -40 to +85 24 Ld SOIC M24.3 X9259US24IZ (Note) X9259US ZI -40 to +85 24 Ld SOIC (Pb-free) M24.3 X9259UV24I* X9259UV I -40 to +85 24 Ld TSSOP MDP0044 X9259UV24IZ* (Note) X9259UV Z I -40 to +85 24 Ld TSSOP (Pb-free) MDP0044 X9259TS24-2.7* X9259TS F 2.7 to 5.5 100 0 to +70 24 Ld SOIC M24.3 X9259TS24Z-2.7* (Note) X9259TS ZF 0 to +70 24 Ld SOIC (Pb-free) M24.3 X9259TS24I-2.7 X9259TS G -40 to +85 24 Ld SOIC M24.3 X9259TS24IZ-2.7 (Note) X9259TS ZG -40 to +85 24 Ld SOIC (Pb-free) M24.3 X9259TV24-2.7 X9259TV F 0 to +70 24 Ld TSSOP MDP0044 X9259TV24Z-2.7 (Note) X9259TV ZF 0 to +70 24 Ld TSSOP (Pb-free) MDP0044 X9259US24-2.7 X9259US F 50 0 to +70 24 Ld SOIC M24.3 X9259US24Z-2.7 (Note) X9259US ZF 0 to +70 24 Ld SOIC (Pb-free) M24.3 X9259US24I-2.7 X9259US G -40 to +85 24 Ld SOIC M24.3 X9259US24IZ-2.7 (Note) X9259US ZG -40 to +85 24 Ld SOIC (Pb-free) M24.3 X9259UV24-2.7* X9259UV F 0 to +70 24 Ld TSSOP MDP0044 X9259UV24Z-2.7 (Note) X9259UV ZF 0 to +70 24 Ld TSSOP (Pb-free) MDP0044 X9259UV24I-2.7* X9259UV G -40 to +85 24 Ld TSSOP MDP0044 X9259UV24IZ-2.7* (Note) X9259UV ZG -40 to +85 24 Ld TSSOP (Pb-free) MDP0044

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

*Add "T1" suffix for tape and reel.

LIMITS

(V)

TOTAL

(kΩ)

RANGE

(°C) PACKAGE PKG. DWG. #

FN8169.5

April 13, 2007

X9259

www.BDTIC.com/Intersil

Circuit Level Applications

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF circuits

• Provide a control variable (I, V, or R) in feedback circuits

System Level Applications

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in communication systems

• Set and regulate the DC biasing point in an RF power amplifier in wireless systems

• Control the gain in audio and home entertainment systems

• Provide the variable DC bias for tuners in RF wireless systems

• Set the operating points in temperature control systems

• Control the operating point for sensors in industrial systems

• Trim offset and gain errors in artificial intelligent systems

Pin Configuration

SOIC/TSSOP

DNC

R R

H3 L3

L0 H0

1 2 3 4 5 6

X9259

7 8

9 10 11

24 23 22 21 20 19

18 17

16 15

14 13

A3 SCL

NC V

A1 SDA

Pin Assignments

(SOIC/

TSSOP) SYMBOL FUNCTION

2 A0 Device Address for 2-Wire bus. (See Note 1) 3R 4R 5R 6 NC1 Must be left unconnected 7V 8R

9R 10 R 11 A2 Device Address for 2-Wire bus. (See Note 1) 12 WP 13 SDA Serial Data Input/Output for 2-Wire bus. 14 A1 Device Address for 2-Wire bus. (See Note 1) 15 R 16 R 17 R 18 V 20 R 21 R 22 R 23 SCL Serial Clock for 2-Wire bus. 24 A3 Device Address for 2-Wire bus. (See Note 1)

6, 19 NC No Connect

1 DNC Do Not Connect

Note 1: A0 through A3 Device address pins must be tied to a logic level.

Wiper Terminal of DCP3

High Terminal of DCP3

Low Terminal of DCP3

System Supply Voltage

Low Terminal of DCP0

High Terminal of DCP0

Wiper Terminal of DCP0

Hardware Write Protect – Active Low

Low Terminal of DCP1

High Terminal of DCP1

Wiper Terminal of DCP1

System Ground

Wiper Terminal of DCP2

High Terminal of DCP2

Low Terminal of DCP2

FN8169.5

April 13, 2007

X9259

www.BDTIC.com/Intersil

Pin Descriptions

Bus Interface Pins

SERIAL DATA INPUT/OUTPUT (SDA)

The SDA is a bidirectional serial data input/output pin for a 2Wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from a 2-Wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL.

It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor.

SERIAL CLOCK (SCL)

This input is used by 2-Wire master to supply 2-Wire serial clock to the X9259.

DEVICE ADDRESS (A3 THROUGH A0)

The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9259. A maximum of 16 devices may occupy the 2-Wire serial bus. Device pins A3 through A0 must be tied to a logic level which specifies the external address of the device, see Figures 3, 4, and 5.

Potentiometer Pins

RH, RL

The R

and RL pins are equivalent to the terminal

connections on a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of R R

and RL0 are the terminals of DCP0 and so on.

and RL such that

The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of R

such that RW0 is the terminal of

DCP0 and so on.

Bias Supply Pins

SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (V

The V

)

pin is the system supply voltage. The VSS pin is

the system ground.

Other Pins

NO CONNECT

No connect pins should be left open. This pins are used for Intersil manufacturing and testing purposes.

HARDWARE WRITE PROTECT INPUT (WP)

The WP Data Registers.

pin when LOW prevents non-volatile writes to the

One of Four Potentiometers

#: 0, 1, 2, or 3

SERIAL DATA PATH FROM INTERFACE

CIRCUITRY

IF WCR = 00[H] then RW is closest to R IF WCR = FF[H] then RW is closest to R

SERIAL BUS INPUT

DR#0

8 8

DR#2

FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM

DR#1

DR#3

UP/DN

MODIFIED SCK

PARALLEL BUS INPUT

WIPER COUNTER REGISTER

(WCR#)

INC/DEC

LOGIC

UP/DN

CLK

COUNTER

- - -

DECODE

DCP

CORE

FN8169.5

April 13, 2007

X9259

www.BDTIC.com/Intersil

Principles of Operation

The X9259 is an integrated circuit incorporating four DCPs and their associated registers and counters, and the serial interface providing direct communication between a host and the potentiometers.

DCP Description

Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (R intermediate node, equivalent to the wiper terminal of a mechanical potentiometer.

The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Counter Register (WCR).

Power Up and Down Recommendations

There are no restrictions on the power-up or power-down conditions of V potentiometer pins provided that V positive than or equal to V V

. The VCC ramp rate specification is always in effect.

Wiper Counter Register (WCR)

The X9259 contains four Wiper Counter Registers, one for each potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 wiper positions along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be

and RL pins). The RW pin is an

and the voltages applied to the

, VL, and VW, i.e., VCC ≥ VH, VL,

is always more

written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decremen t instruction (see Inst ruction section for more details). Finally, it is loaded with the contents of its data register zero (DR#0) upon power-up. (See Figure 1)

The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9259 is powered-down. Although the register is automatically loaded with the value in DR#0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR#0 value into the WCR# (See Design Considerations Section).

Data Registers (DR)

Each of the four DCPs has four 8-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four data registers and the associated Wiper Counter Register. All operations changing data in one of the data registers is a non-volatile operation and takes a maximum of 10ms.

If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data.

Bit [7:0] are used to store one of the 256 wiper positions (0 ~ 255).

TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile).

WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0

(MSB) (LSB)

TABLE 2. DATA REGISTER, DR (8-BIT), BIT [7:0]: Used to store wiper positions or data (Non-volatile).

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(MSB) (LSB)

FN8169.5

April 13, 2007

X9259

www.BDTIC.com/Intersil

Serial Interface

The X9259 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provide the clock for both transmit and receive operations. Therefore, the X9259 operates as a slave device in all applications.

All 2-wire interface operations must begin with a START, followed by an Identification Byte, that selects the X9259. All communication over the 2-wire interface is conducted by sending the MSB of each byte of data first.

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions. See Figure 2. On power up of the X9259 the SDA pin is in the input mode.

START Condition

All commands to the X9259 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9259 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met. See Figure 2.

Acknowledge

An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data. See Figure 3.

The X9259 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Instruction Byte. The X9259 also responds with an ACK after receiving a Data Byte after a Write Instruction.

A valid Identification Byte contains the Device Type Identifier 0101, as the four MSBs, and the Device Address bits matching the logic states of pins A3, A2, A1, and A0, as the four LSBs. See Figure 4.

In the Read mode, the device transmits eight bits of data, releases the SDA line, and then monitors the line for an ACK. The device continues transmitting data if an ACK is detected. The device terminates further data transmissions if an ACK is not detected. The master must then issue a STOP condition to place the device into a known state.

During the internal non-volatile Write operation, the X9259 ignores the inputs at SDA and SCL, and does not issue an ACK after Identification bytes.

STOP Condition

All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. See Figure 2. The STOP condition is also used to place the device into the Standby Power mode after a Read sequence. A STOP condition can only be issued after the transmitting device has released the bus.

FN8169.5

April 13, 2007

SCL

www.BDTIC.com/Intersil

SDA

X9259

START DATA DATA STOP

SCL FROM

MASTER

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS

START ACK

FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER

STABLE CHANGE

Identification Byte

The first byte sent to the X9259 from the host is called the Identification Byte. The most significant four bits are a Device Type Identifier, ID[3:0] bits, which must be 0101. Refer to Table 3.

Only the device which Slave Address matches the incoming device address sent by the master executes the instruction. The A3 - A0 inputs can be actively driven by CMOS input signals or tied to V

INSTRUCTION BYTE (I)

The next byte sent to the X9259 contains the instruction and register pointer information. The four most significant bits are used provide the instruction opcode I [3:0]. The RB and RA bits point to one of the four data registers of each associated XDCP. The least two significant bits point to one of four Wiper Counter Registers or DCPs. The format is sh ow n in Table 4.

or VSS.

DATA

STABLE

81 9

Data Register Selection

DR#0 0 0 DR#1 0 1 DR#2 1 0 DR#3 1 1

#: 0, 1, 2, or 3 The least significant four bits of the Identification Byte are

the Slave Address bits, AD[3:0]. To access the X9259, these four bits must match the logic values of pins A3, A2, A1, and A0.

FN8169.5

April 13, 2007

+ 14 hidden pages