intersil X9259 DATA SHEET

®

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X9259

Single Supply/Low Power/256-Tap/2-Wire bus

Data Sheet April 13, 2007

Quad Digitally-Controlled (XDCP™)
Potentiometers

The X9259 integrates four digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
2-wire bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and four
non-volatile Data Registers that can be directly written to and
read by the user. The content of the WCR controls the
position of the wiper. At power-up, the device recalls the
content of the default Data Registers of each DCP (DR00,
DR10, DR20, and DR30) to the corresponding WCR.

The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.

FN8169.5

Features

• Four Separate Potentiometers in One Package

• 256 Resistor Taps–0.4% Resolution

• 2-Wire Serial Interface for Write, Read, and
Transfer Operations of the Potentiometer

• Wiper Resistance: 100Ω typical @ V

• 4 Non-volatile Data Registers for Each Potentiometer

• Non-volatile Storage of Multiple Wiper Positions

• Standby Current <5µA Max

: 2.7V to 5.5V Operation

•V

CC

•50kΩ, 100kΩ versions of Total Resistance

• Endurance: 100,000 Data Changes per Bit per Register

• 100 year Data Retention

• Single Supply Version of X9258

• 24 Ld SOIC, 24 Ld TSSOP

• Low Power CMOS

• Pb-Free Plus Anneal Available (RoHS Compliant)

CC

= 5V

Functional Diagram

V

CC

A3

A2

A1

A0

SDA

SCL

2-Wire

Interface

V

SS

POWER UP,

INTERFACE

CONTROL

STATUS

AND

WP

WCR0
DR00

DR01
DR02
DR03

R

DCP0

W0

R

DCP1

W1

R

H1

WCR2
DR20

DR21
DR22
DR23

R

L1

R

H0

WCR1
DR10

DR11
DR12
DR13

R

L0

R

DCP2

W2

R

H2

WCR3
DR30

DR31
DR32
DR33

R

L2

R

DCP3

W3

R

H3

R

L3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9259

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Ordering Information

TEMPERATURE

PART

NUMBER PART MARKING

X9259TS24 X9259TS 5 ±10% 100 0 to +70 24 Ld SOIC M24.3
X9259TS24Z (Note) X9259TS Z 0 to +70 24 Ld SOIC (Pb-free) M24.3
X9259TS24I X9259TS I -40 to +85 24 Ld SOIC M24.3
X9259TS24IZ (Note) X9259TS ZI -40 to +85 24 Ld SOIC (Pb-free) M24.3
X9259TV24I X9259TV I -40 to +85 24 Ld TSSOP MDP0044
X9259TV24IZ (Note) X9259TV ZI -40 to +85 24 Ld TSSOP (Pb-free) MDP0044
X9259US24* X9259US 50 0 to +70 24 Ld SOIC M24.3
X9259US24Z* (Note) X9259US Z 0 to +70 24 Ld SOIC (Pb-free) M24.3
X9259US24I X9259US I -40 to +85 24 Ld SOIC M24.3
X9259US24IZ (Note) X9259US ZI -40 to +85 24 Ld SOIC (Pb-free) M24.3
X9259UV24I* X9259UV I -40 to +85 24 Ld TSSOP MDP0044
X9259UV24IZ* (Note) X9259UV Z I -40 to +85 24 Ld TSSOP (Pb-free) MDP0044
X9259TS24-2.7* X9259TS F 2.7 to 5.5 100 0 to +70 24 Ld SOIC M24.3
X9259TS24Z-2.7* (Note) X9259TS ZF 0 to +70 24 Ld SOIC (Pb-free) M24.3
X9259TS24I-2.7 X9259TS G -40 to +85 24 Ld SOIC M24.3
X9259TS24IZ-2.7 (Note) X9259TS ZG -40 to +85 24 Ld SOIC (Pb-free) M24.3
X9259TV24-2.7 X9259TV F 0 to +70 24 Ld TSSOP MDP0044
X9259TV24Z-2.7 (Note) X9259TV ZF 0 to +70 24 Ld TSSOP (Pb-free) MDP0044
X9259US24-2.7 X9259US F 50 0 to +70 24 Ld SOIC M24.3
X9259US24Z-2.7 (Note) X9259US ZF 0 to +70 24 Ld SOIC (Pb-free) M24.3
X9259US24I-2.7 X9259US G -40 to +85 24 Ld SOIC M24.3
X9259US24IZ-2.7 (Note) X9259US ZG -40 to +85 24 Ld SOIC (Pb-free) M24.3
X9259UV24-2.7* X9259UV F 0 to +70 24 Ld TSSOP MDP0044
X9259UV24Z-2.7 (Note) X9259UV ZF 0 to +70 24 Ld TSSOP (Pb-free) MDP0044
X9259UV24I-2.7* X9259UV G -40 to +85 24 Ld TSSOP MDP0044
X9259UV24IZ-2.7* (Note) X9259UV ZG -40 to +85 24 Ld TSSOP (Pb-free) MDP0044

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

*Add "T1" suffix for tape and reel.

V

CC

LIMITS

(V)

R

TOTAL

(kΩ)

RANGE

(°C) PACKAGE PKG. DWG. #

2

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X9259

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Circuit Level Applications

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier
circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and
Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF circuits

• Provide a control variable (I, V, or R) in feedback
circuits

System Level Applications

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems

• Control the gain in audio and home entertainment systems

• Provide the variable DC bias for tuners in RF wireless
systems

• Set the operating points in temperature control
systems

• Control the operating point for sensors in industrial
systems

• Trim offset and gain errors in artificial intelligent
systems

Pin Configuration

SOIC/TSSOP

DNC

A0

R

W3

R
R

NC

V

CC

R
R

R

W0

A2

WP

H3
L3

L0
H0

1
2
3
4
5
6

X9259

7
8

9
10
11

12

24
23
22
21
20
19

18
17

16
15

14
13

A3
SCL

R

L2

R

H2

R

W2

NC
V

SS

R

W1

R

H1

R

L1

A1
SDA

Pin Assignments

PIN

(SOIC/

TSSOP) SYMBOL FUNCTION

2 A0 Device Address for 2-Wire bus. (See Note 1)
3R
4R
5R
6 NC1 Must be left unconnected
7V
8R

9R
10 R
11 A2 Device Address for 2-Wire bus. (See Note 1)
12 WP
13 SDA Serial Data Input/Output for 2-Wire bus.
14 A1 Device Address for 2-Wire bus. (See Note 1)
15 R
16 R
17 R
18 V
20 R
21 R
22 R
23 SCL Serial Clock for 2-Wire bus.
24 A3 Device Address for 2-Wire bus. (See Note 1)

6, 19 NC No Connect

1 DNC Do Not Connect

Note 1: A0 through A3 Device address pins must be tied to a logic
level.

Wiper Terminal of DCP3

W3

High Terminal of DCP3

H3

Low Terminal of DCP3

L3

System Supply Voltage

CC

Low Terminal of DCP0

L0

High Terminal of DCP0

H0

Wiper Terminal of DCP0

W0

Hardware Write Protect – Active Low

Low Terminal of DCP1

L1

High Terminal of DCP1

H1

Wiper Terminal of DCP1

W1

System Ground

SS

Wiper Terminal of DCP2

W2

High Terminal of DCP2

H2

Low Terminal of DCP2

L2

3

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X9259

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Pin Descriptions

Bus Interface Pins

SERIAL DATA INPUT/OUTPUT (SDA)

The SDA is a bidirectional serial data input/output pin for a 2­Wire slave device and is used to transfer data into and out of
the device. It receives device address, opcode, wiper
register address and data sent from a 2-Wire master at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock SCL.

It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs. An open
drain output requires the use of a pull-up resistor.

SERIAL CLOCK (SCL)

This input is used by 2-Wire master to supply 2-Wire serial
clock to the X9259.

DEVICE ADDRESS (A3 THROUGH A0)

The Address inputs are used to set the least significant 4 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the Address input in
order to initiate communication with the X9259. A maximum
of 16 devices may occupy the 2-Wire serial bus. Device pins
A3 through A0 must be tied to a logic level which specifies
the external address of the device, see Figures 3, 4, and 5.

Potentiometer Pins

RH, RL

The R

and RL pins are equivalent to the terminal

H

connections on a mechanical potentiometer. Since there are
4 potentiometers, there are 4 sets of R
R

and RL0 are the terminals of DCP0 and so on.

H0

R

W

and RL such that

H

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4 potentiometers,
there are 4 sets of R

such that RW0 is the terminal of

W

DCP0 and so on.

Bias Supply Pins

SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (V

The V

CC

)

SS

pin is the system supply voltage. The VSS pin is

the system ground.

Other Pins

NO CONNECT

No connect pins should be left open. This pins are used for
Intersil manufacturing and testing purposes.

HARDWARE WRITE PROTECT INPUT (WP)

The WP
Data Registers.

pin when LOW prevents non-volatile writes to the

One of Four Potentiometers

#: 0, 1, 2, or 3

SERIAL DATA PATH
FROM INTERFACE

CIRCUITRY

IF WCR = 00[H] then RW is closest to R
IF WCR = FF[H] then RW is closest to R

SERIAL
BUS
INPUT

DR#0

8 8

DR#2

L

H

FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM

DR#1

DR#3

UP/DN

MODIFIED SCK

PARALLEL
BUS
INPUT

WIPER
COUNTER
REGISTER

(WCR#)

INC/DEC

LOGIC

UP/DN

CLK

COUNTER

- - -

DECODE

DCP

CORE

R

H

R

W

R

L

4

FN8169.5

April 13, 2007

X9259

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Principles of Operation

The X9259 is an integrated circuit incorporating four DCPs
and their associated registers and counters, and the serial
interface providing direct communication between a host
and the potentiometers.

DCP Description

Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (R
intermediate node, equivalent to the wiper terminal of a
mechanical potentiometer.

The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Counter Register
(WCR).

Power Up and Down Recommendations

There are no restrictions on the power-up or power-down
conditions of V
potentiometer pins provided that V
positive than or equal to V
V

. The VCC ramp rate specification is always in effect.

W

Wiper Counter Register (WCR)

The X9259 contains four Wiper Counter Registers, one for
each potentiometer. The Wiper Counter Register can be
envisioned as a 8-bit parallel and serial load counter with its
outputs decoded to select one of 256 wiper positions along
its resistor array. The contents of the WCR can be altered in
four ways: it may be written directly by the host via the Write
Wiper Counter Register instruction (serial load); it may be

and RL pins). The RW pin is an

H

and the voltages applied to the

CC

, VL, and VW, i.e., VCC ≥ VH, VL,

H

is always more

CC

written indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step at a
time by the Increment/Decremen t instruction (see Inst ruction
section for more details). Finally, it is loaded with the
contents of its data register zero (DR#0) upon power-up.
(See Figure 1)

The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9259 is powered-down.
Although the register is automatically loaded with the value
in DR#0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loadings of the DR#0 value
into the WCR# (See Design Considerations Section).

Data Registers (DR)

Each of the four DCPs has four 8-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four data
registers and the associated Wiper Counter Register. All
operations changing data in one of the data registers is a
non-volatile operation and takes a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.

Bit [7:0] are used to store one of the 256 wiper positions
(0 ~ 255).

TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile).

WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0

(MSB) (LSB)

TABLE 2. DATA REGISTER, DR (8-BIT), BIT [7:0]: Used to store wiper positions or data (Non-volatile).

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(MSB) (LSB)

5

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X9259

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Serial Interface

The X9259 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provide the clock for both
transmit and receive operations. Therefore, the X9259
operates as a slave device in all applications.

All 2-wire interface operations must begin with a START,
followed by an Identification Byte, that selects the X9259. All
communication over the 2-wire interface is conducted by
sending the MSB of each byte of data first.

Clock and Data Conventions

Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions. See
Figure 2. On power up of the X9259 the SDA pin is in the
input mode.

START Condition

All commands to the X9259 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X9259 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met. See
Figure 2.

Acknowledge

An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data. See Figure 3.

The X9259 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Instruction Byte.
The X9259 also responds with an ACK after receiving a Data
Byte after a Write Instruction.

A valid Identification Byte contains the Device Type Identifier
0101, as the four MSBs, and the Device Address bits
matching the logic states of pins A3, A2, A1, and A0, as the
four LSBs. See Figure 4.

In the Read mode, the device transmits eight bits of data,
releases the SDA line, and then monitors the line for an
ACK. The device continues transmitting data if an ACK is
detected. The device terminates further data transmissions if
an ACK is not detected. The master must then issue a STOP
condition to place the device into a known state.

During the internal non-volatile Write operation, the X9259
ignores the inputs at SDA and SCL, and does not issue an
ACK after Identification bytes.

STOP Condition

All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH. See Figure 2. The STOP condition is also
used to place the device into the Standby Power mode after
a Read sequence. A STOP condition can only be issued
after the transmitting device has released the bus.

6

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SCL

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SDA

X9259

START DATA DATA STOP

SCL FROM

MASTER

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS

START ACK

FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER

STABLE CHANGE

Identification Byte

The first byte sent to the X9259 from the host is called the
Identification Byte. The most significant four bits are a
Device Type Identifier, ID[3:0] bits, which must be 0101.
Refer to Table 3.

Only the device which Slave Address matches the incoming
device address sent by the master executes the instruction.
The A3 - A0 inputs can be actively driven by CMOS input
signals or tied to V

INSTRUCTION BYTE (I)

The next byte sent to the X9259 contains the instruction and
register pointer information. The four most significant bits are
used provide the instruction opcode I [3:0]. The RB and RA
bits point to one of the four data registers of each associated
XDCP. The least two significant bits point to one of four
Wiper Counter Registers or DCPs. The format is sh ow n in
Table 4.

or VSS.

CC

DATA

STABLE

81 9

Data Register Selection

REGISTER RB RA

DR#0 0 0
DR#1 0 1
DR#2 1 0
DR#3 1 1

#: 0, 1, 2, or 3
The least significant four bits of the Identification Byte are

the Slave Address bits, AD[3:0]. To access the X9259, these
four bits must match the logic values of pins A3, A2, A1, and
A0.

7

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X9259

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TABLE 3. IDENTIFICATION BYTE FORMAT

Device Type

Identifier

ID3 ID2 ID1 ID0 A3 A2 A1 A0

0 1 0 1 Logic value of pins A3, A2, A1, and A0

(MSB) (LSB)

TABLE 4. INSTRUCTION BYTE FORMAT

Slave Address

Instruction

Opcode

Register

Selection

DCP Selection

(WCR Selection)

I3 I2 I1 I0 RB RA P1 P0

(MSB) (LSB)

TABLE 5. INSTRUCTION SET

INSTRUCTION SET

INSTRUCTION

Read Wiper Counter
Register

Write Wiper Counter Register 1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Counter

Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed to by

Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register

XFR Data Register to Wiper
Counter Register

XFR Wiper Counter Register to
Data Register

Global XFR Data Registers to Wiper
Counter Registers

Global XFR Wiper Counter
Registers to Data Register

Increment/Decrement Wiper
Counter Register

1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Counter Register

pointed to by P1 - P0

Register pointed to by P1 - P0

P1 - P0 and RB - RA

pointed to by P1 - P0 and RB - RA

1 1 0 1 1/0 1/0 1/0 1/0 Transfer the contents o f t he Da ta Register pointed to

by P1 - P0 and RB - RA to its
associated Wiper C o u n te r R e g i s ter

1 1 1 0 1/0 1/0 1/0 1/0 Transfer the contents of the Wiper Counter Register

pointed to by P1 - P0 to the Data Register pointed to
by RB - RA

0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers pointed to

by RB - RA of all four pots to their respective Wiper
Counter Registers

1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter

Registers to their respective data Registers pointed to
by RB - RA of all four DCPs

0 0 1 0 0 0 1/0 1/0 Enable Increment/decrement of the Control Latch

pointed to by P1 - P0

OPERATIONI3 I2 I1 I0 RB RA P1 P0

Note: 1/0 = data is one or zero

8

FN8169.5

April 13, 2007

X9259

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Instructions

Four of the nine instructions are three bytes in length. These
instructions are:

• Read Wiper Counter Register – read the current wiper
position of the selected potentiometer,

• Write Wiper Counter Register – change current wiper
position of the selected potentiometer,

• Read Data Register – read the contents of the selected
Data Register;

• Write Data Register – write a new value to the selected
Data Register.

The basic sequence of the three byte instructions is
illustrated in Figure 5. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper to
this action is delayed by t
(current wiper position), to a Data Register is a write to non­volatile memory and takes a minimum of t
The transfer can occur between one of the four
potentiometer’s WCR, and one of its associated registers,
DRs; or it may occur globally, where the transfer occurs
between all potentiometers and one associated register.

Four instructions require a two-byte sequence to complete.
These instructions transfer data between the host and the
X9259; either between the host and one of the data registers

. A transfer from the WCR

WRL

to complete.

WR

or directly between the host and the Wiper Counter Register.
These instructions are:

• XFR Data Register to Wiper Counter Register – This
transfers the contents of one specified Data Register to
the associated Wiper Counter Register.

• XFR Wiper Counter Register to Data Register – This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.

• Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.

• Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.

Increment/Decrement Command

The final command is Increment/Decrement (Figure 6 and

7). The Increment/Decrement command is different from the

other commands. Once the command is issued and the
X9259 has responded with an Acknowledge, the master can
clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (t
selected wiper moves one wiper position towards the R
terminal. Similarly, for each SCL clock pulse while SDA is
LOW, the selected wiper moves one resistor wiper position
towards the R

terminal.

L

See Instruction format for more details.

) while SDA is HIGH, the

HIGH

H

SCL

SDA

SCL

SDA

0101

S

ID3 ID2

T
A

Device ID

R
T

ID3 ID2 ID1 ID0

S
T
A
R
T

ID0

ID1

0101

A1

A2 A0

A3

Device ID

A3

A2 A1 A0

External
Address

FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE 2-WIRE INTERFACE

External
Address

FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE

I3

A
C
K

A
C
K

I1

I2

Instruction
Opcode

I2 I1

I3

Instruction
Opcode

I0 RB RA

Register
Address

I0

RB RA P1

Register
Address

P1 P0

Pot/WCR

Address

DCP/WCR

Address

A

D7 D6 D5 D4 D3 D2 D1 D0
C
K

Data for WCR[7:0] or DR[7:0]

P0

S

A

T

C

O

K

P

A

S

C

T

K

O
P

9

FN8169.5

April 13, 2007

SCL

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X9259

SDA

INC/DEC

Issued

R

0101

ID3 ID2 ID1 ID0

S
T
A
R
T

CMD

SCL

SDA

W

Device ID

A3

A2 A1 A0

External
Address

FIGURE 6. INCREMENT/DECREMENT INSTRUCTION SEQUENCE 2-WIRE INTERFACE

I3 I2

A
C
K

Voltage Out

I1

Instruction
Opcode

I0

RB

RA P1 P0

Register
Address

Pot/WCR

Address

A

I
N
C
1

t

WRID

I
N
C

2

C
K

D

I

E

N

C

C

1

n

S

D

T

E

O

C

P

n

FIGURE 7. INCREMENT/DECREMENT TIMING SPEC

10

FN8169.5

April 13, 2007

Instruction Format

www.BDTIC.com/Intersil

Read Wiper Counter Register (WCR)

X9259

Device Type

S

Identifier

T
A
R

0101A3A2A1A0 100100P1 P0

T

Device

Addresses

Instruction
S
A
C
K

Opcode

DR/WCR

Addresses

Write Wiper Counter Register (WCR)

Device Type

S

Identifier

T
A
R

0101A3A2A1A0 101000P1 P0

T

Device

Addresses

Instruction
S
A
C
K

Opcode

DR/WCR

Addresses

Read Data Register (DR)

Device Type

S

Identifier

T
A
R

0101A3A2A1A0 1011RBRAP1 P0

T

Device

Addresses

Instruction
S
A
C
K

Opcode

DR/WCR

Addresses

Write Data Register (DR)

Wiper Position

S

(Sent by X9259 on SDA)

A

W

W

W

W

C

C

C

R

K

R

7

6

Wiper Position

S

(Sent by Master on SDA)

A

W

W

C

C

C

R

K

R

7

6

S

(Sent by X9259 on SDA)

A

W

W

C

C

C

R

K

R

7

W

C

C

C

R

R

R

5

4

3

W

W

W

C

C

C

R

R

R

5

4

3

Wiper Position

W

W

W

C

C

C

R

R

R

5

4

6

3

W
C
R

2

W
C
R

2

W
C
R

S

M

T

A

W

W

O

C

C

C

P

K

R

R

1

0

S

S

T

A

W

W

O

C

C

C

P

K

R

R

1

0

S

M

T

A

W

W

O

C

C

C

P

K

R

R

2

1

0

Device Type

S

Identifier

T
A

R

0101A3A2A1A0 1100RBRAP1 P0

T

Device

Addresses

Instruction
S
A
C
K

Opcode

DR/WCR

Addresses

S
A
C
K

Global XFR Data Register (DR) to Wiper Counter Register (WCR)

Device Type

S

Identifier

T
A
R

0 1 0 1 A3 A2 A1 A0 0 0 0 1 RB RA 0 0

T

Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the Master/Slave.

(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

Device

Addresses

S
A
C
K

Instruction

Opcode

DR/WCR

Addresses

Wiper Position

(Sent by Master on SDA)

W

W

W

W

W

W

W

C

C

C

C

R

R

7

6

S
A
C
K

C

R

R

R

5

4

3

S
T

O

P

W

C

C

R

R

2

1

S

S

T

A

O

C

C

P

K

R

0

WRITE CYCLE

HIGH-VOLTAGE

11

FN8169.5

April 13, 2007

X9259

www.BDTIC.com/Intersil

Global XFR Wiper Counter Register (WCR) to Data Register (DR)

Device Type

S

Identifier

T
A

R

0 1 0 1A3A2A1A0 1000RBRA0 0

T

Device

Addresses

Instruction

S
A
C
K

Opcode

DR/WCR

Addresses

S

S

T

A
C
K

HIGH-VOLTAGE

O

WRITE CYCLE

P

Transfer Wiper Counter Register (WCR) to Data Register (DR)

S

Device Type

T

Identifier

A

R

0 1 0 1A3A2A1A0 1110RBRAP1 P0

T

Device

Addresses

Instruction

S
A
C
K

Opcode

DR/WCR

Addresses

S

S

A

T

HIGH-VOLTAGE

C

O

WRITE CYCLE

K

P

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Device Type

S

Identifier

T
A

R

0 1 0 1 A3 A2 A1 A0 1 1 0 1 RB RA P1 P0

T

Device

Addresses

Instruction

S
A
C
K

Opcode

DR/WCR

Addresses

S

S

T

A

O

C

P

K

Increment/Decrement Wiper Counter Register (WCR)

Device Type

S

Identifier

T
A
R

0101A3A2A1A0 001000 P1 P0 I/DI/D. . . .I/DI/D

T

Device

Addresses

Instruction

S

A
C
K

Opcode

DR/WCR

Addresses

S
A
C
K

Increment/Decrement

(Sent by Master on SDA)

S
T
O
P

Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the Master/Slave.

(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

12

FN8169.5

April 13, 2007

X9259

www.BDTIC.com/Intersil

Absolute Maximum Ratings Recommended Operating Conditions

Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on SCL, SDA, any address input, V

with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

ΔV = | (V

Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . .300°C

(10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to ab solute maxim um
rating conditions for extended periods may a ffe ct d evice reli abi lit y.

) |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V

H–VL

CC

Analog Specifications Over recommended industrial (2.7V) operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS

R

TOTAL

R

TOTAL

R

W

End to End Resistance T version 100 kΩ
End to End Resistance U version 50 kΩ
End to End Resistance Tolerance ±20 %

Wiper Resistance

V(VCC)

I

= @ VCC = 3V

W

R

TOTAL

Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Temperature (Industrial). . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage (V

X9259. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%

X9259-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

Wiper current ...........................................................................±3mA

Power rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mW

) (Note 4) Limits

CC

LIMITS

MIN TYP MAX UNITS

300 Ω

V(VCC)

= @ VCC = 5V

I

W

R

TOTAL

V

TERM

C

H/CL/CW

NOTES:

1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.

2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.

3. MI = RTOT / 255 or (R

4. During power up V

5. n = 0, 1, 2, …,255; m =0, 1, 2, …, 254.

Voltage on any RH or RL Pin V
Noise (Note 6) Ref: 1V -120 dB/√Hz
Resolution
Absolute Linearity

Relative Linearity

Temperature Coefficient of R
(Note 6)

Ratiometric Temp. Coefficient (Note 6) ±20 ppm/°C
Potentiometer Capacitances (Note 6) See Macro model 10/10/25 pF

(Note 1) R

(Note 2) R

– RL) / 255, single pot

H

> VH, VL, and VW.

CC

TOTAL

= 0V V

SS

w(n)(actual)

- [R

w(n + 1)

- R

w(n)(expected)

w(n) + MI

(Note 5) -1 +1 MI (Note 3)

] (Note 5) -0.6 +0.6 MI (Note 3)

SS

0.4 %

±300 ppm/°C

220 Ω

V

CC

V

13

FN8169.5

April 13, 2007

X9259

www.BDTIC.com/Intersil

DC Electrical Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

CC2

VCC supply current
(active)

VCC supply current
(non-volatile write)

f

= 400kHz; VCC = +6V;

SCL

SDA = Open; (for 2-Wire, Active, Read and
Volatile Write States only)

f

= 400kHz; VCC = +6V;

SCL

SDA = Open; (for 2-Wire, Active,
Non-volatile Write State only)

MIN TYP MAX UNITS

LIMITS

3mA

5mA

I

SB

I

I

LO

V
V

V

V

OH

V

OH

VCC current (standby) V

Input leakage current VIN = VSS to V

LI

Output leakage current V
Input HIGH voltage VCC x 0.7 V

IH

Input LOW voltage VCC x 0.3 V

IL

Output LOW voltage IOL = 3mA 0.4 V

OL

Output HIGH voltage IOH = -1mA, VCC ≥ +3V VCC - 0.8 V
Output HIGH voltage IOH = -0.4mA, VCC ≤ +3V VCC - 0.4 V

= +6V; VIN = VSS or VCC; SDA = VCC;

CC

(for 2-Wire, Standby State only)

CC

= VSS to V

OUT

CC

5 μA

10 μA
10 μA

Endurance and Data Retention

PARAMETER MIN UNITS

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 years

Capacitance

SYMBOL TEST MAX UNITS TEST CONDITIONS

C
CIN (Note 6) Input capacitance (SCL, WP, A2, A1 and A0) 6 pF VIN = 0V

(Note 6) Input / Output capacitance (SDA) 8 pF V

IN/OUT

OUT

= 0V

Power-up Timing

SYMBOL PARAMETER MIN MAX UNITS

(Note 6) VCC Power-up rate 0.2 V/ms

tr VCC

(Note 7) Power-up to initiation of read operation 1 ms

tPUR

(Note 7) Power-up to initiation of write operation 50 ms

tPUW

A.C. Test Conditions

Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level V

NOTES:

6. This parameter is not 100% tested

and t

7. t

PUR

parameters are periodically sampled and not 100% tested.

are the delays required from the time the power supply (VCC) is stable until the specific instruction can be issued. These

PUW

CC

x 0.5

14

FN8169.5

April 13, 2007

Equivalent A.C. Load Circuit

www.BDTIC.com/Intersil

X9259

SDA pin

5V

1533Ω

100pF

R

H

SPICE Macromodel

R

C

L

10pF

TOTAL

R

W

C

W

25pF

C

10pF

R

L

L

AC Timing

SYMBOL PARAMETER MIN MAX UNITS

f

SCL

t

CYC

t

HIGH

t

LOW

t

SU:STA

t

HD:STA

t

SU:STO

t

SU:DAT

t

HD:DAT

t

R

t

F

t

AA

t

DH

T

I

t

BUF

t

SU:WPA

t

HD:WPA

Clock Frequency 400 kHz
Clock Cycle Time 2500 ns
Clock High Time 600 ns
Clock Low Time 1300 ns
Start Setup Time 600 ns
Start Hold Time 600 ns
Stop Setup Time 600 ns
SDA Data Input Setup Time 100 ns
SDA Data Input Hold Time 30 ns
SCL and SDA Rise Time 300 ns
SCL and SDA Fall Time 300 ns
SCL Low to SDA Data Output Valid Time 0.9 μs
SDA Data Output Hold Time 0 ns
Noise Suppression Time Constant at SCL and SDA inputs 50 ns
Bus Free Time (Prior to Any Transmission) 1200 ns
A0, A1 Setup Time 0 ns
A0, A1 Hold Time 0 ns

High-Voltage Write Cycle Timing

SYMBOL PARAMETER TYP MAX UNITS

t

WR

High-voltage write cycle time (store instructions) 5 10 ms

XDCP Timing

SYMBOL PARAMETER MIN MAX UNITS

t

WRPO

t

WRL

Wiper response time after the third (last) power supply is stable 5 10 μs
Wiper response time after instruction issued (all load instructions) 5 10 μs

15

FN8169.5

April 13, 2007

X9259

www.BDTIC.com/Intersil

Symbol Table

WAVEFORM INPUTS OUTPUTS

Timing Diagrams

Start and Stop Timing

SCL

t

SU:STA

SDA

.

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

N/A Center Line

is High
Impedance

(START) (STOP)

t

F

t

SU:STO

t

F

t

HD:STA

t

R

t

R

Input Timing

SCL

SDA

Output Timing

SCL

SDA

t

CYC

t

SU:DAT

t

HIGH

t

LOW

t

HD:DAT

t

AA

t

DH

t

BUF

16

FN8169.5

April 13, 2007

XDCP Timing (for All Load Instructions)

www.BDTIC.com/Intersil

SCL

X9259

(STOP)

SDA

VWx

Write Protect and Device Address Pins Timing

(START) (STOP)

SCL

SDA

t

SU:WPA

WP

A0, A1

LSB

t

WRL

...

(Any Instruction)

...

...

t

HD:WPA

17

FN8169.5

April 13, 2007

Applications Information

www.BDTIC.com/Intersil

Basic Configurations of Electronic Potentiometers

V

R

RW

X9259

+V

R

I

Three terminal
Potentiometer;
Variable voltage divider

Application Circuits

Non inverting Amplifier Voltage Regulator

V

S

VO = (1+R2/R1)V

Offset Voltage Adjustment Comparator with Hysteresis

Two terminal Variable
Resistor;
Variable current

+

–

R

R

1

S

V

O

2

IN

317

R

1

I

adj

R

2

VO (REG) = 1.25V (1+R2/R1)+I

VO (REG)V

adj R2

–

+

R

2

TL072

V

S

V

O

}

R

VUL = {R1/(R1+R2)} VO(max)
RL

= {R1/(R1+R2)} VO(min)

L

V

S

10kΩ

R

1

100kΩ

-12V+12V

10kΩ10kΩ

18

–

+

}

R

2

1

V

O

FN8169.5

April 13, 2007

Application Circuits (continued)

www.BDTIC.com/Intersil

Attenuator Filter

R

1

V

S

R

3

R

4

VO = G V

-1/2 ≤ G ≤ +1/2

R

–

+

R1 = R2 = R3 = R4 = 10kΩ

S

Inverting Amplifier Equivalent L-R Circuit

R

R

V

S

2

1

}

}

VO = G V
G = - R2/R

–

+

S

1

X9259

C

V

S

2

V

O

R

G

O

fc = 1/(2πRC)

C

1

V

V

O

S

Z

IN

+

–

R

1

= 1 + R2/R

R

2

R

1

R

3

V

O

R

2

1

+

–

Function Generator

–

+

frequency ∝ R1, R2, C
amplitude ∝ R

19

, R

A

B

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R

R

2

R

}

A

R

}

B

R

1

+ R3) >> R

1

C

–

+

2

FN8169.5

April 13, 2007

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

X9259

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.5985 0.6141 15.20 15.60 3
E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6

N24 247

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 4/06

20

FN8169.5

April 13, 2007

X9259

www.BDTIC.com/Intersil

Thin Shrink Small Outline Package Family (TSSOP)

C

SEATING
PLANE

N LEADS

0.25 CAB

M

E

E1

B

0.10 C

N

1

TOP VIEW

e

b

SEE DETAIL “X”

(N/2)+1

SIDE VIEW

(N/2)

0.10 CABM

AD

PIN #1 I.D.

0.20 C2XB A

N/2 LEAD TIPS

0.05

MDP0044

THIN SHRINK SMALL OUTLINE PACKAGE FAMILY

MILLIMETERS

SYMBOL

A 1.20 1.20 1.20 1.20 1.20 Max

A1 0.10 0.10 0.10 0.10 0.10 ±0.05

A2 0.90 0.90 0.90 0.90 0.90 ±0.05

b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06

c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06

D 5.00 5.00 6.50 7.80 9.70 ±0.10

E 6.40 6.40 6.40 6.40 6.40 Basic

E1 4.40 4.40 4.40 4.40 4.40 ±0.10

H

e 0.65 0.65 0.65 0.65 0.65 Basic

L 0.60 0.60 0.60 0.60 0.60 ±0.15

L1 1.00 1.00 1.00 1.00 1.00 Reference

NOTES:

1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.

3. Dimensions “D” and “E1” are measured at dAtum Plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

TOLERANCE14 LD 16 LD 20 LD 24 LD 28 LD

Rev. F 2/07

c

A2

A

A1

END VIEW

DETAIL X

L1

GAUGE
PLANE

0.25

L

0° - 8°

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

21

FN8169.5

April 13, 2007