intersil X9258 DATA SHEET

®

www.BDTIC.com/Intersil

X9258

Low Noise/Low Power/2-Wire Bus/256 Taps

Data Sheet FN8168.4August 30, 2006

Quad Digital Controlled Potentiometers
(XDCP™)

FEATURES

• Four potentiometers in one package

• 256 resistor taps/pot–0.4% resolution

• 2-wire serial interface

• Wiper resistance, 40Ω typical @ V+ = 5V, V- = -5V

• Four nonvolatile data registers for each pot

• Nonvolatile storage of wiper position

• Standby current <5µA max (total package)

• Power supplies
—V
—V+ = 2.7V to 5.5V
—V- = -2.7V to -5.5V

• 100kΩ, 50kΩ total pot resistance

• High reliability
—Endurance – 100,000 data changes per bit per

—Register data retention – 100 years

• 24 Ld SOIC, 24 Ld TSSOP

• Dual supply version of X9259

• Pb-free plus anneal available (RoHS compliant)

= 2.7V to 5.5V

CC

register

DESCRIPTION

The X9258 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.

The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-wire bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and 4 nonvolatile Data Registers (DR0:DR3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array though the switches. Power
up recalls the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

BLOCK DIAGRAM

V

CC

V

SS

V+
V-

WP

SCL

SDA

A0
A1

A2
A3

Interface

and

Control

Circuitry

Data

Pot 0

R0R

1

Wiper
Counter
Register

3

1

3

(WCR)

Wiper

Counter
Register

(WCR)

Resistor

Array
Pot 1

R2R

8

R0R

R2R

VH0/R

VL0/R

VW0/R

VW1/R

V

H1/RH1

VL1/R

W0

W1

L0

L1

H0

R0R

R2R

R0R

R2R

1

3

1

3

Wiper
Counter
Register

(WCR)

Wiper

Counter

Register

(WCR)

Resistor

Array
Pot 2

Resistor

Array

Pot 3

V

H2/RH2

VL2/R

VW2/R

VW3/R

V

H3/RH3

VL3/R

L2

W2

W3

L3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Ordering Information

www.BDTIC.com/Intersil

X9258

POTENTIOMETER

PART

PART NUMBER

X9258US24* X9258US 5 ±10 50 0 to 70 24 Ld SOIC (300 mil) M24.3
X9258US24Z* (Note) X9258US Z 0 to 70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9258US24I* X9258US I -40 to 85 24 Ld SOIC (300 mil) M24.3
X9258US24IZ* (Note) X9258US ZI -40 to 85 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9258UV24 X9258UV 0 to 70 24 Ld TSSOP (4.4mm) MDP0044
X9258UV24I X9258UV I -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9258UV24IZ (Note) X9258UV ZI -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9258TS24 X9258TS 100 0 to 70 24 Ld SOIC (300 mil) M24.3
X9258TS24Z (Note) X9258TS Z 0 to 70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9258TS24I X9258TS I -40 to 85 24 Ld SOIC (300 mil) M24.3
X9258TS24IZ (Note) X9258TS ZI -40 to 85 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9258TV24I X9258TV I -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9258US24-2.7* X9258US F 2.7 to 5.5 50 0 to 70 24 Ld SOIC (300 mil) M24.3
X9258US24Z-2.7* (Note) X9258US ZF 0 to 70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9258US24I-2.7* X9258US G -40 to 85 24 Ld SOIC (300 mil) M24.3
X9258US24IZ-2.7*

(Note)
X9258UV24-2.7 X9258UV F 0 to 70 24 Ld TSSOP (4.4mm) MDP0044
X9258UV24I-2.7 X9258UV G -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9258UV24IZ-2.7 (Note) X9258UV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9258UV24Z-2.7 (Note) X9258UV ZF 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9258TS24-2.7* X9258TS F 100 0 to 70 24 Ld SOIC (300 mil) M24.3
X9258TS24Z-2.7* (Note) X9258TS ZF 0 to 70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9258TS24I-2.7* X9258TS G -40 to 85 24 Ld SOIC (300 mil) M24.3
X9258TS24IZ-2.7*

(Note)
X9258TV24-2.7 X9258TV F 0 to 70 24 Ld TSSOP (4.4mm) MDP0044
X9258TV24I-2.7 X9258TV G -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9258TV24IZ-2.7 (Note) X9258TV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9258TV24Z-2.7 (Note) X9258TV ZF 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING

X9258US ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) M24.3

X9258TS ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) M24.3

V

LIMITS

CC

(V)

ORGANIZATION

(kΩ)

TEMPERATURE

RANGE

(°C) PACKAGE

PKG.

DWG. #

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X9258

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PIN DESCRIPTIONS

Host Interface Pins

ERIAL CLOCK (SCL)

S

The SCL input is used to clock data into and out of the
X9258.

ERIAL DATA (SDA)

S

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.

EVICE ADDRESS (A

D

0

- A3)

The Address inputs are used to set the least
significant 4 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the address input in order to initiate
communication with the X9258. A maximum of 16
devices may occupy the 2-wire serial bus.

Potentiometer Pins

V

H/RH

V

L3/RL3

The V

(VH0/R

)

H/RH

- VH3/RH3), VL/RL (VL0/R

H0

L0

-

and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.

V

W/RW (VW0/RW0

- VW3/RW3)

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

Hardware Write Protect Input (WP)

The WP pin when low prevents nonvolatile writes to
the Data Registers.

Analog Supplies V+, V-

The Analog Supplies V+, V- are the supply voltages
for the DCP analog section.

PIN CONFIGURATION

SOIC/TSSOP

A3

SCL

V

L2/RL2

VH2/R

VW2/R

V–

V

SS

VW1/R

VH1/R

VL1/R

A1

SDA

H2

W2

W1

H1

L1

V

W3/RW3

VH3/R

V

L3/RL3

VL0/R

VH0/R

VW0/R

V

NC

A0

H3

V+

CC

H0

W0

A2

WP

1

2

3

4

5

6

X9258

7

L0

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

PIN NAMES

Symbol Description

SCL Serial Clock

SDA Serial Data

A0-A3 Device Address

V

H0/RH0

V

L0/RL0

V

W0/RW0

- VH3/RH3,

- VL3/R

L3

- VW3/R

Potentiometer Pins
(terminal equivalent)

Potentiometers Pins

W3

(wiper equivalent)

WP

Hardware Write Protection

V+,V- Analog Supplies

V

CC

V

SS

System Supply Voltage

System Ground

NC No Connection (Allowed)

PRINCIPLES OF OPERATION

The X9258 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the DCP potentiometers.

Serial Interface—2-Wire

The X9258 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers

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X9258

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and provide the clock for both transmit and receive
operations. Therefore, the X9258 will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods (t
SCL HIGH are reserved for indicating start and stop
conditions.

Start Condition

All commands to the X9258 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

The X9258 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9258 will respond with a final acknowledge.

Array Description

The X9258 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that
are connected in series. The physical ends of each
array are equivalent to the fixed terminals of a
mechanical potentiometer (V

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper

) output. Within each individual array only one

(V

W

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
8 bits of the WCR are decoded to select, and enable,
one of 256 switches.

). SDA state changes during

LOW

). The X9258 continuously

HIGH

and VL/RL inputs).

H/RH

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1). For the X9258 this is
fixed as 0101[B].

Figure 1. Slave Address

Device Type

Identifier

100

The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0 - A3 inputs. The X9258 compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9258 to respond with an acknowledge. The

- A3 inputs can be actively driven by CMOS input

A

0

signals or tied to V

Acknowledge Polling

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms nonvolatile write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9258
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9258 is still busy with the write operation no ACK will
be returned. If the X9258 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.

or VSS.

CC

1

A3 A2 A1 A0

Device Address

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X9258

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ACK Polling Sequence

Nonvolatile Write

Command Completed

EnterACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Yes

Further

Operation?

Yes

Issue

Instruction

Proceed

No

No

Issue STOP

Issue STOP

Proceed

Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the Wiper Counter Register
and one of the data registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
action will be delayed t

. A transfer from the Wiper

WRL

Counter Register (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

WR

between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all of the potentiometers
and one of their associated registers.

Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9258; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are: Read Wiper Counter Register (read the current
wiper position of the selected pot), Write Wiper
Counter Register (change current wiper position of the
selected pot), Read Data Register (read the contents
of the selected nonvolatile register) and Write Data
Register (write a new value to the selected data
register). The sequence of operations is shown in
Figure 4.

Instruction Structure

The next byte sent to the X9258 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the two pots and when applicable
they point to one of four associated registers. The
format is shown below in Figure 2.

Figure 2. Instruction Byte Format

Register

Select

I1I2I3 I0 R1 R0 P1 P0

Instructions

Wiper Counter

Register Select

The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the four
registers that is to be acted upon when a register
oriented instruction is issued. The last bits (P1, P0)
select which one of the four potentiometers is to be
affected by the instruction.

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Figure 3. Two-Byte Instruction Sequence

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SCL

SDA

S

0101A3A2A1A0A
T
A
R
T

X9258

I3 I2 I1 I0 R1 R0 P1 P0 A
C
K

S

C

T

K

O
P

The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9258 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine

Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the V

terminal. A detailed illustration of

L/RL

the sequence and timing for this operation are shown
in Figures 5 and 6 respectively.

tuning capability to the host. For each SCL clock pulse

) while SDA is HIGH, the selected wiper will

(t

HIGH

move one resistor segment towards the V

terminal.

H

Table 1. Instruction Set

Instruction Set

Instruction

Read Wiper Counter
Register

Write Wiper Counter
Register

0

1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Counter Register

pointed to by P

1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Counter Register

pointed to by P

OperationI3I2I1I0R1R0P1P

- P

1

0

- P

1

0

Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed

to by P

- P0 and R1 - R

1

0

Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register pointed to

- P0 and R1 - R

by P

XFR Data Register to
Wiper Counter Register

1

1 1 0 1 1/0 1/0 1/0 1/0 Transfer the contents of the Data Register pointed

to by P

- P0 and R1 - R0 to its associated Wiper

1

0

Counter Register

XFR Wiper Counter
Register to Data
Register

Global XFR Data
Registers to Wiper
Counter Registers

Global XFR Wiper
Counter Registers
to Data Register

Increment/Decrement
Wiper Counter Register

1 1 1 0 1/0 1/0 1/0 1/0 Transfer the contents of the Wiper Counter Reg-

ister pointed to by P
pointed to by R

- P0 to the Data Register

1

- R

1

0

0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers

pointed to by R

- R0 of all four pots to their re-

1

spective Wiper Counter Registers

1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter

Registers to their respective data Registers
pointed to by R

- R0 of all four pots

1

0 0 1 0 0 0 1/0 1/0 Enable Increment/decrement of the Control Latch

pointed to by P

- P

1

0

Note: (1) 1/0 = data is one or zero

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