intersil X9252 DATA SHEET

®

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X9252

Low Power + Quad 256-tap + 2-Wire Bus + Up/Down Interface

Data Sheet November 14, 2005

Quad Digitally-Controlled (XDCP™)
Potentiometer

The X9252 integrates 4 digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented
using 255 resistive elements in a series array. Between each
pair of elements are tap points connected to wiper terminals
through switches. The position of each wiper on the array is
controlled by the user through the Up/Down (U/D
bus interface. The wiper of each potentiometer has an
associated volatile Wiper Counter Register (WCR) and four
non-volatile Data Registers (DRs) that can be directly written
to and read by the user. The contents of the WCR controls
the position of the wiper on the resistor array through the
switches. At power-up, the device recalls the contents of the
default data registers DR00, DR10, DR20, DR30, to the
corresponding WCR.

Each DCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including the programming of bias voltages, the
implementation of ladder networks, and three resistor
programmable networks.

) or 2-wire

FN8167.2

Features

• Quad Solid State Potentiometer

• 256 Wiper Tap Points-0.4% Resolution

• 2-Wire Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer

• Up/Down Interface for Individual Potentiometers

• Wiper Resistance: 40Ω Typical

• Non-Volatile Storage of Wiper Positions

• Power On Recall. Loads Saved Wiper Position on Power­Up.

• Standby Current < 100µA Max

• Maximum Wiper Current: 3mA

: 2.7V to 5.5V Operation

•V

CC

•2.8kΩ,10kΩ, 50kΩ, 100kΩ Version of Total Pot Resistance

• Endurance: 100,000 Data Changes per Bit per Register

• 100 yr. Data Retention

• 24 Ld SOIC, 24 Ld TSSOP

• Pb-Free Plus Anneal Available (RoHS Compliant)

Pinout

(24 LD SOIC/TSSOP)

DS0

R

R

R
U/D

V

R

R

R

WP

A0

W3

H3
L3

CC

L0
H0

W0

A2

1
2
3
4

5
6
7

8
9
10

11
12

X9252

TOP VIEW

X9252

24

DS1

23
22
21
20

19
18

17
16

15
14
13

SCL
R

L2

R

H2

R

W2

CS
V

SS

R

W1

R

H1

R

L1

A1
SDA

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Ordering Information

www.BDTIC.com/Intersil

X9252

PART NUMBER PART MARKING R

(kΩ) TEMP RANGE (°C) PACKAGE

TOTAL

X9252YS24I-2.7 2.8 -40 to 85 24 Ld SOIC (300 mil)

X9252YS24IZ-2.7 (Note) -40 to 85 24 Ld SOIC (300 mil) (Pb-Free)

X9252YV24I-2.7 X9252YV G -40 to 85 24 Ld TSSOP (4.4mm)

X9252YV24IZ-2.7 (Note) X9252YV Z G -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free)

X9252WS24I-2.7 X9252WS G 10 -40 to 85 24 Ld SOIC (300 mil)

X9252WS24IZ-2.7 (Note) X9252WS Z G -40 to 85 24 Ld SOIC (300 mil) (Pb-Free)

X9252WV24I-2.7 X9252WV G -40 to 85 24 Ld TSSOP (4.4mm)

X9252WV24IZ-2.7 (Note) X9252WV Z G -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free)

X9252US24I-2.7 X9252US G 50 -40 to 85 24 Ld SOIC (300 mil)

X9252US24IZ-2.7 (Note) X9252US Z G -40 to 85 24 Ld SOIC (300 mil) (Pb-Free)

X9252UV24I-2.7 X9252UV G -40 to 85 24 Ld TSSOP (4.4mm)

X9252UV24IZ-2.7 (Note) X9252UV Z G -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free)

X9252TS24I-2.7 X9252TS G 100 -40 to 85 24 Ld SOIC (300 mil)

X9252TS24IZ-2.7 (Note) X9252TS Z G -40 to 85 24 Ld SOIC (300 mil) (Pb-Free)

X9252TV24I-2.7 X9252TV G -40 to 85 24 Ld TSSOP (4.4mm)

X9252TV24IZ-2.7 (Note) X9252TV Z G -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free)

Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Functional Diagram

R

DCP1

W1

R

H1

R

L1

A2

A1

A0

SDA

SCL

DS0

DS1

CS

U/D

V

CC

2-Wire

Interface

Up-Down

Interface

V

SS

POWER UP,

INTERFACE

CONTROL

AND

STATUS

WP

WCR0
DR00

DR01
DR02
DR03

R

DCP0

W0

R

H0

WCR1
DR10

DR11
DR12
DR13

R

L0

Pin Descriptions

SOIC/TSSOP PIN SYMBOL BRIEF DESCRIPTION

1 DS0 DCP select for Up/Down interface.

2 A0 Device address for 2-wire bus.

3 RW3 Wiper terminal of DCP3.

4 RH3 High terminal of DCP3.

WCR2
DR20

DR21
DR22
DR23

R

DCP2

W2

R

DCP3

W3

R

H3

R

L3

R

H2

WCR3
DR30

DR31
DR32
DR33

R

L2

2

FN8167.2

November 14, 2005

X9252

www.BDTIC.com/Intersil

Pin Descriptions (Continued)

SOIC/TSSOP PIN SYMBOL BRIEF DESCRIPTION

5 RL3 Low terminal of DCP3.

6U/D

7 VCC System supply voltage

8 RL0 Low terminal of DCP0.

9 RH0 High terminal of DCP0.

10 RW0 Wiper terminal of DCP0.

11 A2 Device address for 2-wire bus.

12 WP

13 SDA Serial data input/output for 2-wire bus.

14 A1 Device address for 2-wire bus.

15 RL1 Low terminal of DCP1.

16 RH1 High terminal of DCP1.

17 RW1 Wiper terminal DCP1.

18 VSS System ground

19 CS

20 RW2 Wiper terminal of DCP2.

21 RH2 High terminal of DCP2.

22 RL2 Low terminal of DCP2.

23 SCL Serial clock for 2-wire bus.

24 DS1 DCP select for up/down interface.

Increment/decrement for up/down interface.

Hardware write protect

Chip select for Up/Down interface.

Pin Descriptions

Bus Interface Pins

Serial Data Input/Output (SDA)

The SDA is a bidirectional serial data input/output pin for the
2-wire interface. It receives device address, operation code,
wiper register address and data from a 2-wire external master
device at the rising edge of the serial clock SCL, and it shifts
out data after each falling edge of the serial clock SCL.

SDA requires an external pull-up resistor, since it’s an open
drain output.

Serial Clock (SCL)

This input is the serial clock of the 2-wire and Up/Down
interface.

Device Address (A2-A0)

The Address inputs are used to set the least significant 3 bits of
the 8-bit 2-wire interface slave address. A match in the slave
address serial data stream must be made with the Address
input pins in order to initiate communication with the X9252. A
maximum of 8 devices may occupy the 2-wire serial bus.

Chip Select (CS

When the CS
are possible using the SCL and U/D

)

pin is low, increment or decrement operations

pins. The 2-wire

interface is disabled at this time. When CS
interface is enabled.

Up or Down Control (U/D

The U/D
and held LOW during decrement operations.

DCP Select (DS1-DS0)

The DS1-DS0 select one of the four DCPs for an Up/Down
interface operation.

Hardware Write Protect Input (WP

When the WP
DCP Data Registers are disabled. This includes both 2-wire
interface non-volatile “Write”, and Up/Down interface “Store”
operations.

input pin is held HIGH during increment operations

pin is set low, “write” operations to non volatile

)

is high, the 2-wire

)

DCP Pins

RH0, RL0, RH1, RL1, RH2, RL2, RH3, and R

These pins are equivalent to the terminal connections on
mechanical potentiometers. Since there are 4 DCPs, there is
one set of R

RW0, RW1, RW2, and RW3

The wiper pins are equivalent to the wiper terminal of
mechanical potentiometers. Since there are four DCPs,
there are 4 R

and RL for each DCP.

H

pins.

W

L3

3

FN8167.2

November 14, 2005

X9252

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Absolute Maximum Ratings Recommended Operating Conditions

Junction Temperature under bias. . . . . . . . . . . . . . .-65°C to +135°C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any digital interface pin
with respect to V
V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

CC

Voltage at any DCP pin with
respect to V

Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300°C

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation
of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

R

TOTAL

Matching

I

(Note 5) Wiper current See test circuit -3.0 +3.0 mA

W

R

W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

SS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to V

SS

End to end resistance Y, W, U, T versions respectively 2.8, 10,

End to end resistance tolerance -20 +20 %

Power rating 25°C, each DCP 50 mW

DCP to DCP resistance matching 0.75 2.0 %

Wiper resistance

CC

Wiper current =

Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

Supply Voltage (V

V

CC

R

TOTAL

)(Note 4) Limits . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

TYP

(Note 4) MAX UNIT

50, 100

50 150 Ω

kΩ

V

TERM

C

H/CL/CW

I

OL

Voltage on any DCP pin Vss Vcc V

Noise (Note 5) Ref: 1kHz -120 dBV

Resolution 0.4 %

Absolute linearity (Note 1) V(R

Relative linearity (Note 2) -0.3 +0.3 MI

Temperature coefficient of resistance
(Note 5)

Ratiometric Temperature (Note 5)
Coefficient

Potentiometer Capacitance (Note 5) See equivalent circuit 10/10/25 pF

Leakage on DCP pins Voltage at pin from VSS to V

)=V(RH1)=V(RH2)=V(RH3)=V

H0

V(RL0)=V(RL1)=V(RL2)=V(RL3)=V

CC

CC

SS

-1 +1 MI
(Note 3)

(Note 3)

±300 ppm/°C

-20 +20 ppm/°C

0.1 10 µA

DC Electrical Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNITS

I

CC1

I

CC2

I

CC3

I

SB

VCC supply current (Volatile write/read) f

VCC supply current (active) f

VCC supply current (nonvolatile write) f

VCC current (standby) V

= 400kHz;SDA = Open; (for 2-Wire, Active,

SCL

Read and Volatile Write States only)

= 200kHz;

SCL

interface, increment, decrement)

(for U/D

= 400kHz; SDA = Open;

SCL

(for 2-Wire, Active, Nonvolatile Write State only)

= +5.5V; VIN = VSS or VCC; SDA = VCC;

CC

(for 2-Wire, Standby State only)

3mA

3mA

5mA

100 µA

4

FN8167.2

November 14, 2005

X9252

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DC Electrical Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNITS

I

V

V

V

Endurance and Data Retention

Capacitance

Symbol Test Test Conditions Max. Units

C

IN/OUT

C

IN

Leakage current, bus interface pins Voltage at pin from VSS to V

L

Input HIGH voltage VCC x 0.7 VCC + 1 V

IH

Input LOW voltage -1 VCC x 0.3 V

IL

SDA pin output LOW voltage IOL = 3mA 0.4 V

OL

PARAMETER MIN UNITS

Minimum endurance 100,000 Data changes per bit

Data retention 100 Years

(Note 5) Input / Output capacitance (SDA) V

(Note 5) Input capacitance (SCL, WP, DS0, DS1, CS, U/D, A2, A1 and

A0)

CC

= 0V 8 pF

OUT

VIN = 0V 6 pF

-10 10 µA

Power-Up Timing

SYMBOL PARAMETER MAX UNITS

tD (Notes 5, 9) Power Up Delay from VCC power up (VCC above 2.7V) to wiper position recall

completed, and communication interfaces ready for operation.

2ms

A.C. Test Conditions

nput Pulse Levels VCC x 0.1 to VCC x 0.9

I

Input rise and fall times 10ns

Input and output timing threshold level V

External load at pin SDA 2.3kΩ to V

x 0.5

CC

and 100pF to V

CC

SS

2-Wire Interface timing (s)

SYMBOL PARAMETER MIN MAX UNITS

f

SCL

t

HIGH

t

LOW

t

SU:STA

t

HD:STA

t

SU:STO

t

SU:DAT

t

HD:DAT

(Note 5) SCL and SDA Rise Time 300 ns

t

R

(Note 5) SCL and SDA Fall Time 300 ns

t

F

(Note 5) SCL Low to SDA Data Output Valid Time 0.9 µs

t

AA

t

DH

(Note 5) Pulse Width Suppression Time at SCL and SDA inputs 50 ns

t

IN

Clock Frequency 400 kHz

Clock High Time 600 ns

Clock Low Time 1300 ns

Start Condition Setup Time 600 ns

Start Condition Hold Time 600 ns

Stop Condition Setup Time 600 ns

SDA Data Input Setup Time 100 ns

SDA Data Input Hold Time 30 ns

SDA Data Output Hold Time 0 ns

5

FN8167.2

November 14, 2005

X9252

www.BDTIC.com/Intersil

2-Wire Interface timing (s) (Continued)

SYMBOL PARAMETER MIN MAX UNITS

t

(Note 5) Bus Free Time (Prior to Any Transmission) 1200 ns

BUF

t

SU:WPA

A0, A1, A2 and WP

(Note 5)

t

HD:WPA

(Note 5)

A0, A1, A2 and WP Hold Time 600 ns

SDA vs SCL Timing

Setup Time 600 ns

SCL

t

SU:STA

(Input Timing)

(Output Timing)

WP

, A0, A1, and A2 Pin Timing

SDA

SDA

SCL

SDA IN

WP, A0, A1, or A2

t

HD:STA

START

t

F

t

SU:DAT

t

SU:WP

Clk 1

t

HIGH

t

LOW

t

HD:DAT

t

HD:WP

t

R

t

SU:STO

t

AA

STOP

t

DH

t

BUF

Increment/Decrement Timing

SYMBOL PARAMETER MIN TYP (Note 4) MAX UNITS

t

CI

(Note 5) SCL HIGH to U/D, DS0 or DS1 change 600 ns

t

ID

t

(Note 5) U/D, DS0 or DS1 to SCL setup 600 ns

DI

t

IL

t

IH

t

IC

t

CPHS

t

CPHNS

(Note 5)

(Note 5) SCL to RW change 100 500 µs

t

IW

t

CYC

tR, tF (Note 5) SCL input rise and fall time 500 µs

CS to SCL Setup 600 ns

SCL LOW period 2.5 µs

SCL HIGH period 2.5 µs

SCL inactive to CS inactive (Nonvolatile Store Setup Time) 1 µs

CS deselect time (STORE) 10 ms

deselect time (NO STORE) 1 µs

CS

SCL cycle time 5 µs

6

FN8167.2

November 14, 2005