intersil X9251 DATA SHEET

www.BDTIC.com/Intersil

X9251

Single Supply/Low Power/256-Tap/SPI Bus

Data Sheet April 13, 2007

Quad Digitally-Controlled (XDCP™) Potentiometer

The X9251 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometers are imple-mented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The content of the WCR controls the position of the wiper. At power-up, the device recalls the content of the default Data Registers of each DCP (DR00, DR10, DR20, and DR30) to the corresponding WCR.

The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

FN8166.5

Features

• Four potentiometers in one package

• 256 resistor taps–0.4% resolution

• SPI Serial Interface for write, read, and transfer operations of the potentiometer

• Wiper resistance: 100Ω typical @ V

• 4 Non-volatile data registers for each potentiometer

• Non-volatile storage of multiple wiper positions

• Standby current <5µA max

: 2.7V to 5.5V Operation

•V

•50kΩ, 100kΩ versions of total resistance

• 100 year data retentio n

• Single supply version of X9250

• Endurance: 100,000 data changes per bit per register

• 24 Ld SOIC, 24 Ld TSSOP

• Low power CMOS

= 5V

Functional Diagram

HOLD

SCK

SPI

Interface

POWER UP,

INTERFACE

CONTROL

AND

STATUS

WCR0 DR00

DR01 DR02 DR03

DCP0

• Pb-free plus anneal available (RoHS compliant)

DCP1

WCR2 DR20

DR21 DR22 DR23

WCR1 DR10

DR11 DR12 DR13

DCP2

WCR3 DR30

DR31 DR32 DR33

DCP3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9251

www.BDTIC.com/Intersil

Ordering Information

POTENTIOMENTER

PART

PART NUMBER

X9251US24 X9251US 5 ±10% 50 0 to +70 24 Ld SOIC (300 mil) M24.3 X9251US24Z (Note) X9251US Z 0 to +70 24 Ld SOIC (300 mil) (Pb-free) M24.3 X9251UV24 X9251UV 0 to +70 24 Ld TSSOP (4.4mm) MDP0044 X9251UV24Z (Note) X9251UV Z 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9251TS24 X9251TS 100 0 to +70 24 Ld SOIC (300 mil) M24.3 X9251TS24Z (Note) X9251TS Z 0 to +70 24 Ld SOIC (300 mil) (Pb-free) M24.3 X9251TS24I X9251TS I -40 to +85 24 Ld SOIC (300 mil) M24.3 X9251TS24IZ (Note) X9251TS ZI -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3 X9251TV24I X9251TV I -40 to +85 24 Ld TSSOP (4.4mm) MDP0044 X9251TV24IZ (Note) X9251TV ZI -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9251US24I-2.7 X9251US G 2.7 to 5.5 50 -40 to +85 24 Ld SOIC (300 mil) M24.3 X9251US24IZ-2.7 (Note) X9251US ZG -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3 X9251UV24-2.7 X9251UV F 0 to +70 24 Ld TSSOP (4.4mm) MDP0044 X9251UV24Z-2.7 (Note) X9251UV ZF 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9251UV24I-2.7 X9251UV G -40 to +85 24 Ld TSSOP (4.4mm) MDP0044 X9251UV24IZ-2.7 (Note) X9251UV ZG -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9251TS24-2.7 X9251TS F 100 0 to +70 24 Ld SOIC (300 mil) M24.3 X9251TS24Z-2.7 (Note) X9251TS ZF 0 to +70 24 Ld SOIC (300 mil) (Pb-free) M24.3 X9251TV24-2.7 X9251TV F 0 to +70 24 Ld TSSOP (4.4mm) MDP0044 X9251TV24Z-2.7 (Note) X9251TV ZF 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9251TV24I-2.7 X9251TV G -40 to +85 24 Ld TSSOP (4.4mm) MDP0044 X9251TV24IZ-2.7 (Note) X9251TV ZG -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING

LIMITS

(V)

ORGANIZATION

(kΩ)

TEMP RANGE

(°C) PACKAGE

PKG.

DWG. #

FN8166.5

April 13, 2007

X9251

www.BDTIC.com/Intersil

Circuit Level Applications

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF circuits

• Provide a control variable (I, V, or R) in feedback circuits

System Level Applications

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in communication systems

• Set and regulate the DC biasing point in an RF power amplifier in wireless systems

• Control the gain in audio and home entertainment systems

• Provide the variable DC bias for tuners in RF wireless systems

• Set the operating points in temperature control systems

• Control the operating point for sensors in industrial systems

• Trim offset and gain errors in artificial intelligent systems

Pinout

X9251

(24 LD SOIC/TSSOP)

TOP VIEW

HOLD

SCK

X9251

Pin Assignments

(SOIC) SYMBOL FUNCTION

1 SO Serial Data Output for SPI bus 2 A0 Device Address for SPI bus. (See Note 1) 3R 4R 5R 7V 8R

9R 10 R 11 CS 12 WP 13 SI Serial Data Input for SPI bus 14 A1 Device Address for SPI bus. (See Note 1) 15 R 16 R 17 R 18 V 20 R 21 R 22 R 23 SCK Serial Clock for SPI bus 24 HOLD

6, 19 NC No Connect

NOTE:

1. A0 and A1 device address pins must be tied to a logic level.

Wiper Terminal of DCP3

High Terminal of DCP3

Low Terminal of DCP3

System Supply Voltage

Low Terminal of DCP0

High Terminal of DCP0

Wiper Terminal of DCP0

SPI bus. Chip Select active low input Hardware Write Protect - active low

Low Terminal of DCP1

High Terminal of DCP1

Wiper Terminal of DCP1

System Ground

Wiper Terminal of DCP2

High Terminal of DCP2

Low Terminal of DCP2

Device select. Pauses the SPI serial bus.

FN8166.5

April 13, 2007

X9251

www.BDTIC.com/Intersil

Pin Descriptions

Bus Interface Pins

SERIAL OUTPUT (SO)

SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.

SERIAL INPUT (SI)

SI is the serial data input pin. All opcodes, byte addresses and data to be written to the device registers are input on this pin. Data is latched by the rising edge of the serial clock.

SERIAL CLOCK (SCK)

The SCK input is used to clock data into and out of the X9251.

HOLD (HOLD

is used in conjunction with the CS pin to select the

HOLD device. Once the part is selected and a serial sequence is underway, HOLD communication with the controller without resetting the serial sequence. To pause, HOLD SCK is LOW. To resume communication, HOLD HIGH, again while SCK is LOW. If the pause feature is not used, HOLD

DEVICE ADDRESS (A1 AND A0)

The address inputs are used to set the two least significant bits of the slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9251. Device pins A1 and A0 must be tied to a logic level which specifies the internal address of the device, see Figures 2, 3, 4, 5 and 6.

)

may be used to pause the serial

must be brought LOW while

is brought

should be held HIGH at all times.

Supply Pins

SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (V

The V

the system ground.

)

pin is the system supply voltage. The VSS pin is

Other Pins

NO CONNECT

No connect pins should be left floating . This pins are used for Intersil manufacturing and testing purposes.

HARDWARE WRITE PROTECT INPUT (WP)

The WP Data Registers.

pin when LOW prevents non-volatile writes to the

Principles of Operation

The X9251 is an integrated circuit incorporating four DCPs and their associated registers and counters, and a serial interface providing direct communication between a host and the potentiometers.

DCP Description

Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (R intermediate node, equivalent to the wiper terminal of a mechanical potentiometer.

The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Counter Register (WCR).

and RL pins). The RW pin is an

CHIP SELECT (CS

When CS is at high impedance, and (unless an internal write cycle is underway) the device is in the standby state. CS enables the X9251, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS operation.

is HIGH, the X9251 is deselected and the SO pin

)

LOW

is required prior to the start of any

Potentiometer Pins

RH, RL

The R connections on a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of R RH0 and RL0 are the terminals of DCP0 and so on.

The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of R DCP0 and so on.

and RL pins are equivalent to the terminal

such that RW0 is the terminals of

and RL such that

FN8166.5

April 13, 2007

One of Four Potentiometers

www.BDTIC.com/Intersil

X9251

#: 0, 1, 2, or 3

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

DR#0

8 8

DR#2

IF WCR = 00[H] then RW is closet to R IF WCR = FF[H] then RW is closet to R

FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM

Power Up and Down Recommendations

There are no restrictions on the power-up or power-down conditions of V potentiometer pins provided that V positive than or equal to V V

). The VCC ramp rate specification is always in effect.

and the voltages applied to the

, VL, and VW (i.e., VCC ≥ VH, VL,

is always more

Wiper Counter Register (WCR)

The X9251 contains four Wiper Counter Registers, one for each potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 wiper positions along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction (See Instruction section for more details). Finally, it is loaded with the contents of its Data Register zero (DR#0) upon power-up. (See Figure 1)

The wiper counter register is a volatile register; that is, its contents are lost when the X9251 is powered-down. Although the register is automatically loaded with the value in DR#0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR#0 value into the WCR#.

DR#1

DR#3

UP/DN

MODIFIED SCK

Data Registers (DR)

Each of the four DCPs has four 8-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the Data Registers is a non-volatile operation and takes a maximum of 10ms.

If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data.

Bits [7:0] are used to store one of the 256 wiper positions or data (0 ~ 255).

Status Register (SR)

This 1-bit Status Register is used to store the system status. WIP: Write In Progress status bit, read only.

• When WIP = 1, indicates that high-voltage write cycle is in

• When WIP = 0, indicates that no high-voltage write cycle is

SERIAL BUS INPUT

PARALLEL BUS INPUT

COUNTER REGISTER

UP/DN

CLK

progress.

in progress.

WIPER

(WCR#)

INC/DEC

LOGIC

COUNTER

- - -

DECODE

DCP

CORE

FN8166.5

April 13, 2007

X9251

www.BDTIC.com/Intersil

TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE)

WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0 (MSB) (LSB)

TABLE 2. DATA REGISTER, DR (8-bit), DR[7:0]: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE)

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

(MSB) (LSB)

Serial Interface

The X9251 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in, on the rising SCK. CS pins must be HIGH during the entire operation.

The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count.

must be LOW and the HOLD and WP

The least significant four bits of the Identification Byte are the Slave Address bits, AD[3:0]. For the X9251, A3 is 0, A2 is 0, A1 is the logic value at the input pin A1, and A0 is the logic value at the input pin A0. Only the device which Slave Address matches the incoming bits sent by the master executes the instruction. The A1 and A0 inputs can be actively driven by CMOS input signals or tied to V

Instruction Byte

The next byte sent to the X9251 contains the instruction and

Identification Byte

The first byte sent to the X9251 from the host, following a CS going HIGH to LOW, is called the Identification Byte. The most significant four bits of the Identification Byte are a Device Type Identifier , ID[3:0]. For the X9251, this is fixed as 0101 (refer to Table 3).

TABLE 3. IDENTIFICATION BYTE FORMAT

Device Type

Identifier

ID3 ID2 ID1 ID0 A3 A2 A1 A0

010100Pin A1

(MSB) (LSB)

register pointer information. The four most significant bits are used provide the instruction opcode (I[3:0]). The RB and RA bits point to one of the four Data Registers of each associated XDCP. The least two significant bits point to one of four Wiper Counter Registers or DCPs.The format is shown below in Table 4.

Slave Address

Logic Value

or VSS.

Logic Value

Pin A0

TABLE 4. INSTRUCTION BYTE FORMAT

Instruction

Opcode

I3 I2 I1 I0 RB RA P1 P0

(MSB) (LSB)

Selection

DCP Selection

(WCR Selection)

Data Register Selection

DR#0 0 0 DR#1 0 1 DR#2 1 0 DR#3 1 1

#: 0, 1, 2, or 3

FN8166.5

April 13, 2007

+ 14 hidden pages