intersil X9251 DATA SHEET

®

www.BDTIC.com/Intersil

X9251

Single Supply/Low Power/256-Tap/SPI Bus

Data Sheet April 13, 2007

Quad Digitally-Controlled (XDCP™)
Potentiometer

The X9251 integrates four digitally controlled potentio­meters (XDCP) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometers are imple-mented
with a combination of resistor elements and CMOS switches.
The position of the wipers are controlled by the user through
the SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and four
non-volatile Data Registers that can be directly written to and
read by the user. The content of the WCR controls the
position of the wiper. At power-up, the device recalls the
content of the default Data Registers of each DCP (DR00,
DR10, DR20, and DR30) to the corresponding WCR.

The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.

FN8166.5

Features

• Four potentiometers in one package

• 256 resistor taps–0.4% resolution

• SPI Serial Interface for write, read, and transfer operations
of the potentiometer

• Wiper resistance: 100Ω typical @ V

• 4 Non-volatile data registers for each
potentiometer

• Non-volatile storage of multiple wiper positions

• Standby current <5µA max

: 2.7V to 5.5V Operation

•V

CC

•50kΩ, 100kΩ versions of total resistance

• 100 year data retentio n

• Single supply version of X9250

• Endurance: 100,000 data changes per bit per register

• 24 Ld SOIC, 24 Ld TSSOP

• Low power CMOS

CC

= 5V

Functional Diagram

V

CC

HOLD

A1

A0

SO

SI

SCK

CS

SPI

Interface

V

SS

POWER UP,

INTERFACE

CONTROL

AND

STATUS

WP

WCR0
DR00

DR01
DR02
DR03

R

DCP0

W0

• Pb-free plus anneal available (RoHS compliant)

R

W1

DCP1

R

H1

WCR2
DR20

DR21
DR22
DR23

R

L1

R

H0

WCR1
DR10

DR11
DR12
DR13

R

L0

R

DCP2

W2

R

H2

R

L2

WCR3
DR30

DR31
DR32
DR33

R

DCP3

W3

R

H3

R

L3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9251

www.BDTIC.com/Intersil

Ordering Information

POTENTIOMENTER

PART

PART NUMBER

X9251US24 X9251US 5 ±10% 50 0 to +70 24 Ld SOIC (300 mil) M24.3
X9251US24Z (Note) X9251US Z 0 to +70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9251UV24 X9251UV 0 to +70 24 Ld TSSOP (4.4mm) MDP0044
X9251UV24Z (Note) X9251UV Z 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9251TS24 X9251TS 100 0 to +70 24 Ld SOIC (300 mil) M24.3
X9251TS24Z (Note) X9251TS Z 0 to +70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9251TS24I X9251TS I -40 to +85 24 Ld SOIC (300 mil) M24.3
X9251TS24IZ (Note) X9251TS ZI -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9251TV24I X9251TV I -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9251TV24IZ (Note) X9251TV ZI -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9251US24I-2.7 X9251US G 2.7 to 5.5 50 -40 to +85 24 Ld SOIC (300 mil) M24.3
X9251US24IZ-2.7 (Note) X9251US ZG -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9251UV24-2.7 X9251UV F 0 to +70 24 Ld TSSOP (4.4mm) MDP0044
X9251UV24Z-2.7 (Note) X9251UV ZF 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9251UV24I-2.7 X9251UV G -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9251UV24IZ-2.7 (Note) X9251UV ZG -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9251TS24-2.7 X9251TS F 100 0 to +70 24 Ld SOIC (300 mil) M24.3
X9251TS24Z-2.7 (Note) X9251TS ZF 0 to +70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9251TV24-2.7 X9251TV F 0 to +70 24 Ld TSSOP (4.4mm) MDP0044
X9251TV24Z-2.7 (Note) X9251TV ZF 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9251TV24I-2.7 X9251TV G -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9251TV24IZ-2.7 (Note) X9251TV ZG -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING

V

CC

LIMITS

(V)

ORGANIZATION

(kΩ)

TEMP RANGE

(°C) PACKAGE

PKG.

DWG. #

2

FN8166.5

April 13, 2007

X9251

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Circuit Level Applications

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier
circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and
Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF circuits

• Provide a control variable (I, V, or R) in feedback
circuits

System Level Applications

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems

• Control the gain in audio and home entertainment systems

• Provide the variable DC bias for tuners in RF wireless
systems

• Set the operating points in temperature control
systems

• Control the operating point for sensors in industrial
systems

• Trim offset and gain errors in artificial intelligent
systems

Pinout

X9251

(24 LD SOIC/TSSOP)

TOP VIEW

HOLD

SCK

R

L2

R

H2

R

W2

NC

V

SS

R

W1

R

H1

R

L1

A1

SI

R

R

R

V

R

SO

R

NC

R

WP

A0

W3

CC

W0

CS

1

2

3

H3

L3

L0

H0

4

5

6

X9251

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

Pin Assignments

PIN

(SOIC) SYMBOL FUNCTION

1 SO Serial Data Output for SPI bus
2 A0 Device Address for SPI bus. (See Note 1)
3R
4R
5R
7V
8R

9R
10 R
11 CS
12 WP
13 SI Serial Data Input for SPI bus
14 A1 Device Address for SPI bus. (See Note 1)
15 R
16 R
17 R
18 V
20 R
21 R
22 R
23 SCK Serial Clock for SPI bus
24 HOLD

6, 19 NC No Connect

NOTE:

1. A0 and A1 device address pins must be tied to a logic level.

Wiper Terminal of DCP3

W3

High Terminal of DCP3

H3

Low Terminal of DCP3

L3

System Supply Voltage

CC

Low Terminal of DCP0

L0

High Terminal of DCP0

H0

Wiper Terminal of DCP0

W0

SPI bus. Chip Select active low input
Hardware Write Protect - active low

Low Terminal of DCP1

L1

High Terminal of DCP1

H1

Wiper Terminal of DCP1

W1

System Ground

SS

Wiper Terminal of DCP2

W2

High Terminal of DCP2

H2

Low Terminal of DCP2

L2

Device select. Pauses the SPI serial bus.

3

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X9251

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Pin Descriptions

Bus Interface Pins

SERIAL OUTPUT (SO)

SO is a serial data output pin. During a read cycle, data is
shifted out on this pin. Data is clocked out by the falling edge
of the serial clock.

SERIAL INPUT (SI)

SI is the serial data input pin. All opcodes, byte addresses
and data to be written to the device registers are input on
this pin. Data is latched by the rising edge of the serial clock.

SERIAL CLOCK (SCK)

The SCK input is used to clock data into and out of the
X9251.

HOLD (HOLD

is used in conjunction with the CS pin to select the

HOLD
device. Once the part is selected and a serial sequence is
underway, HOLD
communication with the controller without resetting the serial
sequence. To pause, HOLD
SCK is LOW. To resume communication, HOLD
HIGH, again while SCK is LOW. If the pause feature is not
used, HOLD

DEVICE ADDRESS (A1 AND A0)

The address inputs are used to set the two least significant
bits of the slave address. A match in the slave address serial
data stream must be made with the address input in order to
initiate communication with the X9251. Device pins A1 and
A0 must be tied to a logic level which specifies the internal
address of the device, see Figures 2, 3, 4, 5 and 6.

)

may be used to pause the serial

must be brought LOW while

is brought

should be held HIGH at all times.

Supply Pins

SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (V

The V

CC

the system ground.

)

SS

pin is the system supply voltage. The VSS pin is

Other Pins

NO CONNECT

No connect pins should be left floating . This pins are
used for Intersil manufacturing and testing purposes.

HARDWARE WRITE PROTECT INPUT (WP)

The WP
Data Registers.

pin when LOW prevents non-volatile writes to the

Principles of Operation

The X9251 is an integrated circuit incorporating four DCPs
and their associated registers and counters, and a serial
interface providing direct communication between a host
and the potentiometers.

DCP Description

Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (R
intermediate node, equivalent to the wiper terminal of a
mechanical potentiometer.

The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Counter Register
(WCR).

and RL pins). The RW pin is an

H

CHIP SELECT (CS

When CS
is at high impedance, and (unless an internal write cycle is
underway) the device is in the standby state. CS
enables the X9251, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS
operation.

is HIGH, the X9251 is deselected and the SO pin

)

LOW

is required prior to the start of any

Potentiometer Pins

RH, RL

The R
connections on a mechanical potentiometer. Since there are
4 potentiometers, there are 4 sets of R
RH0 and RL0 are the terminals of DCP0 and so on.

R

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4 potentiometers,
there are 4 sets of R
DCP0 and so on.

and RL pins are equivalent to the terminal

H

W

such that RW0 is the terminals of

W

4

and RL such that

H

FN8166.5

April 13, 2007

One of Four Potentiometers

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X9251

#: 0, 1, 2, or 3

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

DR#0

8 8

DR#2

IF WCR = 00[H] then RW is closet to R
IF WCR = FF[H] then RW is closet to R

L

H

FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM

Power Up and Down Recommendations

There are no restrictions on the power-up or power-down
conditions of V
potentiometer pins provided that V
positive than or equal to V
V

). The VCC ramp rate specification is always in effect.

W

and the voltages applied to the

CC

, VL, and VW (i.e., VCC ≥ VH, VL,

H

is always more

CC

Wiper Counter Register (WCR)

The X9251 contains four Wiper Counter Registers, one for
each potentiometer. The Wiper Counter Register can be
envisioned as a 8-bit parallel and serial load counter with its
outputs decoded to select one of 256 wiper positions along
its resistor array. The contents of the WCR can be altered in
four ways: it may be written directly by the host via the Write
Wiper Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step at a
time by the Increment/Decrement instruction (See
Instruction section for more details). Finally, it is loaded with
the contents of its Data Register zero (DR#0) upon
power-up. (See Figure 1)

The wiper counter register is a volatile register; that is, its
contents are lost when the X9251 is powered-down.
Although the register is automatically loaded with the value
in DR#0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loadings of the DR#0 value
into the WCR#.

DR#1

DR#3

UP/DN

MODIFIED SCK

Data Registers (DR)

Each of the four DCPs has four 8-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the associated Wiper Counter Register. All
operations changing data in one of the Data Registers is a
non-volatile operation and takes a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.

Bits [7:0] are used to store one of the 256 wiper positions or
data (0 ~ 255).

Status Register (SR)

This 1-bit Status Register is used to store the system status.
WIP: Write In Progress status bit, read only.

• When WIP = 1, indicates that high-voltage write cycle is in

• When WIP = 0, indicates that no high-voltage write cycle is

SERIAL
BUS
INPUT

PARALLEL
BUS
INPUT

COUNTER
REGISTER

UP/DN

CLK

progress.

in progress.

WIPER

(WCR#)

INC/DEC

LOGIC

COUNTER

- - -

DECODE

DCP

CORE

R

H

R

W

R

L

5

FN8166.5

April 13, 2007

X9251

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TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE)

WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
(MSB) (LSB)

TABLE 2. DATA REGISTER, DR (8-bit), DR[7:0]: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE)

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

(MSB) (LSB)

Serial Interface

The X9251 supports the SPI interface hardware conventions.
The device is accessed via the SI input with data clocked in,
on the rising SCK. CS
pins must be HIGH during the entire operation.

The SO and SI pins can be connected together, since they
have three state outputs. This can help to reduce system pin
count.

must be LOW and the HOLD and WP

The least significant four bits of the Identification Byte are the
Slave Address bits, AD[3:0]. For the X9251, A3 is 0, A2 is 0,
A1 is the logic value at the input pin A1, and A0 is the logic
value at the input pin A0. Only the device which Slave
Address matches the incoming bits sent by the master
executes the instruction. The A1 and A0 inputs can be actively
driven by CMOS input signals or tied to V

Instruction Byte

The next byte sent to the X9251 contains the instruction and

Identification Byte

The first byte sent to the X9251 from the host, following a CS
going HIGH to LOW, is called the Identification Byte. The
most significant four bits of the Identification Byte are a
Device Type Identifier , ID[3:0]. For the X9251, this is fixed as
0101 (refer to Table 3).

TABLE 3. IDENTIFICATION BYTE FORMAT

Device Type

Identifier

ID3 ID2 ID1 ID0 A3 A2 A1 A0

010100Pin A1

(MSB) (LSB)

register pointer information. The four most significant bits are
used provide the instruction opcode (I[3:0]). The RB and RA
bits point to one of the four Data Registers of each associated
XDCP. The least two significant bits point to one of four Wiper
Counter Registers or DCPs.The format is shown below in
Table 4.

Slave Address

Logic Value

or VSS.

CC

Logic Value

Pin A0

TABLE 4. INSTRUCTION BYTE FORMAT

Instruction

Opcode

I3 I2 I1 I0 RB RA P1 P0

(MSB) (LSB)

Register

Selection

DCP Selection

(WCR Selection)

Data Register Selection

REGISTER RB RA

DR#0 0 0
DR#1 0 1
DR#2 1 0
DR#3 1 1

#: 0, 1, 2, or 3

6

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X9251

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TABLE 5. INSTRUCTION SET

INSTRUCTION SET

INSTRUCTION

Read Wiper Counter Register 1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Counter Register

pointed to by P1 - P0

Write Wiper Counter Register 1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Counter

Register pointed to by P1 - P0

Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed to

Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register

XFR Data Register to
Wiper Counter Register

XFR Wiper Counter
Register to Data Register

Global XFR Data Registers to
Wiper Counter Registers

Global XFR Wiper Counter
Registers to Data Register

Increment/Decrement
Wiper Counter Register

NOTE: 1/0 = data is one or zero

1 1 0 1 1/0 1/0 1/0 1/0 Transfer the contents of the Dat a Register pointed to

1 1 1 0 1/0 1/0 1/0 1/0 Transfer the contents of the Wiper Counter Register

0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers pointed

1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter

0 0 1 0 0 0 1/0 1/0 Enable Increment/decrement of the Control Latch

by P1 - P0 and RB - RA

pointed to by P1 - P0 and RB - RA

by P1 - P0 and RB - RA to its
associated Wiper Counter Register

pointed to by P1 - P0 to the Data Register pointed
to by RB - RA

to by RB - RA of all four pots to their respective
Wiper Counter Registers

Registers to their respective data Registers pointed
to by RB - RA of all four pots

pointed to by P1 - P0

OPERATIONI3 I2 I1 I0 RB RA P1 P0

Instructions

Four of the nine instructions are three bytes in length. These
instructions are:

• Read Wiper Counter Register – read the current wiper
position of the selected potentiometer,

• Write Wiper Counter Register – change current wiper
position of the selected potentiometer,

• Read Data Register – read the contents of the selected
Data Register,

• Write Data Register – write a new value to the selected
Data Register,

• Read Status – this command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress.

The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper to
this action is delayed by t
(current wiper position), to a Data Register is a write to non­volatile memory and takes a minimum of t
The transfer can occur between one of the four
potentiometer’s WCR, and one of its associated registers,

. A transfer from the WCR

WRL

WR

to complete.

DRs; or it may occur globally, where the transfer occurs
between all potentiometers and one associated register. The
Read Status Register instruction is the only unique format
(See Figure 5).

Four instructions require a two-byte sequence to complete.
These instructions transfer data between the host and the
X9251; either between the host and one of the data registers
or directly between the host and the Wiper Counter Register.
These instructions are:

• XFR Data Register to Wiper Counter Register – This
transfers the contents of one specified Data Register to
the associated Wiper Counter Register.

• XFR Wiper Counter Register to Data Register – This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.

• Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.

• Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.

7

FN8166.5

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X9251

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Increment/Decrement Command

The final command is Increment/Decrement (See Figures 6
and 7). The Increment/Decrement command is different from
the other commands. Once the command is issued and the
X9251 has responded with an Acknowledge, the master can
clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.

CS

SCK

CS

SI

0101

ID3 ID2 ID1 ID0 0

DEVICE ID

0

0

A1 A0

0

INTERNAL

ADDRESS

FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE

For each SCK clock pulse (t

) while SI is HIGH, the

HIGH

selected wiper moves one wiper position towards the R
terminal. Similarly, for each SCK clock pulse while SI is
LOW, the selected wiper moves one wiper position towards
the R

terminal. A detailed illustration of the sequence and

L

timing for this operation are shown. See Instruction format
for more details.

I3

I2

INSTRUCTION

OPCODE

I1

RB RA P0

I0

REGISTER
ADDRESS

P1

DCP/WCR

ADDRESS

H

SCK

SI

CS

SCK

SI

S0

0101

ID3 ID2 ID1 ID0

DEVICE ID

0101

ID3 ID2 ID1 ID0

DEVICE ID

00

00

A1 A0

INTERNAL
ADDRESS

I3 I2

I1

INSTRUCTION

OPCODE

RB RA P0

I0

REGISTER
ADDRESS

P1

DCP/WCR

ADDRESS

D7 D6 D5 D4 D3 D2 D1 D0

DATA FOR WCR[7:0] OR DR[7:0]

FIGURE 3. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE; WRITE CASE

00

00

A1 A0

INTERNAL
ADDRESS

I2

I3

INSTRUCTION

OPCODE

X

I1

RB RA P0

I0

REGISTER
ADDRESS

P1

DCP/WCR

ADDRESS

D7 D6 D5 D4 D3 D2 D1 D0

X

X

XX

DON’T CARE

XX

X

FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE, READ CASE

8

WCR[7:0]

DATA REGISTER BIT [7:0]

OR

FN8166.5

April 13, 2007

CS

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SCK

X9251

SI

CS

SCK

0 101

ID3 ID2 ID1 ID0

SI

ID3 ID2 ID1 ID0

DEVICE ID

FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTER)

0101

DEVICE ID

I1

I1

1

RB RA

I0

REGISTER
ADDRESS

I0

RB RA P0

REGISTER

ADDRESS

P0

P1

POT/WCR
ADDRESS

P1

POT/WCR
ADDRESS

00

00

00

00

A1 A0

INTERNAL
ADDRESS

A1 A0

INTERNAL
ADDRESS

101

I3

I2

INSTRUCTION
OPCODE

I3I2

INSTRUCTION

OPCODE

FIGURE 6. INCREMENT/DECREMENT INSTRUCTION SEQUENCE

0

0

I

N
C

2

00

D

I

E

N

C

C

1

n

00

WIP

STATUS

BIT

D
E
C

n

0

I

N
C

1

SCK

SI

R

W

INC/DEC CMD ISSUED

FIGURE 7. INCREMENT/DECREMENT TIMING SPEC

VOLTAGE OUT

t

WRID

9

FN8166.5

April 13, 2007

Instruction Format

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Read Wiper Counter Register (WCR)

X9251

CS

Falling

Edge

Device Type

Identifier

010100A1A010010000

Device

Addresses

Write Wiper Counter Register (WCR)

CS

Falling

Edge

Device Type

Identifier

010100A1A010100000

Device

Addresses

Read Data Register (DR)

CS

Falling

Edge

Device Type

Identifier

010100A1A01011RBRAP1 P0

Device

Addresses

Write Data Register (DR)

CS

Falling

Edge

Device Type

Identifier

010100A1A01100RBRAP1 P0

Device

Addresses

Instruction

Opcode

Instruction

Opcode

Instruction

Opcode

Instruction

Opcode

WCR

Addresses

WCR

Addresses

DR and WCR

Addresses

DR and WCR

Addresses

Wiper Position

(Sent by X9251 on SO)

W

W

W

W

W

W

C

C

C
R
7

W

W
C
R

7

D7D 6D5D4D3D2D1D

D7D 6D5D4D3D2D1D

C

R

R

R

6

5

4

Data Byte

(Sent by Host on SI)

W

W

C

C

C

R

R

R

6

5

4

Data Byte

(Sent by X9271 on SO)

Data Byte

(Sent by Host on SI)

W

C

C

C

R

R

R

3

2

1

W

W

W

C

C

C

R

R

R

3

2

1

CS

W

Rising

C

Edge

R
0

CS

W

Rising

C

Edge

R
0

CS

Rising

Edge

0

CS

HIGH-VOLTAGE

WRITE CYCLE

0

Rising

Edge

Global Transfer Data Register (DR) to Wipe r Counter Register (WCR)

CS

Falling

Edge

NOTES:

1. “A1 ~ A0”: stands for the device addresses sent by the master.

2. WPx refers to wiper position data in the Counter Register

3. “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).

4. “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).

Identifier

010100A1A00001RBRA00

Device Type

Device

Addresses

Instruction

Opcode

DR

Addresses

CS

Rising

Edge

10

FN8166.5

April 13, 2007

X9251

www.BDTIC.com/Intersil

Global Transfer Wiper Counter Register (WCR) to Data Register (DR)

CS

Falling

Edge

Device Type

Identifier

010100A1A01000RBRA00

Device

Addresses

Instruction

Opcode

DR

Addresses

CS

Rising

Edge

Transfer Wiper Counter Register (WCR) to Data Register (DR)

CS

Falling

Edge

Device Type

Identifier

010100A1A01110RBRA0 0

Device

Addresses

Instruction

Opcode

DR and WCR

Addresses

CS

Rising

Edge

Transfer Data Register (DR) to Wiper Counter Register (WCR)

CS

Falling

Edge

Device Type

Identifier

010 100A1A01101RBRA0 0

Device

Addresses

Instruction

Opcode

DR and WCR

Addresses

Rising

Edge

Increment/Decrement Wiper Counter Register (WCR)

CS

Falling

Edge

Device Type

Identifier

0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 0 I/D I/D . . . . I/D I/D

Device

Addresses

Instruction

Opcode

WCR

Addresses

Read Status Register (SR)

CS

Falling

Edge

NOTES:

1. “A1 ~ A0”: stands for the device addresses sent by the master.

2. WPx refers to wiper position data in the Counter Register

3. “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).

4. “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).

Device Type

Identifier

010100A1A00101000100000 00 WIP

Device

Addresses

Instruction

Opcode

WCR

Addresses

HIGH-VOLTAGE

WRITE CYCLE

HIGH-VOLTAGE

WRITE CYCLE

CS

Increment/Decrement

(Sent by Master on SI)

Data Byte

(Sent by X9251 on SO)

CS

Rising

Edge

CS

Rising

Edge

11

FN8166.5

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X9251

www.BDTIC.com/Intersil

Absolute Maximum Ratings Operating Conditions

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on SCK, CS

with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

ΔV = | (V

Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

Wiper Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA

Power Rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mW

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

- VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V

H

, SI, SO, WP, HOLD, V

CC

Analog Characteristics (Over the recommended operating conditions unless otherwise specified.)

SYMBOL PARAMETER TEST CONDITIONS

R

TOTAL

R

TOTAL

R

W

End to End Resistance T version 100 kΩ
End to End Resistance U version 50 kΩ
End to End Resistance Tolerance ±20 %
Wiper Resistance

V(VCC)

= @ VCC = 3V

I

W

R

TOTAL

Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage (V

X9251. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%

X9251-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

) Limits (Note 4)

CC

LIMITS

MIN TYP MAX UNITS

300 Ω

V(VCC)

I

= @ VCC = 5V

W

R

TOTAL

V

TERM

C

H/CL/CW

NOTES:

1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.

2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.

3. MI = RTOT/255 or (R

4. During power up V

5. n = 0, 1, 2, …,255; m = 0, 1, 2, …, 254.

Voltage on any RH or RL Pin V
Noise

(Note 6) Ref: 1V -120 dBV/√Hz

Resolution
Absolute Linearity

Relative Linearity

Temperature Coefficient of R
Ratiometric Temp. Coefficient (Note 6) ±20 ppm/°C
Potentiometer Capacitances See Macro model, (Note 6) 10/10/25 pF

(Note 1) R

(Note 2) R

- RL)/255, single pot

H

> VH, VL, and VW.

CC

TOTAL

= 0V V

SS

w(n)(actual)

w(n + 1)

(Note 6) ±300 ppm/°C

- R

- [R

w(n)(expected)

w(n) + MI

(Note 5) -1 +1 MI (Note 3)

] (Note 5) -0.6 +0.6 MI (Note 3)

SS

0.4 %

220 Ω

V

CC

V

12

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April 13, 2007

X9251

www.BDTIC.com/Intersil

DC Operating Characteristics (Over the recommended operating conditions unless otherwise specified.)

LIMITS

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

CC2

I

I
I
V
V

V
V
V

SB

LI

LO

OL
OH
OH

VCC supply current
(active)

VCC supply current
(non-volatile write)

VCC current (standby) SCK = SI = VSS, Addr. = VSS,

Input leakage current VIN = VSS to V
Output leakage current V
Input HIGH voltage VCC x 0.7 V

IH

Input LOW voltage VCC x 0.3 V

IL

Output LOW voltage IOL = 3mA 0.4 V
Output HIGH voltage IOH = -1mA, VCC ≥ +3V VCC - 0.8 V
Output HIGH voltage IOH = -0.4mA, VCC ≤ +3V VCC - 0.4 V

f

= 2.5 MHz, SO = Open, V

SCK

Other Inputs = V
f

= 2.5MHz, SO = Open, V

SCK

Other Inputs = V

CS

= VCC = 6V

= VSS to V

OUT

SS

SS

CC

CC

CC

CC

= 6V

= 6V

Endurance and Data Retention

PARAMETER MIN UNITS

Minimum endurance 100,000 Data changes per bit per register
Data retention 100 years

MIN. TYP MAX UNITS

400 μA

15mA

3 μA

10 μA
10 μA

Capacitance

SYMBOL TEST TEST CONDITIONS TYP UNITS

C

(Note 6) Input/Output capacitance (SI) V

IN/OUT

(Note 6) Output capacitance (SO) V

C

OUT

C

(Note 6) Input capacitance (A0, A1, CS, WP, HOLD, and SCK) VIN = 0V 6 pF

IN

= 0V 8 pF

OUT

= 0V 8 pF

OUT

Power-Up Timing

SYMBOL PARAMETER MIN MAX UNITS

(Note 6) VCC Power-up rate 0.2 V/ms

t

r VCC

(Note 7) Power-up to initiation of read operation 1 ms

t

PUR

(Note 7) Power-up to initiation of write operation 50 ms

t

PUW

A.C. Test Conditions

nput Pulse Levels VCC x 0.1 to VCC x 0.9

I

Input rise and fall times 10ns
Input and output timing level V

NOTES:

6. This parameter is not 100% tested
and t

7. t

PUR

parameters are periodically sampled and not 100% tested.

are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These

PUW

CC

x 0.5

13

FN8166.5

April 13, 2007

Equivalent A.C. Load Circuit

www.BDTIC.com/Intersil

V

CC

X9251

SPICE Macromodel

SO pin

2kΩ

2kΩ

10pF

R

H

10pF

R

TOTAL

C

L

C

W

25pF

R

W

C

L

10pF

R

L

AC TIMING

SYMBOL PARAMETER MIN MAX UNITS

f

SCK

t

CYC

t

WH

t

WL

t

LEAD

t

LAG

t

SU

t

H

t

RI

t

FI

t

DIS

t

V

t

HO

(Note 6) SO output rise time 100 ns

t

RO

(Note 6) SO output fall time 100 ns

t

FO

t

HOLD

t

HSU

t

HH

t

HZ

t

LZ

T

I

t

CS

t

WPASU

t

WPAH

SPI clock frequency 2MHz
SPI clock cycle rime 500 ns
SPI clock high rime 200 ns
SPI clock low time 200 ns
Lead time 250 ns
Lag time 250 ns
SI, SCK, HOLD and CS input setup time 50 ns
SI, SCK, HOLD and CS input hold time 50 ns
SI, SCK, HOLD and CS input rise time 2 μs
SI, SCK, HOLD and CS input fall time 2 μs
SO output disable time 0 250 ns
SO output valid time 200 ns
SO output hold time 0 ns

HOLD time 400 ns
HOLD setup time 100 ns
HOLD hold time 100 ns
HOLD low to output in high Z 100 ns
HOLD high to output in low Z 100 ns
Noise suppression time constant at SI, SCK, HOLD and CS inputs 10 ns
CS deselect time 2 μs
WP, A0 setup time 0 ns
WP, A0 hold time 0 ns

High-Voltage Write Cycle Timing

SYMBOL PARAMETER TYP MAX UNITS

t

WR

High-voltage write cycle time (store instructions) 5 10 ms

XDCP Timing

SYMBOL PARAMETER MIN MAX UNITS

(Note 6) Wiper response time after the third (last) power supply is stable 5 10 μs

t

WRPO

(Note 6) Wiper response time after instruction issued (all load instructions) 5 10 μs

t

WRL

14

FN8166.5

April 13, 2007

Symbol Table

www.BDTIC.com/Intersil

WAVEFORM INPUTS OUTPUTS

X9251

Timing Diagrams

Input Timing

CS

SCK

t

SU

SI

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

N/A Center Line

is High
Impedance

t

LEAD

t

H

MSB LSB

t

WL

t

CYC

...

t

WH

...

t

FI

t

CS

t

LAG

t

RI

SO

Output Timing

CS

SCK

SO

ADDR

SI

HIGH IMPEDANCE

t

V

MSB LSB

t

HO

...

...

t

DIS

15

FN8166.5

April 13, 2007

Hold Timing

www.BDTIC.com/Intersil

CS

t

HSU

X9251

t

HH

SCK

SO

HOLD

t

RO

SI

t

HOLD

t

FO

t

HZ

XDCP Timing (for All Load Instructions)

CS

SCK

SI

MSB

...

t

LZ

...

...

t

WRL

LSB

VWx

HIGH IMPEDANCE

SO

Write Protect and Device Address Pins Timing

CS

t

WP

A0

A1

WPASU

(ANY INSTRUCTION)

t

WPAH

16

FN8166.5

April 13, 2007

Applications information

www.BDTIC.com/Intersil

Basic Configurations of Electronic Potentiometers

V

R

RW

X9251

+V

R

I

Three terminal
Potentiometer;
Variable voltage divider

Application Circuits

NON INVERTING AMPLIFIER VOLTAGE REGULATOR

V

S

VO = (1+R2/R1)V

OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERESIS

Two terminal Variable
Resistor;
Variable current

+

–

R

R

1

S

V

O

2

IN

VO (REG) = 1.25V (1+R2/R1)+I

317

R

1

I

adj

R

2

VO (REG)V

adj R2

–

+

R

2

TL072

V

S

V

O

}

R

VUL = {R1/(R1+R2)} VO(max)
RL

= {R1/(R1+R2)} VO(min)

L

V

S

10kΩ

R

1

100kΩ

-12V+12V

10kΩ10kΩ

17

–

+

}

R

2

1

V

O

FN8166.5

April 13, 2007

Application Circuits (continued)

www.BDTIC.com/Intersil

ATTENUATOR FILTER

R

1

V

S

V

S

R

3

R

4

VO = G V

-1/2 ≤ G ≤ +1/2

INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT

R

R

1

}

VO = G V
G = - R2/R

2

}

R

–

+

R1 = R2 = R3 = R4 = 10kΩ

S

–

+

S

1

X9251

C

V

S

2

V

O

V

V

O

S

Z

IN

R

C

1

G

= 1 + R2/R

O

fc = 1/(2πRC)

+

–

R

R

1

1

R

2

+

–

R

1

R

3

V

O

2

FUNCTION GENERATOR

–

+

frequency ∝ R1, R2, C
amplitude ∝ R

, R

A

B

18

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R

R

2

R

}

A

R

}

B

R

1

+ R3) >> R

1

C

–

+

2

FN8166.5

April 13, 2007

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

X9251

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.5985 0.6141 15.20 15.60 3
E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6

N24 247

α

0° 8° 0° 8° -

NOTESMIN MAX MIN M AX

Rev. 1 4/06

19

FN8166.5

April 13, 2007

X9251

www.BDTIC.com/Intersil

Thin Shrink Small Outline Package Family (TSSOP)

E

C

SEATING
PLANE

N LEADS

0.25 CAB

M

N

E1

1

B

e

0.10 C

TOP VIEW

b

SIDE VIEW

SEE DETAIL “X”

(N/2)+1

(N/2)

0.10 CABM

AD

PIN #1 I.D.

0.20 C2XB A

N/2 LEAD TIPS

0.05

MDP0044

THIN SHRINK SMALL OUTLINE PACKAGE FAMILY

MILLIMETERS

SYMBOL

A 1.20 1.20 1.20 1.20 1.20 Max

A1 0.10 0.10 0.10 0.10 0.10 ±0.05

A2 0.90 0.90 0.90 0.90 0.90 ±0.05

b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06

c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06

D 5.00 5.00 6.50 7.80 9.70 ±0.10

E 6.40 6.40 6.40 6.40 6.40 Basic

E1 4.40 4.40 4.40 4.40 4.40 ±0.10

H

e 0.65 0.65 0.65 0.65 0.65 Basic

L 0.60 0.60 0.60 0.60 0.60 ±0.15

L1 1.00 1.00 1.00 1.00 1.00 Reference

NOTES:

1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.

3. Dimensions “D” and “E1” are measured at dAtum Plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

TOLERANCE14 LD 16 LD 20 LD 24 LD 28 LD

Rev. F 2/07

c

A2

A

A1

END VIEW

DETAIL X

L1

GAUGE
PLANE

0.25

L

0° - 8°

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

20

FN8166.5

April 13, 2007