intersil X9250 DATA SHEET

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X9250

Low Noise/Low Power/SPI Bus/256 Taps

Data Sheet FN8165.3August 29, 2006

Quad Digitally Controlled Potentiometers (XDCP™)

FEATURES

• Four potentiometers in one package

• 256 resistor taps/pot - 0.4% resolution

• SPI serial interface

• Wiper resistance, 40Ω typical @ V

• Four nonvolatile data registers for each pot

• Nonvolatile storage of wiper position

• Standby current < 5µA max (total package)

• Power supplies —V

= 2.7V to 5.5V

—V+ = 2.7V to 5.5V —V– = -2.7V to -5.5V

• 100kΩ, 50kΩ total pot resistance

• High reliability —Endurance – 100,000 data changes per bit per

—Register data retention - 100 years

• 24 Ld SOIC, 24 Ld TSSOP

• Dual supply version of X9251

• Pb-free plus anneal available (RoHS compliant)

= 5V

DESCRIPTION

The X9250 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power up recalls the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

BLOCK DIAGRAM

HOLD

SCK

A0 A1

V+

V-

Interface

and

Control

Circuitry

Data

Pot 0

R0R

Wiper

Counter Register

(WCR)

Wiper Counter Register

(WCR)

Resistor

Array

Pot1

R2R

R0R

R2R

VH0/R

VL0/R

VW0/R

VW1/R

H1/RH1

VL1/R

R0R

R2R

R0R

R2R

Wiper

Counter Register

(WCR)

Wiper

Counter

(WCR)

Resistor

Array Pot 2

Resistor

Array Pot 3

H2/RH2

VL2/R

VW2/R

VW3/R

H3/RH3

VL3/R

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Ordering Information

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X9250

PART

PART NUMBER

X9250TS24I X9250TS I 5 ±10% 100 -40 to +85 24 Ld SOIC (300 mil) M24.3 X9250TS24IZ (Note) X9250TS ZI -40 to +85 24 Ld SOIC (300 mil)

X9250TV24I X9250TV I -40 to +85 24 Ld TSSOP

X9250TV24IZ (Note) X9250TV ZI -40 to +85 24 Ld TSSOP

X9250US24 X9250US 50 0 to +70 24 Ld SOIC (300 mil) M24.3 X9250US24Z (Note) X9250US Z 0 to +70 24 Ld SOIC (300 mil)

X9250US24I X9250US I -40 to +85 24 Ld SOIC (300 mil) M24.3 X9250US24IZ (Note) X9250US ZI -40 to +85 24 Ld SOIC (300 mil)

X9250UV24I X9250UV I -40 to +85 24 Ld TSSOP

X9250UV24IZ (Note) X9250UV ZI -40 to +85 24 Ld TSSOP

X9250TS24-2.7 X9250TS F -2.7 to 5.5 100 0 to +70 24 Ld SOIC (300 mil) M24.3 X9250TS24Z-2.7 (Note) X9250TS ZF 0 to +70 24 Ld SOIC (300 mil)

X9250TS24I-2.7* X9250TS G -40 to +85 24 Ld SOIC (300 mil) M24.3 X9250TS24IZ-2.7*

(Note) X9250TV24I-2.7 X9250TV G -40 to +85 24 Ld TSSOP

X9250TV24IZ-2.7 (Note) X9250TV ZG -40 to +85 24 Ld TSSOP

X9250US24-2.7* X9250US F 50 0 to +70 24 Ld SOIC (300 mil) M24.3 X9250US24Z-2.7* (Note) X9250US ZF 0 to +70 24 Ld SOIC (300 mil)

X9250US24I-2.7 X9250US G -40 to +85 24 Ld SOIC (300 mil) M24.3 X9250US24IZ-2.7 (Note) X9250US ZG -40 to +85 24 Ld SOIC (300 mil)

X9250UV24-2.7 X9250UV F 0 to +70 24 Ld TSSOP

X9250UV24Z-2.7 (Note) X9250UV ZF 0 to +70 24 Ld TSSOP

X9250UV24I-2.7 X9250UV G -40 to +85 24 Ld TSSOP

X9250UV24IZ-2.7 (Note) X9250UV ZG -40 to +85 24 Ld TSSOP

*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING VCC LIMITS (V)

X9250TS ZG -40 to +85 24 Ld SOIC (300 mil)

POTENTIOMETER

ORGANIZATION (kΩ)

TEMP. RANGE

(°C) PACKAGE PKG . DWG. #

M24.3

(Pb-free)

MDP0044

(4.4mm)

MDP0044

(4.4mm) (Pb-free)

M24.3

(Pb-free)

M24.3

(Pb-free)

MDP0044

(4.4mm)

MDP0044

(4.4mm) (Pb-free)

M24.3

(Pb-free)

M24.3

(Pb-free)

MDP0044

(4.4mm)

MDP0044

(4.4mm) (Pb-free)

M24.3

(Pb-free)

M24.3

(Pb-free)

MDP0044

(4.4mm)

MDP0044

(4.4mm) (Pb-free)

MDP0044

(4.4mm)

MDP0044

(4.4mm) (Pb-free)

FN8165.3

August 29, 2006

X9250

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PIN DESCRIPTIONS

Serial Output (SO)

SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.

Serial Input

SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock.

Serial Clock (SCK)

The SCK input is used to clock data into and out of the X9250.

Chip Select (CS

When CS

is HIGH, the X9250 is deselected and the

)

SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS

LOW enables the X9250, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS

required prior to the start of any operation.

Hold (HOLD

HOLD

)

is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD

may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD

must be brought LOW while SCK is LOW. To resume communication, HOLD

is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times.

Device Address (A

- A1)

The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9250. A maximum of 4 devices may occupy the SPI serial bus.

Potentiometer Pins

H/RH

L3/RL3

The R

(VH0/R

)

and RL pins are equivalent to the terminal

- VH3/RH3), VL/RL (VL0/R

connections on a mechanical potentiometer.

W/RW

(VW0/R

W0 - VW3/RW3

)

The wiper pins are equivalent to the wiper terminal of a mechanical potentiometer.

Hardware Write Protect Input (WP

The WP

pin when LOW prevents nonvolatile writes to

)

the Data Registers.

Analog Supplies (V+, V-)

The analog supplies V+, V- are the supply voltages for the XDCP analog section.

PIN CONFIGURATION

SOIC/TSSOP

W3/RW3

VH3/R

L3/RL3

VL0/R

VH0/R

VW0/R

V+

X9250

HOLD

SCK

L2/RL2

VH2/R

VW2/R

V–

VW1/R

VH1/R

VL1/R

PIN NAMES

Symbol Description

SCK Serial Clock

SI, SO Serial Data

0-A1

H0/RH0–VH3/RH3

L0/RL0–VL3/RL3

W0/RW0–VW3/RW3

Device Address

Potentiometer Pins (terminal equivalent)

Potentiometer Pins (wiper equivalent)

Hardware Write Protection

V+,V- Analog Supplies

System Supply Voltage

System Ground

NC No Connection

FN8165.3

August 29, 2006

X9250

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DEVICE DESCRIPTION

Serial Interface

The X9250 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS LOW and the HOLD during the entire operation.

The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count.

Array Description

The X9250 is comprised of four resistor arrays. Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (V

At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (V switch may be turned on at a time.

These switches are controlled by a Wiper Counter Register (WCR). The 8 bits of the WCR are decoded to select, and enable, one of 256 switches.

) output. Within each individual array only one

W/RW

and WP pins must be HIGH

and VL/RL inputs).

H/RH

must be

Wiper Counter Register (WCR)

The X9250 contains four Wiper Counter Registers, one for each XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register or Global XFR Data Register instructions (parallel load); it can be modified one step at a time by the increment/decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9250 is powereddown. Although the register is automatically loaded with the value in R0 upon power-up, this may be different from the value present at power-down.

Data Registers

Each potentiometer has four 8-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms.

If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data.

Data Register Detail

(MSB) (LSB)

D7 D6 D5 D4 D3 D2 D1 D0

NV NV NV NV NV NV NV NV

FN8165.3

August 29, 2006

Figure 1. Detailed Potentiometer Block Diagram

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(One of Four Arrays)

X9250

Serial Data Path

From Interface

Circuitry

If WCR = 00[H] then VW/RW = VL/R

If WCR = FF[H] then V

W/RW

= VH/R

Modified SCK

Write in Process

The contents of the Data Registers are saved to nonvolatile memory when the CS

pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a write in process bit (WIP). The WIP bit is read with a read status command.

Serial Bus

UP/DN

Input

Parallel Bus Input

Wiper

Counter

(WCR)

Inc/Dec

Logic

UP/DN

CLK

C o u n

D e c o d e

Figure 2. Identification Byte Format

Device Type

Identifier

100

VH/R

VL/R

VW/R

0 0 A1 A0

Device Address

INSTRUCTIONS

Identification (ID) Byte

The first byte sent to the X9250 from the host, following a CS

going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier, for the X9250 this is fixed as 0101[B] (refer to Figure 2).

The two least significant bits in the ID byte select one of four devices on the bus. The physical device address is defined by the state of the A

- A1 input

pins. The X9250 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9250 to successfully continue the command sequence. The A

- A1 inputs

can be actively driven by CMOS input signals or tied to

or VSS.

The remaining two bits in the slave byte must be set to 0.

Instruction Byte

The next byte sent to the X9250 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of the four pots and, when applicable, they point to one of four associated registers. The format is shown below in Figure 3.

Figure 3. Instruction Byte Format

Select

I1I2I3 I0 R1 R0 P1 P0

Instructions

Pot Select

August 29, 2006

FN8165.3

X9250

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The four high order bits of the instruction byte specify the operation. The next two bits (R one of the four registers that is to be acted upon when a register oriented instruction is issued. The last two bits (P1 and P potentiometers is to be affected by the instruction.

Four of the ten instructions are two bytes in length and end with the transmission of the instruction byte. These instructions are:

– XFR Data Register to Wiper Counter Register

transfers the contents of one specified Data Register to the associated Wiper Counter Register.

– XFR Wiper Counter Register to Data Register

transfers the contents of the specified Wiper Counter Register to the specified associated Data Register.

– Global XFR Data Register to Wiper Counter Regiter

This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers.

– Global XFR Wiper Counter Register to Data Regiter

This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers.

The basic sequence of the two byte instructions is illustrated in Figure 4. These two-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by t from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of t between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register.

) selects which one of the four

to complete. The transfer can occur

and R0) select

—This

. A transfer

WRL

—

Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9250; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are:

– Read Wiper Counter Register

wiper position of the selected pot,

– Write Wiper Counter Register

wiper position of the selected pot,

– Read Data Register

selected data register;

– Write Data Register

selected data register.

– Read Status

of the WIP bit which indicates if the internal write cycle is in progress.

The sequence of these operations is shown in Figure 5 and Figure 6.

The final command is Increment/Decrement. It is different from the other commands, because it’s length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse

) while SI is HIGH, the selected wiper will move

HIGH

one resistor segment towards the V Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the V sequence and timing for this operation are shown in Figure 7 and Figure 8.

—This command returns the contents

L/RL

—read the contents of the

—write a new value to the

terminal. A detailed illustration of the

—read the current

—change current

terminal.

H/RH

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